Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
| 2 | #define _INTEL_RINGBUFFER_H_ |
| 3 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 4 | /* |
| 5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
| 6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
| 7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
| 8 | * |
| 9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
| 10 | * cacheline, the Head Pointer must not be greater than the Tail |
| 11 | * Pointer." |
| 12 | */ |
| 13 | #define I915_RING_FREE_SPACE 64 |
| 14 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 15 | struct intel_hw_status_page { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 16 | u32 *page_addr; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 17 | unsigned int gfx_addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 18 | struct drm_i915_gem_object *obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 19 | }; |
| 20 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
| 22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 23 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
| 25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 26 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
| 28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 29 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
| 31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 32 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
| 34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 35 | |
Ben Widawsky | b7287d8 | 2011-04-25 11:22:22 -0700 | [diff] [blame] | 36 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
| 37 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) |
| 38 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 39 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame^] | 40 | struct intel_ring_hangcheck { |
| 41 | u32 seqno; |
| 42 | }; |
| 43 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 44 | struct intel_ring_buffer { |
| 45 | const char *name; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 46 | enum intel_ring_id { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 47 | RCS = 0x0, |
| 48 | VCS, |
| 49 | BCS, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 50 | } id; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 51 | #define I915_NUM_RINGS 3 |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 52 | u32 mmio_base; |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 53 | void __iomem *virtual_start; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 54 | struct drm_device *dev; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 55 | struct drm_i915_gem_object *obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 56 | |
Chris Wilson | 8c0a6bf | 2010-12-09 12:56:37 +0000 | [diff] [blame] | 57 | u32 head; |
| 58 | u32 tail; |
Chris Wilson | 780f0ca | 2010-09-23 17:45:39 +0100 | [diff] [blame] | 59 | int space; |
Chris Wilson | c2c347a9 | 2010-10-27 15:11:53 +0100 | [diff] [blame] | 60 | int size; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 61 | int effective_size; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 62 | struct intel_hw_status_page status_page; |
| 63 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 64 | /** We track the position of the requests in the ring buffer, and |
| 65 | * when each is retired we increment last_retired_head as the GPU |
| 66 | * must have finished processing the request and so we know we |
| 67 | * can advance the ringbuffer up to that position. |
| 68 | * |
| 69 | * last_retired_head is set to -1 after the value is consumed so |
| 70 | * we can detect new retirements. |
| 71 | */ |
| 72 | u32 last_retired_head; |
| 73 | |
Chris Wilson | 7338aef | 2012-04-24 21:48:47 +0100 | [diff] [blame] | 74 | u32 irq_refcount; /* protected by dev_priv->irq_lock */ |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 75 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 76 | u32 trace_irq_seqno; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 77 | u32 sync_seqno[I915_NUM_RINGS-1]; |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 78 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 79 | void (*irq_put)(struct intel_ring_buffer *ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 80 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 81 | int (*init)(struct intel_ring_buffer *ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 82 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 83 | void (*write_tail)(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 84 | u32 value); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 85 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
| 86 | u32 invalidate_domains, |
| 87 | u32 flush_domains); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 88 | int (*add_request)(struct intel_ring_buffer *ring); |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 89 | /* Some chipsets are not quite as coherent as advertised and need |
| 90 | * an expensive kick to force a true read of the up-to-date seqno. |
| 91 | * However, the up-to-date seqno is not always required and the last |
| 92 | * seen value is good enough. Note that the seqno will always be |
| 93 | * monotonic, even if not coherent. |
| 94 | */ |
| 95 | u32 (*get_seqno)(struct intel_ring_buffer *ring, |
| 96 | bool lazy_coherency); |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 97 | void (*set_seqno)(struct intel_ring_buffer *ring, |
| 98 | u32 seqno); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 99 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
Chris Wilson | d7d4eed | 2012-10-17 12:09:54 +0100 | [diff] [blame] | 100 | u32 offset, u32 length, |
| 101 | unsigned flags); |
| 102 | #define I915_DISPATCH_SECURE 0x1 |
Daniel Vetter | b45305f | 2012-12-17 16:21:27 +0100 | [diff] [blame] | 103 | #define I915_DISPATCH_PINNED 0x2 |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 104 | void (*cleanup)(struct intel_ring_buffer *ring); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 105 | int (*sync_to)(struct intel_ring_buffer *ring, |
| 106 | struct intel_ring_buffer *to, |
| 107 | u32 seqno); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 108 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 109 | u32 semaphore_register[3]; /*our mbox written by others */ |
| 110 | u32 signal_mbox[2]; /* mboxes this ring signals to */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 111 | /** |
| 112 | * List of objects currently involved in rendering from the |
| 113 | * ringbuffer. |
| 114 | * |
| 115 | * Includes buffers having the contents of their GPU caches |
| 116 | * flushed, not necessarily primitives. last_rendering_seqno |
| 117 | * represents when the rendering involved will be completed. |
| 118 | * |
| 119 | * A reference is held on the buffer while on this list. |
| 120 | */ |
| 121 | struct list_head active_list; |
| 122 | |
| 123 | /** |
| 124 | * List of breadcrumbs associated with GPU requests currently |
| 125 | * outstanding. |
| 126 | */ |
| 127 | struct list_head request_list; |
| 128 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 129 | /** |
| 130 | * Do we have some not yet emitted requests outstanding? |
| 131 | */ |
Chris Wilson | 5d97eb6 | 2010-11-10 20:40:02 +0000 | [diff] [blame] | 132 | u32 outstanding_lazy_request; |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 133 | bool gpu_caches_dirty; |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 134 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 135 | wait_queue_head_t irq_queue; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 136 | |
Ben Widawsky | 12b0286 | 2012-06-04 14:42:50 -0700 | [diff] [blame] | 137 | /** |
| 138 | * Do an explicit TLB flush before MI_SET_CONTEXT |
| 139 | */ |
| 140 | bool itlb_before_ctx_switch; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 141 | struct i915_hw_context *default_context; |
Chris Wilson | 112522f | 2013-05-02 16:48:07 +0300 | [diff] [blame] | 142 | struct i915_hw_context *last_context; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 143 | |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame^] | 144 | struct intel_ring_hangcheck hangcheck; |
| 145 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 146 | void *private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 147 | }; |
| 148 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 149 | static inline bool |
| 150 | intel_ring_initialized(struct intel_ring_buffer *ring) |
| 151 | { |
| 152 | return ring->obj != NULL; |
| 153 | } |
| 154 | |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 155 | static inline unsigned |
| 156 | intel_ring_flag(struct intel_ring_buffer *ring) |
| 157 | { |
| 158 | return 1 << ring->id; |
| 159 | } |
| 160 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 161 | static inline u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 162 | intel_ring_sync_index(struct intel_ring_buffer *ring, |
| 163 | struct intel_ring_buffer *other) |
| 164 | { |
| 165 | int idx; |
| 166 | |
| 167 | /* |
| 168 | * cs -> 0 = vcs, 1 = bcs |
| 169 | * vcs -> 0 = bcs, 1 = cs, |
| 170 | * bcs -> 0 = cs, 1 = vcs. |
| 171 | */ |
| 172 | |
| 173 | idx = (other - ring) - 1; |
| 174 | if (idx < 0) |
| 175 | idx += I915_NUM_RINGS; |
| 176 | |
| 177 | return idx; |
| 178 | } |
| 179 | |
| 180 | static inline u32 |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 181 | intel_read_status_page(struct intel_ring_buffer *ring, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 182 | int reg) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 183 | { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 184 | /* Ensure that the compiler doesn't optimize away the load. */ |
| 185 | barrier(); |
| 186 | return ring->status_page.page_addr[reg]; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 187 | } |
| 188 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 189 | static inline void |
| 190 | intel_write_status_page(struct intel_ring_buffer *ring, |
| 191 | int reg, u32 value) |
| 192 | { |
| 193 | ring->status_page.page_addr[reg] = value; |
| 194 | } |
| 195 | |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 196 | /** |
| 197 | * Reads a dword out of the status page, which is written to from the command |
| 198 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
| 199 | * MI_STORE_DATA_IMM. |
| 200 | * |
| 201 | * The following dwords have a reserved meaning: |
| 202 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
| 203 | * 0x04: ring 0 head pointer |
| 204 | * 0x05: ring 1 head pointer (915-class) |
| 205 | * 0x06: ring 2 head pointer (915-class) |
| 206 | * 0x10-0x1b: Context status DWords (GM45) |
| 207 | * 0x1f: Last written status offset. (GM45) |
| 208 | * |
| 209 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
| 210 | */ |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 211 | #define I915_GEM_HWS_INDEX 0x20 |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 212 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
| 213 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 214 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 215 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 216 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 217 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 218 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
| 219 | u32 data) |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 220 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 221 | iowrite32(data, ring->virtual_start + ring->tail); |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 222 | ring->tail += 4; |
| 223 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 224 | void intel_ring_advance(struct intel_ring_buffer *ring); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 225 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
Mika Kuoppala | f7e98ad | 2012-12-19 11:13:06 +0200 | [diff] [blame] | 226 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno); |
Chris Wilson | a7b9761 | 2012-07-20 12:41:08 +0100 | [diff] [blame] | 227 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
| 228 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 229 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 230 | int intel_init_render_ring_buffer(struct drm_device *dev); |
| 231 | int intel_init_bsd_ring_buffer(struct drm_device *dev); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 232 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 233 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 234 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
| 235 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); |
Daniel Vetter | 79f321b | 2010-09-24 21:20:10 +0200 | [diff] [blame] | 236 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 237 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
| 238 | { |
| 239 | return ring->tail; |
| 240 | } |
| 241 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 242 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
| 243 | { |
| 244 | BUG_ON(ring->outstanding_lazy_request == 0); |
| 245 | return ring->outstanding_lazy_request; |
| 246 | } |
| 247 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 248 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
| 249 | { |
| 250 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |
| 251 | ring->trace_irq_seqno = seqno; |
| 252 | } |
| 253 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 254 | /* DRI warts */ |
| 255 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); |
| 256 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 257 | #endif /* _INTEL_RINGBUFFER_H_ */ |