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Vladimir Barinov3d9edf02007-07-10 13:03:43 +01001/*
2 * TI DaVinci GPIO Support
3 *
David Brownelldce11152008-09-07 23:41:04 -07004 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01005 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
Russell King2f8163b2011-07-26 10:53:52 +010012#include <linux/gpio.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010013#include <linux/errno.h>
14#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010015#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
KV Sujith118150f2013-08-18 10:48:58 +053018#include <linux/irq.h>
Lad, Prabhakar9211ff32013-11-21 23:45:27 +053019#include <linux/irqdomain.h>
KV Sujithc7708442013-11-21 23:45:29 +053020#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
KV Sujith118150f2013-08-18 10:48:58 +053023#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-davinci.h>
Grygorii Strashko0d978eb2013-11-26 21:40:09 +020025#include <linux/irqchip/chained_irq.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010026
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040027struct davinci_gpio_regs {
28 u32 dir;
29 u32 out_data;
30 u32 set_data;
31 u32 clr_data;
32 u32 in_data;
33 u32 set_rising;
34 u32 clr_rising;
35 u32 set_falling;
36 u32 clr_falling;
37 u32 intstat;
38};
39
Grygorii Strashko0c6feb02014-02-13 17:58:45 +020040typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
41
Philip Avinash131a10a2013-08-18 10:48:57 +053042#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
43
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040044#define chip2controller(chip) \
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040045 container_of(chip, struct davinci_gpio_controller, chip)
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040046
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040047static void __iomem *gpio_base;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010048
KV Sujith118150f2013-08-18 10:48:58 +053049static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010050{
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040051 void __iomem *ptr;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040052
53 if (gpio < 32 * 1)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040054 ptr = gpio_base + 0x10;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040055 else if (gpio < 32 * 2)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040056 ptr = gpio_base + 0x38;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040057 else if (gpio < 32 * 3)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040058 ptr = gpio_base + 0x60;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040059 else if (gpio < 32 * 4)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040060 ptr = gpio_base + 0x88;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040061 else if (gpio < 32 * 5)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040062 ptr = gpio_base + 0xb0;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040063 else
64 ptr = NULL;
65 return ptr;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010066}
67
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040068static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
Kevin Hilman21ce8732010-02-25 16:49:56 -080069{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040070 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080071
Thomas Gleixner6845664a2011-03-24 13:25:22 +010072 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
Kevin Hilman21ce8732010-02-25 16:49:56 -080073
74 return g;
75}
76
KV Sujith118150f2013-08-18 10:48:58 +053077static int davinci_gpio_irq_setup(struct platform_device *pdev);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010078
79/*--------------------------------------------------------------------------*/
80
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040081/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040082static inline int __davinci_direction(struct gpio_chip *chip,
83 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010084{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040085 struct davinci_gpio_controller *d = chip2controller(chip);
86 struct davinci_gpio_regs __iomem *g = d->regs;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040087 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010088 u32 temp;
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040089 u32 mask = 1 << offset;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010090
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040091 spin_lock_irqsave(&d->lock, flags);
Lad, Prabhakar388291c2013-12-11 23:22:07 +053092 temp = readl_relaxed(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040093 if (out) {
94 temp &= ~mask;
Lad, Prabhakar388291c2013-12-11 23:22:07 +053095 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040096 } else {
97 temp |= mask;
98 }
Lad, Prabhakar388291c2013-12-11 23:22:07 +053099 writel_relaxed(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400100 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -0700101
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100102 return 0;
103}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100104
Cyril Chemparathyba4a9842010-05-01 18:37:51 -0400105static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
106{
107 return __davinci_direction(chip, offset, false, 0);
108}
109
110static int
111davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
112{
113 return __davinci_direction(chip, offset, true, value);
114}
115
David Brownelldce11152008-09-07 23:41:04 -0700116/*
117 * Read the pin's value (works even if it's set up as output);
118 * returns zero/nonzero.
119 *
120 * Note that changes are synched to the GPIO clock, so reading values back
121 * right after you've set them may give old values.
122 */
123static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100124{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400125 struct davinci_gpio_controller *d = chip2controller(chip);
126 struct davinci_gpio_regs __iomem *g = d->regs;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100127
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530128 return (1 << offset) & readl_relaxed(&g->in_data);
David Brownelldce11152008-09-07 23:41:04 -0700129}
130
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100131/*
David Brownelldce11152008-09-07 23:41:04 -0700132 * Assuming the pin is muxed as a gpio output, set its output value.
133 */
134static void
135davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
136{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400137 struct davinci_gpio_controller *d = chip2controller(chip);
138 struct davinci_gpio_regs __iomem *g = d->regs;
David Brownelldce11152008-09-07 23:41:04 -0700139
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530140 writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
David Brownelldce11152008-09-07 23:41:04 -0700141}
142
KV Sujithc7708442013-11-21 23:45:29 +0530143static struct davinci_gpio_platform_data *
144davinci_gpio_get_pdata(struct platform_device *pdev)
145{
146 struct device_node *dn = pdev->dev.of_node;
147 struct davinci_gpio_platform_data *pdata;
148 int ret;
149 u32 val;
150
151 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
152 return pdev->dev.platform_data;
153
154 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
155 if (!pdata)
156 return NULL;
157
158 ret = of_property_read_u32(dn, "ti,ngpio", &val);
159 if (ret)
160 goto of_err;
161
162 pdata->ngpio = val;
163
164 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
165 if (ret)
166 goto of_err;
167
168 pdata->gpio_unbanked = val;
169
170 return pdata;
171
172of_err:
173 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
174 return NULL;
175}
176
Alexander Holler758afe42014-03-05 12:21:01 +0100177#ifdef CONFIG_OF_GPIO
178static int davinci_gpio_of_xlate(struct gpio_chip *gc,
179 const struct of_phandle_args *gpiospec,
180 u32 *flags)
181{
182 struct davinci_gpio_controller *chips = dev_get_drvdata(gc->dev);
183 struct davinci_gpio_platform_data *pdata = dev_get_platdata(gc->dev);
184
185 if (gpiospec->args[0] > pdata->ngpio)
186 return -EINVAL;
187
188 if (gc != &chips[gpiospec->args[0] / 32].chip)
189 return -EINVAL;
190
191 if (flags)
192 *flags = gpiospec->args[1];
193
194 return gpiospec->args[0] % 32;
195}
196#endif
197
KV Sujith118150f2013-08-18 10:48:58 +0530198static int davinci_gpio_probe(struct platform_device *pdev)
David Brownelldce11152008-09-07 23:41:04 -0700199{
200 int i, base;
Mark A. Greera9949552009-04-15 12:40:35 -0700201 unsigned ngpio;
KV Sujith118150f2013-08-18 10:48:58 +0530202 struct davinci_gpio_controller *chips;
203 struct davinci_gpio_platform_data *pdata;
204 struct davinci_gpio_regs __iomem *regs;
205 struct device *dev = &pdev->dev;
206 struct resource *res;
David Brownelldce11152008-09-07 23:41:04 -0700207
KV Sujithc7708442013-11-21 23:45:29 +0530208 pdata = davinci_gpio_get_pdata(pdev);
KV Sujith118150f2013-08-18 10:48:58 +0530209 if (!pdata) {
210 dev_err(dev, "No platform data found\n");
211 return -EINVAL;
212 }
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400213
KV Sujithc7708442013-11-21 23:45:29 +0530214 dev->platform_data = pdata;
215
Mark A. Greera9949552009-04-15 12:40:35 -0700216 /*
217 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800218 * and "ngpio" is one more than the largest zero-based
219 * bit index that's valid.
220 */
KV Sujith118150f2013-08-18 10:48:58 +0530221 ngpio = pdata->ngpio;
Mark A. Greera9949552009-04-15 12:40:35 -0700222 if (ngpio == 0) {
KV Sujith118150f2013-08-18 10:48:58 +0530223 dev_err(dev, "How many GPIOs?\n");
David Brownell474dad52008-12-07 11:46:23 -0800224 return -EINVAL;
225 }
226
Grygorii Strashkoc21d5002013-11-21 17:34:35 +0200227 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
228 ngpio = ARCH_NR_GPIOS;
David Brownell474dad52008-12-07 11:46:23 -0800229
KV Sujith118150f2013-08-18 10:48:58 +0530230 chips = devm_kzalloc(dev,
231 ngpio * sizeof(struct davinci_gpio_controller),
232 GFP_KERNEL);
Jingoo Han9ea9363c2014-04-29 17:33:26 +0900233 if (!chips)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400234 return -ENOMEM;
KV Sujith118150f2013-08-18 10:48:58 +0530235
236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
KV Sujith118150f2013-08-18 10:48:58 +0530237 gpio_base = devm_ioremap_resource(dev, res);
238 if (IS_ERR(gpio_base))
239 return PTR_ERR(gpio_base);
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400240
David Brownell474dad52008-12-07 11:46:23 -0800241 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
David Brownelldce11152008-09-07 23:41:04 -0700242 chips[i].chip.label = "DaVinci";
243
244 chips[i].chip.direction_input = davinci_direction_in;
245 chips[i].chip.get = davinci_gpio_get;
246 chips[i].chip.direction_output = davinci_direction_out;
247 chips[i].chip.set = davinci_gpio_set;
248
249 chips[i].chip.base = base;
David Brownell474dad52008-12-07 11:46:23 -0800250 chips[i].chip.ngpio = ngpio - base;
David Brownelldce11152008-09-07 23:41:04 -0700251 if (chips[i].chip.ngpio > 32)
252 chips[i].chip.ngpio = 32;
253
KV Sujithc7708442013-11-21 23:45:29 +0530254#ifdef CONFIG_OF_GPIO
Alexander Holler758afe42014-03-05 12:21:01 +0100255 chips[i].chip.of_gpio_n_cells = 2;
256 chips[i].chip.of_xlate = davinci_gpio_of_xlate;
257 chips[i].chip.dev = dev;
KV Sujithc7708442013-11-21 23:45:29 +0530258 chips[i].chip.of_node = dev->of_node;
259#endif
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400260 spin_lock_init(&chips[i].lock);
261
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400262 regs = gpio2regs(base);
263 chips[i].regs = regs;
264 chips[i].set_data = &regs->set_data;
265 chips[i].clr_data = &regs->clr_data;
266 chips[i].in_data = &regs->in_data;
David Brownelldce11152008-09-07 23:41:04 -0700267
268 gpiochip_add(&chips[i].chip);
269 }
270
KV Sujith118150f2013-08-18 10:48:58 +0530271 platform_set_drvdata(pdev, chips);
272 davinci_gpio_irq_setup(pdev);
David Brownelldce11152008-09-07 23:41:04 -0700273 return 0;
274}
David Brownelldce11152008-09-07 23:41:04 -0700275
276/*--------------------------------------------------------------------------*/
277/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100278 * We expect irqs will normally be set up as input pins, but they can also be
279 * used as output pins ... which is convenient for testing.
280 *
David Brownell474dad52008-12-07 11:46:23 -0800281 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700282 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100283 *
David Brownell474dad52008-12-07 11:46:23 -0800284 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100285 * serve as EDMA event triggers.
286 */
287
Lennert Buytenhek23265442010-11-29 10:27:27 +0100288static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100289{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100290 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100291 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100292
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530293 writel_relaxed(mask, &g->clr_falling);
294 writel_relaxed(mask, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100295}
296
Lennert Buytenhek23265442010-11-29 10:27:27 +0100297static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100298{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100299 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100300 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100301 unsigned status = irqd_get_trigger_type(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100302
David Brownelldf4aab42009-05-04 13:14:27 -0700303 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
304 if (!status)
305 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
306
307 if (status & IRQ_TYPE_EDGE_FALLING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530308 writel_relaxed(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700309 if (status & IRQ_TYPE_EDGE_RISING)
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530310 writel_relaxed(mask, &g->set_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100311}
312
Lennert Buytenhek23265442010-11-29 10:27:27 +0100313static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100314{
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100315 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
316 return -EINVAL;
317
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100318 return 0;
319}
320
321static struct irq_chip gpio_irqchip = {
322 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100323 .irq_enable = gpio_irq_enable,
324 .irq_disable = gpio_irq_disable,
325 .irq_set_type = gpio_irq_type,
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100326 .flags = IRQCHIP_SET_TYPE_MASKED,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100327};
328
329static void
330gpio_irq_handler(unsigned irq, struct irq_desc *desc)
331{
Thomas Gleixner74164012011-06-06 11:51:43 +0200332 struct davinci_gpio_regs __iomem *g;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100333 u32 mask = 0xffff;
Ido Yarivf299bb92011-07-12 00:03:11 +0300334 struct davinci_gpio_controller *d;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100335
Ido Yarivf299bb92011-07-12 00:03:11 +0300336 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
337 g = (struct davinci_gpio_regs __iomem *)d->regs;
Thomas Gleixner74164012011-06-06 11:51:43 +0200338
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100339 /* we only care about one bank */
340 if (irq & 1)
341 mask <<= 16;
342
343 /* temporarily mask (level sensitive) parent IRQ */
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200344 chained_irq_enter(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100345 while (1) {
346 u32 status;
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530347 int bit;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100348
349 /* ack any irqs */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530350 status = readl_relaxed(&g->intstat) & mask;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100351 if (!status)
352 break;
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530353 writel_relaxed(status, &g->intstat);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100354
355 /* now demux them to the right lowlevel handler */
Ido Yarivf299bb92011-07-12 00:03:11 +0300356
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100357 while (status) {
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530358 bit = __ffs(status);
359 status &= ~BIT(bit);
360 generic_handle_irq(
361 irq_find_mapping(d->irq_domain,
362 d->chip.base + bit));
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100363 }
364 }
Grygorii Strashko0d978eb2013-11-26 21:40:09 +0200365 chained_irq_exit(irq_desc_get_chip(desc), desc);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100366 /* now it may re-trigger */
367}
368
David Brownell7a360712009-06-25 17:01:31 -0700369static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
370{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400371 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700372
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200373 if (d->irq_domain)
374 return irq_create_mapping(d->irq_domain, d->chip.base + offset);
375 else
376 return -ENXIO;
David Brownell7a360712009-06-25 17:01:31 -0700377}
378
379static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
380{
KV Sujith118150f2013-08-18 10:48:58 +0530381 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700382
Philip Avinash131a10a2013-08-18 10:48:57 +0530383 /*
384 * NOTE: we assume for now that only irqs in the first gpio_chip
David Brownell7a360712009-06-25 17:01:31 -0700385 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
386 */
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530387 if (offset < d->gpio_unbanked)
KV Sujith118150f2013-08-18 10:48:58 +0530388 return d->gpio_irq + offset;
David Brownell7a360712009-06-25 17:01:31 -0700389 else
390 return -ENODEV;
391}
392
Sekhar Noriab2dde92012-03-11 18:16:11 +0530393static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700394{
Sekhar Noriab2dde92012-03-11 18:16:11 +0530395 struct davinci_gpio_controller *d;
396 struct davinci_gpio_regs __iomem *g;
Sekhar Noriab2dde92012-03-11 18:16:11 +0530397 u32 mask;
398
399 d = (struct davinci_gpio_controller *)data->handler_data;
400 g = (struct davinci_gpio_regs __iomem *)d->regs;
KV Sujith118150f2013-08-18 10:48:58 +0530401 mask = __gpio_mask(data->irq - d->gpio_irq);
David Brownell7a360712009-06-25 17:01:31 -0700402
403 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
404 return -EINVAL;
405
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530406 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
David Brownell7a360712009-06-25 17:01:31 -0700407 ? &g->set_falling : &g->clr_falling);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530408 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
David Brownell7a360712009-06-25 17:01:31 -0700409 ? &g->set_rising : &g->clr_rising);
410
411 return 0;
412}
413
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530414static int
415davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
416 irq_hw_number_t hw)
417{
418 struct davinci_gpio_regs __iomem *g = gpio2regs(hw);
419
420 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
421 "davinci_gpio");
422 irq_set_irq_type(irq, IRQ_TYPE_NONE);
423 irq_set_chip_data(irq, (__force void *)g);
424 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
425 set_irq_flags(irq, IRQF_VALID);
426
427 return 0;
428}
429
430static const struct irq_domain_ops davinci_gpio_irq_ops = {
431 .map = davinci_gpio_irq_map,
432 .xlate = irq_domain_xlate_onetwocell,
433};
434
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200435static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
436{
437 static struct irq_chip_type gpio_unbanked;
438
439 gpio_unbanked = *container_of(irq_get_chip(irq),
440 struct irq_chip_type, chip);
441
442 return &gpio_unbanked.chip;
443};
444
445static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
446{
447 static struct irq_chip gpio_unbanked;
448
449 gpio_unbanked = *irq_get_chip(irq);
450 return &gpio_unbanked;
451};
452
453static const struct of_device_id davinci_gpio_ids[];
454
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100455/*
David Brownell474dad52008-12-07 11:46:23 -0800456 * NOTE: for suspend/resume, probably best to make a platform_device with
457 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100458 * calls ... so if no gpios are wakeup events the clock can be disabled,
459 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800460 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100461 */
462
KV Sujith118150f2013-08-18 10:48:58 +0530463static int davinci_gpio_irq_setup(struct platform_device *pdev)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100464{
Alexander Shiyan58c0f5a2014-02-15 17:12:05 +0400465 unsigned gpio, bank;
466 int irq;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100467 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800468 u32 binten = 0;
Mark A. Greera9949552009-04-15 12:40:35 -0700469 unsigned ngpio, bank_irq;
KV Sujith118150f2013-08-18 10:48:58 +0530470 struct device *dev = &pdev->dev;
471 struct resource *res;
472 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
473 struct davinci_gpio_platform_data *pdata = dev->platform_data;
474 struct davinci_gpio_regs __iomem *g;
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200475 struct irq_domain *irq_domain = NULL;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200476 const struct of_device_id *match;
477 struct irq_chip *irq_chip;
478 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
479
480 /*
481 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
482 */
483 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
484 match = of_match_device(of_match_ptr(davinci_gpio_ids),
485 dev);
486 if (match)
487 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
David Brownell474dad52008-12-07 11:46:23 -0800488
KV Sujith118150f2013-08-18 10:48:58 +0530489 ngpio = pdata->ngpio;
490 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
491 if (!res) {
492 dev_err(dev, "Invalid IRQ resource\n");
493 return -EBUSY;
David Brownell474dad52008-12-07 11:46:23 -0800494 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100495
KV Sujith118150f2013-08-18 10:48:58 +0530496 bank_irq = res->start;
497
498 if (!bank_irq) {
499 dev_err(dev, "Invalid IRQ resource\n");
500 return -ENODEV;
501 }
502
503 clk = devm_clk_get(dev, "gpio");
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100504 if (IS_ERR(clk)) {
505 printk(KERN_ERR "Error %ld getting gpio clock?\n",
506 PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800507 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100508 }
Murali Karicherice6b6582012-08-30 14:03:57 -0400509 clk_prepare_enable(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100510
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200511 if (!pdata->gpio_unbanked) {
512 irq = irq_alloc_descs(-1, 0, ngpio, 0);
513 if (irq < 0) {
514 dev_err(dev, "Couldn't allocate IRQ numbers\n");
515 return irq;
516 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530517
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200518 irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0,
519 &davinci_gpio_irq_ops,
520 chips);
521 if (!irq_domain) {
522 dev_err(dev, "Couldn't register an IRQ domain\n");
523 return -ENODEV;
524 }
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530525 }
526
Philip Avinash131a10a2013-08-18 10:48:57 +0530527 /*
528 * Arrange gpio_to_irq() support, handling either direct IRQs or
David Brownell7a360712009-06-25 17:01:31 -0700529 * banked IRQs. Having GPIOs in the first GPIO bank use direct
530 * IRQs, while the others use banked IRQs, would need some setup
531 * tweaks to recognize hardware which can do that.
532 */
533 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
534 chips[bank].chip.to_irq = gpio_to_irq_banked;
Grygorii Strashko6075a8b2013-12-18 12:07:51 +0200535 chips[bank].irq_domain = irq_domain;
David Brownell7a360712009-06-25 17:01:31 -0700536 }
537
538 /*
539 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
540 * controller only handling trigger modes. We currently assume no
541 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
542 */
KV Sujith118150f2013-08-18 10:48:58 +0530543 if (pdata->gpio_unbanked) {
David Brownell7a360712009-06-25 17:01:31 -0700544 /* pass "bank 0" GPIO IRQs to AINTC */
545 chips[0].chip.to_irq = gpio_to_irq_unbanked;
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530546 chips[0].gpio_irq = bank_irq;
547 chips[0].gpio_unbanked = pdata->gpio_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700548 binten = BIT(0);
549
550 /* AINTC handles mask/unmask; GPIO handles triggering */
551 irq = bank_irq;
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200552 irq_chip = gpio_get_irq_chip(irq);
553 irq_chip->name = "GPIO-AINTC";
554 irq_chip->irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700555
556 /* default trigger: both edges */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400557 g = gpio2regs(0);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530558 writel_relaxed(~0, &g->set_falling);
559 writel_relaxed(~0, &g->set_rising);
David Brownell7a360712009-06-25 17:01:31 -0700560
561 /* set the direct IRQs up to use that irqchip */
KV Sujith118150f2013-08-18 10:48:58 +0530562 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200563 irq_set_chip(irq, irq_chip);
Sekhar Noriab2dde92012-03-11 18:16:11 +0530564 irq_set_handler_data(irq, &chips[gpio / 32]);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100565 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
David Brownell7a360712009-06-25 17:01:31 -0700566 }
567
568 goto done;
569 }
570
571 /*
572 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
573 * then chain through our own handler.
574 */
Lad, Prabhakar9211ff32013-11-21 23:45:27 +0530575 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
David Brownell7a360712009-06-25 17:01:31 -0700576 /* disabled by default, enabled only as needed */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400577 g = gpio2regs(gpio);
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530578 writel_relaxed(~0, &g->clr_falling);
579 writel_relaxed(~0, &g->clr_rising);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100580
Ido Yarivf299bb92011-07-12 00:03:11 +0300581 /*
582 * Each chip handles 32 gpios, and each irq bank consists of 16
583 * gpio irqs. Pass the irq bank's corresponding controller to
584 * the chained irq handler.
585 */
Thomas Gleixner20483d02015-07-13 23:22:44 +0200586 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
587 &chips[gpio / 32]);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100588
David Brownell474dad52008-12-07 11:46:23 -0800589 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100590 }
591
David Brownell7a360712009-06-25 17:01:31 -0700592done:
Philip Avinash131a10a2013-08-18 10:48:57 +0530593 /*
594 * BINTEN -- per-bank interrupt enable. genirq would also let these
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100595 * bits be set/cleared dynamically.
596 */
Lad, Prabhakar388291c2013-12-11 23:22:07 +0530597 writel_relaxed(binten, gpio_base + BINTEN);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100598
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100599 return 0;
600}
KV Sujith118150f2013-08-18 10:48:58 +0530601
KV Sujithc7708442013-11-21 23:45:29 +0530602#if IS_ENABLED(CONFIG_OF)
603static const struct of_device_id davinci_gpio_ids[] = {
Grygorii Strashko0c6feb02014-02-13 17:58:45 +0200604 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
605 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
KV Sujithc7708442013-11-21 23:45:29 +0530606 { /* sentinel */ },
607};
608MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
609#endif
610
KV Sujith118150f2013-08-18 10:48:58 +0530611static struct platform_driver davinci_gpio_driver = {
612 .probe = davinci_gpio_probe,
613 .driver = {
KV Sujithc7708442013-11-21 23:45:29 +0530614 .name = "davinci_gpio",
KV Sujithc7708442013-11-21 23:45:29 +0530615 .of_match_table = of_match_ptr(davinci_gpio_ids),
KV Sujith118150f2013-08-18 10:48:58 +0530616 },
617};
618
619/**
620 * GPIO driver registration needs to be done before machine_init functions
621 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
622 */
623static int __init davinci_gpio_drv_reg(void)
624{
625 return platform_driver_register(&davinci_gpio_driver);
626}
627postcore_initcall(davinci_gpio_drv_reg);