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Hong Xucce783c2012-04-17 14:26:29 +08001/*
2 * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
3 *
4 * Copyright (C) 2012 Atmel,
5 * 2012 Hong Xu <hong.xu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9N12 SoC";
14 compatible = "atmel,at91sam9n12";
15 interrupt-parent = <&aic>;
16
17 aliases {
18 serial0 = &dbgu;
19 serial1 = &usart0;
20 serial2 = &usart1;
21 serial3 = &usart2;
22 serial4 = &usart3;
23 gpio0 = &pioA;
24 gpio1 = &pioB;
25 gpio2 = &pioC;
26 gpio3 = &pioD;
27 tcb0 = &tcb0;
28 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020029 i2c0 = &i2c0;
30 i2c1 = &i2c1;
Bo Shen544ae6b2013-01-11 15:08:30 +010031 ssc0 = &ssc0;
Hong Xucce783c2012-04-17 14:26:29 +080032 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm926ejs";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x10000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020056 #interrupt-cells = <3>;
Hong Xucce783c2012-04-17 14:26:29 +080057 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
60 };
61
62 ramc0: ramc@ffffe800 {
63 compatible = "atmel,at91sam9g45-ddramc";
64 reg = <0xffffe800 0x200>;
65 };
66
67 pmc: pmc@fffffc00 {
68 compatible = "atmel,at91rm9200-pmc";
69 reg = <0xfffffc00 0x100>;
70 };
71
72 rstc@fffffe00 {
73 compatible = "atmel,at91sam9g45-rstc";
74 reg = <0xfffffe00 0x10>;
75 };
76
77 pit: timer@fffffe30 {
78 compatible = "atmel,at91sam9260-pit";
79 reg = <0xfffffe30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020080 interrupts = <1 4 7>;
Hong Xucce783c2012-04-17 14:26:29 +080081 };
82
83 shdwc@fffffe10 {
84 compatible = "atmel,at91sam9x5-shdwc";
85 reg = <0xfffffe10 0x10>;
86 };
87
Ludovic Desroches98731372012-11-19 12:23:36 +010088 mmc0: mmc@f0008000 {
89 compatible = "atmel,hsmci";
90 reg = <0xf0008000 0x600>;
91 interrupts = <12 4 0>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 status = "disabled";
95 };
96
Hong Xucce783c2012-04-17 14:26:29 +080097 tcb0: timer@f8008000 {
98 compatible = "atmel,at91sam9x5-tcb";
99 reg = <0xf8008000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200100 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800101 };
102
103 tcb1: timer@f800c000 {
104 compatible = "atmel,at91sam9x5-tcb";
105 reg = <0xf800c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200106 interrupts = <17 4 0>;
Hong Xucce783c2012-04-17 14:26:29 +0800107 };
108
109 dma: dma-controller@ffffec00 {
110 compatible = "atmel,at91sam9g45-dma";
111 reg = <0xffffec00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200112 interrupts = <20 4 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200113 #dma-cells = <2>;
Hong Xucce783c2012-04-17 14:26:29 +0800114 };
115
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800116 pinctrl@fffff400 {
117 #address-cells = <1>;
118 #size-cells = <1>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800119 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800120 ranges = <0xfffff400 0xfffff400 0x800>;
Hong Xucce783c2012-04-17 14:26:29 +0800121
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800122 atmel,mux-mask = <
123 /* A B C */
124 0xffffffff 0xffe07983 0x00000000 /* pioA */
125 0x00040000 0x00047e0f 0x00000000 /* pioB */
126 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
127 0x003fffff 0x003f8000 0x00000000 /* pioD */
128 >;
129
130 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800131 dbgu {
132 pinctrl_dbgu: dbgu-0 {
133 atmel,pins =
134 <0 9 0x1 0x0 /* PA9 periph A */
135 0 10 0x1 0x1>; /* PA10 periph with pullup */
136 };
137 };
138
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800139 usart0 {
140 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800141 atmel,pins =
142 <0 1 0x1 0x1 /* PA1 periph A with pullup */
143 0 0 0x1 0x0>; /* PA0 periph A */
144 };
145
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800146 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800147 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800148 <0 2 0x1 0x0>; /* PA2 periph A */
149 };
150
151 pinctrl_usart0_cts: usart0_cts-0 {
152 atmel,pins =
153 <0 3 0x1 0x0>; /* PA3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800154 };
155 };
156
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800157 usart1 {
158 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800159 atmel,pins =
160 <0 6 0x1 0x1 /* PA6 periph A with pullup */
161 0 5 0x1 0x0>; /* PA5 periph A */
162 };
163 };
164
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800165 usart2 {
166 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800167 atmel,pins =
168 <0 8 0x1 0x1 /* PA8 periph A with pullup */
169 0 7 0x1 0x0>; /* PA7 periph A */
170 };
171
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800172 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800173 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800174 <1 0 0x2 0x0>; /* PB0 periph B */
175 };
176
177 pinctrl_usart2_cts: usart2_cts-0 {
178 atmel,pins =
179 <1 1 0x2 0x0>; /* PB1 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800180 };
181 };
182
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800183 usart3 {
184 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800185 atmel,pins =
186 <2 23 0x2 0x1 /* PC23 periph B with pullup */
187 2 22 0x2 0x0>; /* PC22 periph B */
188 };
189
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800190 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800191 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800192 <2 24 0x2 0x0>; /* PC24 periph B */
193 };
194
195 pinctrl_usart3_cts: usart3_cts-0 {
196 atmel,pins =
197 <2 25 0x2 0x0>; /* PC25 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800198 };
199 };
200
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800201 uart0 {
202 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800203 atmel,pins =
204 <2 9 0x3 0x1 /* PC9 periph C with pullup */
205 2 8 0x3 0x0>; /* PC8 periph C */
206 };
207 };
208
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800209 uart1 {
210 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800211 atmel,pins =
212 <2 16 0x3 0x1 /* PC17 periph C with pullup */
213 2 17 0x3 0x0>; /* PC16 periph C */
214 };
215 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800216
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800217 nand {
218 pinctrl_nand: nand-0 {
219 atmel,pins =
220 <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
221 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
222 };
223 };
224
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800225 mmc0 {
226 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
227 atmel,pins =
228 <0 17 0x1 0x0 /* PA17 periph A */
229 0 16 0x1 0x1 /* PA16 periph A with pullup */
230 0 15 0x1 0x1>; /* PA15 periph A with pullup */
231 };
232
233 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
234 atmel,pins =
235 <0 18 0x1 0x1 /* PA18 periph A with pullup */
236 0 19 0x1 0x1 /* PA19 periph A with pullup */
237 0 20 0x1 0x1>; /* PA20 periph A with pullup */
238 };
239
240 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
241 atmel,pins =
242 <0 11 0x2 0x1 /* PA11 periph B with pullup */
243 0 12 0x2 0x1 /* PA12 periph B with pullup */
244 0 13 0x2 0x1 /* PA13 periph B with pullup */
245 0 14 0x2 0x1>; /* PA14 periph B with pullup */
246 };
247 };
248
Bo Shen544ae6b2013-01-11 15:08:30 +0100249 ssc0 {
250 pinctrl_ssc0_tx: ssc0_tx-0 {
251 atmel,pins =
252 <0 24 0x2 0x0 /* PA24 periph B */
253 0 25 0x2 0x0 /* PA25 periph B */
254 0 26 0x2 0x0>; /* PA26 periph B */
255 };
256
257 pinctrl_ssc0_rx: ssc0_rx-0 {
258 atmel,pins =
259 <0 27 0x2 0x0 /* PA27 periph B */
260 0 28 0x2 0x0 /* PA28 periph B */
261 0 29 0x2 0x0>; /* PA29 periph B */
262 };
263 };
264
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800265 pioA: gpio@fffff400 {
266 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
267 reg = <0xfffff400 0x200>;
268 interrupts = <2 4 1>;
269 #gpio-cells = <2>;
270 gpio-controller;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 };
Hong Xucce783c2012-04-17 14:26:29 +0800274
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800275 pioB: gpio@fffff600 {
276 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
277 reg = <0xfffff600 0x200>;
278 interrupts = <2 4 1>;
279 #gpio-cells = <2>;
280 gpio-controller;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
Hong Xucce783c2012-04-17 14:26:29 +0800284
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800285 pioC: gpio@fffff800 {
286 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
287 reg = <0xfffff800 0x200>;
288 interrupts = <3 4 1>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 };
294
295 pioD: gpio@fffffa00 {
296 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
297 reg = <0xfffffa00 0x200>;
298 interrupts = <3 4 1>;
299 #gpio-cells = <2>;
300 gpio-controller;
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 };
Hong Xucce783c2012-04-17 14:26:29 +0800304 };
305
306 dbgu: serial@fffff200 {
307 compatible = "atmel,at91sam9260-usart";
308 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200309 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_dbgu>;
Hong Xucce783c2012-04-17 14:26:29 +0800312 status = "disabled";
313 };
314
Bo Shen544ae6b2013-01-11 15:08:30 +0100315 ssc0: ssc@f0010000 {
316 compatible = "atmel,at91sam9g45-ssc";
317 reg = <0xf0010000 0x4000>;
318 interrupts = <28 4 5>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
321 status = "disabled";
322 };
323
Hong Xucce783c2012-04-17 14:26:29 +0800324 usart0: serial@f801c000 {
325 compatible = "atmel,at91sam9260-usart";
326 reg = <0xf801c000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200327 interrupts = <5 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800328 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800329 pinctrl-0 = <&pinctrl_usart0>;
Hong Xucce783c2012-04-17 14:26:29 +0800330 status = "disabled";
331 };
332
333 usart1: serial@f8020000 {
334 compatible = "atmel,at91sam9260-usart";
335 reg = <0xf8020000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200336 interrupts = <6 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800337 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800338 pinctrl-0 = <&pinctrl_usart1>;
Hong Xucce783c2012-04-17 14:26:29 +0800339 status = "disabled";
340 };
341
342 usart2: serial@f8024000 {
343 compatible = "atmel,at91sam9260-usart";
344 reg = <0xf8024000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200345 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800346 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800347 pinctrl-0 = <&pinctrl_usart2>;
Hong Xucce783c2012-04-17 14:26:29 +0800348 status = "disabled";
349 };
350
351 usart3: serial@f8028000 {
352 compatible = "atmel,at91sam9260-usart";
353 reg = <0xf8028000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200354 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800355 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800356 pinctrl-0 = <&pinctrl_usart3>;
Hong Xucce783c2012-04-17 14:26:29 +0800357 status = "disabled";
358 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200359
360 i2c0: i2c@f8010000 {
361 compatible = "atmel,at91sam9x5-i2c";
362 reg = <0xf8010000 0x100>;
363 interrupts = <9 4 6>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366 status = "disabled";
367 };
368
369 i2c1: i2c@f8014000 {
370 compatible = "atmel,at91sam9x5-i2c";
371 reg = <0xf8014000 0x100>;
372 interrupts = <10 4 6>;
373 #address-cells = <1>;
374 #size-cells = <0>;
375 status = "disabled";
376 };
Hong Xucce783c2012-04-17 14:26:29 +0800377 };
378
379 nand0: nand@40000000 {
380 compatible = "atmel,at91rm9200-nand";
381 #address-cells = <1>;
382 #size-cells = <1>;
383 reg = < 0x40000000 0x10000000
384 0xffffe000 0x00000600
385 0xffffe600 0x00000200
Josh Wuc18c6b22013-01-23 20:47:10 +0800386 0x00108000 0x00018000
Hong Xucce783c2012-04-17 14:26:29 +0800387 >;
Josh Wuc18c6b22013-01-23 20:47:10 +0800388 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
Hong Xucce783c2012-04-17 14:26:29 +0800389 atmel,nand-addr-offset = <21>;
390 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_nand>;
Hong Xucce783c2012-04-17 14:26:29 +0800393 gpios = <&pioD 5 0
394 &pioD 4 0
395 0
396 >;
397 status = "disabled";
398 };
399
400 usb0: ohci@00500000 {
401 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
402 reg = <0x00500000 0x00100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200403 interrupts = <22 4 2>;
Hong Xucce783c2012-04-17 14:26:29 +0800404 status = "disabled";
405 };
406 };
407
408 i2c@0 {
409 compatible = "i2c-gpio";
410 gpios = <&pioA 30 0 /* sda */
411 &pioA 31 0 /* scl */
412 >;
413 i2c-gpio,sda-open-drain;
414 i2c-gpio,scl-open-drain;
415 i2c-gpio,delay-us = <2>; /* ~100 kHz */
416 #address-cells = <1>;
417 #size-cells = <0>;
418 status = "disabled";
419 };
420};