H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_MSR_INDEX_H |
| 2 | #define _ASM_X86_MSR_INDEX_H |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 3 | |
| 4 | /* CPU model specific register (MSR) numbers */ |
| 5 | |
| 6 | /* x86-64 specific MSRs */ |
| 7 | #define MSR_EFER 0xc0000080 /* extended feature register */ |
| 8 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ |
| 9 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ |
| 10 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ |
| 11 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ |
| 12 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ |
| 13 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ |
| 14 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ |
Sheng Yang | 5df9740 | 2009-12-16 13:48:04 +0800 | [diff] [blame] | 15 | #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 16 | |
| 17 | /* EFER bits: */ |
| 18 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ |
| 19 | #define _EFER_LME 8 /* Long mode enable */ |
| 20 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
| 21 | #define _EFER_NX 11 /* No execute enable */ |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 22 | #define _EFER_SVME 12 /* Enable virtualization */ |
Joerg Roedel | eec4b14 | 2010-05-05 16:04:44 +0200 | [diff] [blame] | 23 | #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ |
Alexander Graf | d206269 | 2009-02-02 16:23:50 +0100 | [diff] [blame] | 24 | #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 25 | |
| 26 | #define EFER_SCE (1<<_EFER_SCE) |
| 27 | #define EFER_LME (1<<_EFER_LME) |
| 28 | #define EFER_LMA (1<<_EFER_LMA) |
| 29 | #define EFER_NX (1<<_EFER_NX) |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 30 | #define EFER_SVME (1<<_EFER_SVME) |
Joerg Roedel | eec4b14 | 2010-05-05 16:04:44 +0200 | [diff] [blame] | 31 | #define EFER_LMSLE (1<<_EFER_LMSLE) |
Alexander Graf | d206269 | 2009-02-02 16:23:50 +0100 | [diff] [blame] | 32 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 33 | |
| 34 | /* Intel MSRs. Some also available on other CPUs */ |
| 35 | #define MSR_IA32_PERFCTR0 0x000000c1 |
| 36 | #define MSR_IA32_PERFCTR1 0x000000c2 |
| 37 | #define MSR_FSB_FREQ 0x000000cd |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 38 | #define MSR_NHM_PLATFORM_INFO 0x000000ce |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 39 | |
Len Brown | 14796fc | 2011-01-18 20:48:27 -0500 | [diff] [blame] | 40 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
| 41 | #define NHM_C3_AUTO_DEMOTE (1UL << 25) |
| 42 | #define NHM_C1_AUTO_DEMOTE (1UL << 26) |
Len Brown | bfb53cc | 2011-02-16 01:32:48 -0500 | [diff] [blame] | 43 | #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 44 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) |
| 45 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) |
Len Brown | 14796fc | 2011-01-18 20:48:27 -0500 | [diff] [blame] | 46 | |
Konrad Rzeszutek Wilk | 05e99c8cf | 2013-03-20 14:21:10 +0000 | [diff] [blame] | 47 | #define MSR_PLATFORM_INFO 0x000000ce |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 48 | #define MSR_MTRRcap 0x000000fe |
| 49 | #define MSR_IA32_BBL_CR_CTL 0x00000119 |
john cooper | 91c9c3e | 2011-01-21 00:21:00 -0500 | [diff] [blame] | 50 | #define MSR_IA32_BBL_CR_CTL3 0x0000011e |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 51 | |
| 52 | #define MSR_IA32_SYSENTER_CS 0x00000174 |
| 53 | #define MSR_IA32_SYSENTER_ESP 0x00000175 |
| 54 | #define MSR_IA32_SYSENTER_EIP 0x00000176 |
| 55 | |
| 56 | #define MSR_IA32_MCG_CAP 0x00000179 |
| 57 | #define MSR_IA32_MCG_STATUS 0x0000017a |
| 58 | #define MSR_IA32_MCG_CTL 0x0000017b |
| 59 | |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 60 | #define MSR_OFFCORE_RSP_0 0x000001a6 |
| 61 | #define MSR_OFFCORE_RSP_1 0x000001a7 |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 62 | #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad |
| 63 | #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae |
Len Brown | c4d3066 | 2015-04-10 00:22:56 -0400 | [diff] [blame] | 64 | #define MSR_TURBO_RATIO_LIMIT 0x000001ad |
| 65 | #define MSR_TURBO_RATIO_LIMIT1 0x000001ae |
| 66 | #define MSR_TURBO_RATIO_LIMIT2 0x000001af |
Andi Kleen | a7e3ed1 | 2011-03-03 10:34:47 +0800 | [diff] [blame] | 67 | |
Stephane Eranian | 225ce53 | 2012-02-09 23:20:52 +0100 | [diff] [blame] | 68 | #define MSR_LBR_SELECT 0x000001c8 |
| 69 | #define MSR_LBR_TOS 0x000001c9 |
| 70 | #define MSR_LBR_NHM_FROM 0x00000680 |
| 71 | #define MSR_LBR_NHM_TO 0x000006c0 |
| 72 | #define MSR_LBR_CORE_FROM 0x00000040 |
| 73 | #define MSR_LBR_CORE_TO 0x00000060 |
| 74 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 75 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 |
| 76 | #define MSR_IA32_DS_AREA 0x00000600 |
| 77 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 78 | #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 79 | |
Alexander Shishkin | 52ca9ce | 2015-01-30 12:39:52 +0200 | [diff] [blame] | 80 | #define MSR_IA32_RTIT_CTL 0x00000570 |
| 81 | #define RTIT_CTL_TRACEEN BIT(0) |
| 82 | #define RTIT_CTL_OS BIT(2) |
| 83 | #define RTIT_CTL_USR BIT(3) |
| 84 | #define RTIT_CTL_CR3EN BIT(7) |
| 85 | #define RTIT_CTL_TOPA BIT(8) |
| 86 | #define RTIT_CTL_TSC_EN BIT(10) |
| 87 | #define RTIT_CTL_DISRETC BIT(11) |
| 88 | #define RTIT_CTL_BRANCH_EN BIT(13) |
| 89 | #define MSR_IA32_RTIT_STATUS 0x00000571 |
| 90 | #define RTIT_STATUS_CONTEXTEN BIT(1) |
| 91 | #define RTIT_STATUS_TRIGGEREN BIT(2) |
| 92 | #define RTIT_STATUS_ERROR BIT(4) |
| 93 | #define RTIT_STATUS_STOPPED BIT(5) |
| 94 | #define MSR_IA32_RTIT_CR3_MATCH 0x00000572 |
| 95 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 |
| 96 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 |
| 97 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 98 | #define MSR_MTRRfix64K_00000 0x00000250 |
| 99 | #define MSR_MTRRfix16K_80000 0x00000258 |
| 100 | #define MSR_MTRRfix16K_A0000 0x00000259 |
| 101 | #define MSR_MTRRfix4K_C0000 0x00000268 |
| 102 | #define MSR_MTRRfix4K_C8000 0x00000269 |
| 103 | #define MSR_MTRRfix4K_D0000 0x0000026a |
| 104 | #define MSR_MTRRfix4K_D8000 0x0000026b |
| 105 | #define MSR_MTRRfix4K_E0000 0x0000026c |
| 106 | #define MSR_MTRRfix4K_E8000 0x0000026d |
| 107 | #define MSR_MTRRfix4K_F0000 0x0000026e |
| 108 | #define MSR_MTRRfix4K_F8000 0x0000026f |
| 109 | #define MSR_MTRRdefType 0x000002ff |
| 110 | |
venkatesh.pallipadi@intel.com | 2e5d9c8 | 2008-03-18 17:00:14 -0700 | [diff] [blame] | 111 | #define MSR_IA32_CR_PAT 0x00000277 |
| 112 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 113 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
| 114 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
| 115 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
| 116 | #define MSR_IA32_LASTINTFROMIP 0x000001dd |
| 117 | #define MSR_IA32_LASTINTTOIP 0x000001de |
| 118 | |
Roland McGrath | d2499d8 | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 119 | /* DEBUGCTLMSR bits (others vary by model): */ |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 120 | #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ |
| 121 | #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ |
| 122 | #define DEBUGCTLMSR_TR (1UL << 6) |
| 123 | #define DEBUGCTLMSR_BTS (1UL << 7) |
| 124 | #define DEBUGCTLMSR_BTINT (1UL << 8) |
| 125 | #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) |
| 126 | #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) |
| 127 | #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) |
Roland McGrath | d2499d8 | 2008-01-30 13:30:54 +0100 | [diff] [blame] | 128 | |
Len Brown | 6792041 | 2013-01-31 15:22:15 -0500 | [diff] [blame] | 129 | #define MSR_IA32_POWER_CTL 0x000001fc |
| 130 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 131 | #define MSR_IA32_MC0_CTL 0x00000400 |
| 132 | #define MSR_IA32_MC0_STATUS 0x00000401 |
| 133 | #define MSR_IA32_MC0_ADDR 0x00000402 |
| 134 | #define MSR_IA32_MC0_MISC 0x00000403 |
| 135 | |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 136 | /* C-state Residency Counters */ |
| 137 | #define MSR_PKG_C3_RESIDENCY 0x000003f8 |
| 138 | #define MSR_PKG_C6_RESIDENCY 0x000003f9 |
| 139 | #define MSR_PKG_C7_RESIDENCY 0x000003fa |
| 140 | #define MSR_CORE_C3_RESIDENCY 0x000003fc |
| 141 | #define MSR_CORE_C6_RESIDENCY 0x000003fd |
| 142 | #define MSR_CORE_C7_RESIDENCY 0x000003fe |
Dasaratharaman Chandramouli | fb5d432 | 2015-05-20 09:49:34 -0700 | [diff] [blame] | 143 | #define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 144 | #define MSR_PKG_C2_RESIDENCY 0x0000060d |
Kristen Carlson Accardi | ca58710 | 2012-11-21 05:22:43 -0800 | [diff] [blame] | 145 | #define MSR_PKG_C8_RESIDENCY 0x00000630 |
| 146 | #define MSR_PKG_C9_RESIDENCY 0x00000631 |
| 147 | #define MSR_PKG_C10_RESIDENCY 0x00000632 |
Linus Torvalds | 6842d98 | 2012-12-18 12:34:29 -0800 | [diff] [blame] | 148 | |
| 149 | /* Run Time Average Power Limiting (RAPL) Interface */ |
| 150 | |
| 151 | #define MSR_RAPL_POWER_UNIT 0x00000606 |
| 152 | |
| 153 | #define MSR_PKG_POWER_LIMIT 0x00000610 |
| 154 | #define MSR_PKG_ENERGY_STATUS 0x00000611 |
| 155 | #define MSR_PKG_PERF_STATUS 0x00000613 |
| 156 | #define MSR_PKG_POWER_INFO 0x00000614 |
| 157 | |
| 158 | #define MSR_DRAM_POWER_LIMIT 0x00000618 |
| 159 | #define MSR_DRAM_ENERGY_STATUS 0x00000619 |
| 160 | #define MSR_DRAM_PERF_STATUS 0x0000061b |
| 161 | #define MSR_DRAM_POWER_INFO 0x0000061c |
| 162 | |
| 163 | #define MSR_PP0_POWER_LIMIT 0x00000638 |
| 164 | #define MSR_PP0_ENERGY_STATUS 0x00000639 |
| 165 | #define MSR_PP0_POLICY 0x0000063a |
| 166 | #define MSR_PP0_PERF_STATUS 0x0000063b |
| 167 | |
| 168 | #define MSR_PP1_POWER_LIMIT 0x00000640 |
| 169 | #define MSR_PP1_ENERGY_STATUS 0x00000641 |
| 170 | #define MSR_PP1_POLICY 0x00000642 |
| 171 | |
Len Brown | 0b2bb69 | 2015-03-26 00:50:30 -0400 | [diff] [blame] | 172 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 |
| 173 | #define MSR_PKG_ANY_CORE_C0_RES 0x00000659 |
| 174 | #define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A |
| 175 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B |
| 176 | |
Len Brown | 144b44b | 2013-11-09 00:30:16 -0500 | [diff] [blame] | 177 | #define MSR_CORE_C1_RES 0x00000660 |
| 178 | |
Len Brown | 8c058d53 | 2014-07-31 15:21:24 -0400 | [diff] [blame] | 179 | #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 |
| 180 | #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 |
| 181 | |
Len Brown | 3a9a941 | 2014-08-15 02:39:52 -0400 | [diff] [blame] | 182 | #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 183 | #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 |
| 184 | #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 |
| 185 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 186 | /* Hardware P state interface */ |
| 187 | #define MSR_PPERF 0x0000064e |
| 188 | #define MSR_PERF_LIMIT_REASONS 0x0000064f |
| 189 | #define MSR_PM_ENABLE 0x00000770 |
| 190 | #define MSR_HWP_CAPABILITIES 0x00000771 |
| 191 | #define MSR_HWP_REQUEST_PKG 0x00000772 |
| 192 | #define MSR_HWP_INTERRUPT 0x00000773 |
| 193 | #define MSR_HWP_REQUEST 0x00000774 |
| 194 | #define MSR_HWP_STATUS 0x00000777 |
| 195 | |
| 196 | /* CPUID.6.EAX */ |
| 197 | #define HWP_BASE_BIT (1<<7) |
| 198 | #define HWP_NOTIFICATIONS_BIT (1<<8) |
| 199 | #define HWP_ACTIVITY_WINDOW_BIT (1<<9) |
| 200 | #define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) |
| 201 | #define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) |
| 202 | |
| 203 | /* IA32_HWP_CAPABILITIES */ |
| 204 | #define HWP_HIGHEST_PERF(x) (x & 0xff) |
| 205 | #define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) |
| 206 | #define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) |
| 207 | #define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) |
| 208 | |
| 209 | /* IA32_HWP_REQUEST */ |
| 210 | #define HWP_MIN_PERF(x) (x & 0xff) |
| 211 | #define HWP_MAX_PERF(x) ((x & 0xff) << 8) |
| 212 | #define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) |
| 213 | #define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) |
| 214 | #define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) |
| 215 | #define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) |
| 216 | |
| 217 | /* IA32_HWP_STATUS */ |
| 218 | #define HWP_GUARANTEED_CHANGE(x) (x & 0x1) |
| 219 | #define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) |
| 220 | |
| 221 | /* IA32_HWP_INTERRUPT */ |
| 222 | #define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) |
| 223 | #define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) |
| 224 | |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 225 | #define MSR_AMD64_MC0_MASK 0xc0010044 |
| 226 | |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 227 | #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) |
| 228 | #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) |
| 229 | #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) |
| 230 | #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) |
| 231 | |
Joerg Roedel | 5bbc097 | 2011-04-15 14:47:40 +0200 | [diff] [blame] | 232 | #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) |
| 233 | |
Andi Kleen | 03195c6 | 2009-02-12 13:49:35 +0100 | [diff] [blame] | 234 | /* These are consecutive and not in the normal 4er MCE bank block */ |
| 235 | #define MSR_IA32_MC0_CTL2 0x00000280 |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 236 | #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) |
| 237 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 238 | #define MSR_P6_PERFCTR0 0x000000c1 |
| 239 | #define MSR_P6_PERFCTR1 0x000000c2 |
| 240 | #define MSR_P6_EVNTSEL0 0x00000186 |
| 241 | #define MSR_P6_EVNTSEL1 0x00000187 |
| 242 | |
Vince Weaver | e717bf4 | 2012-09-26 14:12:52 -0400 | [diff] [blame] | 243 | #define MSR_KNC_PERFCTR0 0x00000020 |
| 244 | #define MSR_KNC_PERFCTR1 0x00000021 |
| 245 | #define MSR_KNC_EVNTSEL0 0x00000028 |
| 246 | #define MSR_KNC_EVNTSEL1 0x00000029 |
| 247 | |
Andi Kleen | 069e0c3 | 2013-06-25 08:12:33 -0700 | [diff] [blame] | 248 | /* Alternative perfctr range with full access. */ |
| 249 | #define MSR_IA32_PMC0 0x000004c1 |
| 250 | |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 251 | /* AMD64 MSRs. Not complete. See the architecture manual for a more |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 252 | complete list. */ |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 253 | |
Andreas Herrmann | 29d0887 | 2008-12-16 19:16:34 +0100 | [diff] [blame] | 254 | #define MSR_AMD64_PATCH_LEVEL 0x0000008b |
Joerg Roedel | fbc0db7 | 2011-03-25 09:44:46 +0100 | [diff] [blame] | 255 | #define MSR_AMD64_TSC_RATIO 0xc0000104 |
stephane eranian | 12db648 | 2008-03-07 13:05:39 -0800 | [diff] [blame] | 256 | #define MSR_AMD64_NB_CFG 0xc001001f |
Andreas Herrmann | 29d0887 | 2008-12-16 19:16:34 +0100 | [diff] [blame] | 257 | #define MSR_AMD64_PATCH_LOADER 0xc0010020 |
Andreas Herrmann | 035a02c | 2010-03-19 12:09:22 +0100 | [diff] [blame] | 258 | #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 |
| 259 | #define MSR_AMD64_OSVW_STATUS 0xc0010141 |
Borislav Petkov | 3b56496 | 2014-01-15 00:07:11 +0100 | [diff] [blame] | 260 | #define MSR_AMD64_LS_CFG 0xc0011020 |
Joerg Roedel | 67ec660 | 2010-05-17 14:43:35 +0200 | [diff] [blame] | 261 | #define MSR_AMD64_DC_CFG 0xc0011022 |
Boris Ostrovsky | f0322bd | 2013-01-29 16:32:49 -0500 | [diff] [blame] | 262 | #define MSR_AMD64_BU_CFG2 0xc001102a |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 263 | #define MSR_AMD64_IBSFETCHCTL 0xc0011030 |
| 264 | #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 |
| 265 | #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 266 | #define MSR_AMD64_IBSFETCH_REG_COUNT 3 |
| 267 | #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 268 | #define MSR_AMD64_IBSOPCTL 0xc0011033 |
| 269 | #define MSR_AMD64_IBSOPRIP 0xc0011034 |
| 270 | #define MSR_AMD64_IBSOPDATA 0xc0011035 |
| 271 | #define MSR_AMD64_IBSOPDATA2 0xc0011036 |
| 272 | #define MSR_AMD64_IBSOPDATA3 0xc0011037 |
| 273 | #define MSR_AMD64_IBSDCLINAD 0xc0011038 |
| 274 | #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 275 | #define MSR_AMD64_IBSOP_REG_COUNT 7 |
| 276 | #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 277 | #define MSR_AMD64_IBSCTL 0xc001103a |
Robert Richter | 25da695 | 2010-09-21 15:49:31 +0200 | [diff] [blame] | 278 | #define MSR_AMD64_IBSBRTARGET 0xc001103b |
Aravind Gopalakrishnan | 904cb36 | 2014-11-10 14:24:26 -0600 | [diff] [blame] | 279 | #define MSR_AMD64_IBSOPDATA4 0xc001103d |
Robert Richter | b7074f1 | 2011-12-15 17:56:37 +0100 | [diff] [blame] | 280 | #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 281 | |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 282 | /* Fam 16h MSRs */ |
| 283 | #define MSR_F16H_L2I_PERF_CTL 0xc0010230 |
| 284 | #define MSR_F16H_L2I_PERF_CTR 0xc0010231 |
Jacob Shin | d6d55f0 | 2014-05-29 17:26:50 +0200 | [diff] [blame] | 285 | #define MSR_F16H_DR1_ADDR_MASK 0xc0011019 |
| 286 | #define MSR_F16H_DR2_ADDR_MASK 0xc001101a |
| 287 | #define MSR_F16H_DR3_ADDR_MASK 0xc001101b |
| 288 | #define MSR_F16H_DR0_ADDR_MASK 0xc0011027 |
Jacob Shin | c43ca50 | 2013-04-19 16:34:28 -0500 | [diff] [blame] | 289 | |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 290 | /* Fam 15h MSRs */ |
| 291 | #define MSR_F15H_PERF_CTL 0xc0010200 |
| 292 | #define MSR_F15H_PERF_CTR 0xc0010201 |
Jacob Shin | e259514 | 2013-02-06 11:26:29 -0600 | [diff] [blame] | 293 | #define MSR_F15H_NB_PERF_CTL 0xc0010240 |
| 294 | #define MSR_F15H_NB_PERF_CTR 0xc0010241 |
Robert Richter | da169f5 | 2010-09-24 15:54:43 +0200 | [diff] [blame] | 295 | |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 296 | /* Fam 10h MSRs */ |
| 297 | #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 |
| 298 | #define FAM10H_MMIO_CONF_ENABLE (1<<0) |
| 299 | #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf |
| 300 | #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 |
Jan Beulich | 37db6c8 | 2010-11-16 08:25:08 +0000 | [diff] [blame] | 301 | #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 302 | #define FAM10H_MMIO_CONF_BASE_SHIFT 20 |
Andreas Herrmann | 9d260eb | 2009-12-16 15:43:55 +0100 | [diff] [blame] | 303 | #define MSR_FAM10H_NODE_ID 0xc001100c |
Yinghai Lu | 2274c33 | 2008-01-30 13:33:18 +0100 | [diff] [blame] | 304 | |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 305 | /* K8 MSRs */ |
| 306 | #define MSR_K8_TOP_MEM1 0xc001001a |
| 307 | #define MSR_K8_TOP_MEM2 0xc001001d |
| 308 | #define MSR_K8_SYSCFG 0xc0010010 |
Thomas Gleixner | aa83f3f | 2008-06-09 17:11:13 +0200 | [diff] [blame] | 309 | #define MSR_K8_INT_PENDING_MSG 0xc0010055 |
| 310 | /* C1E active bits in int pending message */ |
| 311 | #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 |
Andi Kleen | 8346ea1 | 2008-03-12 03:53:32 +0100 | [diff] [blame] | 312 | #define MSR_K8_TSEG_ADDR 0xc0010112 |
Stephane Eranian | 4f8a6b1 | 2007-10-19 20:35:03 +0200 | [diff] [blame] | 313 | #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ |
| 314 | #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ |
| 315 | #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ |
| 316 | |
| 317 | /* K7 MSRs */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 318 | #define MSR_K7_EVNTSEL0 0xc0010000 |
| 319 | #define MSR_K7_PERFCTR0 0xc0010004 |
| 320 | #define MSR_K7_EVNTSEL1 0xc0010001 |
| 321 | #define MSR_K7_PERFCTR1 0xc0010005 |
| 322 | #define MSR_K7_EVNTSEL2 0xc0010002 |
| 323 | #define MSR_K7_PERFCTR2 0xc0010006 |
| 324 | #define MSR_K7_EVNTSEL3 0xc0010003 |
| 325 | #define MSR_K7_PERFCTR3 0xc0010007 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 326 | #define MSR_K7_CLK_CTL 0xc001001b |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 327 | #define MSR_K7_HWCR 0xc0010015 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 328 | #define MSR_K7_FID_VID_CTL 0xc0010041 |
| 329 | #define MSR_K7_FID_VID_STATUS 0xc0010042 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 330 | |
| 331 | /* K6 MSRs */ |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 332 | #define MSR_K6_WHCR 0xc0000082 |
| 333 | #define MSR_K6_UWCCR 0xc0000085 |
| 334 | #define MSR_K6_EPMR 0xc0000086 |
| 335 | #define MSR_K6_PSOR 0xc0000087 |
| 336 | #define MSR_K6_PFIR 0xc0000088 |
| 337 | |
| 338 | /* Centaur-Hauls/IDT defined MSRs. */ |
| 339 | #define MSR_IDT_FCR1 0x00000107 |
| 340 | #define MSR_IDT_FCR2 0x00000108 |
| 341 | #define MSR_IDT_FCR3 0x00000109 |
| 342 | #define MSR_IDT_FCR4 0x0000010a |
| 343 | |
| 344 | #define MSR_IDT_MCR0 0x00000110 |
| 345 | #define MSR_IDT_MCR1 0x00000111 |
| 346 | #define MSR_IDT_MCR2 0x00000112 |
| 347 | #define MSR_IDT_MCR3 0x00000113 |
| 348 | #define MSR_IDT_MCR4 0x00000114 |
| 349 | #define MSR_IDT_MCR5 0x00000115 |
| 350 | #define MSR_IDT_MCR6 0x00000116 |
| 351 | #define MSR_IDT_MCR7 0x00000117 |
| 352 | #define MSR_IDT_MCR_CTRL 0x00000120 |
| 353 | |
| 354 | /* VIA Cyrix defined MSRs*/ |
| 355 | #define MSR_VIA_FCR 0x00001107 |
| 356 | #define MSR_VIA_LONGHAUL 0x0000110a |
| 357 | #define MSR_VIA_RNG 0x0000110b |
| 358 | #define MSR_VIA_BCR2 0x00001147 |
| 359 | |
| 360 | /* Transmeta defined MSRs */ |
| 361 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 |
| 362 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 |
| 363 | #define MSR_TMTA_LRTI_READOUT 0x80868018 |
| 364 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a |
| 365 | |
| 366 | /* Intel defined MSRs. */ |
| 367 | #define MSR_IA32_P5_MC_ADDR 0x00000000 |
| 368 | #define MSR_IA32_P5_MC_TYPE 0x00000001 |
| 369 | #define MSR_IA32_TSC 0x00000010 |
| 370 | #define MSR_IA32_PLATFORM_ID 0x00000017 |
| 371 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a |
Jes Sorensen | b9a52c4 | 2010-09-09 12:06:45 +0200 | [diff] [blame] | 372 | #define MSR_EBC_FREQUENCY_ID 0x0000002c |
Len Brown | 1ed5101 | 2013-02-10 17:19:24 -0500 | [diff] [blame] | 373 | #define MSR_SMI_COUNT 0x00000034 |
Sheng Yang | 315a655 | 2008-09-09 14:54:53 +0800 | [diff] [blame] | 374 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
Will Auld | ba90463 | 2012-11-29 12:42:50 -0800 | [diff] [blame] | 375 | #define MSR_IA32_TSC_ADJUST 0x0000003b |
Liu, Jinsong | da8999d | 2014-02-24 10:55:46 +0000 | [diff] [blame] | 376 | #define MSR_IA32_BNDCFGS 0x00000d90 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 377 | |
Fenghua Yu | 6229ad2 | 2014-05-29 11:12:30 -0700 | [diff] [blame] | 378 | #define MSR_IA32_XSS 0x00000da0 |
| 379 | |
Shane Wang | cafd665 | 2010-04-29 12:09:01 -0400 | [diff] [blame] | 380 | #define FEATURE_CONTROL_LOCKED (1<<0) |
| 381 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) |
| 382 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
Sheng Yang | defed7e | 2008-09-11 15:27:50 +0800 | [diff] [blame] | 383 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 384 | #define MSR_IA32_APICBASE 0x0000001b |
| 385 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| 386 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| 387 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
| 388 | |
Liu, Jinsong | b90dfb0 | 2011-09-22 16:53:58 +0800 | [diff] [blame] | 389 | #define MSR_IA32_TSCDEADLINE 0x000006e0 |
| 390 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 391 | #define MSR_IA32_UCODE_WRITE 0x00000079 |
| 392 | #define MSR_IA32_UCODE_REV 0x0000008b |
| 393 | |
Eugene Korenevsky | e9ac033 | 2014-12-11 08:53:27 +0300 | [diff] [blame] | 394 | #define MSR_IA32_SMM_MONITOR_CTL 0x0000009b |
| 395 | #define MSR_IA32_SMBASE 0x0000009e |
| 396 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 397 | #define MSR_IA32_PERF_STATUS 0x00000198 |
| 398 | #define MSR_IA32_PERF_CTL 0x00000199 |
Srinidhi Kasagar | e7ddf4b | 2014-12-19 23:13:51 +0530 | [diff] [blame] | 399 | #define INTEL_PERF_CTL_MASK 0xffff |
Matthew Garrett | f594065 | 2012-09-04 08:28:06 +0000 | [diff] [blame] | 400 | #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 |
Matthew Garrett | 3dc9a63 | 2012-09-04 08:28:02 +0000 | [diff] [blame] | 401 | #define MSR_AMD_PERF_STATUS 0xc0010063 |
| 402 | #define MSR_AMD_PERF_CTL 0xc0010062 |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 403 | |
| 404 | #define MSR_IA32_MPERF 0x000000e7 |
| 405 | #define MSR_IA32_APERF 0x000000e8 |
| 406 | |
| 407 | #define MSR_IA32_THERM_CONTROL 0x0000019a |
| 408 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 409 | |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 410 | #define THERM_INT_HIGH_ENABLE (1 << 0) |
| 411 | #define THERM_INT_LOW_ENABLE (1 << 1) |
| 412 | #define THERM_INT_PLN_ENABLE (1 << 24) |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 413 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 414 | #define MSR_IA32_THERM_STATUS 0x0000019c |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 415 | |
| 416 | #define THERM_STATUS_PROCHOT (1 << 0) |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 417 | #define THERM_STATUS_POWER_LIMIT (1 << 10) |
Thomas Gleixner | ba2d0f2 | 2009-04-08 12:31:24 +0200 | [diff] [blame] | 418 | |
Bartlomiej Zolnierkiewicz | f3a0867 | 2009-07-29 00:04:59 +0200 | [diff] [blame] | 419 | #define MSR_THERM2_CTL 0x0000019d |
| 420 | |
| 421 | #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) |
| 422 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 423 | #define MSR_IA32_MISC_ENABLE 0x000001a0 |
| 424 | |
Carsten Emde | a321ced | 2010-05-24 14:33:41 -0700 | [diff] [blame] | 425 | #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 |
| 426 | |
Dirk Brandewie | 2f86dc4 | 2014-11-06 09:40:47 -0800 | [diff] [blame] | 427 | #define MSR_MISC_PWR_MGMT 0x000001aa |
| 428 | |
Venkatesh Pallipadi | 23016bf | 2010-06-03 23:22:28 -0400 | [diff] [blame] | 429 | #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |
Len Brown | abe48b1 | 2011-07-14 00:53:24 -0400 | [diff] [blame] | 430 | #define ENERGY_PERF_BIAS_PERFORMANCE 0 |
| 431 | #define ENERGY_PERF_BIAS_NORMAL 6 |
H. Peter Anvin | 4bb8217 | 2011-07-14 14:58:44 -0700 | [diff] [blame] | 432 | #define ENERGY_PERF_BIAS_POWERSAVE 15 |
Venkatesh Pallipadi | 23016bf | 2010-06-03 23:22:28 -0400 | [diff] [blame] | 433 | |
Fenghua Yu | 9792db6 | 2010-07-29 17:13:42 -0700 | [diff] [blame] | 434 | #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 |
| 435 | |
| 436 | #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) |
| 437 | #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) |
| 438 | |
| 439 | #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 |
| 440 | |
| 441 | #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) |
| 442 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
| 443 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
| 444 | |
R, Durgadoss | 9e76a97 | 2011-01-03 17:22:04 +0530 | [diff] [blame] | 445 | /* Thermal Thresholds Support */ |
| 446 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) |
| 447 | #define THERM_SHIFT_THRESHOLD0 8 |
| 448 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) |
| 449 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) |
| 450 | #define THERM_SHIFT_THRESHOLD1 16 |
| 451 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) |
| 452 | #define THERM_STATUS_THRESHOLD0 (1 << 6) |
| 453 | #define THERM_LOG_THRESHOLD0 (1 << 7) |
| 454 | #define THERM_STATUS_THRESHOLD1 (1 << 8) |
| 455 | #define THERM_LOG_THRESHOLD1 (1 << 9) |
| 456 | |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 457 | /* MISC_ENABLE bits: architectural */ |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 458 | #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 |
| 459 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) |
| 460 | #define MSR_IA32_MISC_ENABLE_TCC_BIT 1 |
| 461 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) |
| 462 | #define MSR_IA32_MISC_ENABLE_EMON_BIT 7 |
| 463 | #define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) |
| 464 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 |
| 465 | #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) |
| 466 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 |
| 467 | #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) |
| 468 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 |
| 469 | #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) |
| 470 | #define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 |
| 471 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) |
| 472 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 |
Andres Freund | c45f773 | 2014-05-09 03:29:17 +0200 | [diff] [blame] | 473 | #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 474 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 |
| 475 | #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) |
| 476 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 |
| 477 | #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 478 | |
| 479 | /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ |
H. Peter Anvin | 0b131be | 2014-03-13 15:40:52 -0700 | [diff] [blame] | 480 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 |
| 481 | #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) |
| 482 | #define MSR_IA32_MISC_ENABLE_TM1_BIT 3 |
| 483 | #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) |
| 484 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 |
| 485 | #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) |
| 486 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 |
| 487 | #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) |
| 488 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 |
| 489 | #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) |
| 490 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 |
| 491 | #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) |
| 492 | #define MSR_IA32_MISC_ENABLE_FERR_BIT 10 |
| 493 | #define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) |
| 494 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 |
| 495 | #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) |
| 496 | #define MSR_IA32_MISC_ENABLE_TM2_BIT 13 |
| 497 | #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) |
| 498 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 |
| 499 | #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) |
| 500 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 |
| 501 | #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) |
| 502 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 |
| 503 | #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) |
| 504 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 |
| 505 | #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) |
| 506 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 |
| 507 | #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) |
| 508 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 |
| 509 | #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) |
H. Peter Anvin | bdf21a4 | 2009-01-21 15:01:56 -0800 | [diff] [blame] | 510 | |
Suresh Siddha | 279f146 | 2012-10-22 14:37:58 -0700 | [diff] [blame] | 511 | #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
| 512 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 513 | /* P4/Xeon+ specific */ |
| 514 | #define MSR_IA32_MCG_EAX 0x00000180 |
| 515 | #define MSR_IA32_MCG_EBX 0x00000181 |
| 516 | #define MSR_IA32_MCG_ECX 0x00000182 |
| 517 | #define MSR_IA32_MCG_EDX 0x00000183 |
| 518 | #define MSR_IA32_MCG_ESI 0x00000184 |
| 519 | #define MSR_IA32_MCG_EDI 0x00000185 |
| 520 | #define MSR_IA32_MCG_EBP 0x00000186 |
| 521 | #define MSR_IA32_MCG_ESP 0x00000187 |
| 522 | #define MSR_IA32_MCG_EFLAGS 0x00000188 |
| 523 | #define MSR_IA32_MCG_EIP 0x00000189 |
| 524 | #define MSR_IA32_MCG_RESERVED 0x0000018a |
| 525 | |
| 526 | /* Pentium IV performance counter MSRs */ |
| 527 | #define MSR_P4_BPU_PERFCTR0 0x00000300 |
| 528 | #define MSR_P4_BPU_PERFCTR1 0x00000301 |
| 529 | #define MSR_P4_BPU_PERFCTR2 0x00000302 |
| 530 | #define MSR_P4_BPU_PERFCTR3 0x00000303 |
| 531 | #define MSR_P4_MS_PERFCTR0 0x00000304 |
| 532 | #define MSR_P4_MS_PERFCTR1 0x00000305 |
| 533 | #define MSR_P4_MS_PERFCTR2 0x00000306 |
| 534 | #define MSR_P4_MS_PERFCTR3 0x00000307 |
| 535 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 |
| 536 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 |
| 537 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a |
| 538 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b |
| 539 | #define MSR_P4_IQ_PERFCTR0 0x0000030c |
| 540 | #define MSR_P4_IQ_PERFCTR1 0x0000030d |
| 541 | #define MSR_P4_IQ_PERFCTR2 0x0000030e |
| 542 | #define MSR_P4_IQ_PERFCTR3 0x0000030f |
| 543 | #define MSR_P4_IQ_PERFCTR4 0x00000310 |
| 544 | #define MSR_P4_IQ_PERFCTR5 0x00000311 |
| 545 | #define MSR_P4_BPU_CCCR0 0x00000360 |
| 546 | #define MSR_P4_BPU_CCCR1 0x00000361 |
| 547 | #define MSR_P4_BPU_CCCR2 0x00000362 |
| 548 | #define MSR_P4_BPU_CCCR3 0x00000363 |
| 549 | #define MSR_P4_MS_CCCR0 0x00000364 |
| 550 | #define MSR_P4_MS_CCCR1 0x00000365 |
| 551 | #define MSR_P4_MS_CCCR2 0x00000366 |
| 552 | #define MSR_P4_MS_CCCR3 0x00000367 |
| 553 | #define MSR_P4_FLAME_CCCR0 0x00000368 |
| 554 | #define MSR_P4_FLAME_CCCR1 0x00000369 |
| 555 | #define MSR_P4_FLAME_CCCR2 0x0000036a |
| 556 | #define MSR_P4_FLAME_CCCR3 0x0000036b |
| 557 | #define MSR_P4_IQ_CCCR0 0x0000036c |
| 558 | #define MSR_P4_IQ_CCCR1 0x0000036d |
| 559 | #define MSR_P4_IQ_CCCR2 0x0000036e |
| 560 | #define MSR_P4_IQ_CCCR3 0x0000036f |
| 561 | #define MSR_P4_IQ_CCCR4 0x00000370 |
| 562 | #define MSR_P4_IQ_CCCR5 0x00000371 |
| 563 | #define MSR_P4_ALF_ESCR0 0x000003ca |
| 564 | #define MSR_P4_ALF_ESCR1 0x000003cb |
| 565 | #define MSR_P4_BPU_ESCR0 0x000003b2 |
| 566 | #define MSR_P4_BPU_ESCR1 0x000003b3 |
| 567 | #define MSR_P4_BSU_ESCR0 0x000003a0 |
| 568 | #define MSR_P4_BSU_ESCR1 0x000003a1 |
| 569 | #define MSR_P4_CRU_ESCR0 0x000003b8 |
| 570 | #define MSR_P4_CRU_ESCR1 0x000003b9 |
| 571 | #define MSR_P4_CRU_ESCR2 0x000003cc |
| 572 | #define MSR_P4_CRU_ESCR3 0x000003cd |
| 573 | #define MSR_P4_CRU_ESCR4 0x000003e0 |
| 574 | #define MSR_P4_CRU_ESCR5 0x000003e1 |
| 575 | #define MSR_P4_DAC_ESCR0 0x000003a8 |
| 576 | #define MSR_P4_DAC_ESCR1 0x000003a9 |
| 577 | #define MSR_P4_FIRM_ESCR0 0x000003a4 |
| 578 | #define MSR_P4_FIRM_ESCR1 0x000003a5 |
| 579 | #define MSR_P4_FLAME_ESCR0 0x000003a6 |
| 580 | #define MSR_P4_FLAME_ESCR1 0x000003a7 |
| 581 | #define MSR_P4_FSB_ESCR0 0x000003a2 |
| 582 | #define MSR_P4_FSB_ESCR1 0x000003a3 |
| 583 | #define MSR_P4_IQ_ESCR0 0x000003ba |
| 584 | #define MSR_P4_IQ_ESCR1 0x000003bb |
| 585 | #define MSR_P4_IS_ESCR0 0x000003b4 |
| 586 | #define MSR_P4_IS_ESCR1 0x000003b5 |
| 587 | #define MSR_P4_ITLB_ESCR0 0x000003b6 |
| 588 | #define MSR_P4_ITLB_ESCR1 0x000003b7 |
| 589 | #define MSR_P4_IX_ESCR0 0x000003c8 |
| 590 | #define MSR_P4_IX_ESCR1 0x000003c9 |
| 591 | #define MSR_P4_MOB_ESCR0 0x000003aa |
| 592 | #define MSR_P4_MOB_ESCR1 0x000003ab |
| 593 | #define MSR_P4_MS_ESCR0 0x000003c0 |
| 594 | #define MSR_P4_MS_ESCR1 0x000003c1 |
| 595 | #define MSR_P4_PMH_ESCR0 0x000003ac |
| 596 | #define MSR_P4_PMH_ESCR1 0x000003ad |
| 597 | #define MSR_P4_RAT_ESCR0 0x000003bc |
| 598 | #define MSR_P4_RAT_ESCR1 0x000003bd |
| 599 | #define MSR_P4_SAAT_ESCR0 0x000003ae |
| 600 | #define MSR_P4_SAAT_ESCR1 0x000003af |
| 601 | #define MSR_P4_SSU_ESCR0 0x000003be |
| 602 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ |
| 603 | |
| 604 | #define MSR_P4_TBPU_ESCR0 0x000003c2 |
| 605 | #define MSR_P4_TBPU_ESCR1 0x000003c3 |
| 606 | #define MSR_P4_TC_ESCR0 0x000003c4 |
| 607 | #define MSR_P4_TC_ESCR1 0x000003c5 |
| 608 | #define MSR_P4_U2L_ESCR0 0x000003b0 |
| 609 | #define MSR_P4_U2L_ESCR1 0x000003b1 |
| 610 | |
Lin Ming | cb7d6b5 | 2010-03-18 18:33:12 +0800 | [diff] [blame] | 611 | #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 |
| 612 | |
H. Peter Anvin | 4bc5aa9 | 2007-05-02 19:27:12 +0200 | [diff] [blame] | 613 | /* Intel Core-based CPU performance counters */ |
| 614 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 |
| 615 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a |
| 616 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b |
| 617 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d |
| 618 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e |
| 619 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f |
| 620 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 |
| 621 | |
| 622 | /* Geode defined MSRs */ |
| 623 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 |
| 624 | |
Sheng Yang | 315a655 | 2008-09-09 14:54:53 +0800 | [diff] [blame] | 625 | /* Intel VT MSRs */ |
| 626 | #define MSR_IA32_VMX_BASIC 0x00000480 |
| 627 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 |
| 628 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 |
| 629 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 |
| 630 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 |
| 631 | #define MSR_IA32_VMX_MISC 0x00000485 |
| 632 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 |
| 633 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 |
| 634 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 |
| 635 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 |
| 636 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a |
| 637 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
| 638 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 639 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d |
| 640 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e |
| 641 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f |
| 642 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 |
Jan Kiszka | cae5013 | 2014-01-04 18:47:22 +0100 | [diff] [blame] | 643 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 644 | |
| 645 | /* VMX_BASIC bits and bitmasks */ |
| 646 | #define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
Jan Kiszka | 3dbcd8d | 2014-06-16 13:59:40 +0200 | [diff] [blame] | 647 | #define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
Nadav Har'El | b87a51a | 2011-05-25 23:04:25 +0300 | [diff] [blame] | 648 | #define VMX_BASIC_64 0x0001000000000000LLU |
| 649 | #define VMX_BASIC_MEM_TYPE_SHIFT 50 |
| 650 | #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
| 651 | #define VMX_BASIC_MEM_TYPE_WB 6LLU |
| 652 | #define VMX_BASIC_INOUT 0x0040000000000000LLU |
Sheng Yang | 315a655 | 2008-09-09 14:54:53 +0800 | [diff] [blame] | 653 | |
Abel Gordon | 89662e5 | 2013-04-18 14:34:55 +0300 | [diff] [blame] | 654 | /* MSR_IA32_VMX_MISC bits */ |
| 655 | #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
Arthur Chunqi Li | 7854cbc | 2013-09-16 16:11:44 +0800 | [diff] [blame] | 656 | #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 657 | /* AMD-V MSRs */ |
| 658 | |
| 659 | #define MSR_VM_CR 0xc0010114 |
Alexander Graf | 0367b43 | 2009-06-15 15:21:22 +0200 | [diff] [blame] | 660 | #define MSR_VM_IGNNE 0xc0010115 |
Alexander Graf | 9962d03 | 2008-11-25 20:17:02 +0100 | [diff] [blame] | 661 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| 662 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 663 | #endif /* _ASM_X86_MSR_INDEX_H */ |