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Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_SPECTRUM_H
38#define _MLXSW_SPECTRUM_H
39
40#include <linux/types.h>
41#include <linux/netdevice.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010044#include <linux/list.h>
Ido Schimmel8e8dfe92016-04-06 17:10:10 +020045#include <linux/dcbnl.h>
Jiri Pirko5e9c16c2016-07-04 08:23:04 +020046#include <linux/in6.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020047#include <net/switchdev.h>
48
Elad Raz3a49b4f2016-01-10 21:06:28 +010049#include "port.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020050#include "core.h"
51
52#define MLXSW_SP_VFID_BASE VLAN_N_VID
Ido Schimmel99724c12016-07-04 08:23:14 +020053#define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
54
55#define MLXSW_SP_RFID_BASE 15360
56#define MLXSW_SP_RIF_MAX 800
Ido Schimmel7f71eb42015-12-15 16:03:37 +010057
Jiri Pirko0d65fc12015-12-03 12:12:28 +010058#define MLXSW_SP_LAG_MAX 64
59#define MLXSW_SP_PORT_PER_LAG_MAX 16
Jiri Pirko56ade8f2015-10-16 14:01:37 +020060
Elad Raz53ae6282016-01-10 21:06:26 +010061#define MLXSW_SP_MID_MAX 7000
62
Ido Schimmel18f1e702016-02-26 17:32:31 +010063#define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
64
Jiri Pirko53342022016-07-04 08:23:08 +020065#define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
66#define MLXSW_SP_LPM_TREE_MAX 22
67#define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
68
Jiri Pirko6b75c482016-07-04 08:23:09 +020069#define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
70
Ido Schimmel18f1e702016-02-26 17:32:31 +010071#define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
72
Ido Schimmel1a198442016-04-06 17:10:02 +020073#define MLXSW_SP_BYTES_PER_CELL 96
74
75#define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
Jiri Pirko0f433fa2016-04-14 18:19:24 +020076#define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
Ido Schimmel1a198442016-04-06 17:10:02 +020077
Ido Schimmel9f7ec052016-04-06 17:10:14 +020078/* Maximum delay buffer needed in case of PAUSE frames, in cells.
79 * Assumes 100m cable and maximum MTU.
80 */
81#define MLXSW_SP_PAUSE_DELAY 612
82
Ido Schimmeld81a6bd2016-04-06 17:10:16 +020083#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
84
85static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
86{
87 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
88 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
89}
90
Jiri Pirko56ade8f2015-10-16 14:01:37 +020091struct mlxsw_sp_port;
92
Jiri Pirko0d65fc12015-12-03 12:12:28 +010093struct mlxsw_sp_upper {
94 struct net_device *dev;
95 unsigned int ref_count;
96};
97
Ido Schimmeld0ec8752016-06-20 23:04:12 +020098struct mlxsw_sp_fid {
Ido Schimmel1c800752016-06-20 23:04:20 +020099 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100100 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200101 unsigned int ref_count;
102 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200103 struct mlxsw_sp_rif *r;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200104 u16 fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100105};
106
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200107struct mlxsw_sp_rif {
108 struct net_device *dev;
Ido Schimmel99724c12016-07-04 08:23:14 +0200109 unsigned int ref_count;
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200110 struct mlxsw_sp_fid *f;
111 unsigned char addr[ETH_ALEN];
112 int mtu;
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200113 u16 rif;
114};
115
Elad Raz3a49b4f2016-01-10 21:06:28 +0100116struct mlxsw_sp_mid {
117 struct list_head list;
118 unsigned char addr[ETH_ALEN];
119 u16 vid;
120 u16 mid;
121 unsigned int ref_count;
122};
123
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100124static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
125{
126 return MLXSW_SP_VFID_BASE + vfid;
127}
128
Ido Schimmelaac78a42015-12-15 16:03:42 +0100129static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
130{
131 return fid - MLXSW_SP_VFID_BASE;
132}
133
134static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
135{
Ido Schimmel99724c12016-07-04 08:23:14 +0200136 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
137}
138
139static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
140{
141 return fid >= MLXSW_SP_RFID_BASE;
142}
143
144static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
145{
146 return MLXSW_SP_RFID_BASE + rif;
Ido Schimmelaac78a42015-12-15 16:03:42 +0100147}
148
Jiri Pirko078f9c72016-04-14 18:19:19 +0200149struct mlxsw_sp_sb_pr {
150 enum mlxsw_reg_sbpr_mode mode;
151 u32 size;
152};
153
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200154struct mlxsw_cp_sb_occ {
155 u32 cur;
156 u32 max;
157};
158
Jiri Pirko078f9c72016-04-14 18:19:19 +0200159struct mlxsw_sp_sb_cm {
160 u32 min_buff;
161 u32 max_buff;
162 u8 pool;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200163 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200164};
165
166struct mlxsw_sp_sb_pm {
167 u32 min_buff;
168 u32 max_buff;
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200169 struct mlxsw_cp_sb_occ occ;
Jiri Pirko078f9c72016-04-14 18:19:19 +0200170};
171
172#define MLXSW_SP_SB_POOL_COUNT 4
173#define MLXSW_SP_SB_TC_COUNT 8
174
175struct mlxsw_sp_sb {
176 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
177 struct {
178 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
179 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
180 } ports[MLXSW_PORT_MAX_PORTS];
181};
182
Jiri Pirko5e9c16c2016-07-04 08:23:04 +0200183#define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
184
185struct mlxsw_sp_prefix_usage {
186 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
187};
188
Jiri Pirko53342022016-07-04 08:23:08 +0200189enum mlxsw_sp_l3proto {
190 MLXSW_SP_L3_PROTO_IPV4,
191 MLXSW_SP_L3_PROTO_IPV6,
192};
193
194struct mlxsw_sp_lpm_tree {
195 u8 id; /* tree ID */
196 unsigned int ref_count;
197 enum mlxsw_sp_l3proto proto;
198 struct mlxsw_sp_prefix_usage prefix_usage;
199};
200
Jiri Pirko6b75c482016-07-04 08:23:09 +0200201struct mlxsw_sp_fib;
202
203struct mlxsw_sp_vr {
204 u16 id; /* virtual router ID */
205 bool used;
206 enum mlxsw_sp_l3proto proto;
207 u32 tb_id; /* kernel fib table id */
208 struct mlxsw_sp_lpm_tree *lpm_tree;
209 struct mlxsw_sp_fib *fib;
210};
211
Jiri Pirko53342022016-07-04 08:23:08 +0200212struct mlxsw_sp_router {
213 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
Jiri Pirko6b75c482016-07-04 08:23:09 +0200214 struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX];
Jiri Pirko53342022016-07-04 08:23:08 +0200215};
216
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200217struct mlxsw_sp {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100218 struct {
219 struct list_head list;
Ido Schimmel99724c12016-07-04 08:23:14 +0200220 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +0100221 } br_vfids;
Elad Raz3a49b4f2016-01-10 21:06:28 +0100222 struct {
223 struct list_head list;
Ido Schimmeld8651fd2016-06-20 23:04:07 +0200224 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
Elad Raz3a49b4f2016-01-10 21:06:28 +0100225 } br_mids;
Ido Schimmel14d39462016-06-20 23:04:15 +0200226 struct list_head fids; /* VLAN-aware bridge FIDs */
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200227 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200228 struct mlxsw_sp_port **ports;
229 struct mlxsw_core *core;
230 const struct mlxsw_bus_info *bus_info;
231 unsigned char base_mac[ETH_ALEN];
232 struct {
233 struct delayed_work dw;
234#define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
235 unsigned int interval; /* ms */
236 } fdb_notify;
Ido Schimmel869f63a2016-03-08 12:59:33 -0800237#define MLXSW_SP_MIN_AGEING_TIME 10
238#define MLXSW_SP_MAX_AGEING_TIME 1000000
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200239#define MLXSW_SP_DEFAULT_AGEING_TIME 300
240 u32 ageing_time;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100241 struct mlxsw_sp_upper master_bridge;
242 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
Ido Schimmel558c2d52016-02-26 17:32:29 +0100243 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
Jiri Pirko078f9c72016-04-14 18:19:19 +0200244 struct mlxsw_sp_sb sb;
Jiri Pirko53342022016-07-04 08:23:08 +0200245 struct mlxsw_sp_router router;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200246};
247
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100248static inline struct mlxsw_sp_upper *
249mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
250{
251 return &mlxsw_sp->lags[lag_id];
252}
253
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200254struct mlxsw_sp_port_pcpu_stats {
255 u64 rx_packets;
256 u64 rx_bytes;
257 u64 tx_packets;
258 u64 tx_bytes;
259 struct u64_stats_sync syncp;
260 u32 tx_dropped;
261};
262
263struct mlxsw_sp_port {
Jiri Pirko932762b2016-04-08 19:11:21 +0200264 struct mlxsw_core_port core_port; /* must be first */
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200265 struct net_device *dev;
266 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
267 struct mlxsw_sp *mlxsw_sp;
268 u8 local_port;
269 u8 stp_state;
Jiri Pirko0d9b9702015-10-28 10:16:56 +0100270 u8 learning:1,
271 learning_sync:1,
Ido Schimmel02930382015-10-28 10:16:58 +0100272 uc_flood:1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100273 bridged:1,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100274 lagged:1,
275 split:1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200276 u16 pvid;
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100277 u16 lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100278 struct {
279 struct list_head list;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200280 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100281 u16 vid;
282 } vport;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200283 struct {
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200284 u8 tx_pause:1,
285 rx_pause:1;
286 } link;
287 struct {
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200288 struct ieee_ets *ets;
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200289 struct ieee_maxrate *maxrate;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200290 struct ieee_pfc *pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200291 } dcb;
Ido Schimmeld664b412016-06-09 09:51:40 +0200292 struct {
293 u8 module;
294 u8 width;
295 u8 lane;
296 } mapping;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200297 /* 802.1Q bridge VLANs */
Ido Schimmelbd40e9d2015-12-15 16:03:36 +0100298 unsigned long *active_vlans;
Elad Razfc1273a2016-01-06 13:01:11 +0100299 unsigned long *untagged_vlans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200300 /* VLAN interfaces */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100301 struct list_head vports_list;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200302};
303
Jiri Pirko7ce856a2016-07-04 08:23:12 +0200304struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
305void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
306
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200307static inline bool
308mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
311}
312
Jiri Pirko0d65fc12015-12-03 12:12:28 +0100313static inline struct mlxsw_sp_port *
314mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
315{
316 struct mlxsw_sp_port *mlxsw_sp_port;
317 u8 local_port;
318
319 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
320 lag_id, port_index);
321 mlxsw_sp_port = mlxsw_sp->ports[local_port];
322 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
323}
324
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100325static inline u16
326mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
327{
328 return mlxsw_sp_vport->vport.vid;
329}
330
Ido Schimmel6381b3a2016-06-20 23:04:16 +0200331static inline bool
332mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
333{
334 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
335
336 return vid != 0;
337}
338
Ido Schimmel41b996c2016-06-20 23:04:17 +0200339static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
340 struct mlxsw_sp_fid *f)
341{
342 mlxsw_sp_vport->vport.f = f;
343}
344
345static inline struct mlxsw_sp_fid *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200346mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100347{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200348 return mlxsw_sp_vport->vport.f;
349}
350
351static inline struct net_device *
352mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
353{
354 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
355
Ido Schimmel56918b62016-06-20 23:04:18 +0200356 return f ? f->dev : NULL;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100357}
358
359static inline struct mlxsw_sp_port *
360mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
361{
362 struct mlxsw_sp_port *mlxsw_sp_vport;
363
364 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
365 vport.list) {
366 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
367 return mlxsw_sp_vport;
368 }
369
370 return NULL;
371}
372
Ido Schimmelaac78a42015-12-15 16:03:42 +0100373static inline struct mlxsw_sp_port *
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200374mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
375 u16 fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100376{
377 struct mlxsw_sp_port *mlxsw_sp_vport;
378
379 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
380 vport.list) {
Ido Schimmel41b996c2016-06-20 23:04:17 +0200381 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
382
Ido Schimmel56918b62016-06-20 23:04:18 +0200383 if (f && f->fid == fid)
Ido Schimmelaac78a42015-12-15 16:03:42 +0100384 return mlxsw_sp_vport;
385 }
386
387 return NULL;
388}
389
Ido Schimmelfa3054f2016-07-02 11:00:16 +0200390static inline struct mlxsw_sp_rif *
391mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
392 const struct net_device *dev)
393{
394 int i;
395
396 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
397 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
398 return mlxsw_sp->rifs[i];
399
400 return NULL;
401}
402
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200403enum mlxsw_sp_flood_table {
404 MLXSW_SP_FLOOD_TABLE_UC,
405 MLXSW_SP_FLOOD_TABLE_BM,
406};
407
408int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200409void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200410int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
Jiri Pirko0f433fa2016-04-14 18:19:24 +0200411int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
412 unsigned int sb_index, u16 pool_index,
413 struct devlink_sb_pool_info *pool_info);
414int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
415 unsigned int sb_index, u16 pool_index, u32 size,
416 enum devlink_sb_threshold_type threshold_type);
417int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
418 unsigned int sb_index, u16 pool_index,
419 u32 *p_threshold);
420int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
421 unsigned int sb_index, u16 pool_index,
422 u32 threshold);
423int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
424 unsigned int sb_index, u16 tc_index,
425 enum devlink_sb_pool_type pool_type,
426 u16 *p_pool_index, u32 *p_threshold);
427int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
428 unsigned int sb_index, u16 tc_index,
429 enum devlink_sb_pool_type pool_type,
430 u16 pool_index, u32 threshold);
Jiri Pirko2d0ed392016-04-14 18:19:30 +0200431int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
432 unsigned int sb_index);
433int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
434 unsigned int sb_index);
435int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
436 unsigned int sb_index, u16 pool_index,
437 u32 *p_cur, u32 *p_max);
438int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
439 unsigned int sb_index, u16 tc_index,
440 enum devlink_sb_pool_type pool_type,
441 u32 *p_cur, u32 *p_max);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200442
443int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
444void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
445int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
446void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
447void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
448int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
449 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
450 u16 vid);
451int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
452 u16 vid_end, bool is_member, bool untagged);
453int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
454 u16 vid);
Ido Schimmele6060022016-06-20 23:04:11 +0200455int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
Ido Schimmel47a0a9e2016-06-20 23:04:08 +0200456 bool set);
Ido Schimmel4dc236c2016-01-27 15:20:16 +0100457void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
Ido Schimmel28a01d22016-02-18 11:30:02 +0100458int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +0200459int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
Ido Schimmel6e095fd2016-07-04 08:23:13 +0200460int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
461 bool adding);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200462int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
463 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
464 bool dwrr, u8 dwrr_weight);
465int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
466 u8 switch_prio, u8 tclass);
467int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200468 u8 *prio_tc, bool pause_en,
469 struct ieee_pfc *my_pfc);
Ido Schimmelcc7cf512016-04-06 17:10:11 +0200470int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
471 enum mlxsw_reg_qeec_hr hr, u8 index,
472 u8 next_index, u32 maxrate);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200473
Ido Schimmelf00817d2016-04-06 17:10:09 +0200474#ifdef CONFIG_MLXSW_SPECTRUM_DCB
475
476int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
477void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
478
479#else
480
481static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
482{
483 return 0;
484}
485
486static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
487{}
488
489#endif
490
Ido Schimmel464dce12016-07-02 11:00:15 +0200491int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
492void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
Jiri Pirko61c503f2016-07-04 08:23:11 +0200493int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port,
494 const struct switchdev_obj_ipv4_fib *fib4,
495 struct switchdev_trans *trans);
496int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port,
497 const struct switchdev_obj_ipv4_fib *fib4);
Ido Schimmel464dce12016-07-02 11:00:15 +0200498
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200499#endif