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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Terje Bergstromd43f81c2013-03-22 16:34:09 +02003 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Terje Bergstrom4231c6b2013-03-22 16:34:05 +020010#ifndef HOST1X_DRM_H
11#define HOST1X_DRM_H 1
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000012
Thierry Redinge1e90642013-09-24 13:59:01 +020013#include <uapi/drm/tegra_drm.h>
14#include <linux/host1x.h>
15
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000016#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_fb_helper.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020#include <drm/drm_fixed.h>
21
Stephen Warrenca480802013-11-06 16:20:54 -070022struct reset_control;
23
Arto Merilainende2ba662013-03-22 16:34:08 +020024struct tegra_fb {
25 struct drm_framebuffer base;
26 struct tegra_bo **planes;
27 unsigned int num_planes;
28};
29
Thierry Reding60c2f702013-10-31 13:28:50 +010030#ifdef CONFIG_DRM_TEGRA_FBDEV
Arto Merilainende2ba662013-03-22 16:34:08 +020031struct tegra_fbdev {
32 struct drm_fb_helper base;
33 struct tegra_fb *fb;
34};
Thierry Reding60c2f702013-10-31 13:28:50 +010035#endif
Arto Merilainende2ba662013-03-22 16:34:08 +020036
Thierry Reding386a2a72013-09-24 13:22:17 +020037struct tegra_drm {
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000038 struct drm_device *drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000039
40 struct mutex clients_lock;
41 struct list_head clients;
42
Thierry Reding60c2f702013-10-31 13:28:50 +010043#ifdef CONFIG_DRM_TEGRA_FBDEV
Arto Merilainende2ba662013-03-22 16:34:08 +020044 struct tegra_fbdev *fbdev;
Thierry Reding60c2f702013-10-31 13:28:50 +010045#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000046};
47
Thierry Reding53fa7f72013-09-24 15:35:40 +020048struct tegra_drm_client;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000049
Thierry Redingc88c3632013-09-26 16:08:22 +020050struct tegra_drm_context {
Thierry Reding53fa7f72013-09-24 15:35:40 +020051 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +020052 struct host1x_channel *channel;
53 struct list_head list;
54};
55
Thierry Reding53fa7f72013-09-24 15:35:40 +020056struct tegra_drm_client_ops {
57 int (*open_channel)(struct tegra_drm_client *client,
Thierry Redingc88c3632013-09-26 16:08:22 +020058 struct tegra_drm_context *context);
59 void (*close_channel)(struct tegra_drm_context *context);
Thierry Redingc40f0f12013-10-10 11:00:33 +020060 int (*is_addr_reg)(struct device *dev, u32 class, u32 offset);
Thierry Redingc88c3632013-09-26 16:08:22 +020061 int (*submit)(struct tegra_drm_context *context,
Terje Bergstromd43f81c2013-03-22 16:34:09 +020062 struct drm_tegra_submit *args, struct drm_device *drm,
63 struct drm_file *file);
64};
65
Thierry Redingc40f0f12013-10-10 11:00:33 +020066int tegra_drm_submit(struct tegra_drm_context *context,
67 struct drm_tegra_submit *args, struct drm_device *drm,
68 struct drm_file *file);
69
Thierry Reding53fa7f72013-09-24 15:35:40 +020070struct tegra_drm_client {
71 struct host1x_client base;
Thierry Reding776dc382013-10-14 14:43:22 +020072 struct list_head list;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000073
Thierry Reding53fa7f72013-09-24 15:35:40 +020074 const struct tegra_drm_client_ops *ops;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000075};
76
Thierry Reding53fa7f72013-09-24 15:35:40 +020077static inline struct tegra_drm_client *
Thierry Reding776dc382013-10-14 14:43:22 +020078host1x_to_drm_client(struct host1x_client *client)
Thierry Reding53fa7f72013-09-24 15:35:40 +020079{
80 return container_of(client, struct tegra_drm_client, base);
81}
82
Thierry Reding776dc382013-10-14 14:43:22 +020083extern int tegra_drm_register_client(struct tegra_drm *tegra,
84 struct tegra_drm_client *client);
85extern int tegra_drm_unregister_client(struct tegra_drm *tegra,
86 struct tegra_drm_client *client);
87
Thierry Reding386a2a72013-09-24 13:22:17 +020088extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
89extern int tegra_drm_exit(struct tegra_drm *tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000090
Thierry Reding8620fc62013-12-12 11:03:59 +010091struct tegra_dc_soc_info;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000092struct tegra_output;
93
94struct tegra_dc {
Thierry Reding776dc382013-10-14 14:43:22 +020095 struct host1x_client client;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096 struct device *dev;
Thierry Redingd18d3032013-09-26 16:09:19 +020097 spinlock_t lock;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000098
99 struct drm_crtc base;
100 int pipe;
101
102 struct clk *clk;
Stephen Warrenca480802013-11-06 16:20:54 -0700103 struct reset_control *rst;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000104 void __iomem *regs;
105 int irq;
106
107 struct tegra_output *rgb;
108
109 struct list_head list;
110
111 struct drm_info_list *debugfs_files;
112 struct drm_minor *minor;
113 struct dentry *debugfs;
Thierry Reding3c03c462012-11-28 12:00:18 +0100114
115 /* page-flip handling */
116 struct drm_pending_vblank_event *event;
Thierry Reding8620fc62013-12-12 11:03:59 +0100117
118 const struct tegra_dc_soc_info *soc;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000119};
120
Thierry Reding53fa7f72013-09-24 15:35:40 +0200121static inline struct tegra_dc *
Thierry Reding776dc382013-10-14 14:43:22 +0200122host1x_client_to_dc(struct host1x_client *client)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000123{
124 return container_of(client, struct tegra_dc, client);
125}
126
127static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
128{
Thierry Reding37826512013-11-08 12:30:37 +0100129 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000130}
131
132static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value,
133 unsigned long reg)
134{
135 writel(value, dc->regs + (reg << 2));
136}
137
138static inline unsigned long tegra_dc_readl(struct tegra_dc *dc,
139 unsigned long reg)
140{
141 return readl(dc->regs + (reg << 2));
142}
143
Thierry Redingf34bc782012-11-04 21:47:13 +0100144struct tegra_dc_window {
145 struct {
146 unsigned int x;
147 unsigned int y;
148 unsigned int w;
149 unsigned int h;
150 } src;
151 struct {
152 unsigned int x;
153 unsigned int y;
154 unsigned int w;
155 unsigned int h;
156 } dst;
157 unsigned int bits_per_pixel;
158 unsigned int format;
159 unsigned int stride[2];
160 unsigned long base[3];
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200161 bool bottom_up;
Thierry Reding773af772013-10-04 22:34:01 +0200162 bool tiled;
Thierry Redingf34bc782012-11-04 21:47:13 +0100163};
164
165/* from dc.c */
166extern unsigned int tegra_dc_format(uint32_t format);
167extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
168 const struct tegra_dc_window *window);
Thierry Reding6e5ff992012-11-28 11:45:47 +0100169extern void tegra_dc_enable_vblank(struct tegra_dc *dc);
170extern void tegra_dc_disable_vblank(struct tegra_dc *dc);
Thierry Reding3c03c462012-11-28 12:00:18 +0100171extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc,
172 struct drm_file *file);
Thierry Redingf34bc782012-11-04 21:47:13 +0100173
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000174struct tegra_output_ops {
175 int (*enable)(struct tegra_output *output);
176 int (*disable)(struct tegra_output *output);
177 int (*setup_clock)(struct tegra_output *output, struct clk *clk,
178 unsigned long pclk);
179 int (*check_mode)(struct tegra_output *output,
180 struct drm_display_mode *mode,
181 enum drm_mode_status *status);
182};
183
184enum tegra_output_type {
185 TEGRA_OUTPUT_RGB,
Thierry Redingedec4af2012-11-15 21:28:23 +0000186 TEGRA_OUTPUT_HDMI,
Thierry Redingdec72732013-09-03 08:45:46 +0200187 TEGRA_OUTPUT_DSI,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000188};
189
190struct tegra_output {
191 struct device_node *of_node;
192 struct device *dev;
193
194 const struct tegra_output_ops *ops;
195 enum tegra_output_type type;
196
Thierry Reding9be7d862013-08-30 15:22:36 +0200197 struct drm_panel *panel;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198 struct i2c_adapter *ddc;
199 const struct edid *edid;
200 unsigned int hpd_irq;
201 int hpd_gpio;
202
203 struct drm_encoder encoder;
204 struct drm_connector connector;
205};
206
207static inline struct tegra_output *encoder_to_output(struct drm_encoder *e)
208{
209 return container_of(e, struct tegra_output, encoder);
210}
211
212static inline struct tegra_output *connector_to_output(struct drm_connector *c)
213{
214 return container_of(c, struct tegra_output, connector);
215}
216
217static inline int tegra_output_enable(struct tegra_output *output)
218{
219 if (output && output->ops && output->ops->enable)
220 return output->ops->enable(output);
221
222 return output ? -ENOSYS : -EINVAL;
223}
224
225static inline int tegra_output_disable(struct tegra_output *output)
226{
227 if (output && output->ops && output->ops->disable)
228 return output->ops->disable(output);
229
230 return output ? -ENOSYS : -EINVAL;
231}
232
233static inline int tegra_output_setup_clock(struct tegra_output *output,
234 struct clk *clk, unsigned long pclk)
235{
236 if (output && output->ops && output->ops->setup_clock)
237 return output->ops->setup_clock(output, clk, pclk);
238
239 return output ? -ENOSYS : -EINVAL;
240}
241
242static inline int tegra_output_check_mode(struct tegra_output *output,
243 struct drm_display_mode *mode,
244 enum drm_mode_status *status)
245{
246 if (output && output->ops && output->ops->check_mode)
247 return output->ops->check_mode(output, mode, status);
248
249 return output ? -ENOSYS : -EINVAL;
250}
251
Thierry Reding776dc382013-10-14 14:43:22 +0200252/* from bus.c */
253int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device);
254void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device);
255
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000256/* from rgb.c */
257extern int tegra_dc_rgb_probe(struct tegra_dc *dc);
Thierry Reding59d29c02013-10-14 14:26:42 +0200258extern int tegra_dc_rgb_remove(struct tegra_dc *dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000259extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
260extern int tegra_dc_rgb_exit(struct tegra_dc *dc);
261
262/* from output.c */
Thierry Reding59d29c02013-10-14 14:26:42 +0200263extern int tegra_output_probe(struct tegra_output *output);
264extern int tegra_output_remove(struct tegra_output *output);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000265extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
266extern int tegra_output_exit(struct tegra_output *output);
267
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000268/* from fb.c */
Arto Merilainende2ba662013-03-22 16:34:08 +0200269struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
270 unsigned int index);
Thierry Redingdb7fbdf2013-10-07 09:47:58 +0200271bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
Thierry Reding773af772013-10-04 22:34:01 +0200272bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000273extern int tegra_drm_fb_init(struct drm_device *drm);
274extern void tegra_drm_fb_exit(struct drm_device *drm);
Thierry Reding60c2f702013-10-31 13:28:50 +0100275#ifdef CONFIG_DRM_TEGRA_FBDEV
Arto Merilainende2ba662013-03-22 16:34:08 +0200276extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100277#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000278
Thierry Reding776dc382013-10-14 14:43:22 +0200279extern struct platform_driver tegra_dc_driver;
Thierry Redingdec72732013-09-03 08:45:46 +0200280extern struct platform_driver tegra_dsi_driver;
Thierry Reding776dc382013-10-14 14:43:22 +0200281extern struct platform_driver tegra_hdmi_driver;
282extern struct platform_driver tegra_gr2d_driver;
Thierry Reding5f60ed02013-02-28 08:08:01 +0100283extern struct platform_driver tegra_gr3d_driver;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000284
Terje Bergstrom4231c6b2013-03-22 16:34:05 +0200285#endif /* HOST1X_DRM_H */