blob: 27f5ea1928cc1ebdfb82446519d257aeb326d53b [file] [log] [blame]
Tony Lindgrenf20b9332011-12-16 14:13:09 -08001/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
Benoit Cousson4c94ac22012-10-24 10:47:52 +020015 interrupt-parent = <&intc>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -080016
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 };
22
23 cpus {
24 cpu@0 {
25 compatible = "arm,arm1136jf-s";
26 };
27 };
28
Jon Hunter9b07b472012-10-18 09:28:52 -050029 pmu {
30 compatible = "arm,arm1136-pmu";
31 interrupts = <3>;
32 };
33
Tony Lindgrenf20b9332011-12-16 14:13:09 -080034 soc {
35 compatible = "ti,omap-infra";
36 mpu {
37 compatible = "ti,omap2-mpu";
38 ti,hwmods = "mpu";
39 };
40 };
41
42 ocp {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47 ti,hwmods = "l3_main";
48
49 intc: interrupt-controller@1 {
50 compatible = "ti,omap2-intc";
51 interrupt-controller;
52 #interrupt-cells = <1>;
Jon Hunter95dca122012-06-12 19:40:46 -050053 ti,intc-size = <96>;
54 reg = <0x480FE000 0x1000>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -080055 };
56
57 uart1: serial@4806a000 {
58 compatible = "ti,omap2-uart";
59 ti,hwmods = "uart1";
60 clock-frequency = <48000000>;
61 };
62
63 uart2: serial@4806c000 {
64 compatible = "ti,omap2-uart";
65 ti,hwmods = "uart2";
66 clock-frequency = <48000000>;
67 };
68
69 uart3: serial@4806e000 {
70 compatible = "ti,omap2-uart";
71 ti,hwmods = "uart3";
72 clock-frequency = <48000000>;
73 };
Jon Hunterfab8ad02012-10-19 09:59:00 -050074
75 timer2: timer@4802a000 {
76 compatible = "ti,omap2-timer";
77 reg = <0x4802a000 0x400>;
78 interrupts = <38>;
79 ti,hwmods = "timer2";
80 };
81
82 timer3: timer@48078000 {
83 compatible = "ti,omap2-timer";
84 reg = <0x48078000 0x400>;
85 interrupts = <39>;
86 ti,hwmods = "timer3";
87 };
88
89 timer4: timer@4807a000 {
90 compatible = "ti,omap2-timer";
91 reg = <0x4807a000 0x400>;
92 interrupts = <40>;
93 ti,hwmods = "timer4";
94 };
95
96 timer5: timer@4807c000 {
97 compatible = "ti,omap2-timer";
98 reg = <0x4807c000 0x400>;
99 interrupts = <41>;
100 ti,hwmods = "timer5";
101 ti,timer-dsp;
102 };
103
104 timer6: timer@4807e000 {
105 compatible = "ti,omap2-timer";
106 reg = <0x4807e000 0x400>;
107 interrupts = <42>;
108 ti,hwmods = "timer6";
109 ti,timer-dsp;
110 };
111
112 timer7: timer@48080000 {
113 compatible = "ti,omap2-timer";
114 reg = <0x48080000 0x400>;
115 interrupts = <43>;
116 ti,hwmods = "timer7";
117 ti,timer-dsp;
118 };
119
120 timer8: timer@48082000 {
121 compatible = "ti,omap2-timer";
122 reg = <0x48082000 0x400>;
123 interrupts = <44>;
124 ti,hwmods = "timer8";
125 ti,timer-dsp;
126 };
127
128 timer9: timer@48084000 {
129 compatible = "ti,omap2-timer";
130 reg = <0x48084000 0x400>;
131 interrupts = <45>;
132 ti,hwmods = "timer9";
133 ti,timer-pwm;
134 };
135
136 timer10: timer@48086000 {
137 compatible = "ti,omap2-timer";
138 reg = <0x48086000 0x400>;
139 interrupts = <46>;
140 ti,hwmods = "timer10";
141 ti,timer-pwm;
142 };
143
144 timer11: timer@48088000 {
145 compatible = "ti,omap2-timer";
146 reg = <0x48088000 0x400>;
147 interrupts = <47>;
148 ti,hwmods = "timer11";
149 ti,timer-pwm;
150 };
151
152 timer12: timer@4808a000 {
153 compatible = "ti,omap2-timer";
154 reg = <0x4808a000 0x400>;
155 interrupts = <48>;
156 ti,hwmods = "timer12";
157 ti,timer-pwm;
158 };
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800159 };
160};