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Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +02001/*
2 * Marvell Armada 370/XP SoC timer handling.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * Timer 0 is used as free-running clocksource, while timer 1 is
15 * used as clock_event_device.
Ezequiel Garcia7cd63922013-08-13 11:43:13 -030016 *
17 * ---
18 * Clocksource driver for Armada 370 and Armada XP SoC.
19 * This driver implements one compatible string for each SoC, given
20 * each has its own characteristics:
21 *
22 * * Armada 370 has no 25 MHz fixed timer.
23 *
24 * * Armada XP cannot work properly without such 25 MHz fixed timer as
25 * doing otherwise leads to using a clocksource whose frequency varies
26 * when doing cpufreq frequency changes.
27 *
28 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020029 */
30
31#include <linux/init.h>
32#include <linux/platform_device.h>
33#include <linux/kernel.h>
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010034#include <linux/clk.h>
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080035#include <linux/cpu.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020036#include <linux/timer.h>
37#include <linux/clockchips.h>
38#include <linux/interrupt.h>
39#include <linux/of.h>
40#include <linux/of_irq.h>
41#include <linux/of_address.h>
42#include <linux/irq.h>
43#include <linux/module.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070044#include <linux/sched_clock.h>
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010045#include <linux/percpu.h>
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +010046#include <linux/syscore_ops.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020047
Russell Kingcb0f2532015-10-19 16:19:20 +010048#include <asm/delay.h>
49
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020050/*
51 * Timer block registers.
52 */
53#define TIMER_CTRL_OFF 0x0000
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030054#define TIMER0_EN BIT(0)
55#define TIMER0_RELOAD_EN BIT(1)
56#define TIMER0_25MHZ BIT(11)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020057#define TIMER0_DIV(div) ((div) << 19)
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030058#define TIMER1_EN BIT(2)
59#define TIMER1_RELOAD_EN BIT(3)
60#define TIMER1_25MHZ BIT(12)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020061#define TIMER1_DIV(div) ((div) << 22)
62#define TIMER_EVENTS_STATUS 0x0004
63#define TIMER0_CLR_MASK (~0x1)
64#define TIMER1_CLR_MASK (~0x100)
65#define TIMER0_RELOAD_OFF 0x0010
66#define TIMER0_VAL_OFF 0x0014
67#define TIMER1_RELOAD_OFF 0x0018
68#define TIMER1_VAL_OFF 0x001c
69
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010070#define LCL_TIMER_EVENTS_STATUS 0x0028
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020071/* Global timers are connected to the coherency fabric clock, and the
72 below divider reduces their incrementing frequency. */
73#define TIMER_DIVIDER_SHIFT 5
74#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
75
76/*
77 * SoC-specific data.
78 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010079static void __iomem *timer_base, *local_base;
80static unsigned int timer_clk;
81static bool timer25Mhz = true;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +010082static u32 enable_mask;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020083
84/*
85 * Number of timer ticks per jiffy.
86 */
87static u32 ticks_per_jiffy;
88
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080089static struct clock_event_device __percpu *armada_370_xp_evt;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010090
Ezequiel Garcia35796982013-08-13 11:43:11 -030091static void local_timer_ctrl_clrset(u32 clr, u32 set)
92{
93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
94 local_base + TIMER_CTRL_OFF);
95}
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020096
Stephen Boydd9dbcbe2013-07-18 16:21:27 -070097static u64 notrace armada_370_xp_read_sched_clock(void)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020098{
99 return ~readl(timer_base + TIMER0_VAL_OFF);
100}
101
102/*
103 * Clockevent handling.
104 */
105static int
106armada_370_xp_clkevt_next_event(unsigned long delta,
107 struct clock_event_device *dev)
108{
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200109 /*
110 * Clear clockevent timer interrupt.
111 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100112 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200113
114 /*
115 * Setup new clockevent timer value.
116 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100117 writel(delta, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200118
119 /*
120 * Enable the timer.
121 */
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100122 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200123 return 0;
124}
125
Viresh Kumard96f4412015-06-18 16:24:40 +0530126static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200127{
Viresh Kumard96f4412015-06-18 16:24:40 +0530128 /*
129 * Disable timer.
130 */
131 local_timer_ctrl_clrset(TIMER0_EN, 0);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100132
Viresh Kumard96f4412015-06-18 16:24:40 +0530133 /*
134 * ACK pending timer interrupt.
135 */
136 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
137 return 0;
138}
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200139
Viresh Kumard96f4412015-06-18 16:24:40 +0530140static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
141{
142 /*
143 * Setup timer to fire at 1/HZ intervals.
144 */
145 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
146 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200147
Viresh Kumard96f4412015-06-18 16:24:40 +0530148 /*
149 * Enable timer.
150 */
151 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
152 return 0;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200153}
154
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800155static int armada_370_xp_clkevt_irq;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200156
157static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
158{
159 /*
160 * ACK timer interrupt and call event handler.
161 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800162 struct clock_event_device *evt = dev_id;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200163
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100164 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
165 evt->event_handler(evt);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200166
167 return IRQ_HANDLED;
168}
169
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100170/*
171 * Setup the local clock events for a CPU.
172 */
Richard Cochran2c48fef2016-07-13 17:17:06 +0000173static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100174{
Richard Cochran2c48fef2016-07-13 17:17:06 +0000175 struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
Ezequiel Garcia35796982013-08-13 11:43:11 -0300176 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100177
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100178 if (timer25Mhz)
Ezequiel Garcia35796982013-08-13 11:43:11 -0300179 set = TIMER0_25MHZ;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100180 else
Ezequiel Garcia35796982013-08-13 11:43:11 -0300181 clr = TIMER0_25MHZ;
182 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100183
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800184 evt->name = "armada_370_xp_per_cpu_tick",
185 evt->features = CLOCK_EVT_FEAT_ONESHOT |
186 CLOCK_EVT_FEAT_PERIODIC;
187 evt->shift = 32,
188 evt->rating = 300,
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100189 evt->set_next_event = armada_370_xp_clkevt_next_event,
Viresh Kumard96f4412015-06-18 16:24:40 +0530190 evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
191 evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
192 evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
193 evt->tick_resume = armada_370_xp_clkevt_shutdown;
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800194 evt->irq = armada_370_xp_clkevt_irq;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100195 evt->cpumask = cpumask_of(cpu);
196
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100197 clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
198 enable_percpu_irq(evt->irq, 0);
199
200 return 0;
201}
202
Richard Cochran2c48fef2016-07-13 17:17:06 +0000203static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100204{
Richard Cochran2c48fef2016-07-13 17:17:06 +0000205 struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
206
Viresh Kumard96f4412015-06-18 16:24:40 +0530207 evt->set_state_shutdown(evt);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100208 disable_percpu_irq(evt->irq);
Richard Cochran2c48fef2016-07-13 17:17:06 +0000209 return 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100210}
211
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100212static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
213
214static int armada_370_xp_timer_suspend(void)
215{
216 timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
217 timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
218 return 0;
219}
220
221static void armada_370_xp_timer_resume(void)
222{
223 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
224 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
225 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
226 writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
227}
228
Ben Dooks2c436e42016-06-16 15:47:49 +0200229static struct syscore_ops armada_370_xp_timer_syscore_ops = {
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100230 .suspend = armada_370_xp_timer_suspend,
231 .resume = armada_370_xp_timer_resume,
232};
233
Russell Kingcb0f2532015-10-19 16:19:20 +0100234static unsigned long armada_370_delay_timer_read(void)
235{
236 return ~readl(timer_base + TIMER0_VAL_OFF);
237}
238
239static struct delay_timer armada_370_delay_timer = {
240 .read_current_timer = armada_370_delay_timer_read,
241};
242
Daniel Lezcano12549e22016-06-06 18:00:01 +0200243static int __init armada_370_xp_timer_common_init(struct device_node *np)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200244{
Ezequiel Garcia35796982013-08-13 11:43:11 -0300245 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100246 int res;
247
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200248 timer_base = of_iomap(np, 0);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200249 if (!timer_base) {
250 pr_err("Failed to iomap");
251 return -ENXIO;
252 }
253
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100254 local_base = of_iomap(np, 1);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200255 if (!local_base) {
256 pr_err("Failed to iomap");
257 return -ENXIO;
258 }
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200259
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100260 if (timer25Mhz) {
Linus Torvaldsa4ae54f2013-09-16 16:10:26 -0400261 set = TIMER0_25MHZ;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100262 enable_mask = TIMER0_EN;
263 } else {
Ezequiel Garcia35796982013-08-13 11:43:11 -0300264 clr = TIMER0_25MHZ;
Ezequiel Garcia08cb8e42013-12-02 11:39:56 +0100265 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
266 }
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
Ezequiel Garcia35796982013-08-13 11:43:11 -0300268 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200269
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100270 /*
271 * We use timer 0 as clocksource, and private(local) timer 0
272 * for clockevents
273 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800274 armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200275
276 ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
277
278 /*
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200279 * Setup free-running clocksource timer (interrupts
280 * disabled).
281 */
282 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
283 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
284
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300285 atomic_io_modify(timer_base + TIMER_CTRL_OFF,
286 TIMER0_RELOAD_EN | enable_mask,
287 TIMER0_RELOAD_EN | enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200288
Russell Kingcb0f2532015-10-19 16:19:20 +0100289 armada_370_delay_timer.freq = timer_clk;
290 register_current_timer_delay(&armada_370_delay_timer);
291
Ezequiel Garciac813eff2013-11-26 18:20:14 -0300292 /*
293 * Set scale and timer for sched_clock.
294 */
295 sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
296
Daniel Lezcano12549e22016-06-06 18:00:01 +0200297 res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
298 "armada_370_xp_clocksource",
299 timer_clk, 300, 32, clocksource_mmio_readl_down);
300 if (res) {
301 pr_err("Failed to initialize clocksource mmio");
302 return res;
303 }
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200304
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800305 armada_370_xp_evt = alloc_percpu(struct clock_event_device);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200306 if (!armada_370_xp_evt)
307 return -ENOMEM;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100308
309 /*
310 * Setup clockevent timer (interrupt-driven).
311 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800312 res = request_percpu_irq(armada_370_xp_clkevt_irq,
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100313 armada_370_xp_timer_interrupt,
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800314 "armada_370_xp_per_cpu_tick",
315 armada_370_xp_evt);
316 /* Immediately configure the timer on the boot CPU */
Daniel Lezcano12549e22016-06-06 18:00:01 +0200317 if (res) {
318 pr_err("Failed to request percpu irq");
319 return res;
320 }
321
Richard Cochran2c48fef2016-07-13 17:17:06 +0000322 res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
323 "AP_ARMADA_TIMER_STARTING",
324 armada_370_xp_timer_starting_cpu,
325 armada_370_xp_timer_dying_cpu);
Anna-Maria Gleixner1d661bf2016-07-12 16:40:09 +0200326 if (res) {
Richard Cochran2c48fef2016-07-13 17:17:06 +0000327 pr_err("Failed to setup hotplug state and timer");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200328 return res;
329 }
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100330
331 register_syscore_ops(&armada_370_xp_timer_syscore_ops);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200332
333 return 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100334}
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300335
Daniel Lezcano12549e22016-06-06 18:00:01 +0200336static int __init armada_xp_timer_init(struct device_node *np)
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300337{
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300338 struct clk *clk = of_clk_get_by_name(np, "fixed");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200339 int ret;
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300340
Daniel Lezcano12549e22016-06-06 18:00:01 +0200341 clk = of_clk_get(np, 0);
342 if (IS_ERR(clk)) {
343 pr_err("Failed to get clock");
344 return PTR_ERR(clk);
345 }
346
347 ret = clk_prepare_enable(clk);
348 if (ret)
349 return ret;
350
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300351 timer_clk = clk_get_rate(clk);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300352
Daniel Lezcano12549e22016-06-06 18:00:01 +0200353 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300354}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200355CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300356 armada_xp_timer_init);
357
Daniel Lezcano12549e22016-06-06 18:00:01 +0200358static int __init armada_375_timer_init(struct device_node *np)
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300359{
360 struct clk *clk;
Daniel Lezcano12549e22016-06-06 18:00:01 +0200361 int ret;
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300362
363 clk = of_clk_get_by_name(np, "fixed");
364 if (!IS_ERR(clk)) {
Daniel Lezcano12549e22016-06-06 18:00:01 +0200365 ret = clk_prepare_enable(clk);
366 if (ret)
367 return ret;
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300368 timer_clk = clk_get_rate(clk);
369 } else {
370
371 /*
372 * This fallback is required in order to retain proper
373 * devicetree backwards compatibility.
374 */
375 clk = of_clk_get(np, 0);
376
377 /* Must have at least a clock */
Daniel Lezcano12549e22016-06-06 18:00:01 +0200378 if (IS_ERR(clk)) {
379 pr_err("Failed to get clock");
380 return PTR_ERR(clk);
381 }
382
383 ret = clk_prepare_enable(clk);
384 if (ret)
385 return ret;
386
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300387 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
388 timer25Mhz = false;
389 }
390
Daniel Lezcano12549e22016-06-06 18:00:01 +0200391 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300392}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200393CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300394 armada_375_timer_init);
395
Daniel Lezcano12549e22016-06-06 18:00:01 +0200396static int __init armada_370_timer_init(struct device_node *np)
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300397{
Daniel Lezcano12549e22016-06-06 18:00:01 +0200398 struct clk *clk;
399 int ret;
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300400
Daniel Lezcano12549e22016-06-06 18:00:01 +0200401 clk = of_clk_get(np, 0);
402 if (IS_ERR(clk)) {
403 pr_err("Failed to get clock");
404 return PTR_ERR(clk);
405 }
406
407 ret = clk_prepare_enable(clk);
408 if (ret)
409 return ret;
410
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300411 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
412 timer25Mhz = false;
413
Daniel Lezcano12549e22016-06-06 18:00:01 +0200414 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300415}
Daniel Lezcano177cf6e2016-06-07 00:27:44 +0200416CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300417 armada_370_timer_init);