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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 *
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
31 * Winbond W83759A
32 *
33 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
34 * on PC class systems. There are three hybrid devices that are exceptions
35 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
36 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
37 *
38 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
39 * opti82c465mv/promise 20230c/20630
40 *
41 * Use the autospeed and pio_mask options with:
42 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
43 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
44 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
45 * Winbond W83759A, Promise PDC20230-B
46 *
47 * For now use autospeed and pio_mask as above with the W83759A. This may
48 * change.
49 *
50 * TODO
51 * Merge existing pata_qdi driver
52 *
53 */
54
55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <scsi/scsi_host.h>
62#include <linux/ata.h>
63#include <linux/libata.h>
64#include <linux/platform_device.h>
65
66#define DRV_NAME "pata_legacy"
Jeff Garzik8bc3fc42007-05-21 20:26:38 -040067#define DRV_VERSION "0.5.5"
Jeff Garzik669a5db2006-08-29 18:12:40 -040068
69#define NR_HOST 6
70
71static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
Mikael Pettersson8b966dd2007-03-03 20:57:44 +010072static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 };
Jeff Garzik669a5db2006-08-29 18:12:40 -040073
74struct legacy_data {
75 unsigned long timing;
76 u8 clock[2];
77 u8 last;
78 int fast;
79 struct platform_device *platform_dev;
80
81};
82
83static struct legacy_data legacy_data[NR_HOST];
84static struct ata_host *legacy_host[NR_HOST];
85static int nr_legacy_host;
86
87
88static int probe_all; /* Set to check all ISA port ranges */
89static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */
90static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */
91static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */
Alan Coxf834e492007-02-07 13:46:00 -080092static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */
Jeff Garzik669a5db2006-08-29 18:12:40 -040093static int autospeed; /* Chip present which snoops speed changes */
94static int pio_mask = 0x1F; /* PIO range for autospeed devices */
Alan Coxf834e492007-02-07 13:46:00 -080095static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
Jeff Garzik669a5db2006-08-29 18:12:40 -040096
97/**
98 * legacy_set_mode - mode setting
99 * @ap: IDE interface
Alanb229a7b2007-01-24 11:47:07 +0000100 * @unused: Device that failed when error is returned
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101 *
102 * Use a non standard set_mode function. We don't want to be tuned.
103 *
104 * The BIOS configured everything. Our job is not to fiddle. Just use
105 * whatever PIO the hardware is using and leave it at that. When we
106 * get some kind of nice user driven API for control then we can
107 * expand on this as per hdparm in the base kernel.
108 */
109
Alanb229a7b2007-01-24 11:47:07 +0000110static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400111{
112 int i;
113
114 for (i = 0; i < ATA_MAX_DEVICES; i++) {
115 struct ata_device *dev = &ap->device[i];
116 if (ata_dev_enabled(dev)) {
Alan Coxf834e492007-02-07 13:46:00 -0800117 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400118 dev->pio_mode = XFER_PIO_0;
119 dev->xfer_mode = XFER_PIO_0;
120 dev->xfer_shift = ATA_SHIFT_PIO;
121 dev->flags |= ATA_DFLAG_PIO;
122 }
123 }
Alanb229a7b2007-01-24 11:47:07 +0000124 return 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125}
126
127static struct scsi_host_template legacy_sht = {
128 .module = THIS_MODULE,
129 .name = DRV_NAME,
130 .ioctl = ata_scsi_ioctl,
131 .queuecommand = ata_scsi_queuecmd,
132 .can_queue = ATA_DEF_QUEUE,
133 .this_id = ATA_SHT_THIS_ID,
134 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400135 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
136 .emulated = ATA_SHT_EMULATED,
137 .use_clustering = ATA_SHT_USE_CLUSTERING,
138 .proc_name = DRV_NAME,
139 .dma_boundary = ATA_DMA_BOUNDARY,
140 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900141 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400142 .bios_param = ata_std_bios_param,
143};
144
145/*
146 * These ops are used if the user indicates the hardware
147 * snoops the commands to decide on the mode and handles the
148 * mode selection "magically" itself. Several legacy controllers
149 * do this. The mode range can be set if it is not 0x1F by setting
150 * pio_mask as well.
151 */
152
153static struct ata_port_operations simple_port_ops = {
154 .port_disable = ata_port_disable,
155 .tf_load = ata_tf_load,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = ata_exec_command,
159 .dev_select = ata_std_dev_select,
160
161 .freeze = ata_bmdma_freeze,
162 .thaw = ata_bmdma_thaw,
163 .error_handler = ata_bmdma_error_handler,
164 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500165 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400166
167 .qc_prep = ata_qc_prep,
168 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400169
Tejun Heo0d5ff562007-02-01 15:06:36 +0900170 .data_xfer = ata_data_xfer_noirq,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400171
172 .irq_handler = ata_interrupt,
173 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900174 .irq_on = ata_irq_on,
175 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400176
177 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400178};
179
180static struct ata_port_operations legacy_port_ops = {
181 .set_mode = legacy_set_mode,
182
183 .port_disable = ata_port_disable,
184 .tf_load = ata_tf_load,
185 .tf_read = ata_tf_read,
186 .check_status = ata_check_status,
187 .exec_command = ata_exec_command,
188 .dev_select = ata_std_dev_select,
Jeff Garzika73984a2007-03-09 08:37:46 -0500189 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500191 .freeze = ata_bmdma_freeze,
192 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400193 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500194 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195
196 .qc_prep = ata_qc_prep,
197 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400198
Tejun Heo0d5ff562007-02-01 15:06:36 +0900199 .data_xfer = ata_data_xfer_noirq,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400200
201 .irq_handler = ata_interrupt,
202 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900203 .irq_on = ata_irq_on,
204 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400205
206 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400207};
208
209/*
210 * Promise 20230C and 20620 support
211 *
212 * This controller supports PIO0 to PIO2. We set PIO timings conservatively to
213 * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to
214 * controller and PIO'd to the host and not supported.
215 */
216
217static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
218{
219 int tries = 5;
220 int pio = adev->pio_mode - XFER_PIO_0;
221 u8 rt;
222 unsigned long flags;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400223
Jeff Garzik669a5db2006-08-29 18:12:40 -0400224 /* Safe as UP only. Force I/Os to occur together */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400225
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226 local_irq_save(flags);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400227
Jeff Garzik669a5db2006-08-29 18:12:40 -0400228 /* Unlock the control interface */
229 do
230 {
231 inb(0x1F5);
232 outb(inb(0x1F2) | 0x80, 0x1F2);
233 inb(0x1F2);
234 inb(0x3F6);
235 inb(0x3F6);
236 inb(0x1F2);
237 inb(0x1F2);
238 }
239 while((inb(0x1F2) & 0x80) && --tries);
240
241 local_irq_restore(flags);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400242
Jeff Garzik669a5db2006-08-29 18:12:40 -0400243 outb(inb(0x1F4) & 0x07, 0x1F4);
244
245 rt = inb(0x1F3);
246 rt &= 0x07 << (3 * adev->devno);
247 if (pio)
248 rt |= (1 + 3 * pio) << (3 * adev->devno);
249
250 udelay(100);
251 outb(inb(0x1F2) | 0x01, 0x1F2);
252 udelay(100);
253 inb(0x1F5);
254
255}
256
257static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data)
258{
259 struct ata_port *ap = adev->ap;
260 int slop = buflen & 3;
261 unsigned long flags;
262
263 if (ata_id_has_dword_io(adev->id)) {
264 local_irq_save(flags);
265
266 /* Perform the 32bit I/O synchronization sequence */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900267 ioread8(ap->ioaddr.nsect_addr);
268 ioread8(ap->ioaddr.nsect_addr);
269 ioread8(ap->ioaddr.nsect_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400270
271 /* Now the data */
272
273 if (write_data)
Tejun Heo0d5ff562007-02-01 15:06:36 +0900274 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400275 else
Tejun Heo0d5ff562007-02-01 15:06:36 +0900276 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400277
278 if (unlikely(slop)) {
279 u32 pad;
280 if (write_data) {
281 memcpy(&pad, buf + buflen - slop, slop);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900282 pad = le32_to_cpu(pad);
283 iowrite32(pad, ap->ioaddr.data_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284 } else {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900285 pad = ioread32(ap->ioaddr.data_addr);
286 pad = cpu_to_le16(pad);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287 memcpy(buf + buflen - slop, &pad, slop);
288 }
289 }
290 local_irq_restore(flags);
291 }
292 else
Tejun Heo0d5ff562007-02-01 15:06:36 +0900293 ata_data_xfer_noirq(adev, buf, buflen, write_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294}
295
296static struct ata_port_operations pdc20230_port_ops = {
297 .set_piomode = pdc20230_set_piomode,
298
299 .port_disable = ata_port_disable,
300 .tf_load = ata_tf_load,
301 .tf_read = ata_tf_read,
302 .check_status = ata_check_status,
303 .exec_command = ata_exec_command,
304 .dev_select = ata_std_dev_select,
305
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500306 .freeze = ata_bmdma_freeze,
307 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400308 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500309 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500310 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400311
312 .qc_prep = ata_qc_prep,
313 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400314
Jeff Garzik669a5db2006-08-29 18:12:40 -0400315 .data_xfer = pdc_data_xfer_vlb,
316
317 .irq_handler = ata_interrupt,
318 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900319 .irq_on = ata_irq_on,
320 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321
322 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400323};
324
325/*
326 * Holtek 6560A support
327 *
328 * This controller supports PIO0 to PIO2 (no IORDY even though higher timings
329 * can be loaded).
330 */
331
332static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
333{
334 u8 active, recover;
335 struct ata_timing t;
336
337 /* Get the timing data in cycles. For now play safe at 50Mhz */
338 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
339
340 active = FIT(t.active, 2, 15);
341 recover = FIT(t.recover, 4, 15);
342
343 inb(0x3E6);
344 inb(0x3E6);
345 inb(0x3E6);
346 inb(0x3E6);
347
Tejun Heo0d5ff562007-02-01 15:06:36 +0900348 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
349 ioread8(ap->ioaddr.status_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400350}
351
352static struct ata_port_operations ht6560a_port_ops = {
353 .set_piomode = ht6560a_set_piomode,
354
355 .port_disable = ata_port_disable,
356 .tf_load = ata_tf_load,
357 .tf_read = ata_tf_read,
358 .check_status = ata_check_status,
359 .exec_command = ata_exec_command,
360 .dev_select = ata_std_dev_select,
361
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500362 .freeze = ata_bmdma_freeze,
363 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500365 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500366 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400367
368 .qc_prep = ata_qc_prep,
369 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400370
Tejun Heo0d5ff562007-02-01 15:06:36 +0900371 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400372
373 .irq_handler = ata_interrupt,
374 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900375 .irq_on = ata_irq_on,
376 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400377
378 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379};
380
381/*
382 * Holtek 6560B support
383 *
384 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting
385 * unless we see an ATAPI device in which case we force it off.
386 *
387 * FIXME: need to implement 2nd channel support.
388 */
389
390static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
391{
392 u8 active, recover;
393 struct ata_timing t;
394
395 /* Get the timing data in cycles. For now play safe at 50Mhz */
396 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
397
398 active = FIT(t.active, 2, 15);
399 recover = FIT(t.recover, 2, 16);
400 recover &= 0x15;
401
402 inb(0x3E6);
403 inb(0x3E6);
404 inb(0x3E6);
405 inb(0x3E6);
406
Tejun Heo0d5ff562007-02-01 15:06:36 +0900407 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400408
409 if (adev->class != ATA_DEV_ATA) {
410 u8 rconf = inb(0x3E6);
411 if (rconf & 0x24) {
412 rconf &= ~ 0x24;
413 outb(rconf, 0x3E6);
414 }
415 }
Tejun Heo0d5ff562007-02-01 15:06:36 +0900416 ioread8(ap->ioaddr.status_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400417}
418
419static struct ata_port_operations ht6560b_port_ops = {
420 .set_piomode = ht6560b_set_piomode,
421
422 .port_disable = ata_port_disable,
423 .tf_load = ata_tf_load,
424 .tf_read = ata_tf_read,
425 .check_status = ata_check_status,
426 .exec_command = ata_exec_command,
427 .dev_select = ata_std_dev_select,
428
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500429 .freeze = ata_bmdma_freeze,
430 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400431 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500432 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500433 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400434
435 .qc_prep = ata_qc_prep,
436 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400437
Tejun Heo0d5ff562007-02-01 15:06:36 +0900438 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400439
440 .irq_handler = ata_interrupt,
441 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900442 .irq_on = ata_irq_on,
443 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400444
445 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400446};
447
448/*
449 * Opti core chipset helpers
450 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400451
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452/**
453 * opti_syscfg - read OPTI chipset configuration
454 * @reg: Configuration register to read
455 *
456 * Returns the value of an OPTI system board configuration register.
457 */
458
459static u8 opti_syscfg(u8 reg)
460{
461 unsigned long flags;
462 u8 r;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400463
Jeff Garzik669a5db2006-08-29 18:12:40 -0400464 /* Uniprocessor chipset and must force cycles adjancent */
465 local_irq_save(flags);
466 outb(reg, 0x22);
467 r = inb(0x24);
468 local_irq_restore(flags);
469 return r;
470}
471
472/*
473 * Opti 82C611A
474 *
475 * This controller supports PIO0 to PIO3.
476 */
477
478static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev)
479{
480 u8 active, recover, setup;
481 struct ata_timing t;
482 struct ata_device *pair = ata_dev_pair(adev);
483 int clock;
484 int khz[4] = { 50000, 40000, 33000, 25000 };
485 u8 rc;
486
487 /* Enter configuration mode */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900488 ioread16(ap->ioaddr.error_addr);
489 ioread16(ap->ioaddr.error_addr);
490 iowrite8(3, ap->ioaddr.nsect_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400491
492 /* Read VLB clock strapping */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900493 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400494
495 /* Get the timing data in cycles */
496 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
497
498 /* Setup timing is shared */
499 if (pair) {
500 struct ata_timing tp;
501 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
502
503 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
504 }
505
506 active = FIT(t.active, 2, 17) - 2;
507 recover = FIT(t.recover, 1, 16) - 1;
508 setup = FIT(t.setup, 1, 4) - 1;
509
510 /* Select the right timing bank for write timing */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900511 rc = ioread8(ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400512 rc &= 0x7F;
513 rc |= (adev->devno << 7);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900514 iowrite8(rc, ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400515
516 /* Write the timings */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900517 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400518
519 /* Select the right bank for read timings, also
520 load the shared timings for address */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900521 rc = ioread8(ap->ioaddr.device_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400522 rc &= 0xC0;
523 rc |= adev->devno; /* Index select */
524 rc |= (setup << 4) | 0x04;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900525 iowrite8(rc, ap->ioaddr.device_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526
527 /* Load the read timings */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900528 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400529
530 /* Ensure the timing register mode is right */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900531 rc = ioread8(ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400532 rc &= 0x73;
533 rc |= 0x84;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900534 iowrite8(rc, ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400535
536 /* Exit command mode */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900537 iowrite8(0x83, ap->ioaddr.nsect_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400538}
539
540
541static struct ata_port_operations opti82c611a_port_ops = {
542 .set_piomode = opti82c611a_set_piomode,
543
544 .port_disable = ata_port_disable,
545 .tf_load = ata_tf_load,
546 .tf_read = ata_tf_read,
547 .check_status = ata_check_status,
548 .exec_command = ata_exec_command,
549 .dev_select = ata_std_dev_select,
550
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500551 .freeze = ata_bmdma_freeze,
552 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400553 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500554 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500555 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400556
557 .qc_prep = ata_qc_prep,
558 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400559
Tejun Heo0d5ff562007-02-01 15:06:36 +0900560 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400561
562 .irq_handler = ata_interrupt,
563 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900564 .irq_on = ata_irq_on,
565 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400566
567 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400568};
569
570/*
571 * Opti 82C465MV
572 *
573 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
574 * version is dual channel but doesn't have a lot of unique registers.
575 */
576
577static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
578{
579 u8 active, recover, setup;
580 struct ata_timing t;
581 struct ata_device *pair = ata_dev_pair(adev);
582 int clock;
583 int khz[4] = { 50000, 40000, 33000, 25000 };
584 u8 rc;
585 u8 sysclk;
586
587 /* Get the clock */
588 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
589
590 /* Enter configuration mode */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900591 ioread16(ap->ioaddr.error_addr);
592 ioread16(ap->ioaddr.error_addr);
593 iowrite8(3, ap->ioaddr.nsect_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400594
595 /* Read VLB clock strapping */
596 clock = 1000000000 / khz[sysclk];
597
598 /* Get the timing data in cycles */
599 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
600
601 /* Setup timing is shared */
602 if (pair) {
603 struct ata_timing tp;
604 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
605
606 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
607 }
608
609 active = FIT(t.active, 2, 17) - 2;
610 recover = FIT(t.recover, 1, 16) - 1;
611 setup = FIT(t.setup, 1, 4) - 1;
612
613 /* Select the right timing bank for write timing */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900614 rc = ioread8(ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400615 rc &= 0x7F;
616 rc |= (adev->devno << 7);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900617 iowrite8(rc, ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400618
619 /* Write the timings */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900620 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400621
622 /* Select the right bank for read timings, also
623 load the shared timings for address */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900624 rc = ioread8(ap->ioaddr.device_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400625 rc &= 0xC0;
626 rc |= adev->devno; /* Index select */
627 rc |= (setup << 4) | 0x04;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900628 iowrite8(rc, ap->ioaddr.device_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400629
630 /* Load the read timings */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900631 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400632
633 /* Ensure the timing register mode is right */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900634 rc = ioread8(ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400635 rc &= 0x73;
636 rc |= 0x84;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900637 iowrite8(rc, ap->ioaddr.lbal_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400638
639 /* Exit command mode */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900640 iowrite8(0x83, ap->ioaddr.nsect_addr);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400641
642 /* We need to know this for quad device on the MVB */
643 ap->host->private_data = ap;
644}
645
646/**
647 * opt82c465mv_qc_issue_prot - command issue
648 * @qc: command pending
649 *
650 * Called when the libata layer is about to issue a command. We wrap
651 * this interface so that we can load the correct ATA timings. The
652 * MVB has a single set of timing registers and these are shared
653 * across channels. As there are two registers we really ought to
654 * track the last two used values as a sort of register window. For
655 * now we just reload on a channel switch. On the single channel
656 * setup this condition never fires so we do nothing extra.
657 *
658 * FIXME: dual channel needs ->serialize support
659 */
660
661static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
662{
663 struct ata_port *ap = qc->ap;
664 struct ata_device *adev = qc->dev;
665
666 /* If timings are set and for the wrong channel (2nd test is
667 due to a libata shortcoming and will eventually go I hope) */
668 if (ap->host->private_data != ap->host
669 && ap->host->private_data != NULL)
670 opti82c46x_set_piomode(ap, adev);
671
672 return ata_qc_issue_prot(qc);
673}
674
675static struct ata_port_operations opti82c46x_port_ops = {
676 .set_piomode = opti82c46x_set_piomode,
677
678 .port_disable = ata_port_disable,
679 .tf_load = ata_tf_load,
680 .tf_read = ata_tf_read,
681 .check_status = ata_check_status,
682 .exec_command = ata_exec_command,
683 .dev_select = ata_std_dev_select,
684
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500685 .freeze = ata_bmdma_freeze,
686 .thaw = ata_bmdma_thaw,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400687 .error_handler = ata_bmdma_error_handler,
Jeff Garzikbf7551c2007-03-02 18:09:05 -0500688 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500689 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400690
691 .qc_prep = ata_qc_prep,
692 .qc_issue = opti82c46x_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400693
Tejun Heo0d5ff562007-02-01 15:06:36 +0900694 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400695
696 .irq_handler = ata_interrupt,
697 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900698 .irq_on = ata_irq_on,
699 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400700
701 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400702};
703
704
705/**
706 * legacy_init_one - attach a legacy interface
707 * @port: port number
708 * @io: I/O port start
709 * @ctrl: control port
710 * @irq: interrupt line
711 *
712 * Register an ISA bus IDE interface. Such interfaces are PIO and we
713 * assume do not support IRQ sharing.
714 */
715
716static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq)
717{
718 struct legacy_data *ld = &legacy_data[nr_legacy_host];
Tejun Heo5d728822007-04-17 23:44:08 +0900719 struct ata_host *host;
720 struct ata_port *ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400721 struct platform_device *pdev;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400722 struct ata_port_operations *ops = &legacy_port_ops;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900723 void __iomem *io_addr, *ctrl_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400724 int pio_modes = pio_mask;
725 u32 mask = (1 << port);
Alan Coxf834e492007-02-07 13:46:00 -0800726 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
Tejun Heo24dc5f32007-01-20 16:00:28 +0900727 int ret;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400728
729 pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0);
Tejun Heo24dc5f32007-01-20 16:00:28 +0900730 if (IS_ERR(pdev))
731 return PTR_ERR(pdev);
732
733 ret = -EBUSY;
734 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
735 devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL)
736 goto fail;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400737
Tejun Heo0d5ff562007-02-01 15:06:36 +0900738 ret = -ENOMEM;
739 io_addr = devm_ioport_map(&pdev->dev, io, 8);
740 ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1);
741 if (!io_addr || !ctrl_addr)
742 goto fail;
743
Jeff Garzik669a5db2006-08-29 18:12:40 -0400744 if (ht6560a & mask) {
745 ops = &ht6560a_port_ops;
746 pio_modes = 0x07;
Alan Coxf834e492007-02-07 13:46:00 -0800747 iordy = ATA_FLAG_NO_IORDY;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400748 }
749 if (ht6560b & mask) {
750 ops = &ht6560b_port_ops;
751 pio_modes = 0x1F;
752 }
753 if (opti82c611a & mask) {
754 ops = &opti82c611a_port_ops;
755 pio_modes = 0x0F;
756 }
757 if (opti82c46x & mask) {
758 ops = &opti82c46x_port_ops;
759 pio_modes = 0x0F;
760 }
761
762 /* Probe for automatically detectable controllers */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400763
Jeff Garzik669a5db2006-08-29 18:12:40 -0400764 if (io == 0x1F0 && ops == &legacy_port_ops) {
765 unsigned long flags;
766
767 local_irq_save(flags);
768
769 /* Probes */
770 inb(0x1F5);
771 outb(inb(0x1F2) | 0x80, 0x1F2);
772 inb(0x1F2);
773 inb(0x3F6);
774 inb(0x3F6);
775 inb(0x1F2);
776 inb(0x1F2);
777
778 if ((inb(0x1F2) & 0x80) == 0) {
779 /* PDC20230c or 20630 ? */
780 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n");
781 pio_modes = 0x07;
782 ops = &pdc20230_port_ops;
Alan Coxf834e492007-02-07 13:46:00 -0800783 iordy = ATA_FLAG_NO_IORDY;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400784 udelay(100);
785 inb(0x1F5);
786 } else {
787 outb(0x55, 0x1F2);
788 inb(0x1F2);
789 inb(0x1F2);
790 if (inb(0x1F2) == 0x00) {
791 printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n");
792 }
793 }
794 local_irq_restore(flags);
795 }
796
797
798 /* Chip does mode setting by command snooping */
799 if (ops == &legacy_port_ops && (autospeed & mask))
800 ops = &simple_port_ops;
Alan Coxf834e492007-02-07 13:46:00 -0800801
Tejun Heo5d728822007-04-17 23:44:08 +0900802 ret = -ENOMEM;
803 host = ata_host_alloc(&pdev->dev, 1);
804 if (!host)
805 goto fail;
806 ap = host->ports[0];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400807
Tejun Heo5d728822007-04-17 23:44:08 +0900808 ap->ops = ops;
809 ap->pio_mask = pio_modes;
810 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
811 ap->ioaddr.cmd_addr = io_addr;
812 ap->ioaddr.altstatus_addr = ctrl_addr;
813 ap->ioaddr.ctl_addr = ctrl_addr;
814 ata_std_ports(&ap->ioaddr);
815 ap->private_data = ld;
816
817 ret = ata_host_activate(host, irq, ata_interrupt, 0, &legacy_sht);
818 if (ret)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400819 goto fail;
Tejun Heo24dc5f32007-01-20 16:00:28 +0900820
Jeff Garzik669a5db2006-08-29 18:12:40 -0400821 legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev);
822 ld->platform_dev = pdev;
823 return 0;
824
825fail:
826 platform_device_unregister(pdev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400827 return ret;
828}
829
830/**
831 * legacy_check_special_cases - ATA special cases
832 * @p: PCI device to check
833 * @master: set this if we find an ATA master
834 * @master: set this if we find an ATA secondary
835 *
836 * A small number of vendors implemented early PCI ATA interfaces on bridge logic
837 * without the ATA interface being PCI visible. Where we have a matching PCI driver
838 * we must skip the relevant device here. If we don't know about it then the legacy
839 * driver is the right driver anyway.
840 */
841
842static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary)
843{
844 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
845 if (p->vendor == 0x1078 && p->device == 0x0000) {
846 *primary = *secondary = 1;
847 return;
848 }
849 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
850 if (p->vendor == 0x1078 && p->device == 0x0002) {
851 *primary = *secondary = 1;
852 return;
853 }
854 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
855 if (p->vendor == 0x8086 && p->device == 0x1234) {
856 u16 r;
857 pci_read_config_word(p, 0x6C, &r);
858 if (r & 0x8000) { /* ATA port enabled */
859 if (r & 0x4000)
860 *secondary = 1;
861 else
862 *primary = 1;
863 }
864 return;
865 }
866}
867
868
869/**
870 * legacy_init - attach legacy interfaces
871 *
872 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
873 * Right now we do not scan the ide0 and ide1 address but should do so
874 * for non PCI systems or systems with no PCI IDE legacy mode devices.
875 * If you fix that note there are special cases to consider like VLB
876 * drivers and CS5510/20.
877 */
878
879static __init int legacy_init(void)
880{
881 int i;
882 int ct = 0;
883 int primary = 0;
884 int secondary = 0;
885 int last_port = NR_HOST;
886
887 struct pci_dev *p = NULL;
888
889 for_each_pci_dev(p) {
890 int r;
891 /* Check for any overlap of the system ATA mappings. Native mode controllers
892 stuck on these addresses or some devices in 'raid' mode won't be found by
893 the storage class test */
894 for (r = 0; r < 6; r++) {
895 if (pci_resource_start(p, r) == 0x1f0)
896 primary = 1;
897 if (pci_resource_start(p, r) == 0x170)
898 secondary = 1;
899 }
900 /* Check for special cases */
901 legacy_check_special_cases(p, &primary, &secondary);
902
903 /* If PCI bus is present then don't probe for tertiary legacy ports */
904 if (probe_all == 0)
905 last_port = 2;
906 }
907
Jeff Garzik85cd7252006-08-31 00:03:49 -0400908 /* If an OPTI 82C46X is present find out where the channels are */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400909 if (opti82c46x) {
910 static const char *optis[4] = {
911 "3/463MV", "5MV",
912 "5MVA", "5MVB"
913 };
914 u8 chans = 1;
915 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400916
Jeff Garzik669a5db2006-08-29 18:12:40 -0400917 opti82c46x = 3; /* Assume master and slave first */
918 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
919 if (ctrl == 3)
920 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
921 ctrl = opti_syscfg(0xAC);
922 /* Check enabled and this port is the 465MV port. On the
923 MVB we may have two channels */
924 if (ctrl & 8) {
925 if (ctrl & 4)
926 opti82c46x = 2; /* Slave */
927 else
928 opti82c46x = 1; /* Master */
929 if (chans == 2)
930 opti82c46x = 3; /* Master and Slave */
931 } /* Slave only */
932 else if (chans == 1)
933 opti82c46x = 1;
934 }
935
936 for (i = 0; i < last_port; i++) {
937 /* Skip primary if we have seen a PCI one */
938 if (i == 0 && primary == 1)
939 continue;
940 /* Skip secondary if we have seen a PCI one */
941 if (i == 1 && secondary == 1)
942 continue;
943 if (legacy_init_one(i, legacy_port[i],
944 legacy_port[i] + 0x0206,
945 legacy_irq[i]) == 0)
946 ct++;
947 }
948 if (ct != 0)
949 return 0;
950 return -ENODEV;
951}
952
953static __exit void legacy_exit(void)
954{
955 int i;
956
957 for (i = 0; i < nr_legacy_host; i++) {
958 struct legacy_data *ld = &legacy_data[i];
Tejun Heo24dc5f32007-01-20 16:00:28 +0900959
960 ata_host_detach(legacy_host[i]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400961 platform_device_unregister(ld->platform_dev);
962 if (ld->timing)
963 release_region(ld->timing, 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400964 }
965}
966
967MODULE_AUTHOR("Alan Cox");
968MODULE_DESCRIPTION("low-level driver for legacy ATA");
969MODULE_LICENSE("GPL");
970MODULE_VERSION(DRV_VERSION);
971
972module_param(probe_all, int, 0);
973module_param(autospeed, int, 0);
974module_param(ht6560a, int, 0);
975module_param(ht6560b, int, 0);
976module_param(opti82c611a, int, 0);
977module_param(opti82c46x, int, 0);
978module_param(pio_mask, int, 0);
Alan Coxf834e492007-02-07 13:46:00 -0800979module_param(iordy_mask, int, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400980
981module_init(legacy_init);
982module_exit(legacy_exit);
983