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gerrit-public.fairphone.software / kernel / msm-4.9 / 9aeb7f2568b0b0de90efe7ce051509e6e37c9a93 / . / drivers / clk / msm / clock-gcc-8952.c
blob: 47619f540b5cc78896b122c81f1e85991b08e83d [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]205 F_APCS_PLL(1171200000, 61, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]206 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]207 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
208 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]209};
210
211static struct pll_clk a53ss_c0_pll = {
212 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
213 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
214 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
215 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
216 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
217 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
218 .freq_tbl = apcs_c0_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]219 .config_ctl_reg = (void __iomem *)APCS_C0_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]220 .masks = {
221 .vco_mask = BM(29, 28),
222 .pre_div_mask = BIT(12),
223 .post_div_mask = BM(9, 8),
224 .mn_en_mask = BIT(24),
225 .main_output_mask = BIT(0),
226 },
227 .base = &virt_bases[APCS_C0_PLL_BASE],
228 .spm_ctrl = {
229 .offset = 0x50,
230 .event_bit = 0x4,
231 },
232 .c = {
233 .parent = &xo_a_clk_src.c,
234 .dbg_name = "a53ss_c0_pll",
235 .ops = &clk_ops_sr2_pll,
236 .vdd_class = &vdd_sr2_pll,
237 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
238 [VDD_SR2_PLL_SVS] = 1000000000,
239 [VDD_SR2_PLL_NOM] = 1900000000,
240 },
241 .num_fmax = VDD_SR2_PLL_NUM,
242 CLK_INIT(a53ss_c0_pll.c),
243 },
244};
245
246static struct pll_freq_tbl apcs_c1_pll_freq[] = {
247 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
263 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]264 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]265 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
269 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
270 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
271 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
272 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
273 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]274 F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
275 F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),
276 F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]277};
278
279static struct pll_clk a53ss_c1_pll = {
280 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
281 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
282 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
283 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
284 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
285 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
286 .freq_tbl = apcs_c1_pll_freq,
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]287 .config_ctl_reg = (void __iomem *)APCS_C1_PLL_CONFIG_CTL,
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]288 .masks = {
289 .vco_mask = BM(29, 28),
290 .pre_div_mask = BIT(12),
291 .post_div_mask = BM(9, 8),
292 .mn_en_mask = BIT(24),
293 .main_output_mask = BIT(0),
294 },
295 .base = &virt_bases[APCS_C1_PLL_BASE],
296 .spm_ctrl = {
297 .offset = 0x50,
298 .event_bit = 0x4,
299 },
300 .c = {
301 .parent = &xo_a_clk_src.c,
302 .dbg_name = "a53ss_c1_pll",
303 .ops = &clk_ops_sr2_pll,
304 .vdd_class = &vdd_hf_pll,
305 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
306 [VDD_HF_PLL_SVS] = 1000000000,
307 [VDD_HF_PLL_NOM] = 2000000000,
308 },
309 .num_fmax = VDD_HF_PLL_NUM,
310 CLK_INIT(a53ss_c1_pll.c),
311 },
312};
313
314static struct pll_vote_clk gpll0_sleep_clk_src = {
315 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
316 .en_mask = BIT(23),
317 .status_reg = (void __iomem *)GPLL0_MODE,
318 .status_mask = BIT(30),
319 .base = &virt_bases[GCC_BASE],
320 .c = {
321 .parent = &xo_clk_src.c,
322 .rate = 800000000,
323 .dbg_name = "gpll0_sleep_clk_src",
324 .ops = &clk_ops_pll_sleep_vote,
325 CLK_INIT(gpll0_sleep_clk_src.c),
326 },
327};
328
329static unsigned int soft_vote_gpll0;
330
331/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
332 * gets set from PLL voting FSM.It indicates when
333 * FSM has enabled the PLL and PLL should be locked.
334 */
335static struct pll_vote_clk gpll0_clk_src_8952 = {
336 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
337 .en_mask = BIT(0),
338 .status_reg = (void __iomem *)GPLL0_STATUS,
339 .status_mask = BIT(17),
340 .soft_vote = &soft_vote_gpll0,
341 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
342 .base = &virt_bases[GCC_BASE],
343 .c = {
344 .parent = &xo_clk_src.c,
345 .rate = 800000000,
346 .dbg_name = "gpll0_clk_src_8952",
347 .ops = &clk_ops_pll_acpu_vote,
348 CLK_INIT(gpll0_clk_src_8952.c),
349 },
350};
351
352static struct pll_vote_clk gpll0_clk_src_8937 = {
353 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
354 .en_mask = BIT(0),
355 .status_reg = (void __iomem *)GPLL0_MODE,
356 .status_mask = BIT(30),
357 .soft_vote = &soft_vote_gpll0,
358 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
359 .base = &virt_bases[GCC_BASE],
360 .c = {
361 .parent = &gpll0_sleep_clk_src.c,
362 .rate = 800000000,
363 .dbg_name = "gpll0_clk_src_8937",
364 .ops = &clk_ops_pll_acpu_vote,
365 CLK_INIT(gpll0_clk_src_8937.c),
366 },
367};
368
369DEFINE_EXT_CLK(gpll0_clk_src, NULL);
370DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
371DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
372DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
373DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
374DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
375DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
376DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
377
378/* Don't vote for xo if using this clock to allow xo shutdown */
379static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
380 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
381 .en_mask = BIT(0),
382 .status_reg = (void __iomem *)GPLL0_STATUS,
383 .status_mask = BIT(17),
384 .soft_vote = &soft_vote_gpll0,
385 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
386 .base = &virt_bases[GCC_BASE],
387 .c = {
388 .parent = &xo_a_clk_src.c,
389 .rate = 800000000,
390 .dbg_name = "gpll0_ao_clk_src_8952",
391 .ops = &clk_ops_pll_acpu_vote,
392 CLK_INIT(gpll0_ao_clk_src_8952.c),
393 },
394};
395
396static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
397 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
398 .en_mask = BIT(0),
399 .status_reg = (void __iomem *)GPLL0_MODE,
400 .status_mask = BIT(30),
401 .soft_vote = &soft_vote_gpll0,
402 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
403 .base = &virt_bases[GCC_BASE],
404 .c = {
405 .parent = &xo_a_clk_src.c,
406 .rate = 800000000,
407 .dbg_name = "gpll0_ao_clk_src_8937",
408 .ops = &clk_ops_pll_acpu_vote,
409 CLK_INIT(gpll0_ao_clk_src_8937.c),
410 },
411};
412
413static struct pll_vote_clk gpll6_clk_src = {
414 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
415 .en_mask = BIT(7),
416 .status_reg = (void __iomem *)GPLL6_STATUS,
417 .status_mask = BIT(17),
418 .base = &virt_bases[GCC_BASE],
419 .c = {
420 .parent = &xo_clk_src.c,
421 .rate = 1080000000,
422 .dbg_name = "gpll6_clk_src",
423 .ops = &clk_ops_pll_vote,
424 CLK_INIT(gpll6_clk_src.c),
425 },
426};
427
428DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
429DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
430
431static struct alpha_pll_masks pll_masks_p = {
432 .lock_mask = BIT(31),
433 .active_mask = BIT(30),
434 .vco_mask = BM(21, 20) >> 20,
435 .vco_shift = 20,
436 .alpha_en_mask = BIT(24),
437 .output_mask = 0xf,
438 .update_mask = BIT(22),
439 .post_div_mask = BM(11, 8),
440 .test_ctl_lo_mask = BM(31, 0),
441 .test_ctl_hi_mask = BM(31, 0),
442};
443
444/* Slewing plls won't allow to change vco_sel.
445 * Hence will have only one vco table entry
446 */
447static struct alpha_pll_vco_tbl p_vco[] = {
448 VCO(0, 700000000, 1400000000),
449};
450
451/* Slewing plls won't allow to change vco_sel.
452 * Hence will have only one vco table entry
453 */
454static struct alpha_pll_vco_tbl p_vco_8937[] = {
455 VCO(1, 525000000, 1066000000),
456};
457
458static struct alpha_pll_clk gpll3_clk_src = {
459 .masks = &pll_masks_p,
460 .base = &virt_bases[GCC_BASE],
461 .offset = GPLL3_MODE,
462 .vco_tbl = p_vco,
463 .num_vco = ARRAY_SIZE(p_vco),
464 .enable_config = 1,
465 /*
466 * gpll3 is dedicated to oxili and has a fuse implementation for
467 * post divider to limit frequency. HW with fuse blown has a divider
468 * value set to 2. So lets stick to divide by 2 in software to avoid
469 * conflicts.
470 */
471 .post_div_config = 1 << 8,
472 .slew = true,
473 .config_ctl_val = 0x4001055b,
474 .test_ctl_hi_val = 0x40000600,
475 .c = {
476 .rate = 1050000000,
477 .parent = &xo_clk_src.c,
478 .dbg_name = "gpll3_clk_src",
479 .ops = &clk_ops_dyna_alpha_pll,
480 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
481 CLK_INIT(gpll3_clk_src.c),
482 },
483};
484
485static struct pll_vote_clk gpll4_clk_src = {
486 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
487 .en_mask = BIT(5),
488 .status_reg = (void __iomem *)GPLL4_MODE,
489 .status_mask = BIT(30),
490 .base = &virt_bases[GCC_BASE],
491 .c = {
492 .rate = 1152000000,
493 .parent = &xo_clk_src.c,
494 .dbg_name = "gpll4_clk_src",
495 .ops = &clk_ops_pll_vote,
496 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
497 CLK_INIT(gpll4_clk_src.c),
498 },
499};
500DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
501
502static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
503 F( 40000000, gpll0, 10, 1, 2),
504 F( 61540000, gpll0, 13, 0, 0),
505 F( 80000000, gpll0, 10, 0, 0),
506 F_END
507};
508
509static struct rcg_clk camss_top_ahb_clk_src = {
510 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
511 .set_rate = set_rate_mnd,
512 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
513 .current_freq = &rcg_dummy_freq,
514 .base = &virt_bases[GCC_BASE],
515 .c = {
516 .dbg_name = "camss_top_ahb_clk_src",
517 .ops = &clk_ops_rcg_mnd,
518 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
519 NOMINAL, 80000000),
520 CLK_INIT(camss_top_ahb_clk_src.c),
521 },
522};
523
524static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
525 F( 19200000, xo_a, 1, 0, 0),
526 F( 50000000, gpll0, 16, 0, 0),
527 F( 100000000, gpll0, 8, 0, 0),
528 F( 133330000, gpll0, 6, 0, 0),
529 F_END
530};
531
532static struct rcg_clk apss_ahb_clk_src = {
533 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
534 .set_rate = set_rate_hid,
535 .freq_tbl = ftbl_gcc_apss_ahb_clk,
536 .current_freq = &rcg_dummy_freq,
537 .base = &virt_bases[GCC_BASE],
538 .c = {
539 .dbg_name = "apss_ahb_clk_src",
540 .ops = &clk_ops_rcg,
541 CLK_INIT(apss_ahb_clk_src.c),
542 },
543};
544
545static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
546 F( 100000000, gpll0, 8, 0, 0),
547 F( 160000000, gpll0, 5, 0, 0),
548 F( 200000000, gpll0, 4, 0, 0),
549 F_END
550};
551
552static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
553 F( 100000000, gpll0, 8, 0, 0),
554 F( 160000000, gpll0, 5, 0, 0),
555 F( 200000000, gpll0, 4, 0, 0),
556 F( 266670000, gpll0, 3, 0, 0),
557 F_END
558};
559
560
561static struct rcg_clk csi0_clk_src = {
562 .cmd_rcgr_reg = CSI0_CMD_RCGR,
563 .set_rate = set_rate_hid,
564 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
565 .current_freq = &rcg_dummy_freq,
566 .base = &virt_bases[GCC_BASE],
567 .c = {
568 .dbg_name = "csi0_clk_src",
569 .ops = &clk_ops_rcg,
570 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
571 NOMINAL, 200000000),
572 CLK_INIT(csi0_clk_src.c),
573 },
574};
575
576static struct rcg_clk csi1_clk_src = {
577 .cmd_rcgr_reg = CSI1_CMD_RCGR,
578 .set_rate = set_rate_hid,
579 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
580 .current_freq = &rcg_dummy_freq,
581 .base = &virt_bases[GCC_BASE],
582 .c = {
583 .dbg_name = "csi1_clk_src",
584 .ops = &clk_ops_rcg,
585 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
586 NOMINAL, 200000000),
587 CLK_INIT(csi1_clk_src.c),
588 },
589};
590
591static struct rcg_clk csi2_clk_src = {
592 .cmd_rcgr_reg = CSI2_CMD_RCGR,
593 .set_rate = set_rate_hid,
594 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
595 .current_freq = &rcg_dummy_freq,
596 .base = &virt_bases[GCC_BASE],
597 .c = {
598 .dbg_name = "csi2_clk_src",
599 .ops = &clk_ops_rcg,
600 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
601 NOMINAL, 200000000),
602 CLK_INIT(csi2_clk_src.c),
603 },
604};
605
606static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
607 F( 133330000, gpll0, 6, 0, 0),
608 F( 180000000, gpll6, 6, 0, 0),
609 F( 228570000, gpll0, 3.5, 0, 0),
610 F( 266670000, gpll0, 3, 0, 0),
611 F( 308570000, gpll6, 3.5, 0, 0),
612 F_END
613};
614
615static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
616 F( 166150000, gpll6, 6.5, 0, 0),
617 F( 240000000, gpll6, 4.5, 0, 0),
618 F( 308570000, gpll6, 3.5, 0, 0),
619 F( 320000000, gpll0, 2.5, 0, 0),
620 F( 360000000, gpll6, 3, 0, 0),
621 F_END
622};
623
624static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
625 F( 160000000, gpll0, 5, 0, 0),
626 F( 200000000, gpll0, 4, 0, 0),
627 F( 270000000, gpll6, 4, 0, 0),
628 F( 308570000, gpll6, 3.5, 0, 0),
629 F( 329140000, gpll4_out, 3.5, 0, 0),
630 F( 360000000, gpll6, 3, 0, 0),
631 F_END
632};
633
634static struct rcg_clk vcodec0_clk_src = {
635 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
636 .set_rate = set_rate_mnd,
637 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
638 .current_freq = &rcg_dummy_freq,
639 .base = &virt_bases[GCC_BASE],
640 .c = {
641 .dbg_name = "vcodec0_clk_src",
642 .ops = &clk_ops_rcg_mnd,
643 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
644 NOMINAL, 228570000, NOM_PLUS, 266670000,
645 HIGH, 308570000),
646 CLK_INIT(vcodec0_clk_src.c),
647 },
648};
649
650static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
651 F( 50000000, gpll0, 16, 0, 0),
652 F( 80000000, gpll0, 10, 0, 0),
653 F( 100000000, gpll0, 8, 0, 0),
654 F( 133330000, gpll0, 6, 0, 0),
655 F( 160000000, gpll0, 5, 0, 0),
656 F( 177780000, gpll0, 4.5, 0, 0),
657 F( 200000000, gpll0, 4, 0, 0),
658 F( 266670000, gpll0, 3, 0, 0),
659 F( 308570000, gpll6, 3.5, 0, 0),
660 F( 320000000, gpll0, 2.5, 0, 0),
661 F( 360000000, gpll6, 3, 0, 0),
662 F_END
663};
664
665static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
666 F( 50000000, gpll0, 16, 0, 0),
667 F( 80000000, gpll0, 10, 0, 0),
668 F( 100000000, gpll0, 8, 0, 0),
669 F( 133333333, gpll0, 6, 0, 0),
670 F( 160000000, gpll0, 5, 0, 0),
671 F( 177780000, gpll0, 4.5, 0, 0),
672 F( 200000000, gpll0, 4, 0, 0),
673 F( 266670000, gpll0, 3, 0, 0),
674 F( 308570000, gpll6, 3.5, 0, 0),
675 F( 320000000, gpll0, 2.5, 0, 0),
676 F( 360000000, gpll6, 3, 0, 0),
677 F( 400000000, gpll0, 2, 0, 0),
678 F( 432000000, gpll6, 2.5, 0, 0),
679 F_END
680};
681
682static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
683 F( 50000000, gpll0, 16, 0, 0),
684 F( 80000000, gpll0, 10, 0, 0),
685 F( 100000000, gpll0, 8, 0, 0),
686 F( 133333333, gpll0, 6, 0, 0),
687 F( 160000000, gpll0, 5, 0, 0),
688 F( 177780000, gpll0, 4.5, 0, 0),
689 F( 200000000, gpll0, 4, 0, 0),
690 F( 266670000, gpll0, 3, 0, 0),
691 F( 308570000, gpll6, 3.5, 0, 0),
692 F( 320000000, gpll0, 2.5, 0, 0),
693 F( 329140000, gpll4_out, 3.5, 0, 0),
694 F( 360000000, gpll6, 3, 0, 0),
695 F_END
696};
697
698static struct rcg_clk vfe0_clk_src = {
699 .cmd_rcgr_reg = VFE0_CMD_RCGR,
700 .set_rate = set_rate_hid,
701 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
702 .current_freq = &rcg_dummy_freq,
703 .base = &virt_bases[GCC_BASE],
704 .c = {
705 .dbg_name = "vfe0_clk_src",
706 .ops = &clk_ops_rcg,
707 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
708 NOMINAL, 308570000, NOM_PLUS, 320000000,
709 HIGH, 360000000),
710 CLK_INIT(vfe0_clk_src.c),
711 },
712};
713
714static struct rcg_clk vfe1_clk_src = {
715 .cmd_rcgr_reg = VFE1_CMD_RCGR,
716 .set_rate = set_rate_hid,
717 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
718 .current_freq = &rcg_dummy_freq,
719 .base = &virt_bases[GCC_BASE],
720 .c = {
721 .dbg_name = "vfe1_clk_src",
722 .ops = &clk_ops_rcg,
723 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
724 NOMINAL, 308570000, NOM_PLUS, 320000000,
725 HIGH, 360000000),
726 CLK_INIT(vfe1_clk_src.c),
727 },
728};
729
730static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
731 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
732 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
733 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
734 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
735 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
736 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
737 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
738 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
739 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
740 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
741 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
742 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
743 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
744 F_END
745};
746
747static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
748 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
749 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
750 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
751 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
752 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
753 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
754 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
755 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
756 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
757 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
758 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
759 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
760 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
761 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
762 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
763 F_END
764};
765
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]766static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_sdm439[] = {
767 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
768 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
769 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
770 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
771 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
772 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
773 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
774 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
775 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
776 F_SLEW( 259200000, 1296000000, gpll3, 2.5, 0, 0),
777 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
778 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
779 F_SLEW( 355200000, 710400000, gpll3, 1, 0, 0),
780 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
781 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
782 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
783 F_SLEW( 510000000, 1020000000, gpll3, 1, 0, 0),
784 F_SLEW( 560000000, 1120000000, gpll3, 1, 0, 0),
785 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
786 F_END
787};
788
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]789static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
790 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
791 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
792 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
793 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
794 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
795 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
796 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
797 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
798 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
799 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
800 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
801 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
802 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
803 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
804 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
805 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
806 F_END
807};
808
809static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
810 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
811 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
812 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
813 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
814 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
815 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
816 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
817 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
818 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
819 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
820 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
821 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
822 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
823 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
824 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
825 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
826 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
827 F_END
828};
829
830static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
831 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
832 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
833 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
834 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
835 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
836 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
837 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
838 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
839 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
840 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
841 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
842 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
843 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
844 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
845 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
846 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
847 F_END
848};
849
850static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
851 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
852 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
853 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
854 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
855 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
856 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
857 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
858 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
859 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
860 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
861 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
862 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
863 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
864 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
865 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
866 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
867 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
868 F_END
869};
870
871static struct rcg_clk gfx3d_clk_src = {
872 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
873 .set_rate = set_rate_hid,
874 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
875 .current_freq = &rcg_dummy_freq,
876 .base = &virt_bases[GCC_BASE],
877 .c = {
878 .dbg_name = "gfx3d_clk_src",
879 .ops = &clk_ops_rcg,
880 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
881 NOMINAL, 465000000, NOM_PLUS, 500000000,
882 HIGH, 550000000),
883 CLK_INIT(gfx3d_clk_src.c),
884 },
885};
886
887static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
888 F( 19200000, xo, 1, 0, 0),
889 F( 50000000, gpll0, 16, 0, 0),
890 F_END
891};
892
893static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
894 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
895 .set_rate = set_rate_hid,
896 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
897 .current_freq = &rcg_dummy_freq,
898 .base = &virt_bases[GCC_BASE],
899 .c = {
900 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
901 .ops = &clk_ops_rcg,
902 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
903 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
904 },
905};
906
907static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
908 F( 960000, xo, 10, 1, 2),
909 F( 4800000, xo, 4, 0, 0),
910 F( 9600000, xo, 2, 0, 0),
911 F( 16000000, gpll0, 10, 1, 5),
912 F( 19200000, xo, 1, 0, 0),
913 F( 25000000, gpll0, 16, 1, 2),
914 F( 50000000, gpll0, 16, 0, 0),
915 F_END
916};
917
918static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
919 F( 960000, xo, 10, 1, 2),
920 F( 4800000, xo, 4, 0, 0),
921 F( 9600000, xo, 2, 0, 0),
922 F( 16000000, gpll0, 10, 1, 5),
923 F( 19200000, xo, 1, 0, 0),
924 F( 25000000, gpll0, 16, 1, 2),
925 F( 40000000, gpll0, 10, 1, 2),
926 F( 50000000, gpll0, 16, 0, 0),
927 F_END
928};
929
930static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
931 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
932 .set_rate = set_rate_mnd,
933 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
934 .current_freq = &rcg_dummy_freq,
935 .base = &virt_bases[GCC_BASE],
936 .c = {
937 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
938 .ops = &clk_ops_rcg_mnd,
939 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
940 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
941 },
942};
943
944static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
945 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
946 .set_rate = set_rate_hid,
947 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
948 .current_freq = &rcg_dummy_freq,
949 .base = &virt_bases[GCC_BASE],
950 .c = {
951 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
952 .ops = &clk_ops_rcg,
953 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
954 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
955 },
956};
957
958static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
959 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
960 .set_rate = set_rate_mnd,
961 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
962 .current_freq = &rcg_dummy_freq,
963 .base = &virt_bases[GCC_BASE],
964 .c = {
965 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
966 .ops = &clk_ops_rcg_mnd,
967 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
968 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
969 },
970};
971
972static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
973 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
974 .set_rate = set_rate_hid,
975 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
976 .current_freq = &rcg_dummy_freq,
977 .base = &virt_bases[GCC_BASE],
978 .c = {
979 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
980 .ops = &clk_ops_rcg,
981 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
982 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
983 },
984};
985
986static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
987 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
988 .set_rate = set_rate_mnd,
989 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
990 .current_freq = &rcg_dummy_freq,
991 .base = &virt_bases[GCC_BASE],
992 .c = {
993 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
994 .ops = &clk_ops_rcg_mnd,
995 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
996 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
997 },
998};
999
1000static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
1001 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
1002 .set_rate = set_rate_hid,
1003 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1004 .current_freq = &rcg_dummy_freq,
1005 .base = &virt_bases[GCC_BASE],
1006 .c = {
1007 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
1008 .ops = &clk_ops_rcg,
1009 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1010 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
1011 },
1012};
1013
1014static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
1015 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
1016 .set_rate = set_rate_mnd,
1017 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1018 .current_freq = &rcg_dummy_freq,
1019 .base = &virt_bases[GCC_BASE],
1020 .c = {
1021 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
1022 .ops = &clk_ops_rcg_mnd,
1023 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1024 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
1025 },
1026};
1027
1028static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
1029 F( 3686400, gpll0, 1, 72, 15625),
1030 F( 7372800, gpll0, 1, 144, 15625),
1031 F( 14745600, gpll0, 1, 288, 15625),
1032 F( 16000000, gpll0, 10, 1, 5),
1033 F( 19200000, xo, 1, 0, 0),
1034 F( 24000000, gpll0, 1, 3, 100),
1035 F( 25000000, gpll0, 16, 1, 2),
1036 F( 32000000, gpll0, 1, 1, 25),
1037 F( 40000000, gpll0, 1, 1, 20),
1038 F( 46400000, gpll0, 1, 29, 500),
1039 F( 48000000, gpll0, 1, 3, 50),
1040 F( 51200000, gpll0, 1, 8, 125),
1041 F( 56000000, gpll0, 1, 7, 100),
1042 F( 58982400, gpll0, 1, 1152, 15625),
1043 F( 60000000, gpll0, 1, 3, 40),
1044 F( 64000000, gpll0, 1, 2, 25),
1045 F_END
1046};
1047
1048static struct rcg_clk blsp1_uart1_apps_clk_src = {
1049 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1050 .set_rate = set_rate_mnd,
1051 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1052 .current_freq = &rcg_dummy_freq,
1053 .base = &virt_bases[GCC_BASE],
1054 .c = {
1055 .dbg_name = "blsp1_uart1_apps_clk_src",
1056 .ops = &clk_ops_rcg_mnd,
1057 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1058 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1059 },
1060};
1061
1062static struct rcg_clk blsp1_uart2_apps_clk_src = {
1063 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1064 .set_rate = set_rate_mnd,
1065 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1066 .current_freq = &rcg_dummy_freq,
1067 .base = &virt_bases[GCC_BASE],
1068 .c = {
1069 .dbg_name = "blsp1_uart2_apps_clk_src",
1070 .ops = &clk_ops_rcg_mnd,
1071 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1072 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1073 },
1074};
1075
1076static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1077 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1078 .set_rate = set_rate_hid,
1079 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1080 .current_freq = &rcg_dummy_freq,
1081 .base = &virt_bases[GCC_BASE],
1082 .c = {
1083 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1084 .ops = &clk_ops_rcg,
1085 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1086 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1087 },
1088};
1089
1090static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1091 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1092 .set_rate = set_rate_mnd,
1093 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1094 .current_freq = &rcg_dummy_freq,
1095 .base = &virt_bases[GCC_BASE],
1096 .c = {
1097 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1098 .ops = &clk_ops_rcg_mnd,
1099 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1100 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1101 },
1102};
1103
1104static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1105 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1106 .set_rate = set_rate_hid,
1107 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1108 .current_freq = &rcg_dummy_freq,
1109 .base = &virt_bases[GCC_BASE],
1110 .c = {
1111 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1112 .ops = &clk_ops_rcg,
1113 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1114 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1115 },
1116};
1117
1118static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1119 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1120 .set_rate = set_rate_mnd,
1121 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1122 .current_freq = &rcg_dummy_freq,
1123 .base = &virt_bases[GCC_BASE],
1124 .c = {
1125 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1126 .ops = &clk_ops_rcg_mnd,
1127 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1128 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1129 },
1130};
1131
1132static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1133 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1134 .set_rate = set_rate_hid,
1135 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1136 .current_freq = &rcg_dummy_freq,
1137 .base = &virt_bases[GCC_BASE],
1138 .c = {
1139 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1140 .ops = &clk_ops_rcg,
1141 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1142 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1143 },
1144};
1145
1146static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1147 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1148 .set_rate = set_rate_mnd,
1149 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1150 .current_freq = &rcg_dummy_freq,
1151 .base = &virt_bases[GCC_BASE],
1152 .c = {
1153 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1154 .ops = &clk_ops_rcg_mnd,
1155 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1156 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1157 },
1158};
1159
1160static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1161 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1162 .set_rate = set_rate_hid,
1163 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1164 .current_freq = &rcg_dummy_freq,
1165 .base = &virt_bases[GCC_BASE],
1166 .c = {
1167 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1168 .ops = &clk_ops_rcg,
1169 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1170 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1171 },
1172};
1173
1174static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1175 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1176 .set_rate = set_rate_mnd,
1177 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1178 .current_freq = &rcg_dummy_freq,
1179 .base = &virt_bases[GCC_BASE],
1180 .c = {
1181 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1182 .ops = &clk_ops_rcg_mnd,
1183 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1184 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1185 },
1186};
1187
1188static struct rcg_clk blsp2_uart1_apps_clk_src = {
1189 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1190 .set_rate = set_rate_mnd,
1191 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1192 .current_freq = &rcg_dummy_freq,
1193 .base = &virt_bases[GCC_BASE],
1194 .c = {
1195 .dbg_name = "blsp2_uart1_apps_clk_src",
1196 .ops = &clk_ops_rcg_mnd,
1197 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1198 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1199 },
1200};
1201
1202static struct rcg_clk blsp2_uart2_apps_clk_src = {
1203 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1204 .set_rate = set_rate_mnd,
1205 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1206 .current_freq = &rcg_dummy_freq,
1207 .base = &virt_bases[GCC_BASE],
1208 .c = {
1209 .dbg_name = "blsp2_uart2_apps_clk_src",
1210 .ops = &clk_ops_rcg_mnd,
1211 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1212 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1213 },
1214};
1215
1216static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1217 F( 19200000, xo, 1, 0, 0),
1218 F( 37500000, gpll0_out_aux, 1, 3, 64),
1219 F_END
1220};
1221
1222static struct rcg_clk cci_clk_src = {
1223 .cmd_rcgr_reg = CCI_CMD_RCGR,
1224 .set_rate = set_rate_mnd,
1225 .freq_tbl = ftbl_gcc_camss_cci_clk,
1226 .current_freq = &rcg_dummy_freq,
1227 .base = &virt_bases[GCC_BASE],
1228 .c = {
1229 .dbg_name = "cci_clk_src",
1230 .ops = &clk_ops_rcg_mnd,
1231 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1232 CLK_INIT(cci_clk_src.c),
1233 },
1234};
1235
1236static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1237 F( 133330000, gpll0, 6, 0, 0),
1238 F( 180000000, gpll6, 6, 0, 0),
1239 F( 266670000, gpll0, 3, 0, 0),
1240 F( 308570000, gpll6, 3.5, 0, 0),
1241 F( 320000000, gpll0, 2.5, 0, 0),
1242 F_END
1243};
1244
1245static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1246 F( 133333333, gpll0, 6, 0, 0),
1247 F( 160000000, gpll0, 5, 0, 0),
1248 F( 200000000, gpll0, 4, 0, 0),
1249 F( 266666667, gpll0, 3, 0, 0),
1250 F( 308570000, gpll6, 3.5, 0, 0),
1251 F( 320000000, gpll0, 2.5, 0, 0),
1252 F( 360000000, gpll6, 3, 0, 0),
1253 F_END
1254};
1255
1256static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1257 F( 133330000, gpll0, 6, 0, 0),
1258 F( 160000000, gpll0, 5, 0, 0),
1259 F( 266670000, gpll0, 3, 0, 0),
1260 F( 308570000, gpll6, 3.5, 0, 0),
1261 F( 320000000, gpll0, 2.5, 0, 0),
1262 F( 360000000, gpll6, 3, 0, 0),
1263 F_END
1264};
1265
1266static struct rcg_clk cpp_clk_src = {
1267 .cmd_rcgr_reg = CPP_CMD_RCGR,
1268 .set_rate = set_rate_hid,
1269 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1270 .current_freq = &rcg_dummy_freq,
1271 .base = &virt_bases[GCC_BASE],
1272 .c = {
1273 .dbg_name = "cpp_clk_src",
1274 .ops = &clk_ops_rcg,
1275 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1276 NOMINAL, 266670000, NOM_PLUS, 308570000,
1277 HIGH, 320000000),
1278 CLK_INIT(cpp_clk_src.c),
1279 },
1280};
1281
1282static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1283 F( 100000000, gpll0, 8, 0, 0),
1284 F( 160000000, gpll0, 5, 0, 0),
1285 F( 200000000, gpll0, 4, 0, 0),
1286 F_END
1287};
1288
1289static struct rcg_clk camss_gp0_clk_src = {
1290 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1291 .set_rate = set_rate_mnd,
1292 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1293 .current_freq = &rcg_dummy_freq,
1294 .base = &virt_bases[GCC_BASE],
1295 .c = {
1296 .dbg_name = "camss_gp0_clk_src",
1297 .ops = &clk_ops_rcg_mnd,
1298 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1299 NOMINAL, 200000000),
1300 CLK_INIT(camss_gp0_clk_src.c),
1301 },
1302};
1303
1304static struct rcg_clk camss_gp1_clk_src = {
1305 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1306 .set_rate = set_rate_mnd,
1307 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1308 .current_freq = &rcg_dummy_freq,
1309 .base = &virt_bases[GCC_BASE],
1310 .c = {
1311 .dbg_name = "camss_gp1_clk_src",
1312 .ops = &clk_ops_rcg_mnd,
1313 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1314 NOMINAL, 200000000),
1315 CLK_INIT(camss_gp1_clk_src.c),
1316 },
1317};
1318
1319static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1320 F( 133330000, gpll0, 6, 0, 0),
1321 F( 266670000, gpll0, 3, 0, 0),
1322 F( 320000000, gpll0, 2.5, 0, 0),
1323 F_END
1324};
1325
1326static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1327 F( 133333333, gpll0, 6, 0, 0),
1328 F( 200000000, gpll0, 4, 0, 0),
1329 F( 266666667, gpll0, 3, 0, 0),
1330 F( 308570000, gpll6, 3.5, 0, 0),
1331 F( 320000000, gpll0, 2.5, 0, 0),
1332 F_END
1333};
1334
1335static struct rcg_clk jpeg0_clk_src = {
1336 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1337 .set_rate = set_rate_hid,
1338 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1339 .current_freq = &rcg_dummy_freq,
1340 .base = &virt_bases[GCC_BASE],
1341 .c = {
1342 .dbg_name = "jpeg0_clk_src",
1343 .ops = &clk_ops_rcg,
1344 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1345 HIGH, 320000000),
1346 CLK_INIT(jpeg0_clk_src.c),
1347 },
1348};
1349
1350static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1351 F( 19200000, xo, 1, 0, 0),
1352 F( 24000000, gpll6, 1, 1, 45),
1353 F( 66670000, gpll0, 12, 0, 0),
1354 F_END
1355};
1356
1357static struct rcg_clk mclk0_clk_src = {
1358 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1359 .set_rate = set_rate_mnd,
1360 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1361 .current_freq = &rcg_dummy_freq,
1362 .base = &virt_bases[GCC_BASE],
1363 .c = {
1364 .dbg_name = "mclk0_clk_src",
1365 .ops = &clk_ops_rcg_mnd,
1366 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1367 CLK_INIT(mclk0_clk_src.c),
1368 },
1369};
1370
1371static struct rcg_clk mclk1_clk_src = {
1372 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1373 .set_rate = set_rate_mnd,
1374 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1375 .current_freq = &rcg_dummy_freq,
1376 .base = &virt_bases[GCC_BASE],
1377 .c = {
1378 .dbg_name = "mclk1_clk_src",
1379 .ops = &clk_ops_rcg_mnd,
1380 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1381 CLK_INIT(mclk1_clk_src.c),
1382 },
1383};
1384
1385static struct rcg_clk mclk2_clk_src = {
1386 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1387 .set_rate = set_rate_mnd,
1388 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1389 .current_freq = &rcg_dummy_freq,
1390 .base = &virt_bases[GCC_BASE],
1391 .c = {
1392 .dbg_name = "mclk2_clk_src",
1393 .ops = &clk_ops_rcg_mnd,
1394 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1395 CLK_INIT(mclk2_clk_src.c),
1396 },
1397};
1398
1399static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1400 F( 100000000, gpll0, 8, 0, 0),
1401 F( 160000000, gpll0, 5, 0, 0),
1402 F( 200000000, gpll0, 4, 0, 0),
1403 F_END
1404};
1405
1406static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1407 F( 100000000, gpll0, 8, 0, 0),
1408 F( 160000000, gpll0, 5, 0, 0),
1409 F( 200000000, gpll0, 4, 0, 0),
1410 F( 266670000, gpll0, 3, 0, 0),
1411 F_END
1412};
1413
1414static struct rcg_clk csi0phytimer_clk_src = {
1415 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1416 .set_rate = set_rate_hid,
1417 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1418 .current_freq = &rcg_dummy_freq,
1419 .base = &virt_bases[GCC_BASE],
1420 .c = {
1421 .dbg_name = "csi0phytimer_clk_src",
1422 .ops = &clk_ops_rcg,
1423 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1424 NOMINAL, 200000000),
1425 CLK_INIT(csi0phytimer_clk_src.c),
1426 },
1427};
1428
1429static struct rcg_clk csi1phytimer_clk_src = {
1430 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1431 .set_rate = set_rate_hid,
1432 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1433 .current_freq = &rcg_dummy_freq,
1434 .base = &virt_bases[GCC_BASE],
1435 .c = {
1436 .dbg_name = "csi1phytimer_clk_src",
1437 .ops = &clk_ops_rcg,
1438 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1439 NOMINAL, 200000000),
1440 CLK_INIT(csi1phytimer_clk_src.c),
1441 },
1442};
1443
1444static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1445 F( 50000000, gpll0, 16, 0, 0),
1446 F( 80000000, gpll0, 10, 0, 0),
1447 F( 100000000, gpll0, 8, 0, 0),
1448 F( 160000000, gpll0, 5, 0, 0),
1449 F_END
1450};
1451
1452static struct rcg_clk crypto_clk_src = {
1453 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1454 .set_rate = set_rate_hid,
1455 .freq_tbl = ftbl_gcc_crypto_clk,
1456 .current_freq = &rcg_dummy_freq,
1457 .base = &virt_bases[GCC_BASE],
1458 .c = {
1459 .dbg_name = "crypto_clk_src",
1460 .ops = &clk_ops_rcg,
1461 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1462 CLK_INIT(crypto_clk_src.c),
1463 },
1464};
1465
1466static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1467 F( 19200000, xo, 1, 0, 0),
1468 F_END
1469};
1470
1471static struct rcg_clk gp1_clk_src = {
1472 .cmd_rcgr_reg = GP1_CMD_RCGR,
1473 .set_rate = set_rate_mnd,
1474 .freq_tbl = ftbl_gcc_gp1_3_clk,
1475 .current_freq = &rcg_dummy_freq,
1476 .base = &virt_bases[GCC_BASE],
1477 .c = {
1478 .dbg_name = "gp1_clk_src",
1479 .ops = &clk_ops_rcg_mnd,
1480 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1481 CLK_INIT(gp1_clk_src.c),
1482 },
1483};
1484
1485static struct rcg_clk gp2_clk_src = {
1486 .cmd_rcgr_reg = GP2_CMD_RCGR,
1487 .set_rate = set_rate_mnd,
1488 .freq_tbl = ftbl_gcc_gp1_3_clk,
1489 .current_freq = &rcg_dummy_freq,
1490 .base = &virt_bases[GCC_BASE],
1491 .c = {
1492 .dbg_name = "gp2_clk_src",
1493 .ops = &clk_ops_rcg_mnd,
1494 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1495 CLK_INIT(gp2_clk_src.c),
1496 },
1497};
1498
1499static struct rcg_clk gp3_clk_src = {
1500 .cmd_rcgr_reg = GP3_CMD_RCGR,
1501 .set_rate = set_rate_mnd,
1502 .freq_tbl = ftbl_gcc_gp1_3_clk,
1503 .current_freq = &rcg_dummy_freq,
1504 .base = &virt_bases[GCC_BASE],
1505 .c = {
1506 .dbg_name = "gp3_clk_src",
1507 .ops = &clk_ops_rcg_mnd,
1508 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1509 CLK_INIT(gp3_clk_src.c),
1510 },
1511};
1512
1513static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1514 {
1515 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1516 | BVAL(4, 0, 0),
1517 .src_clk = &ext_byte0_clk_src.c,
1518 .freq_hz = 0,
1519 },
1520 F_END
1521};
1522
1523static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1524 {
1525 .div_src_val = BVAL(10, 8, xo_source_val)
1526 | BVAL(4, 0, 0),
1527 .src_clk = &xo_clk_src.c,
1528 .freq_hz = 0,
1529 },
1530 {
1531 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1532 | BVAL(4, 0, 0),
1533 .src_clk = &ext_byte0_clk_src.c,
1534 .freq_hz = 0,
1535 },
1536 {
1537 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1538 | BVAL(4, 0, 0),
1539 .src_clk = &ext_byte1_clk_src.c,
1540 .freq_hz = 0,
1541 },
1542 F_END
1543};
1544
1545static struct rcg_clk byte0_clk_src = {
1546 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1547 .set_rate = set_rate_hid,
1548 .current_freq = ftbl_gcc_mdss_byte0_clk,
1549 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1550 .base = &virt_bases[GCC_BASE],
1551 .c = {
1552 .dbg_name = "byte0_clk_src",
1553 .ops = &clk_ops_byte_multiparent,
1554 .flags = CLKFLAG_NO_RATE_CACHE,
1555 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1556 CLK_INIT(byte0_clk_src.c),
1557 },
1558};
1559
1560static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1561 {
1562 .div_src_val = BVAL(10, 8, xo_source_val)
1563 | BVAL(4, 0, 0),
1564 .src_clk = &xo_clk_src.c,
1565 .freq_hz = 0,
1566 },
1567 {
1568 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1569 | BVAL(4, 0, 0),
1570 .src_clk = &ext_byte1_clk_src.c,
1571 .freq_hz = 0,
1572 },
1573 {
1574 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1575 | BVAL(4, 0, 0),
1576 .src_clk = &ext_byte0_clk_src.c,
1577 .freq_hz = 0,
1578 },
1579 F_END
1580};
1581
1582static struct rcg_clk byte1_clk_src = {
1583 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1584 .set_rate = set_rate_hid,
1585 .current_freq = ftbl_gcc_mdss_byte1_clk,
1586 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1587 .base = &virt_bases[GCC_BASE],
1588 .c = {
1589 .dbg_name = "byte1_clk_src",
1590 .ops = &clk_ops_byte_multiparent,
1591 .flags = CLKFLAG_NO_RATE_CACHE,
1592 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1593 CLK_INIT(byte1_clk_src.c),
1594 },
1595};
1596
1597static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1598 F( 19200000, xo, 1, 0, 0),
1599 F_END
1600};
1601
1602static struct rcg_clk esc0_clk_src = {
1603 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1604 .set_rate = set_rate_hid,
1605 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1606 .current_freq = &rcg_dummy_freq,
1607 .base = &virt_bases[GCC_BASE],
1608 .c = {
1609 .dbg_name = "esc0_clk_src",
1610 .ops = &clk_ops_rcg,
1611 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1612 CLK_INIT(esc0_clk_src.c),
1613 },
1614};
1615
1616static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1617 F( 19200000, xo, 1, 0, 0),
1618 F_END
1619};
1620
1621static struct rcg_clk esc1_clk_src = {
1622 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1623 .set_rate = set_rate_hid,
1624 .freq_tbl = ftbl_esc1_clk_src,
1625 .current_freq = &rcg_dummy_freq,
1626 .base = &virt_bases[GCC_BASE],
1627 .c = {
1628 .dbg_name = "esc1_clk_src",
1629 .ops = &clk_ops_rcg,
1630 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1631 CLK_INIT(esc1_clk_src.c),
1632 },
1633};
1634
1635static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1636 F( 50000000, gpll0, 16, 0, 0),
1637 F( 80000000, gpll0, 10, 0, 0),
1638 F( 100000000, gpll0, 8, 0, 0),
1639 F( 145450000, gpll0, 5.5, 0, 0),
1640 F( 160000000, gpll0, 5, 0, 0),
1641 F( 177780000, gpll0, 4.5, 0, 0),
1642 F( 200000000, gpll0, 4, 0, 0),
1643 F( 266670000, gpll0, 3, 0, 0),
1644 F( 320000000, gpll0, 2.5, 0, 0),
1645 F_END
1646};
1647
1648static struct rcg_clk mdp_clk_src = {
1649 .cmd_rcgr_reg = MDP_CMD_RCGR,
1650 .set_rate = set_rate_hid,
1651 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1652 .current_freq = &rcg_dummy_freq,
1653 .base = &virt_bases[GCC_BASE],
1654 .c = {
1655 .dbg_name = "mdp_clk_src",
1656 .ops = &clk_ops_rcg,
1657 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1658 HIGH, 320000000),
1659 CLK_INIT(mdp_clk_src.c),
1660 },
1661};
1662
1663static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1664 {
1665 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1666 | BVAL(4, 0, 0),
1667 .src_clk = &ext_pclk0_clk_src.c,
1668 .freq_hz = 0,
1669 },
1670 F_END
1671};
1672
1673static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1674 {
1675 .div_src_val = BVAL(10, 8, xo_source_val)
1676 | BVAL(4, 0, 0),
1677 .src_clk = &xo_clk_src.c,
1678 .freq_hz = 0,
1679 },
1680 {
1681 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1682 | BVAL(4, 0, 0),
1683 .src_clk = &ext_pclk0_clk_src.c,
1684 .freq_hz = 0,
1685 },
1686 {
1687 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1688 | BVAL(4, 0, 0),
1689 .src_clk = &ext_pclk1_clk_src.c,
1690 .freq_hz = 0,
1691 },
1692 F_END
1693};
1694
1695static struct rcg_clk pclk0_clk_src = {
1696 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1697 .set_rate = set_rate_mnd,
1698 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1699 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1700 .base = &virt_bases[GCC_BASE],
1701 .c = {
1702 .dbg_name = "pclk0_clk_src",
1703 .ops = &clk_ops_pixel_multiparent,
1704 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1705 .flags = CLKFLAG_NO_RATE_CACHE,
1706 CLK_INIT(pclk0_clk_src.c),
1707 },
1708};
1709
1710static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1711 {
1712 .div_src_val = BVAL(10, 8, xo_source_val)
1713 | BVAL(4, 0, 0),
1714 .src_clk = &xo_clk_src.c,
1715 .freq_hz = 0,
1716 },
1717 {
1718 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1719 | BVAL(4, 0, 0),
1720 .src_clk = &ext_pclk1_clk_src.c,
1721 .freq_hz = 0,
1722 },
1723 {
1724 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1725 | BVAL(4, 0, 0),
1726 .src_clk = &ext_pclk0_clk_src.c,
1727 .freq_hz = 0,
1728 },
1729 F_END
1730};
1731
1732static struct rcg_clk pclk1_clk_src = {
1733 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1734 .set_rate = set_rate_mnd,
1735 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1736 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1737 .base = &virt_bases[GCC_BASE],
1738 .c = {
1739 .dbg_name = "pclk1_clk_src",
1740 .ops = &clk_ops_pixel_multiparent,
1741 .flags = CLKFLAG_NO_RATE_CACHE,
1742 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1743 CLK_INIT(pclk1_clk_src.c),
1744 },
1745};
1746
1747static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1748 F( 19200000, xo, 1, 0, 0),
1749 F_END
1750};
1751
1752static struct rcg_clk vsync_clk_src = {
1753 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1754 .set_rate = set_rate_hid,
1755 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1756 .current_freq = &rcg_dummy_freq,
1757 .base = &virt_bases[GCC_BASE],
1758 .c = {
1759 .dbg_name = "vsync_clk_src",
1760 .ops = &clk_ops_rcg,
1761 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1762 CLK_INIT(vsync_clk_src.c),
1763 },
1764};
1765
1766static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1767 F( 64000000, gpll0, 12.5, 0, 0),
1768 F_END
1769};
1770
1771static struct rcg_clk pdm2_clk_src = {
1772 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1773 .set_rate = set_rate_hid,
1774 .freq_tbl = ftbl_gcc_pdm2_clk,
1775 .current_freq = &rcg_dummy_freq,
1776 .base = &virt_bases[GCC_BASE],
1777 .c = {
1778 .dbg_name = "pdm2_clk_src",
1779 .ops = &clk_ops_rcg,
1780 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1781 CLK_INIT(pdm2_clk_src.c),
1782 },
1783};
1784
1785static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1786 F( 144000, xo, 16, 3, 25),
1787 F( 400000, xo, 12, 1, 4),
1788 F( 20000000, gpll0, 10, 1, 4),
1789 F( 25000000, gpll0, 16, 1, 2),
1790 F( 50000000, gpll0, 16, 0, 0),
1791 F( 100000000, gpll0, 8, 0, 0),
1792 F( 177770000, gpll0, 4.5, 0, 0),
1793 F( 192000000, gpll4, 6, 0, 0),
1794 F( 200000000, gpll0, 4, 0, 0),
1795 F( 384000000, gpll4, 3, 0, 0),
1796 F_END
1797};
1798
1799static struct rcg_clk sdcc1_apps_clk_src = {
1800 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1801 .set_rate = set_rate_mnd,
1802 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1803 .current_freq = &rcg_dummy_freq,
1804 .base = &virt_bases[GCC_BASE],
1805 .c = {
1806 .dbg_name = "sdcc1_apps_clk_src",
1807 .ops = &clk_ops_rcg_mnd,
1808 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1809 CLK_INIT(sdcc1_apps_clk_src.c),
1810 },
1811};
1812
1813static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1814 F( 100000000, gpll0_out_main, 8, 0, 0),
1815 F( 200000000, gpll0_out_main, 4, 0, 0),
1816 F_END
1817};
1818
1819static struct rcg_clk sdcc1_ice_core_clk_src = {
1820 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1821 .set_rate = set_rate_mnd,
1822 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1823 .current_freq = &rcg_dummy_freq,
1824 .base = &virt_bases[GCC_BASE],
1825 .c = {
1826 .dbg_name = "sdcc1_ice_core_clk_src",
1827 .ops = &clk_ops_rcg_mnd,
1828 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1829 CLK_INIT(sdcc1_ice_core_clk_src.c),
1830 },
1831};
1832
1833static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1834 F( 144000, xo, 16, 3, 25),
1835 F( 400000, xo, 12, 1, 4),
1836 F( 20000000, gpll0, 10, 1, 4),
1837 F( 25000000, gpll0, 16, 1, 2),
1838 F( 50000000, gpll0, 16, 0, 0),
1839 F( 100000000, gpll0, 8, 0, 0),
1840 F( 177770000, gpll0, 4.5, 0, 0),
1841 F( 200000000, gpll0, 4, 0, 0),
1842 F_END
1843};
1844
1845static struct rcg_clk sdcc2_apps_clk_src = {
1846 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1847 .set_rate = set_rate_mnd,
1848 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1849 .current_freq = &rcg_dummy_freq,
1850 .base = &virt_bases[GCC_BASE],
1851 .c = {
1852 .dbg_name = "sdcc2_apps_clk_src",
1853 .ops = &clk_ops_rcg_mnd,
1854 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1855 CLK_INIT(sdcc2_apps_clk_src.c),
1856 },
1857};
1858
1859static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1860 F( 60000000, gpll6_out_main, 9, 1, 2),
1861 F_END
1862};
1863
1864static struct rcg_clk usb_fs_ic_clk_src = {
1865 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1866 .set_rate = set_rate_mnd,
1867 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1868 .current_freq = &rcg_dummy_freq,
1869 .base = &virt_bases[GCC_BASE],
1870 .c = {
1871 .dbg_name = "usb_fs_ic_clk_src",
1872 .ops = &clk_ops_rcg_mnd,
1873 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1874 CLK_INIT(usb_fs_ic_clk_src.c),
1875 },
1876};
1877
1878static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1879 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1880 F_END
1881};
1882
1883static struct rcg_clk usb_fs_system_clk_src = {
1884 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1885 .set_rate = set_rate_mnd,
1886 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1887 .current_freq = &rcg_dummy_freq,
1888 .base = &virt_bases[GCC_BASE],
1889 .c = {
1890 .dbg_name = "usb_fs_system_clk_src",
1891 .ops = &clk_ops_rcg_mnd,
1892 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1893 CLK_INIT(usb_fs_system_clk_src.c),
1894 },
1895};
1896
1897static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1898 F( 57140000, gpll0, 14, 0, 0),
1899 F( 100000000, gpll0, 8, 0, 0),
1900 F( 133330000, gpll0, 6, 0, 0),
1901 F( 177780000, gpll0, 4.5, 0, 0),
1902 F_END
1903};
1904
1905static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1906 F( 80000000, gpll0, 10, 0, 0),
1907 F( 100000000, gpll0, 8, 0, 0),
1908 F( 133330000, gpll0, 6, 0, 0),
1909 F( 177780000, gpll0, 4.5, 0, 0),
1910 F_END
1911};
1912
1913static struct rcg_clk usb_hs_system_clk_src = {
1914 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1915 .set_rate = set_rate_hid,
1916 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1917 .current_freq = &rcg_dummy_freq,
1918 .base = &virt_bases[GCC_BASE],
1919 .c = {
1920 .dbg_name = "usb_hs_system_clk_src",
1921 .ops = &clk_ops_rcg,
1922 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1923 HIGH, 177780000),
1924 CLK_INIT(usb_hs_system_clk_src.c),
1925 },
1926};
1927
1928static struct branch_clk gcc_bimc_gpu_clk = {
1929 .cbcr_reg = BIMC_GPU_CBCR,
1930 .has_sibling = 1,
1931 .base = &virt_bases[GCC_BASE],
1932 .c = {
1933 .dbg_name = "gcc_bimc_gpu_clk",
1934 .ops = &clk_ops_branch,
1935 CLK_INIT(gcc_bimc_gpu_clk.c),
1936 },
1937};
1938
1939static struct branch_clk gcc_dcc_clk = {
1940 .cbcr_reg = DCC_CBCR,
1941 .has_sibling = 1,
1942 .base = &virt_bases[GCC_BASE],
1943 .c = {
1944 .dbg_name = "gcc_dcc_clk",
1945 .ops = &clk_ops_branch,
1946 CLK_INIT(gcc_dcc_clk.c),
1947 },
1948};
1949
1950static struct local_vote_clk gcc_blsp1_ahb_clk = {
1951 .cbcr_reg = BLSP1_AHB_CBCR,
1952 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1953 .en_mask = BIT(10),
1954 .base = &virt_bases[GCC_BASE],
1955 .c = {
1956 .dbg_name = "gcc_blsp1_ahb_clk",
1957 .ops = &clk_ops_vote,
1958 CLK_INIT(gcc_blsp1_ahb_clk.c),
1959 },
1960};
1961
1962static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1963 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1964 .has_sibling = 0,
1965 .base = &virt_bases[GCC_BASE],
1966 .c = {
1967 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1968 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1969 .ops = &clk_ops_branch,
1970 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1971 },
1972};
1973
1974static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1975 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1976 .has_sibling = 0,
1977 .base = &virt_bases[GCC_BASE],
1978 .c = {
1979 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1980 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1981 .ops = &clk_ops_branch,
1982 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1983 },
1984};
1985
1986static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1987 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1988 .has_sibling = 0,
1989 .base = &virt_bases[GCC_BASE],
1990 .c = {
1991 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1992 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1993 .ops = &clk_ops_branch,
1994 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1995 },
1996};
1997
1998static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1999 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
2000 .has_sibling = 0,
2001 .base = &virt_bases[GCC_BASE],
2002 .c = {
2003 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
2004 .parent = &blsp1_qup2_spi_apps_clk_src.c,
2005 .ops = &clk_ops_branch,
2006 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
2007 },
2008};
2009
2010static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
2011 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
2012 .has_sibling = 0,
2013 .base = &virt_bases[GCC_BASE],
2014 .c = {
2015 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
2016 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
2017 .ops = &clk_ops_branch,
2018 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
2019 },
2020};
2021
2022static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
2023 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
2024 .has_sibling = 0,
2025 .base = &virt_bases[GCC_BASE],
2026 .c = {
2027 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
2028 .parent = &blsp1_qup3_spi_apps_clk_src.c,
2029 .ops = &clk_ops_branch,
2030 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
2031 },
2032};
2033
2034static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2035 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2036 .has_sibling = 0,
2037 .base = &virt_bases[GCC_BASE],
2038 .c = {
2039 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2040 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2041 .ops = &clk_ops_branch,
2042 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2043 },
2044};
2045
2046static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2047 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2048 .has_sibling = 0,
2049 .base = &virt_bases[GCC_BASE],
2050 .c = {
2051 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2052 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2053 .ops = &clk_ops_branch,
2054 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2055 },
2056};
2057
2058static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2059 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2060 .has_sibling = 0,
2061 .base = &virt_bases[GCC_BASE],
2062 .c = {
2063 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2064 .parent = &blsp1_uart1_apps_clk_src.c,
2065 .ops = &clk_ops_branch,
2066 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2067 },
2068};
2069
2070static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2071 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2072 .has_sibling = 0,
2073 .base = &virt_bases[GCC_BASE],
2074 .c = {
2075 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2076 .parent = &blsp1_uart2_apps_clk_src.c,
2077 .ops = &clk_ops_branch,
2078 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2079 },
2080};
2081
2082static struct local_vote_clk gcc_blsp2_ahb_clk = {
2083 .cbcr_reg = BLSP2_AHB_CBCR,
2084 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2085 .en_mask = BIT(20),
2086 .base = &virt_bases[GCC_BASE],
2087 .c = {
2088 .dbg_name = "gcc_blsp2_ahb_clk",
2089 .ops = &clk_ops_vote,
2090 CLK_INIT(gcc_blsp2_ahb_clk.c),
2091 },
2092};
2093
2094static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2095 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2096 .has_sibling = 0,
2097 .base = &virt_bases[GCC_BASE],
2098 .c = {
2099 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2100 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2101 .ops = &clk_ops_branch,
2102 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2103 },
2104};
2105
2106static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2107 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2108 .has_sibling = 0,
2109 .base = &virt_bases[GCC_BASE],
2110 .c = {
2111 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2112 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2113 .ops = &clk_ops_branch,
2114 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2115 },
2116};
2117
2118static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2119 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2120 .has_sibling = 0,
2121 .base = &virt_bases[GCC_BASE],
2122 .c = {
2123 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2124 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2125 .ops = &clk_ops_branch,
2126 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2127 },
2128};
2129
2130static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2131 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2132 .has_sibling = 0,
2133 .base = &virt_bases[GCC_BASE],
2134 .c = {
2135 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2136 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2137 .ops = &clk_ops_branch,
2138 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2139 },
2140};
2141
2142static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2143 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2144 .has_sibling = 0,
2145 .base = &virt_bases[GCC_BASE],
2146 .c = {
2147 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2148 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2149 .ops = &clk_ops_branch,
2150 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2151 },
2152};
2153
2154static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2155 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2156 .has_sibling = 0,
2157 .base = &virt_bases[GCC_BASE],
2158 .c = {
2159 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2160 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2161 .ops = &clk_ops_branch,
2162 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2163 },
2164};
2165
2166static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2167 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2168 .has_sibling = 0,
2169 .base = &virt_bases[GCC_BASE],
2170 .c = {
2171 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2172 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2173 .ops = &clk_ops_branch,
2174 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2175 },
2176};
2177
2178static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2179 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2180 .has_sibling = 0,
2181 .base = &virt_bases[GCC_BASE],
2182 .c = {
2183 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2184 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2185 .ops = &clk_ops_branch,
2186 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2187 },
2188};
2189
2190static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2191 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2192 .has_sibling = 0,
2193 .base = &virt_bases[GCC_BASE],
2194 .c = {
2195 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2196 .parent = &blsp2_uart1_apps_clk_src.c,
2197 .ops = &clk_ops_branch,
2198 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2199 },
2200};
2201
2202static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2203 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2204 .has_sibling = 0,
2205 .base = &virt_bases[GCC_BASE],
2206 .c = {
2207 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2208 .parent = &blsp2_uart2_apps_clk_src.c,
2209 .ops = &clk_ops_branch,
2210 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2211 },
2212};
2213
2214static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2215 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2216 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2217 .en_mask = BIT(7),
2218 .base = &virt_bases[GCC_BASE],
2219 .c = {
2220 .dbg_name = "gcc_boot_rom_ahb_clk",
2221 .ops = &clk_ops_vote,
2222 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2223 },
2224};
2225
2226static struct branch_clk gcc_camss_cci_ahb_clk = {
2227 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2228 .has_sibling = 1,
2229 .base = &virt_bases[GCC_BASE],
2230 .c = {
2231 .dbg_name = "gcc_camss_cci_ahb_clk",
2232 .parent = &camss_top_ahb_clk_src.c,
2233 .ops = &clk_ops_branch,
2234 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2235 },
2236};
2237
2238static struct branch_clk gcc_camss_cci_clk = {
2239 .cbcr_reg = CAMSS_CCI_CBCR,
2240 .has_sibling = 0,
2241 .base = &virt_bases[GCC_BASE],
2242 .c = {
2243 .dbg_name = "gcc_camss_cci_clk",
2244 .parent = &cci_clk_src.c,
2245 .ops = &clk_ops_branch,
2246 CLK_INIT(gcc_camss_cci_clk.c),
2247 },
2248};
2249
2250static struct branch_clk gcc_camss_cpp_ahb_clk = {
2251 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2252 .has_sibling = 1,
2253 .base = &virt_bases[GCC_BASE],
2254 .c = {
2255 .dbg_name = "gcc_camss_cpp_ahb_clk",
2256 .parent = &camss_top_ahb_clk_src.c,
2257 .ops = &clk_ops_branch,
2258 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2259 },
2260};
2261
2262static struct branch_clk gcc_camss_cpp_axi_clk = {
2263 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2264 .has_sibling = 1,
2265 .base = &virt_bases[GCC_BASE],
2266 .c = {
2267 .dbg_name = "gcc_camss_cpp_axi_clk",
2268 .ops = &clk_ops_branch,
2269 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2270 },
2271};
2272
2273static struct branch_clk gcc_camss_cpp_clk = {
2274 .cbcr_reg = CAMSS_CPP_CBCR,
2275 .has_sibling = 0,
2276 .base = &virt_bases[GCC_BASE],
2277 .c = {
2278 .dbg_name = "gcc_camss_cpp_clk",
2279 .parent = &cpp_clk_src.c,
2280 .ops = &clk_ops_branch,
2281 CLK_INIT(gcc_camss_cpp_clk.c),
2282 },
2283};
2284
2285static struct branch_clk gcc_camss_csi0_ahb_clk = {
2286 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2287 .has_sibling = 1,
2288 .base = &virt_bases[GCC_BASE],
2289 .c = {
2290 .dbg_name = "gcc_camss_csi0_ahb_clk",
2291 .parent = &camss_top_ahb_clk_src.c,
2292 .ops = &clk_ops_branch,
2293 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2294 },
2295};
2296
2297static struct branch_clk gcc_camss_csi0_clk = {
2298 .cbcr_reg = CAMSS_CSI0_CBCR,
2299 .has_sibling = 1,
2300 .base = &virt_bases[GCC_BASE],
2301 .c = {
2302 .dbg_name = "gcc_camss_csi0_clk",
2303 .parent = &csi0_clk_src.c,
2304 .ops = &clk_ops_branch,
2305 CLK_INIT(gcc_camss_csi0_clk.c),
2306 },
2307};
2308
2309static struct branch_clk gcc_camss_csi0phy_clk = {
2310 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2311 .has_sibling = 1,
2312 .base = &virt_bases[GCC_BASE],
2313 .c = {
2314 .dbg_name = "gcc_camss_csi0phy_clk",
2315 .parent = &csi0_clk_src.c,
2316 .ops = &clk_ops_branch,
2317 CLK_INIT(gcc_camss_csi0phy_clk.c),
2318 },
2319};
2320
2321static struct branch_clk gcc_camss_csi0pix_clk = {
2322 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2323 .has_sibling = 1,
2324 .base = &virt_bases[GCC_BASE],
2325 .c = {
2326 .dbg_name = "gcc_camss_csi0pix_clk",
2327 .parent = &csi0_clk_src.c,
2328 .ops = &clk_ops_branch,
2329 CLK_INIT(gcc_camss_csi0pix_clk.c),
2330 },
2331};
2332
2333static struct branch_clk gcc_camss_csi0rdi_clk = {
2334 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2335 .has_sibling = 1,
2336 .base = &virt_bases[GCC_BASE],
2337 .c = {
2338 .dbg_name = "gcc_camss_csi0rdi_clk",
2339 .parent = &csi0_clk_src.c,
2340 .ops = &clk_ops_branch,
2341 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2342 },
2343};
2344
2345static struct branch_clk gcc_camss_csi1_ahb_clk = {
2346 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2347 .has_sibling = 1,
2348 .base = &virt_bases[GCC_BASE],
2349 .c = {
2350 .dbg_name = "gcc_camss_csi1_ahb_clk",
2351 .parent = &camss_top_ahb_clk_src.c,
2352 .ops = &clk_ops_branch,
2353 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2354 },
2355};
2356
2357static struct branch_clk gcc_camss_csi1_clk = {
2358 .cbcr_reg = CAMSS_CSI1_CBCR,
2359 .has_sibling = 1,
2360 .base = &virt_bases[GCC_BASE],
2361 .c = {
2362 .dbg_name = "gcc_camss_csi1_clk",
2363 .parent = &csi1_clk_src.c,
2364 .ops = &clk_ops_branch,
2365 CLK_INIT(gcc_camss_csi1_clk.c),
2366 },
2367};
2368
2369static struct branch_clk gcc_camss_csi1phy_clk = {
2370 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2371 .has_sibling = 1,
2372 .base = &virt_bases[GCC_BASE],
2373 .c = {
2374 .dbg_name = "gcc_camss_csi1phy_clk",
2375 .parent = &csi1_clk_src.c,
2376 .ops = &clk_ops_branch,
2377 CLK_INIT(gcc_camss_csi1phy_clk.c),
2378 },
2379};
2380
2381static struct branch_clk gcc_camss_csi1pix_clk = {
2382 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2383 .has_sibling = 1,
2384 .base = &virt_bases[GCC_BASE],
2385 .c = {
2386 .dbg_name = "gcc_camss_csi1pix_clk",
2387 .parent = &csi1_clk_src.c,
2388 .ops = &clk_ops_branch,
2389 CLK_INIT(gcc_camss_csi1pix_clk.c),
2390 },
2391};
2392
2393static struct branch_clk gcc_camss_csi1rdi_clk = {
2394 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2395 .has_sibling = 1,
2396 .base = &virt_bases[GCC_BASE],
2397 .c = {
2398 .dbg_name = "gcc_camss_csi1rdi_clk",
2399 .parent = &csi1_clk_src.c,
2400 .ops = &clk_ops_branch,
2401 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2402 },
2403};
2404
2405static struct branch_clk gcc_camss_csi2_ahb_clk = {
2406 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2407 .has_sibling = 1,
2408 .base = &virt_bases[GCC_BASE],
2409 .c = {
2410 .dbg_name = "gcc_camss_csi2_ahb_clk",
2411 .parent = &camss_top_ahb_clk_src.c,
2412 .ops = &clk_ops_branch,
2413 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2414 },
2415};
2416
2417static struct branch_clk gcc_camss_csi2_clk = {
2418 .cbcr_reg = CAMSS_CSI2_CBCR,
2419 .has_sibling = 1,
2420 .base = &virt_bases[GCC_BASE],
2421 .c = {
2422 .dbg_name = "gcc_camss_csi2_clk",
2423 .parent = &csi2_clk_src.c,
2424 .ops = &clk_ops_branch,
2425 CLK_INIT(gcc_camss_csi2_clk.c),
2426 },
2427};
2428
2429static struct branch_clk gcc_camss_csi2phy_clk = {
2430 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2431 .has_sibling = 1,
2432 .base = &virt_bases[GCC_BASE],
2433 .c = {
2434 .dbg_name = "gcc_camss_csi2phy_clk",
2435 .parent = &csi2_clk_src.c,
2436 .ops = &clk_ops_branch,
2437 CLK_INIT(gcc_camss_csi2phy_clk.c),
2438 },
2439};
2440
2441static struct branch_clk gcc_camss_csi2pix_clk = {
2442 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2443 .has_sibling = 1,
2444 .base = &virt_bases[GCC_BASE],
2445 .c = {
2446 .dbg_name = "gcc_camss_csi2pix_clk",
2447 .parent = &csi2_clk_src.c,
2448 .ops = &clk_ops_branch,
2449 CLK_INIT(gcc_camss_csi2pix_clk.c),
2450 },
2451};
2452
2453static struct branch_clk gcc_camss_csi2rdi_clk = {
2454 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2455 .has_sibling = 1,
2456 .base = &virt_bases[GCC_BASE],
2457 .c = {
2458 .dbg_name = "gcc_camss_csi2rdi_clk",
2459 .parent = &csi2_clk_src.c,
2460 .ops = &clk_ops_branch,
2461 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2462 },
2463};
2464
2465static struct branch_clk gcc_camss_csi_vfe0_clk = {
2466 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2467 .has_sibling = 1,
2468 .base = &virt_bases[GCC_BASE],
2469 .c = {
2470 .dbg_name = "gcc_camss_csi_vfe0_clk",
2471 .parent = &vfe0_clk_src.c,
2472 .ops = &clk_ops_branch,
2473 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2474 },
2475};
2476
2477static struct branch_clk gcc_camss_csi_vfe1_clk = {
2478 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2479 .has_sibling = 1,
2480 .base = &virt_bases[GCC_BASE],
2481 .c = {
2482 .dbg_name = "gcc_camss_csi_vfe1_clk",
2483 .parent = &vfe1_clk_src.c,
2484 .ops = &clk_ops_branch,
2485 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2486 },
2487};
2488
2489static struct branch_clk gcc_camss_gp0_clk = {
2490 .cbcr_reg = CAMSS_GP0_CBCR,
2491 .has_sibling = 0,
2492 .base = &virt_bases[GCC_BASE],
2493 .c = {
2494 .dbg_name = "gcc_camss_gp0_clk",
2495 .parent = &camss_gp0_clk_src.c,
2496 .ops = &clk_ops_branch,
2497 CLK_INIT(gcc_camss_gp0_clk.c),
2498 },
2499};
2500
2501static struct branch_clk gcc_camss_gp1_clk = {
2502 .cbcr_reg = CAMSS_GP1_CBCR,
2503 .has_sibling = 0,
2504 .base = &virt_bases[GCC_BASE],
2505 .c = {
2506 .dbg_name = "gcc_camss_gp1_clk",
2507 .parent = &camss_gp1_clk_src.c,
2508 .ops = &clk_ops_branch,
2509 CLK_INIT(gcc_camss_gp1_clk.c),
2510 },
2511};
2512
2513static struct branch_clk gcc_camss_ispif_ahb_clk = {
2514 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2515 .has_sibling = 0,
2516 .base = &virt_bases[GCC_BASE],
2517 .c = {
2518 .dbg_name = "gcc_camss_ispif_ahb_clk",
2519 .parent = &camss_top_ahb_clk_src.c,
2520 .ops = &clk_ops_branch,
2521 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2522 },
2523};
2524
2525static struct branch_clk gcc_camss_jpeg0_clk = {
2526 .cbcr_reg = CAMSS_JPEG0_CBCR,
2527 .has_sibling = 0,
2528 .base = &virt_bases[GCC_BASE],
2529 .c = {
2530 .dbg_name = "gcc_camss_jpeg0_clk",
2531 .parent = &jpeg0_clk_src.c,
2532 .ops = &clk_ops_branch,
2533 CLK_INIT(gcc_camss_jpeg0_clk.c),
2534 },
2535};
2536
2537static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2538 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2539 .has_sibling = 1,
2540 .base = &virt_bases[GCC_BASE],
2541 .c = {
2542 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2543 .parent = &camss_top_ahb_clk_src.c,
2544 .ops = &clk_ops_branch,
2545 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2546 },
2547};
2548
2549static struct branch_clk gcc_camss_jpeg_axi_clk = {
2550 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2551 .has_sibling = 1,
2552 .base = &virt_bases[GCC_BASE],
2553 .c = {
2554 .dbg_name = "gcc_camss_jpeg_axi_clk",
2555 .ops = &clk_ops_branch,
2556 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2557 },
2558};
2559
2560static struct branch_clk gcc_camss_mclk0_clk = {
2561 .cbcr_reg = CAMSS_MCLK0_CBCR,
2562 .has_sibling = 0,
2563 .base = &virt_bases[GCC_BASE],
2564 .c = {
2565 .dbg_name = "gcc_camss_mclk0_clk",
2566 .parent = &mclk0_clk_src.c,
2567 .ops = &clk_ops_branch,
2568 CLK_INIT(gcc_camss_mclk0_clk.c),
2569 },
2570};
2571
2572static struct branch_clk gcc_camss_mclk1_clk = {
2573 .cbcr_reg = CAMSS_MCLK1_CBCR,
2574 .has_sibling = 0,
2575 .base = &virt_bases[GCC_BASE],
2576 .c = {
2577 .dbg_name = "gcc_camss_mclk1_clk",
2578 .parent = &mclk1_clk_src.c,
2579 .ops = &clk_ops_branch,
2580 CLK_INIT(gcc_camss_mclk1_clk.c),
2581 },
2582};
2583
2584static struct branch_clk gcc_camss_mclk2_clk = {
2585 .cbcr_reg = CAMSS_MCLK2_CBCR,
2586 .has_sibling = 0,
2587 .base = &virt_bases[GCC_BASE],
2588 .c = {
2589 .dbg_name = "gcc_camss_mclk2_clk",
2590 .parent = &mclk2_clk_src.c,
2591 .ops = &clk_ops_branch,
2592 CLK_INIT(gcc_camss_mclk2_clk.c),
2593 },
2594};
2595
2596static struct branch_clk gcc_camss_micro_ahb_clk = {
2597 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2598 .bcr_reg = CAMSS_MICRO_BCR,
2599 .has_sibling = 1,
2600 .base = &virt_bases[GCC_BASE],
2601 .c = {
2602 .dbg_name = "gcc_camss_micro_ahb_clk",
2603 .parent = &camss_top_ahb_clk_src.c,
2604 .ops = &clk_ops_branch,
2605 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2606 },
2607};
2608
2609static struct branch_clk gcc_camss_csi0phytimer_clk = {
2610 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2611 .has_sibling = 0,
2612 .base = &virt_bases[GCC_BASE],
2613 .c = {
2614 .dbg_name = "gcc_camss_csi0phytimer_clk",
2615 .parent = &csi0phytimer_clk_src.c,
2616 .ops = &clk_ops_branch,
2617 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2618 },
2619};
2620
2621static struct branch_clk gcc_camss_csi1phytimer_clk = {
2622 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2623 .has_sibling = 0,
2624 .base = &virt_bases[GCC_BASE],
2625 .c = {
2626 .dbg_name = "gcc_camss_csi1phytimer_clk",
2627 .parent = &csi1phytimer_clk_src.c,
2628 .ops = &clk_ops_branch,
2629 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2630 },
2631};
2632
2633static struct branch_clk gcc_camss_ahb_clk = {
2634 .cbcr_reg = CAMSS_AHB_CBCR,
2635 .has_sibling = 1,
2636 .base = &virt_bases[GCC_BASE],
2637 .c = {
2638 .dbg_name = "gcc_camss_ahb_clk",
2639 .ops = &clk_ops_branch,
2640 CLK_INIT(gcc_camss_ahb_clk.c),
2641 },
2642};
2643
2644static struct branch_clk gcc_camss_top_ahb_clk = {
2645 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2646 .has_sibling = 1,
2647 .base = &virt_bases[GCC_BASE],
2648 .c = {
2649 .dbg_name = "gcc_camss_top_ahb_clk",
2650 .parent = &camss_top_ahb_clk_src.c,
2651 .ops = &clk_ops_branch,
2652 CLK_INIT(gcc_camss_top_ahb_clk.c),
2653 },
2654};
2655
2656static struct branch_clk gcc_camss_vfe0_clk = {
2657 .cbcr_reg = CAMSS_VFE0_CBCR,
2658 .has_sibling = 1,
2659 .base = &virt_bases[GCC_BASE],
2660 .c = {
2661 .dbg_name = "gcc_camss_vfe0_clk",
2662 .parent = &vfe0_clk_src.c,
2663 .ops = &clk_ops_branch,
2664 CLK_INIT(gcc_camss_vfe0_clk.c),
2665 },
2666};
2667
2668static struct branch_clk gcc_camss_vfe_ahb_clk = {
2669 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2670 .has_sibling = 1,
2671 .base = &virt_bases[GCC_BASE],
2672 .c = {
2673 .dbg_name = "gcc_camss_vfe_ahb_clk",
2674 .ops = &clk_ops_branch,
2675 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2676 },
2677};
2678
2679static struct branch_clk gcc_camss_vfe_axi_clk = {
2680 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2681 .has_sibling = 1,
2682 .base = &virt_bases[GCC_BASE],
2683 .c = {
2684 .dbg_name = "gcc_camss_vfe_axi_clk",
2685 .ops = &clk_ops_branch,
2686 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2687 },
2688};
2689
2690static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2691 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2692 .has_sibling = 1,
2693 .base = &virt_bases[GCC_BASE],
2694 .c = {
2695 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2696 .parent = &camss_top_ahb_clk_src.c,
2697 .ops = &clk_ops_branch,
2698 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2699 },
2700};
2701
2702static struct branch_clk gcc_camss_vfe1_axi_clk = {
2703 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2704 .has_sibling = 1,
2705 .base = &virt_bases[GCC_BASE],
2706 .c = {
2707 .dbg_name = "gcc_camss_vfe1_axi_clk",
2708 .ops = &clk_ops_branch,
2709 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2710 },
2711};
2712
2713static struct branch_clk gcc_camss_vfe1_clk = {
2714 .cbcr_reg = CAMSS_VFE1_CBCR,
2715 .has_sibling = 1,
2716 .base = &virt_bases[GCC_BASE],
2717 .c = {
2718 .dbg_name = "gcc_camss_vfe1_clk",
2719 .parent = &vfe1_clk_src.c,
2720 .ops = &clk_ops_branch,
2721 CLK_INIT(gcc_camss_vfe1_clk.c),
2722 },
2723};
2724
2725static struct local_vote_clk gcc_crypto_ahb_clk = {
2726 .cbcr_reg = CRYPTO_AHB_CBCR,
2727 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2728 .en_mask = BIT(0),
2729 .base = &virt_bases[GCC_BASE],
2730 .c = {
2731 .dbg_name = "gcc_crypto_ahb_clk",
2732 .parent = &crypto_clk_src.c,
2733 .ops = &clk_ops_vote,
2734 CLK_INIT(gcc_crypto_ahb_clk.c),
2735 },
2736};
2737
2738static struct local_vote_clk gcc_crypto_axi_clk = {
2739 .cbcr_reg = CRYPTO_AXI_CBCR,
2740 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2741 .en_mask = BIT(1),
2742 .base = &virt_bases[GCC_BASE],
2743 .c = {
2744 .dbg_name = "gcc_crypto_axi_clk",
2745 .ops = &clk_ops_vote,
2746 CLK_INIT(gcc_crypto_axi_clk.c),
2747 },
2748};
2749
2750static struct local_vote_clk gcc_crypto_clk = {
2751 .cbcr_reg = CRYPTO_CBCR,
2752 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2753 .en_mask = BIT(2),
2754 .base = &virt_bases[GCC_BASE],
2755 .c = {
2756 .dbg_name = "gcc_crypto_clk",
2757 .parent = &crypto_clk_src.c,
2758 .ops = &clk_ops_vote,
2759 CLK_INIT(gcc_crypto_clk.c),
2760 },
2761};
2762
2763static struct gate_clk gcc_oxili_gmem_clk = {
2764 .en_reg = OXILI_GMEM_CBCR,
2765 .en_mask = BIT(0),
2766 .delay_us = 50,
2767 .base = &virt_bases[GCC_BASE],
2768 .c = {
2769 .dbg_name = "gcc_oxili_gmem_clk",
2770 .parent = &gfx3d_clk_src.c,
2771 .ops = &clk_ops_gate,
2772 CLK_INIT(gcc_oxili_gmem_clk.c),
2773 },
2774};
2775
2776static struct branch_clk gcc_gp1_clk = {
2777 .cbcr_reg = GP1_CBCR,
2778 .has_sibling = 0,
2779 .base = &virt_bases[GCC_BASE],
2780 .c = {
2781 .dbg_name = "gcc_gp1_clk",
2782 .parent = &gp1_clk_src.c,
2783 .ops = &clk_ops_branch,
2784 CLK_INIT(gcc_gp1_clk.c),
2785 },
2786};
2787
2788static struct branch_clk gcc_gp2_clk = {
2789 .cbcr_reg = GP2_CBCR,
2790 .has_sibling = 0,
2791 .base = &virt_bases[GCC_BASE],
2792 .c = {
2793 .dbg_name = "gcc_gp2_clk",
2794 .parent = &gp2_clk_src.c,
2795 .ops = &clk_ops_branch,
2796 CLK_INIT(gcc_gp2_clk.c),
2797 },
2798};
2799
2800static struct branch_clk gcc_gp3_clk = {
2801 .cbcr_reg = GP3_CBCR,
2802 .has_sibling = 0,
2803 .base = &virt_bases[GCC_BASE],
2804 .c = {
2805 .dbg_name = "gcc_gp3_clk",
2806 .parent = &gp3_clk_src.c,
2807 .ops = &clk_ops_branch,
2808 CLK_INIT(gcc_gp3_clk.c),
2809 },
2810};
2811
2812static struct branch_clk gcc_mdss_ahb_clk = {
2813 .cbcr_reg = MDSS_AHB_CBCR,
2814 .has_sibling = 1,
2815 .base = &virt_bases[GCC_BASE],
2816 .c = {
2817 .dbg_name = "gcc_mdss_ahb_clk",
2818 .ops = &clk_ops_branch,
2819 CLK_INIT(gcc_mdss_ahb_clk.c),
2820 },
2821};
2822
2823static struct branch_clk gcc_mdss_axi_clk = {
2824 .cbcr_reg = MDSS_AXI_CBCR,
2825 .has_sibling = 1,
2826 .base = &virt_bases[GCC_BASE],
2827 .c = {
2828 .dbg_name = "gcc_mdss_axi_clk",
2829 .ops = &clk_ops_branch,
2830 CLK_INIT(gcc_mdss_axi_clk.c),
2831 },
2832};
2833
2834static struct branch_clk gcc_mdss_byte0_clk = {
2835 .cbcr_reg = MDSS_BYTE0_CBCR,
2836 .has_sibling = 0,
2837 .base = &virt_bases[GCC_BASE],
2838 .c = {
2839 .dbg_name = "gcc_mdss_byte0_clk",
2840 .parent = &byte0_clk_src.c,
2841 .ops = &clk_ops_branch,
2842 .flags = CLKFLAG_NO_RATE_CACHE,
2843 CLK_INIT(gcc_mdss_byte0_clk.c),
2844 },
2845};
2846
2847static struct branch_clk gcc_mdss_byte1_clk = {
2848 .cbcr_reg = MDSS_BYTE1_CBCR,
2849 .has_sibling = 0,
2850 .base = &virt_bases[GCC_BASE],
2851 .c = {
2852 .dbg_name = "gcc_mdss_byte1_clk",
2853 .parent = &byte1_clk_src.c,
2854 .ops = &clk_ops_branch,
2855 .flags = CLKFLAG_NO_RATE_CACHE,
2856 CLK_INIT(gcc_mdss_byte1_clk.c),
2857 },
2858};
2859
2860static struct branch_clk gcc_mdss_esc0_clk = {
2861 .cbcr_reg = MDSS_ESC0_CBCR,
2862 .has_sibling = 0,
2863 .base = &virt_bases[GCC_BASE],
2864 .c = {
2865 .dbg_name = "gcc_mdss_esc0_clk",
2866 .parent = &esc0_clk_src.c,
2867 .ops = &clk_ops_branch,
2868 CLK_INIT(gcc_mdss_esc0_clk.c),
2869 },
2870};
2871
2872static struct branch_clk gcc_mdss_esc1_clk = {
2873 .cbcr_reg = MDSS_ESC1_CBCR,
2874 .has_sibling = 0,
2875 .base = &virt_bases[GCC_BASE],
2876 .c = {
2877 .dbg_name = "gcc_mdss_esc1_clk",
2878 .parent = &esc1_clk_src.c,
2879 .ops = &clk_ops_branch,
2880 CLK_INIT(gcc_mdss_esc1_clk.c),
2881 },
2882};
2883
2884static struct branch_clk gcc_mdss_mdp_clk = {
2885 .cbcr_reg = MDSS_MDP_CBCR,
2886 .has_sibling = 0,
2887 .base = &virt_bases[GCC_BASE],
2888 .c = {
2889 .dbg_name = "gcc_mdss_mdp_clk",
2890 .parent = &mdp_clk_src.c,
2891 .ops = &clk_ops_branch,
2892 CLK_INIT(gcc_mdss_mdp_clk.c),
2893 },
2894};
2895
2896static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2897static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2898
2899static struct branch_clk gcc_mdss_pclk0_clk = {
2900 .cbcr_reg = MDSS_PCLK0_CBCR,
2901 .has_sibling = 0,
2902 .base = &virt_bases[GCC_BASE],
2903 .c = {
2904 .dbg_name = "gcc_mdss_pclk0_clk",
2905 .parent = &pclk0_clk_src.c,
2906 .ops = &clk_ops_branch,
2907 .flags = CLKFLAG_NO_RATE_CACHE,
2908 CLK_INIT(gcc_mdss_pclk0_clk.c),
2909 },
2910};
2911
2912static struct branch_clk gcc_mdss_pclk1_clk = {
2913 .cbcr_reg = MDSS_PCLK1_CBCR,
2914 .has_sibling = 0,
2915 .base = &virt_bases[GCC_BASE],
2916 .c = {
2917 .dbg_name = "gcc_mdss_pclk1_clk",
2918 .parent = &pclk1_clk_src.c,
2919 .ops = &clk_ops_branch,
2920 .flags = CLKFLAG_NO_RATE_CACHE,
2921 CLK_INIT(gcc_mdss_pclk1_clk.c),
2922 },
2923};
2924
2925static struct branch_clk gcc_mdss_vsync_clk = {
2926 .cbcr_reg = MDSS_VSYNC_CBCR,
2927 .has_sibling = 0,
2928 .base = &virt_bases[GCC_BASE],
2929 .c = {
2930 .dbg_name = "gcc_mdss_vsync_clk",
2931 .parent = &vsync_clk_src.c,
2932 .ops = &clk_ops_branch,
2933 CLK_INIT(gcc_mdss_vsync_clk.c),
2934 },
2935};
2936
2937static struct branch_clk gcc_mss_cfg_ahb_clk = {
2938 .cbcr_reg = MSS_CFG_AHB_CBCR,
2939 .has_sibling = 1,
2940 .base = &virt_bases[GCC_BASE],
2941 .c = {
2942 .dbg_name = "gcc_mss_cfg_ahb_clk",
2943 .ops = &clk_ops_branch,
2944 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2945 },
2946};
2947
2948static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2949 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2950 .has_sibling = 1,
2951 .base = &virt_bases[GCC_BASE],
2952 .c = {
2953 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2954 .ops = &clk_ops_branch,
2955 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2956 },
2957};
2958
2959static struct local_vote_clk gcc_apss_tcu_clk;
2960static struct branch_clk gcc_bimc_gfx_clk = {
2961 .cbcr_reg = BIMC_GFX_CBCR,
2962 .has_sibling = 1,
2963 .base = &virt_bases[GCC_BASE],
2964 .c = {
2965 .dbg_name = "gcc_bimc_gfx_clk",
2966 .ops = &clk_ops_branch,
2967 CLK_INIT(gcc_bimc_gfx_clk.c),
2968 .depends = &gcc_apss_tcu_clk.c,
2969 },
2970};
2971
2972static struct branch_clk gcc_oxili_ahb_clk = {
2973 .cbcr_reg = OXILI_AHB_CBCR,
2974 .has_sibling = 1,
2975 .base = &virt_bases[GCC_BASE],
2976 .c = {
2977 .dbg_name = "gcc_oxili_ahb_clk",
2978 .ops = &clk_ops_branch,
2979 CLK_INIT(gcc_oxili_ahb_clk.c),
2980 },
2981};
2982
2983static struct branch_clk gcc_oxili_gfx3d_clk = {
2984 .cbcr_reg = OXILI_GFX3D_CBCR,
2985 .has_sibling = 0,
2986 .base = &virt_bases[GCC_BASE],
2987 .c = {
2988 .dbg_name = "gcc_oxili_gfx3d_clk",
2989 .parent = &gfx3d_clk_src.c,
2990 .ops = &clk_ops_branch,
2991 CLK_INIT(gcc_oxili_gfx3d_clk.c),
2992 },
2993};
2994
2995static struct branch_clk gcc_oxili_timer_clk = {
2996 .cbcr_reg = OXILI_TIMER_CBCR,
2997 .has_sibling = 0,
2998 .base = &virt_bases[GCC_BASE],
2999 .c = {
3000 .dbg_name = "gcc_oxili_timer_clk",
3001 .parent = &xo_clk_src.c,
3002 .ops = &clk_ops_branch,
3003 CLK_INIT(gcc_oxili_timer_clk.c),
3004 },
3005};
3006
3007static struct branch_clk gcc_oxili_aon_clk = {
3008 .cbcr_reg = OXILI_AON_CBCR,
3009 .has_sibling = 0,
3010 .base = &virt_bases[GCC_BASE],
3011 .c = {
3012 .dbg_name = "gcc_oxili_aon_clk",
3013 .parent = &gfx3d_clk_src.c,
3014 .ops = &clk_ops_branch,
3015 CLK_INIT(gcc_oxili_aon_clk.c),
3016 },
3017};
3018
3019static struct branch_clk gcc_pdm2_clk = {
3020 .cbcr_reg = PDM2_CBCR,
3021 .has_sibling = 0,
3022 .base = &virt_bases[GCC_BASE],
3023 .c = {
3024 .dbg_name = "gcc_pdm2_clk",
3025 .parent = &pdm2_clk_src.c,
3026 .ops = &clk_ops_branch,
3027 CLK_INIT(gcc_pdm2_clk.c),
3028 },
3029};
3030
3031static struct branch_clk gcc_pdm_ahb_clk = {
3032 .cbcr_reg = PDM_AHB_CBCR,
3033 .has_sibling = 1,
3034 .base = &virt_bases[GCC_BASE],
3035 .c = {
3036 .dbg_name = "gcc_pdm_ahb_clk",
3037 .ops = &clk_ops_branch,
3038 CLK_INIT(gcc_pdm_ahb_clk.c),
3039 },
3040};
3041
3042static struct local_vote_clk gcc_prng_ahb_clk = {
3043 .cbcr_reg = PRNG_AHB_CBCR,
3044 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3045 .en_mask = BIT(8),
3046 .base = &virt_bases[GCC_BASE],
3047 .c = {
3048 .dbg_name = "gcc_prng_ahb_clk",
3049 .ops = &clk_ops_vote,
3050 CLK_INIT(gcc_prng_ahb_clk.c),
3051 },
3052};
3053
3054static struct local_vote_clk gcc_qdss_dap_clk = {
3055 .cbcr_reg = QDSS_DAP_CBCR,
3056 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3057 .en_mask = BIT(21),
3058 .base = &virt_bases[GCC_BASE],
3059 .c = {
3060 .dbg_name = "gcc_qdss_dap_clk",
3061 .ops = &clk_ops_vote,
3062 CLK_INIT(gcc_qdss_dap_clk.c),
3063 },
3064};
3065
3066static struct branch_clk gcc_sdcc1_ahb_clk = {
3067 .cbcr_reg = SDCC1_AHB_CBCR,
3068 .has_sibling = 1,
3069 .base = &virt_bases[GCC_BASE],
3070 .c = {
3071 .dbg_name = "gcc_sdcc1_ahb_clk",
3072 .ops = &clk_ops_branch,
3073 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3074 },
3075};
3076
3077static struct branch_clk gcc_sdcc1_apps_clk = {
3078 .cbcr_reg = SDCC1_APPS_CBCR,
3079 .has_sibling = 0,
3080 .base = &virt_bases[GCC_BASE],
3081 .c = {
3082 .dbg_name = "gcc_sdcc1_apps_clk",
3083 .parent = &sdcc1_apps_clk_src.c,
3084 .ops = &clk_ops_branch,
3085 CLK_INIT(gcc_sdcc1_apps_clk.c),
3086 },
3087};
3088
3089static struct branch_clk gcc_sdcc1_ice_core_clk = {
3090 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3091 .has_sibling = 0,
3092 .base = &virt_bases[GCC_BASE],
3093 .c = {
3094 .dbg_name = "gcc_sdcc1_ice_core_clk",
3095 .parent = &sdcc1_ice_core_clk_src.c,
3096 .ops = &clk_ops_branch,
3097 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3098 }
3099};
3100
3101static struct branch_clk gcc_sdcc2_ahb_clk = {
3102 .cbcr_reg = SDCC2_AHB_CBCR,
3103 .has_sibling = 1,
3104 .base = &virt_bases[GCC_BASE],
3105 .c = {
3106 .dbg_name = "gcc_sdcc2_ahb_clk",
3107 .ops = &clk_ops_branch,
3108 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3109 },
3110};
3111
3112static struct branch_clk gcc_sdcc2_apps_clk = {
3113 .cbcr_reg = SDCC2_APPS_CBCR,
3114 .has_sibling = 0,
3115 .base = &virt_bases[GCC_BASE],
3116 .c = {
3117 .dbg_name = "gcc_sdcc2_apps_clk",
3118 .parent = &sdcc2_apps_clk_src.c,
3119 .ops = &clk_ops_branch,
3120 CLK_INIT(gcc_sdcc2_apps_clk.c),
3121 },
3122};
3123
3124static struct local_vote_clk gcc_cpp_tbu_clk = {
3125 .cbcr_reg = CPP_TBU_CBCR,
3126 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3127 .en_mask = BIT(14),
3128 .base = &virt_bases[GCC_BASE],
3129 .c = {
3130 .dbg_name = "gcc_cpp_tbu_clk",
3131 .ops = &clk_ops_vote,
3132 CLK_INIT(gcc_cpp_tbu_clk.c),
3133 },
3134};
3135
3136static struct local_vote_clk gcc_gfx_tbu_clk = {
3137 .cbcr_reg = GFX_TBU_CBCR,
3138 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3139 .en_mask = BIT(3),
3140 .base = &virt_bases[GCC_BASE],
3141 .c = {
3142 .dbg_name = "gcc_gfx_tbu_clk",
3143 .ops = &clk_ops_vote,
3144 CLK_INIT(gcc_gfx_tbu_clk.c),
3145 },
3146};
3147
3148static struct local_vote_clk gcc_gfx_tcu_clk = {
3149 .cbcr_reg = GFX_TCU_CBCR,
3150 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3151 .en_mask = BIT(2),
3152 .base = &virt_bases[GCC_BASE],
3153 .c = {
3154 .dbg_name = "gcc_gfx_tcu_clk",
3155 .ops = &clk_ops_vote,
3156 CLK_INIT(gcc_gfx_tcu_clk.c),
3157 },
3158};
3159
3160static struct local_vote_clk gcc_apss_tcu_clk = {
3161 .cbcr_reg = APSS_TCU_CBCR,
3162 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3163 .en_mask = BIT(1),
3164 .base = &virt_bases[GCC_BASE],
3165 .c = {
3166 .dbg_name = "gcc_apss_tcu_clk",
3167 .ops = &clk_ops_vote,
3168 CLK_INIT(gcc_apss_tcu_clk.c),
3169 },
3170};
3171
3172static struct local_vote_clk gcc_gtcu_ahb_clk = {
3173 .cbcr_reg = GTCU_AHB_CBCR,
3174 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3175 .en_mask = BIT(13),
3176 .base = &virt_bases[GCC_BASE],
3177 .c = {
3178 .dbg_name = "gcc_gtcu_ahb_clk",
3179 .ops = &clk_ops_vote,
3180 CLK_INIT(gcc_gtcu_ahb_clk.c),
3181 },
3182};
3183
3184static struct local_vote_clk gcc_ipa_tbu_clk = {
3185 .cbcr_reg = IPA_TBU_CBCR,
3186 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3187 .en_mask = BIT(16),
3188 .base = &virt_bases[GCC_BASE],
3189 .c = {
3190 .dbg_name = "gcc_ipa_tbu_clk",
3191 .ops = &clk_ops_vote,
3192 CLK_INIT(gcc_ipa_tbu_clk.c),
3193 },
3194};
3195
3196static struct local_vote_clk gcc_jpeg_tbu_clk = {
3197 .cbcr_reg = JPEG_TBU_CBCR,
3198 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3199 .en_mask = BIT(10),
3200 .base = &virt_bases[GCC_BASE],
3201 .c = {
3202 .dbg_name = "gcc_jpeg_tbu_clk",
3203 .ops = &clk_ops_vote,
3204 CLK_INIT(gcc_jpeg_tbu_clk.c),
3205 },
3206};
3207
3208static struct local_vote_clk gcc_mdp_tbu_clk = {
3209 .cbcr_reg = MDP_TBU_CBCR,
3210 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3211 .en_mask = BIT(4),
3212 .base = &virt_bases[GCC_BASE],
3213 .c = {
3214 .dbg_name = "gcc_mdp_tbu_clk",
3215 .ops = &clk_ops_vote,
3216 CLK_INIT(gcc_mdp_tbu_clk.c),
3217 },
3218};
3219
3220static struct local_vote_clk gcc_smmu_cfg_clk = {
3221 .cbcr_reg = SMMU_CFG_CBCR,
3222 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3223 .en_mask = BIT(12),
3224 .base = &virt_bases[GCC_BASE],
3225 .c = {
3226 .dbg_name = "gcc_smmu_cfg_clk",
3227 .ops = &clk_ops_vote,
3228 CLK_INIT(gcc_smmu_cfg_clk.c),
3229 },
3230};
3231
3232static struct local_vote_clk gcc_venus_tbu_clk = {
3233 .cbcr_reg = VENUS_TBU_CBCR,
3234 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3235 .en_mask = BIT(5),
3236 .base = &virt_bases[GCC_BASE],
3237 .c = {
3238 .dbg_name = "gcc_venus_tbu_clk",
3239 .ops = &clk_ops_vote,
3240 CLK_INIT(gcc_venus_tbu_clk.c),
3241 },
3242};
3243
3244static struct local_vote_clk gcc_vfe1_tbu_clk = {
3245 .cbcr_reg = VFE1_TBU_CBCR,
3246 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3247 .en_mask = BIT(17),
3248 .base = &virt_bases[GCC_BASE],
3249 .c = {
3250 .dbg_name = "gcc_vfe1_tbu_clk",
3251 .ops = &clk_ops_vote,
3252 CLK_INIT(gcc_vfe1_tbu_clk.c),
3253 },
3254};
3255
3256static struct local_vote_clk gcc_vfe_tbu_clk = {
3257 .cbcr_reg = VFE_TBU_CBCR,
3258 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3259 .en_mask = BIT(9),
3260 .base = &virt_bases[GCC_BASE],
3261 .c = {
3262 .dbg_name = "gcc_vfe_tbu_clk",
3263 .ops = &clk_ops_vote,
3264 CLK_INIT(gcc_vfe_tbu_clk.c),
3265 },
3266};
3267
3268static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3269 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3270 .has_sibling = 1,
3271 .base = &virt_bases[GCC_BASE],
3272 .c = {
3273 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3274 .ops = &clk_ops_branch,
3275 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3276 },
3277};
3278
3279static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3280 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3281 .has_sibling = 1,
3282 .base = &virt_bases[GCC_BASE],
3283 .c = {
3284 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3285 .ops = &clk_ops_branch,
3286 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3287 },
3288};
3289
3290static struct branch_clk gcc_usb_fs_ahb_clk = {
3291 .cbcr_reg = USB_FS_AHB_CBCR,
3292 .has_sibling = 1,
3293 .base = &virt_bases[GCC_BASE],
3294 .c = {
3295 .dbg_name = "gcc_usb_fs_ahb_clk",
3296 .ops = &clk_ops_branch,
3297 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3298 },
3299};
3300
3301static struct branch_clk gcc_usb_fs_ic_clk = {
3302 .cbcr_reg = USB_FS_IC_CBCR,
3303 .has_sibling = 0,
3304 .base = &virt_bases[GCC_BASE],
3305 .c = {
3306 .dbg_name = "gcc_usb_fs_ic_clk",
3307 .parent = &usb_fs_ic_clk_src.c,
3308 .ops = &clk_ops_branch,
3309 CLK_INIT(gcc_usb_fs_ic_clk.c),
3310 },
3311};
3312
3313static struct branch_clk gcc_usb_fs_system_clk = {
3314 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3315 .bcr_reg = USB_FS_BCR,
3316 .has_sibling = 0,
3317 .base = &virt_bases[GCC_BASE],
3318 .c = {
3319 .dbg_name = "gcc_usb_fs_system_clk",
3320 .parent = &usb_fs_system_clk_src.c,
3321 .ops = &clk_ops_branch,
3322 CLK_INIT(gcc_usb_fs_system_clk.c),
3323 },
3324};
3325
3326static struct branch_clk gcc_usb_hs_ahb_clk = {
3327 .cbcr_reg = USB_HS_AHB_CBCR,
3328 .has_sibling = 1,
3329 .base = &virt_bases[GCC_BASE],
3330 .c = {
3331 .dbg_name = "gcc_usb_hs_ahb_clk",
3332 .ops = &clk_ops_branch,
3333 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3334 },
3335};
3336
3337static struct branch_clk gcc_usb_hs_system_clk = {
3338 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3339 .bcr_reg = USB_HS_BCR,
3340 .has_sibling = 0,
3341 .base = &virt_bases[GCC_BASE],
3342 .c = {
3343 .dbg_name = "gcc_usb_hs_system_clk",
3344 .parent = &usb_hs_system_clk_src.c,
3345 .ops = &clk_ops_branch,
3346 CLK_INIT(gcc_usb_hs_system_clk.c),
3347 },
3348};
3349
3350static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3351 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3352 .base = &virt_bases[GCC_BASE],
3353 .c = {
3354 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3355 .ops = &clk_ops_rst,
3356 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3357 },
3358};
3359
3360static struct reset_clk gcc_qusb2_phy_clk = {
3361 .reset_reg = QUSB2_PHY_BCR,
3362 .base = &virt_bases[GCC_BASE],
3363 .c = {
3364 .dbg_name = "gcc_qusb2_phy_clk",
3365 .ops = &clk_ops_rst,
3366 CLK_INIT(gcc_qusb2_phy_clk.c),
3367 },
3368};
3369
3370static struct branch_clk gcc_venus0_ahb_clk = {
3371 .cbcr_reg = VENUS0_AHB_CBCR,
3372 .has_sibling = 1,
3373 .base = &virt_bases[GCC_BASE],
3374 .c = {
3375 .dbg_name = "gcc_venus0_ahb_clk",
3376 .ops = &clk_ops_branch,
3377 CLK_INIT(gcc_venus0_ahb_clk.c),
3378 },
3379};
3380
3381static struct branch_clk gcc_venus0_axi_clk = {
3382 .cbcr_reg = VENUS0_AXI_CBCR,
3383 .has_sibling = 1,
3384 .base = &virt_bases[GCC_BASE],
3385 .c = {
3386 .dbg_name = "gcc_venus0_axi_clk",
3387 .ops = &clk_ops_branch,
3388 CLK_INIT(gcc_venus0_axi_clk.c),
3389 },
3390};
3391
3392static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3393 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3394 .has_sibling = 1,
3395 .base = &virt_bases[GCC_BASE],
3396 .c = {
3397 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3398 .parent = &vcodec0_clk_src.c,
3399 .ops = &clk_ops_branch,
3400 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3401 },
3402};
3403
3404static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3405 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3406 .has_sibling = 1,
3407 .base = &virt_bases[GCC_BASE],
3408 .c = {
3409 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3410 .parent = &vcodec0_clk_src.c,
3411 .ops = &clk_ops_branch,
3412 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3413 },
3414};
3415
3416static struct branch_clk gcc_venus0_vcodec0_clk = {
3417 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3418 .has_sibling = 0,
3419 .base = &virt_bases[GCC_BASE],
3420 .c = {
3421 .dbg_name = "gcc_venus0_vcodec0_clk",
3422 .parent = &vcodec0_clk_src.c,
3423 .ops = &clk_ops_branch,
3424 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3425 },
3426};
3427
3428static struct clk_ops clk_ops_debug_mux;
3429
3430static void __iomem *meas_base;
3431
3432static struct measure_clk apc0_m_clk = {
3433 .c = {
3434 .ops = &clk_ops_empty,
3435 .dbg_name = "apc0_m_clk",
3436 CLK_INIT(apc0_m_clk.c),
3437 },
3438};
3439
3440static struct measure_clk apc1_m_clk = {
3441 .c = {
3442 .ops = &clk_ops_empty,
3443 .dbg_name = "apc1_m_clk",
3444 CLK_INIT(apc1_m_clk.c),
3445 },
3446};
3447
3448static struct measure_clk cci_m_clk = {
3449 .c = {
3450 .ops = &clk_ops_empty,
3451 .dbg_name = "cci_m_clk",
3452 CLK_INIT(cci_m_clk.c),
3453 },
3454};
3455
3456static struct mux_clk apss_debug_ter_mux = {
3457 .ops = &mux_reg_ops,
3458 .mask = 0x3,
3459 .shift = 8,
3460 MUX_SRC_LIST(
3461 {&apc0_m_clk.c, 0},
3462 {&apc1_m_clk.c, 1},
3463 {&cci_m_clk.c, 2},
3464 ),
3465 .base = &meas_base,
3466 .c = {
3467 .dbg_name = "apss_debug_ter_mux",
3468 .ops = &clk_ops_gen_mux,
3469 CLK_INIT(apss_debug_ter_mux.c),
3470 },
3471};
3472
3473static struct mux_clk apss_debug_sec_mux = {
3474 .ops = &mux_reg_ops,
3475 .mask = 0x7,
3476 .shift = 12,
3477 MUX_SRC_LIST(
3478 {&apss_debug_ter_mux.c, 0},
3479 ),
3480 MUX_REC_SRC_LIST(
3481 &apss_debug_ter_mux.c,
3482 ),
3483 .base = &meas_base,
3484 .c = {
3485 .dbg_name = "apss_debug_sec_mux",
3486 .ops = &clk_ops_gen_mux,
3487 CLK_INIT(apss_debug_sec_mux.c),
3488 },
3489};
3490
3491static struct mux_clk apss_debug_pri_mux = {
3492 .ops = &mux_reg_ops,
3493 .mask = 0x3,
3494 .shift = 16,
3495 MUX_SRC_LIST(
3496 {&apss_debug_sec_mux.c, 0},
3497 ),
3498 MUX_REC_SRC_LIST(
3499 &apss_debug_sec_mux.c,
3500 ),
3501 .base = &meas_base,
3502 .c = {
3503 .dbg_name = "apss_debug_pri_mux",
3504 .ops = &clk_ops_gen_mux,
3505 CLK_INIT(apss_debug_pri_mux.c),
3506 },
3507};
3508
3509static struct measure_clk_data debug_mux_priv = {
3510 .cxo = &xo_clk_src.c,
3511 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3512 .plltest_val = 0x51A00,
3513 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3514 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3515 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3516 .base = &virt_bases[GCC_BASE],
3517};
3518
3519static struct mux_clk gcc_debug_mux = {
3520 .priv = &debug_mux_priv,
3521 .ops = &mux_reg_ops,
3522 .offset = GCC_DEBUG_CLK_CTL,
3523 .mask = 0x1FF,
3524 .en_offset = GCC_DEBUG_CLK_CTL,
3525 .en_mask = BIT(16),
3526 .base = &virt_bases[GCC_BASE],
3527 MUX_REC_SRC_LIST(
3528 &apss_debug_pri_mux.c,
3529 ),
3530 MUX_SRC_LIST(
3531 { &apss_debug_pri_mux.c, 0x016A},
3532 { &snoc_clk.c, 0x0000 },
3533 { &sysmmnoc_clk.c, 0x0001 },
3534 { &pnoc_clk.c, 0x0008 },
3535 { &bimc_clk.c, 0x0154 },
3536 { &gcc_gp1_clk.c, 0x0010 },
3537 { &gcc_gp2_clk.c, 0x0011 },
3538 { &gcc_gp3_clk.c, 0x0012 },
3539 { &gcc_bimc_gfx_clk.c, 0x002d },
3540 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3541 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3542 { &gcc_apss_tcu_clk.c, 0x0050 },
3543 { &gcc_mdp_tbu_clk.c, 0x0051 },
3544 { &gcc_gfx_tbu_clk.c, 0x0052 },
3545 { &gcc_gfx_tcu_clk.c, 0x0053 },
3546 { &gcc_venus_tbu_clk.c, 0x0054 },
3547 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3548 { &gcc_vfe_tbu_clk.c, 0x005a },
3549 { &gcc_smmu_cfg_clk.c, 0x005b },
3550 { &gcc_jpeg_tbu_clk.c, 0x005c },
3551 { &gcc_usb_hs_system_clk.c, 0x0060 },
3552 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3553 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3554 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3555 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3556 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3557 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3558 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3559 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3560 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3561 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3562 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3563 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3564 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3565 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3566 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3567 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3568 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3569 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3570 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3571 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3572 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3573 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3574 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3575 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3576 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3577 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3578 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3579 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3580 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3581 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3582 { &gcc_camss_ahb_clk.c, 0x00a8 },
3583 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3584 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3585 { &gcc_camss_gp0_clk.c, 0x00ab },
3586 { &gcc_camss_gp1_clk.c, 0x00ac },
3587 { &gcc_camss_mclk0_clk.c, 0x00ad },
3588 { &gcc_camss_mclk1_clk.c, 0x00ae },
3589 { &gcc_camss_cci_clk.c, 0x00af },
3590 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3591 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3592 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3593 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3594 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3595 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3596 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3597 { &gcc_camss_cpp_clk.c, 0x00b9 },
3598 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3599 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3600 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3601 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3602 { &gcc_camss_csi0_clk.c, 0x00c0 },
3603 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3604 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3605 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3606 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3607 { &gcc_camss_csi1_clk.c, 0x00c5 },
3608 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3609 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3610 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3611 { &gcc_pdm2_clk.c, 0x00d2 },
3612 { &gcc_prng_ahb_clk.c, 0x00d8 },
3613 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3614 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3615 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3616 { &gcc_camss_csi2_clk.c, 0x00e3 },
3617 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3618 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3619 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3620 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3621 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3622 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3623 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3624 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3625 { &gcc_crypto_clk.c, 0x0138 },
3626 { &gcc_crypto_axi_clk.c, 0x0139 },
3627 { &gcc_crypto_ahb_clk.c, 0x013a },
3628 { &gcc_bimc_gpu_clk.c, 0x0157 },
3629 { &gcc_ipa_tbu_clk.c, 0x0198 },
3630 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3631 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3632 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3633 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3634 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3635 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3636 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3637 { &gcc_camss_mclk2_clk.c, 0x01bd },
3638 { &gcc_oxili_timer_clk.c, 0x01e9 },
3639 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3640 { &gcc_oxili_ahb_clk.c, 0x01eb },
3641 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3642 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3643 { &gcc_venus0_axi_clk.c, 0x01f2 },
3644 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3645 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3646 { &gcc_mdss_axi_clk.c, 0x01f7 },
3647 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3648 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3649 { &gcc_mdss_vsync_clk.c, 0x01fb },
3650 { &gcc_mdss_byte0_clk.c, 0x01fc },
3651 { &gcc_mdss_esc0_clk.c, 0x01fd },
3652 { &wcnss_m_clk.c, 0x0ec },
3653 ),
3654 .c = {
3655 .dbg_name = "gcc_debug_mux",
3656 .ops = &clk_ops_debug_mux,
3657 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3658 CLK_INIT(gcc_debug_mux.c),
3659 },
3660};
3661
3662static struct mux_clk gcc_debug_mux_8937 = {
3663 .priv = &debug_mux_priv,
3664 .ops = &mux_reg_ops,
3665 .offset = GCC_DEBUG_CLK_CTL,
3666 .mask = 0x1FF,
3667 .en_offset = GCC_DEBUG_CLK_CTL,
3668 .en_mask = BIT(16),
3669 .base = &virt_bases[GCC_BASE],
3670 MUX_REC_SRC_LIST(
3671 &apss_debug_pri_mux.c,
3672 ),
3673 MUX_SRC_LIST(
3674 { &apss_debug_pri_mux.c, 0x016A},
3675 { &snoc_clk.c, 0x0000 },
3676 { &sysmmnoc_clk.c, 0x0001 },
3677 { &pnoc_clk.c, 0x0008 },
3678 { &bimc_clk.c, 0x015A },
3679 { &ipa_clk.c, 0x1B0 },
3680 { &gcc_gp1_clk.c, 0x0010 },
3681 { &gcc_gp2_clk.c, 0x0011 },
3682 { &gcc_gp3_clk.c, 0x0012 },
3683 { &gcc_bimc_gfx_clk.c, 0x002d },
3684 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3685 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3686 { &gcc_qdss_dap_clk.c, 0x0049 },
3687 { &gcc_apss_tcu_clk.c, 0x0050 },
3688 { &gcc_mdp_tbu_clk.c, 0x0051 },
3689 { &gcc_gfx_tbu_clk.c, 0x0052 },
3690 { &gcc_gfx_tcu_clk.c, 0x0053 },
3691 { &gcc_venus_tbu_clk.c, 0x0054 },
3692 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3693 { &gcc_vfe_tbu_clk.c, 0x005a },
3694 { &gcc_smmu_cfg_clk.c, 0x005b },
3695 { &gcc_jpeg_tbu_clk.c, 0x005c },
3696 { &gcc_usb_hs_system_clk.c, 0x0060 },
3697 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3698 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3699 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3700 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3701 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3702 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3703 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3704 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3705 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3706 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3707 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3708 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3709 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3710 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3711 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3712 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3713 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3714 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3715 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3716 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3717 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3718 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3719 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3720 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3721 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3722 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3723 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3724 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3725 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3726 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3727 { &gcc_camss_ahb_clk.c, 0x00a8 },
3728 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3729 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3730 { &gcc_camss_gp0_clk.c, 0x00ab },
3731 { &gcc_camss_gp1_clk.c, 0x00ac },
3732 { &gcc_camss_mclk0_clk.c, 0x00ad },
3733 { &gcc_camss_mclk1_clk.c, 0x00ae },
3734 { &gcc_camss_cci_clk.c, 0x00af },
3735 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3736 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3737 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3738 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3739 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3740 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3741 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3742 { &gcc_camss_cpp_clk.c, 0x00b9 },
3743 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3744 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3745 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3746 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3747 { &gcc_camss_csi0_clk.c, 0x00c0 },
3748 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3749 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3750 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3751 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3752 { &gcc_camss_csi1_clk.c, 0x00c5 },
3753 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3754 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3755 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3756 { &gcc_pdm2_clk.c, 0x00d2 },
3757 { &gcc_prng_ahb_clk.c, 0x00d8 },
3758 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3759 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3760 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3761 { &gcc_camss_csi2_clk.c, 0x00e3 },
3762 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3763 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3764 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3765 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3766 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3767 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3768 { &gcc_crypto_clk.c, 0x0138 },
3769 { &gcc_crypto_axi_clk.c, 0x0139 },
3770 { &gcc_crypto_ahb_clk.c, 0x013a },
3771 { &gcc_bimc_gpu_clk.c, 0x0157 },
3772 { &gcc_ipa_tbu_clk.c, 0x0198 },
3773 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3774 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3775 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3776 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3777 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3778 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3779 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3780 { &gcc_dcc_clk.c, 0x01b9 },
3781 { &gcc_camss_mclk2_clk.c, 0x01bd },
3782 { &gcc_oxili_timer_clk.c, 0x01e9 },
3783 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3784 { &gcc_oxili_aon_clk.c, 0x00ee },
3785 { &gcc_oxili_ahb_clk.c, 0x01eb },
3786 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3787 { &gcc_venus0_axi_clk.c, 0x01f2 },
3788 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3789 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3790 { &gcc_mdss_axi_clk.c, 0x01f7 },
3791 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3792 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3793 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3794 { &gcc_mdss_vsync_clk.c, 0x01fb },
3795 { &gcc_mdss_byte0_clk.c, 0x01fc },
3796 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3797 { &gcc_mdss_esc0_clk.c, 0x01fd },
3798 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3799 { &wcnss_m_clk.c, 0x0ec },
3800 ),
3801 .c = {
3802 .dbg_name = "gcc_debug_mux_8937",
3803 .ops = &clk_ops_debug_mux,
3804 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3805 CLK_INIT(gcc_debug_mux_8937.c),
3806 },
3807};
3808
3809/* Clock lookup */
3810static struct clk_lookup msm_clocks_lookup_common[] = {
3811 /* RPM clocks */
3812 CLK_LIST(xo_clk_src),
3813 CLK_LIST(xo_a_clk_src),
3814 CLK_LIST(xo_otg_clk),
3815 CLK_LIST(xo_lpm_clk),
3816 CLK_LIST(xo_pil_mss_clk),
3817 CLK_LIST(xo_pil_pronto_clk),
3818 CLK_LIST(xo_wlan_clk),
3819 CLK_LIST(xo_pil_lpass_clk),
3820
3821 CLK_LIST(sysmmnoc_msmbus_clk),
3822 CLK_LIST(snoc_msmbus_clk),
3823 CLK_LIST(snoc_msmbus_a_clk),
3824 CLK_LIST(sysmmnoc_msmbus_a_clk),
3825 CLK_LIST(pnoc_msmbus_clk),
3826 CLK_LIST(pnoc_msmbus_a_clk),
3827 CLK_LIST(bimc_msmbus_clk),
3828 CLK_LIST(bimc_msmbus_a_clk),
3829 CLK_LIST(pnoc_keepalive_a_clk),
3830
3831 CLK_LIST(pnoc_usb_a_clk),
3832 CLK_LIST(snoc_usb_a_clk),
3833 CLK_LIST(bimc_usb_a_clk),
3834 CLK_LIST(pnoc_usb_clk),
3835 CLK_LIST(snoc_usb_clk),
3836 CLK_LIST(bimc_usb_clk),
3837
3838 CLK_LIST(snoc_wcnss_a_clk),
3839 CLK_LIST(bimc_wcnss_a_clk),
3840
3841 CLK_LIST(qdss_clk),
3842 CLK_LIST(qdss_a_clk),
3843
3844 CLK_LIST(snoc_clk),
3845 CLK_LIST(sysmmnoc_clk),
3846 CLK_LIST(pnoc_clk),
3847 CLK_LIST(bimc_clk),
3848 CLK_LIST(snoc_a_clk),
3849 CLK_LIST(sysmmnoc_a_clk),
3850 CLK_LIST(pnoc_a_clk),
3851 CLK_LIST(bimc_a_clk),
3852
3853 CLK_LIST(bb_clk1),
3854 CLK_LIST(bb_clk1_a),
3855 CLK_LIST(bb_clk2),
3856 CLK_LIST(bb_clk2_a),
3857 CLK_LIST(rf_clk2),
3858 CLK_LIST(rf_clk2_a),
3859 CLK_LIST(div_clk2),
3860 CLK_LIST(div_clk2_a),
3861
3862 CLK_LIST(bb_clk1_pin),
3863 CLK_LIST(bb_clk1_a_pin),
3864 CLK_LIST(bb_clk2_pin),
3865 CLK_LIST(bb_clk2_a_pin),
3866
3867 CLK_LIST(gpll0_clk_src),
3868 CLK_LIST(gpll0_ao_clk_src),
3869 CLK_LIST(gpll6_clk_src),
3870 CLK_LIST(gpll4_clk_src),
3871 CLK_LIST(gpll3_clk_src),
3872 CLK_LIST(a53ss_c1_pll),
3873 CLK_LIST(gcc_blsp1_ahb_clk),
3874 CLK_LIST(gcc_blsp2_ahb_clk),
3875 CLK_LIST(gcc_boot_rom_ahb_clk),
3876 CLK_LIST(gcc_crypto_ahb_clk),
3877 CLK_LIST(gcc_crypto_axi_clk),
3878 CLK_LIST(gcc_crypto_clk),
3879 CLK_LIST(gcc_prng_ahb_clk),
3880 CLK_LIST(gcc_cpp_tbu_clk),
3881 CLK_LIST(gcc_apss_tcu_clk),
3882 CLK_LIST(gcc_jpeg_tbu_clk),
3883 CLK_LIST(gcc_mdp_tbu_clk),
3884 CLK_LIST(gcc_smmu_cfg_clk),
3885 CLK_LIST(gcc_venus_tbu_clk),
3886 CLK_LIST(gcc_vfe1_tbu_clk),
3887 CLK_LIST(gcc_vfe_tbu_clk),
3888 CLK_LIST(camss_top_ahb_clk_src),
3889 CLK_LIST(apss_ahb_clk_src),
3890 CLK_LIST(csi0_clk_src),
3891 CLK_LIST(csi1_clk_src),
3892 CLK_LIST(csi2_clk_src),
3893 CLK_LIST(vcodec0_clk_src),
3894 CLK_LIST(vfe0_clk_src),
3895 CLK_LIST(vfe1_clk_src),
3896 CLK_LIST(gfx3d_clk_src),
3897 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3898 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3899 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3900 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3901 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3902 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3903 CLK_LIST(blsp1_uart1_apps_clk_src),
3904 CLK_LIST(blsp1_uart2_apps_clk_src),
3905 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3906 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3907 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3908 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3909 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3910 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3911 CLK_LIST(blsp2_uart1_apps_clk_src),
3912 CLK_LIST(blsp2_uart2_apps_clk_src),
3913 CLK_LIST(cci_clk_src),
3914 CLK_LIST(cpp_clk_src),
3915 CLK_LIST(camss_gp0_clk_src),
3916 CLK_LIST(camss_gp1_clk_src),
3917 CLK_LIST(jpeg0_clk_src),
3918 CLK_LIST(mclk0_clk_src),
3919 CLK_LIST(mclk1_clk_src),
3920 CLK_LIST(mclk2_clk_src),
3921 CLK_LIST(csi0phytimer_clk_src),
3922 CLK_LIST(csi1phytimer_clk_src),
3923 CLK_LIST(crypto_clk_src),
3924 CLK_LIST(gp1_clk_src),
3925 CLK_LIST(gp2_clk_src),
3926 CLK_LIST(gp3_clk_src),
3927 CLK_LIST(esc0_clk_src),
3928 CLK_LIST(mdp_clk_src),
3929 CLK_LIST(vsync_clk_src),
3930 CLK_LIST(pdm2_clk_src),
3931 CLK_LIST(sdcc1_apps_clk_src),
3932 CLK_LIST(sdcc1_ice_core_clk_src),
3933 CLK_LIST(sdcc2_apps_clk_src),
3934 CLK_LIST(usb_hs_system_clk_src),
3935 CLK_LIST(gcc_bimc_gpu_clk),
3936 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3937 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3938 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3939 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3940 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3941 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3942 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3943 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3944 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3945 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3946 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3947 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3948 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3949 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3950 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3951 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3952 CLK_LIST(gcc_camss_cci_ahb_clk),
3953 CLK_LIST(gcc_camss_cci_clk),
3954 CLK_LIST(gcc_camss_cpp_ahb_clk),
3955 CLK_LIST(gcc_camss_cpp_axi_clk),
3956 CLK_LIST(gcc_camss_cpp_clk),
3957 CLK_LIST(gcc_camss_csi0_ahb_clk),
3958 CLK_LIST(gcc_camss_csi0_clk),
3959 CLK_LIST(gcc_camss_csi0phy_clk),
3960 CLK_LIST(gcc_camss_csi0pix_clk),
3961 CLK_LIST(gcc_camss_csi0rdi_clk),
3962 CLK_LIST(gcc_camss_csi1_ahb_clk),
3963 CLK_LIST(gcc_camss_csi1_clk),
3964 CLK_LIST(gcc_camss_csi1phy_clk),
3965 CLK_LIST(gcc_camss_csi1pix_clk),
3966 CLK_LIST(gcc_camss_csi1rdi_clk),
3967 CLK_LIST(gcc_camss_csi2_ahb_clk),
3968 CLK_LIST(gcc_camss_csi2_clk),
3969 CLK_LIST(gcc_camss_csi2phy_clk),
3970 CLK_LIST(gcc_camss_csi2pix_clk),
3971 CLK_LIST(gcc_camss_csi2rdi_clk),
3972 CLK_LIST(gcc_camss_csi_vfe0_clk),
3973 CLK_LIST(gcc_camss_csi_vfe1_clk),
3974 CLK_LIST(gcc_camss_gp0_clk),
3975 CLK_LIST(gcc_camss_gp1_clk),
3976 CLK_LIST(gcc_camss_ispif_ahb_clk),
3977 CLK_LIST(gcc_camss_jpeg0_clk),
3978 CLK_LIST(gcc_camss_jpeg_ahb_clk),
3979 CLK_LIST(gcc_camss_jpeg_axi_clk),
3980 CLK_LIST(gcc_camss_mclk0_clk),
3981 CLK_LIST(gcc_camss_mclk1_clk),
3982 CLK_LIST(gcc_camss_mclk2_clk),
3983 CLK_LIST(gcc_camss_micro_ahb_clk),
3984 CLK_LIST(gcc_camss_csi0phytimer_clk),
3985 CLK_LIST(gcc_camss_csi1phytimer_clk),
3986 CLK_LIST(gcc_camss_ahb_clk),
3987 CLK_LIST(gcc_camss_top_ahb_clk),
3988 CLK_LIST(gcc_camss_vfe0_clk),
3989 CLK_LIST(gcc_camss_vfe_ahb_clk),
3990 CLK_LIST(gcc_camss_vfe_axi_clk),
3991 CLK_LIST(gcc_camss_vfe1_ahb_clk),
3992 CLK_LIST(gcc_camss_vfe1_axi_clk),
3993 CLK_LIST(gcc_camss_vfe1_clk),
3994 CLK_LIST(gcc_gp1_clk),
3995 CLK_LIST(gcc_gp2_clk),
3996 CLK_LIST(gcc_gp3_clk),
3997 CLK_LIST(gcc_mdss_ahb_clk),
3998 CLK_LIST(gcc_mdss_axi_clk),
3999 CLK_LIST(gcc_mdss_esc0_clk),
4000 CLK_LIST(gcc_mdss_mdp_clk),
4001 CLK_LIST(gcc_mdss_vsync_clk),
4002 CLK_LIST(gcc_mss_cfg_ahb_clk),
4003 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
4004 CLK_LIST(gcc_bimc_gfx_clk),
4005 CLK_LIST(gcc_oxili_ahb_clk),
4006 CLK_LIST(gcc_oxili_gfx3d_clk),
4007 CLK_LIST(gcc_pdm2_clk),
4008 CLK_LIST(gcc_pdm_ahb_clk),
4009 CLK_LIST(gcc_sdcc1_ahb_clk),
4010 CLK_LIST(gcc_sdcc1_apps_clk),
4011 CLK_LIST(gcc_sdcc1_ice_core_clk),
4012 CLK_LIST(gcc_sdcc2_ahb_clk),
4013 CLK_LIST(gcc_sdcc2_apps_clk),
4014 CLK_LIST(gcc_usb2a_phy_sleep_clk),
4015 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
4016 CLK_LIST(gcc_usb_hs_ahb_clk),
4017 CLK_LIST(gcc_usb_hs_system_clk),
4018 CLK_LIST(gcc_venus0_ahb_clk),
4019 CLK_LIST(gcc_venus0_axi_clk),
4020 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
4021 CLK_LIST(gcc_venus0_vcodec0_clk),
4022
4023 /* Reset clks */
4024 CLK_LIST(gcc_usb2_hs_phy_only_clk),
4025 CLK_LIST(gcc_qusb2_phy_clk),
4026
4027 /* WCNSS Debug */
4028 CLK_LIST(wcnss_m_clk),
4029};
4030
4031static struct clk_lookup msm_clocks_lookup_8952[] = {
4032 CLK_LIST(a53ss_c0_pll),
4033 CLK_LIST(a53ss_cci_pll),
4034 CLK_LIST(ipa_clk),
4035 CLK_LIST(ipa_a_clk),
4036 CLK_LIST(gpll0_clk_src_8952),
4037 CLK_LIST(gpll0_ao_clk_src_8952),
4038 CLK_LIST(gcc_oxili_gmem_clk),
4039 CLK_LIST(usb_fs_ic_clk_src),
4040 CLK_LIST(gcc_usb_fs_ic_clk),
4041 CLK_LIST(usb_fs_system_clk_src),
4042 CLK_LIST(gcc_usb_fs_system_clk),
4043 CLK_LIST(gcc_gfx_tcu_clk),
4044 CLK_LIST(gcc_gfx_tbu_clk),
4045 CLK_LIST(gcc_gtcu_ahb_clk),
4046 CLK_LIST(gcc_ipa_tbu_clk),
4047 CLK_LIST(gcc_usb_fs_ahb_clk),
4048 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4049 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4050 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4051 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4052 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4053 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4054 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4055 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4056 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4057 CLK_LIST(gcc_oxili_timer_clk),
4058};
4059
4060static struct clk_lookup msm_clocks_lookup_8937[] = {
4061 CLK_LIST(gpll0_clk_src_8937),
4062 CLK_LIST(gpll0_ao_clk_src_8937),
4063 CLK_LIST(gpll0_sleep_clk_src),
4064 CLK_LIST(a53ss_c0_pll),
4065 CLK_LIST(esc1_clk_src),
4066 CLK_LIST(gcc_mdss_esc1_clk),
4067 CLK_LIST(gcc_dcc_clk),
4068 CLK_LIST(gcc_oxili_aon_clk),
4069 CLK_LIST(gcc_qdss_dap_clk),
4070 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4071 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4072 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4073 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4074 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4075 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4076 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4077 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4078 CLK_LIST(gcc_oxili_timer_clk),
4079};
4080
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4081static struct clk_lookup msm_clocks_lookup_sdm429[] = {
4082 CLK_LIST(gpll0_clk_src_8937),
4083 CLK_LIST(gpll0_ao_clk_src_8937),
4084 CLK_LIST(gpll0_sleep_clk_src),
4085 CLK_LIST(esc1_clk_src),
4086 CLK_LIST(gcc_mdss_esc1_clk),
4087 CLK_LIST(gcc_dcc_clk),
4088 CLK_LIST(gcc_oxili_aon_clk),
4089 CLK_LIST(gcc_qdss_dap_clk),
4090 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4091 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4092 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4093 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4094 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4095 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4096 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4097 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4098 CLK_LIST(gcc_oxili_timer_clk),
4099};
4100
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4101static struct clk_lookup msm_clocks_lookup_8917[] = {
4102 CLK_LIST(gpll0_clk_src_8937),
4103 CLK_LIST(gpll0_ao_clk_src_8937),
4104 CLK_LIST(gpll0_sleep_clk_src),
4105 CLK_LIST(bimc_gpu_clk),
4106 CLK_LIST(bimc_gpu_a_clk),
4107 CLK_LIST(gcc_dcc_clk),
4108 CLK_LIST(gcc_qdss_dap_clk),
4109 CLK_LIST(gcc_gfx_tcu_clk),
4110 CLK_LIST(gcc_gfx_tbu_clk),
4111 CLK_LIST(gcc_gtcu_ahb_clk),
4112};
4113
4114static struct clk_lookup msm_clocks_lookup_8920[] = {
4115 CLK_LIST(gpll0_clk_src_8937),
4116 CLK_LIST(gpll0_ao_clk_src_8937),
4117 CLK_LIST(gpll0_sleep_clk_src),
4118 CLK_LIST(bimc_gpu_clk),
4119 CLK_LIST(bimc_gpu_a_clk),
4120 CLK_LIST(gcc_dcc_clk),
4121 CLK_LIST(gcc_qdss_dap_clk),
4122 CLK_LIST(gcc_gfx_tcu_clk),
4123 CLK_LIST(gcc_gfx_tbu_clk),
4124 CLK_LIST(gcc_gtcu_ahb_clk),
4125 CLK_LIST(ipa_clk),
4126 CLK_LIST(ipa_a_clk),
4127 CLK_LIST(gcc_ipa_tbu_clk),
4128};
4129
4130static struct clk_lookup msm_clocks_lookup_8940[] = {
4131 CLK_LIST(gpll0_clk_src_8937),
4132 CLK_LIST(gpll0_ao_clk_src_8937),
4133 CLK_LIST(gpll0_sleep_clk_src),
4134 CLK_LIST(a53ss_c0_pll),
4135 CLK_LIST(esc1_clk_src),
4136 CLK_LIST(gcc_mdss_esc1_clk),
4137 CLK_LIST(gcc_dcc_clk),
4138 CLK_LIST(gcc_oxili_aon_clk),
4139 CLK_LIST(gcc_qdss_dap_clk),
4140 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4141 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4142 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4143 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4144 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4145 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4146 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4147 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4148 CLK_LIST(gcc_oxili_timer_clk),
4149 CLK_LIST(ipa_clk),
4150 CLK_LIST(ipa_a_clk),
4151 CLK_LIST(gcc_ipa_tbu_clk),
4152};
4153
4154/* Please note that the order of reg-names is important */
4155static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4156{
4157 int i, count;
4158 const char *str;
4159 struct resource *res;
4160 struct device *dev = &pdev->dev;
4161
4162 count = of_property_count_strings(dev->of_node, "reg-names");
4163 if (count < nbases) {
4164 dev_err(dev, "missing reg-names property, expected %d strings\n",
4165 nbases);
4166 return -EINVAL;
4167 }
4168
4169 for (i = 0; i < nbases; i++) {
4170 of_property_read_string_index(dev->of_node, "reg-names", i,
4171 &str);
4172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4173 if (!res) {
4174 dev_err(dev, "Unable to retrieve register base.\n");
4175 return -ENOMEM;
4176 }
4177
4178 virt_bases[i] = devm_ioremap(dev, res->start,
4179 resource_size(res));
4180 if (!virt_bases[i]) {
4181 dev_err(dev, "Failed to map in CC registers.\n");
4182 return -ENOMEM;
4183 }
4184 }
4185
4186 return 0;
4187}
4188
4189static const struct msm_reset_map gcc_8952_resets[] = {
4190 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4191 [GCC_USB_FS_BCR] = {0x3F000},
4192 [GCC_USB_HS_BCR] = {0x41000},
4193 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4194 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4195};
4196
4197static void override_for_8917(int speed_bin)
4198{
4199 gpll3_clk_src.c.rate = 930000000;
4200
4201 OVERRIDE_FMAX3(csi0,
4202 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4203 /* Frequency Table same as 8937 */
4204 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4205 OVERRIDE_FMAX3(csi1,
4206 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4207 /* Frequency Table same as 8937 */
4208 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4209 OVERRIDE_FMAX3(csi2,
4210 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4211 /* Frequency Table same as 8937 */
4212 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4213
4214 OVERRIDE_FMAX5(vfe0,
4215 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4216 NOM_PLUS, 329140000, HIGH, 360000000);
4217 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4218 OVERRIDE_FMAX5(vfe1,
4219 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4220 NOM_PLUS, 329140000, HIGH, 360000000);
4221 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4222 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4223 OVERRIDE_FMAX5(vcodec0,
4224 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4225 NOM_PLUS, 329140000, HIGH, 360000000);
4226 OVERRIDE_FMAX4(cpp,
4227 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4228 NOM_PLUS, 360000000);
4229 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4230 OVERRIDE_FMAX5(jpeg0,
4231 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4232 NOM_PLUS, 308570000, HIGH, 320000000);
4233 /* Frequency Table same as 8937 */
4234 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4235
4236 if (speed_bin) {
4237 OVERRIDE_FMAX5(gfx3d,
4238 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4239 NOM_PLUS, 523200000, HIGH, 650000000);
4240 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4241 } else {
4242 OVERRIDE_FMAX5(gfx3d,
4243 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4244 NOM_PLUS, 523200000, HIGH, 598000000);
4245 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4246 }
4247
4248 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4249
4250 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4251 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4252 NOMINAL, 266670000);
4253 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4254 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4255 NOMINAL, 266670000);
4256 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4257 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4258 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4259
4260 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4261 /* Frequency Table same as 8937 */
4262 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4263 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4264
4265 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4266 /* Frequency Table same as 8937 */
4267 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4268 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4269
4270 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4271 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4272 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4273 HIGH, 177780000);
4274}
4275
4276static void override_for_8937(int speed_bin)
4277{
4278 gpll3_clk_src.c.rate = 900000000;
4279 gpll3_clk_src.vco_tbl = p_vco_8937;
4280 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4281 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4282
4283 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4284 OVERRIDE_FMAX3(csi0,
4285 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4286 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4287 OVERRIDE_FMAX3(csi1,
4288 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4289 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4290 OVERRIDE_FMAX3(csi2,
4291 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4292 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4293 OVERRIDE_FMAX4(vfe0,
4294 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4295 NOM_PLUS, 432000000);
4296 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4297 OVERRIDE_FMAX4(vfe1,
4298 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4299 NOM_PLUS, 432000000);
4300 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4301
4302 if (speed_bin) {
4303 OVERRIDE_FMAX6(gfx3d,
4304 LOWER, 216000000, LOW, 300000000,
4305 NOMINAL, 375000000, NOM_PLUS, 400000000,
4306 HIGH, 450000000, SUPER_TUR, 475000000);
4307 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4308 } else {
4309 OVERRIDE_FMAX5(gfx3d,
4310 LOWER, 216000000, LOW, 300000000,
4311 NOMINAL, 375000000, NOM_PLUS, 400000000,
4312 HIGH, 450000000);
4313 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4314 }
4315
4316 OVERRIDE_FMAX5(cpp,
4317 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4318 NOM_PLUS, 342860000, HIGH, 360000000);
4319 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4320 OVERRIDE_FMAX5(jpeg0,
4321 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4322 NOM_PLUS, 308570000, HIGH, 320000000);
4323 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4324 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4325 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4326 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4327 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4328 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4329 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4330 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4331 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4332 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4333 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4334 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4335 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4336 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4337 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4338 OVERRIDE_FMAX5(vcodec0,
4339 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4340 NOM_PLUS, 320000000, HIGH, 360000000);
4341 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4342 NOMINAL, 400000000);
4343}
4344
4345static void get_speed_bin(struct platform_device *pdev, int *bin)
4346{
4347 struct resource *res;
4348 void __iomem *base;
4349 u32 config_efuse;
4350
4351 *bin = 0;
4352
4353 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4354 if (!res) {
4355 dev_info(&pdev->dev,
4356 "No GPU speed binning available. Defaulting to 0.\n");
4357 return;
4358 }
4359
4360 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4361 if (!base) {
4362 dev_warn(&pdev->dev,
4363 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4364 return;
4365 }
4366
4367 config_efuse = readl_relaxed(base);
4368 devm_iounmap(&pdev->dev, base);
4369 *bin = (config_efuse >> 31) & 0x1;
4370
4371 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4372}
4373
4374static int msm_gcc_probe(struct platform_device *pdev)
4375{
4376 struct resource *res;
4377 int ret;
4378 int speed_bin;
4379 u32 regval, nbases = N_BASES;
4380 bool compat_bin = false;
4381 bool compat_bin2 = false;
4382 bool compat_bin3 = false;
4383 bool compat_bin4 = false;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4384 bool compat_bin5 = false;
4385 bool compat_bin6 = false;
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4386
4387 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4388 "qcom,gcc-8937");
4389
4390 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4391 "qcom,gcc-8917");
4392
4393 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4394 "qcom,gcc-8940");
4395
4396 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4397 "qcom,gcc-8920");
4398
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4399 compat_bin5 = of_device_is_compatible(pdev->dev.of_node,
4400 "qcom,gcc-sdm429");
4401
4402 compat_bin6 = of_device_is_compatible(pdev->dev.of_node,
4403 "qcom,gcc-sdm439");
4404
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4405 ret = vote_bimc(&bimc_clk, INT_MAX);
4406 if (ret < 0)
4407 return ret;
4408
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4409 if (compat_bin2 || compat_bin4 || compat_bin5)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4410 nbases = APCS_C0_PLL_BASE;
4411
Odelu Kukatla3e82fd32018-06-05 12:08:53 +0530[diff] [blame]4412 if (compat_bin5 || compat_bin6) {
4413 a53ss_c0_pll.c.ops = &clk_ops_acpu_pll;
4414 a53ss_c1_pll.c.ops = &clk_ops_acpu_pll;
4415 }
4416
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4417 ret = get_mmio_addr(pdev, nbases);
4418 if (ret)
4419 return ret;
4420
4421 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4422 if (!res) {
4423 dev_err(&pdev->dev, "Register base not defined\n");
4424 return -ENOMEM;
4425 }
4426
4427 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4428 resource_size(res));
4429 if (!virt_bases[GCC_BASE]) {
4430 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4431 return -ENOMEM;
4432 }
4433
4434 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4435 if (IS_ERR(vdd_dig.regulator[0])) {
4436 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4437 dev_err(&pdev->dev,
4438 "Unable to get vdd_dig regulator!!!\n");
4439 return PTR_ERR(vdd_dig.regulator[0]);
4440 }
4441
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4442 if (!compat_bin2 && !compat_bin4 && !compat_bin5) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4443 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4444 "vdd_sr2_pll");
4445 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4446 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4447 dev_err(&pdev->dev,
4448 "Unable to get vdd_sr2_pll regulator!!!\n");
4449 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4450 }
4451
4452 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4453 "vdd_sr2_dig");
4454 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4455 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4456 dev_err(&pdev->dev,
4457 "Unable to get vdd_sr2_dig regulator!!!\n");
4458 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4459 }
4460 }
4461
4462 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4463 "vdd_hf_pll");
4464 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4465 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4466 dev_err(&pdev->dev,
4467 "Unable to get vdd_sr2_pll regulator!!!\n");
4468 return PTR_ERR(vdd_hf_pll.regulator[0]);
4469 }
4470
4471 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4472 "vdd_hf_dig");
4473 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4474 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4475 dev_err(&pdev->dev,
4476 "Unable to get vdd_hf_dig regulator!!!\n");
4477 return PTR_ERR(vdd_hf_pll.regulator[1]);
4478 }
4479
4480 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4481 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4482 regval |= BIT(0);
4483 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4484
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4485 if (compat_bin || compat_bin3 || compat_bin5 || compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4486 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4487 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4488 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4489 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4490 regval &= ~BIT(0);
4491 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4492
4493 if (compat_bin5 || compat_bin6)
4494 speed_bin = 0;
4495 else
4496 get_speed_bin(pdev, &speed_bin);
4497
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4498 override_for_8937(speed_bin);
4499
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4500 if (compat_bin5 || compat_bin6) {
4501 vdd_dig.num_levels = VDD_DIG_NUM_439;
4502 vdd_dig.cur_level = VDD_DIG_NUM_439;
4503 vdd_sr2_pll.num_levels = VDD_SR2_PLL_NUM_439;
4504 vdd_sr2_pll.cur_level = VDD_SR2_PLL_NUM_439;
4505 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
4506 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
4507
Odelu Kukatlaff4c6a02018-06-28 12:45:16 +0530[diff] [blame]4508 gpll3_clk_src.test_ctl_hi_val = 0x400000;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4509 gpll3_clk_src.vco_tbl = p_vco;
4510 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
4511 gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;
4512 gpll3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 1400000000;
4513 gfx3d_clk_src.freq_tbl =
4514 ftbl_gcc_oxili_gfx3d_clk_sdm439;
4515
4516 gfx3d_clk_src.c.fmax[VDD_DIG_LOWER] = 320000000;
4517 gfx3d_clk_src.c.fmax[VDD_DIG_LOW] = 400000000;
4518 gfx3d_clk_src.c.fmax[VDD_DIG_NOMINAL] = 510000000;
4519 gfx3d_clk_src.c.fmax[VDD_DIG_NOM_PLUS] = 560000000;
4520 gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 650000000;
4521 }
4522
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4523 if (compat_bin3) {
4524 if (speed_bin) {
4525 gfx3d_clk_src.freq_tbl =
4526 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4527 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4528 500000000;
4529 } else {
4530 gfx3d_clk_src.freq_tbl =
4531 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4532 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4533 475000000;
4534 }
4535 }
4536 } else if (compat_bin2 || compat_bin4) {
4537 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4538 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4539 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4540 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4541 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4542 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4543 get_speed_bin(pdev, &speed_bin);
4544 override_for_8917(speed_bin);
4545
4546 if (compat_bin2) {
4547 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4548 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4549 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4550 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4551 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4552 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4553 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4554 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4555 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4556 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4557 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4558 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4559 }
4560 } else {
4561 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4562 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4563 }
4564
4565 ret = of_msm_clock_register(pdev->dev.of_node,
4566 msm_clocks_lookup_common,
4567 ARRAY_SIZE(msm_clocks_lookup_common));
4568 if (ret)
4569 return ret;
4570
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4571 if (compat_bin || compat_bin6)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4572 ret = of_msm_clock_register(pdev->dev.of_node,
4573 msm_clocks_lookup_8937,
4574 ARRAY_SIZE(msm_clocks_lookup_8937));
4575 else if (compat_bin2)
4576 ret = of_msm_clock_register(pdev->dev.of_node,
4577 msm_clocks_lookup_8917,
4578 ARRAY_SIZE(msm_clocks_lookup_8917));
4579 else if (compat_bin3)
4580 ret = of_msm_clock_register(pdev->dev.of_node,
4581 msm_clocks_lookup_8940,
4582 ARRAY_SIZE(msm_clocks_lookup_8940));
4583 else if (compat_bin4)
4584 ret = of_msm_clock_register(pdev->dev.of_node,
4585 msm_clocks_lookup_8920,
4586 ARRAY_SIZE(msm_clocks_lookup_8920));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4587 else if (compat_bin5)
4588 ret = of_msm_clock_register(pdev->dev.of_node,
4589 msm_clocks_lookup_sdm429,
4590 ARRAY_SIZE(msm_clocks_lookup_sdm429));
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4591 else
4592 ret = of_msm_clock_register(pdev->dev.of_node,
4593 msm_clocks_lookup_8952,
4594 ARRAY_SIZE(msm_clocks_lookup_8952));
4595 if (ret)
4596 return ret;
4597
4598 ret = enable_rpm_scaling();
4599 if (ret)
4600 return ret;
4601
4602 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4603 clk_prepare_enable(&apss_ahb_clk_src.c);
4604
4605 /*
4606 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4607 */
4608 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4609 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4610
4611 clk_prepare_enable(&xo_a_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4612
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4613 if (!compat_bin && !compat_bin3 && !compat_bin5 && !compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4614 /* Configure Sleep and Wakeup cycles for GMEM clock */
4615 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4616 regval ^= 0xFF0;
4617 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4618 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4619 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4620 } else {
4621 /* Configure Sleep and Wakeup cycles for OXILI clock */
4622 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4623 regval &= ~0xF0;
4624 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4625 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4626 }
4627
4628 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4629 if (ret)
4630 return ret;
4631
4632 msm_reset_controller_register(pdev, gcc_8952_resets,
4633 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4634
4635 dev_info(&pdev->dev, "Registered GCC clocks\n");
4636
4637 return 0;
4638}
4639
4640static const struct of_device_id msm_clock_gcc_match_table[] = {
4641 { .compatible = "qcom,gcc-8952" },
4642 { .compatible = "qcom,gcc-8937" },
4643 { .compatible = "qcom,gcc-8917" },
4644 { .compatible = "qcom,gcc-8940" },
4645 { .compatible = "qcom,gcc-8920" },
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame]4646 { .compatible = "qcom,gcc-sdm439" },
4647 { .compatible = "qcom,gcc-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4648 {}
4649};
4650
4651static struct platform_driver msm_clock_gcc_driver = {
4652 .probe = msm_gcc_probe,
4653 .driver = {
4654 .name = "qcom,gcc-8952",
4655 .of_match_table = msm_clock_gcc_match_table,
4656 .owner = THIS_MODULE,
4657 },
4658};
4659
4660static int msm_gcc_spm_probe(struct platform_device *pdev)
4661{
4662 struct resource *res = NULL;
4663 bool compat_bin = false;
4664
4665 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4666 "qcom,spm-8952");
4667
4668 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4669 if (!res) {
4670 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4671 return -ENOMEM;
4672 }
4673
4674 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4675 resource_size(res));
4676 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4677 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4678 return -ENOMEM;
4679 }
4680
4681 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4682 if (!res) {
4683 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4684 return -ENOMEM;
4685 }
4686
4687 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4688 resource_size(res));
4689 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4690 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4691 return -ENOMEM;
4692 }
4693
4694 if (compat_bin) {
4695 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4696 "spm_cci_base");
4697 if (!res) {
4698 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4699 return -ENOMEM;
4700 }
4701
4702 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4703 res->start, resource_size(res));
4704 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4705 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4706 return -ENOMEM;
4707 }
4708 }
4709
4710 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4711
4712 return 0;
4713}
4714
4715static const struct of_device_id msm_clock_spm_match_table[] = {
4716 { .compatible = "qcom,gcc-spm-8952" },
4717 { .compatible = "qcom,gcc-spm-8937" },
4718 {}
4719};
4720
4721static struct platform_driver msm_clock_spm_driver = {
4722 .probe = msm_gcc_spm_probe,
4723 .driver = {
4724 .name = "qcom,gcc-spm-8952",
4725 .of_match_table = msm_clock_spm_match_table,
4726 .owner = THIS_MODULE,
4727 },
4728};
4729
4730static int __init msm_gcc_init(void)
4731{
4732 int ret;
4733
4734 ret = platform_driver_register(&msm_clock_gcc_driver);
4735 if (!ret)
4736 ret = platform_driver_register(&msm_clock_spm_driver);
4737
4738 return ret;
4739}
4740
4741static struct clk_lookup msm_clocks_measure[] = {
4742 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4743 CLK_LIST(apss_debug_pri_mux),
4744 CLK_LIST(apc0_m_clk),
4745 CLK_LIST(apc1_m_clk),
4746 CLK_LIST(cci_m_clk),
4747};
4748
4749static struct clk_lookup msm_clocks_measure_8937[] = {
4750 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4751 CLK_LIST(apss_debug_pri_mux),
4752 CLK_LIST(apc0_m_clk),
4753 CLK_LIST(apc1_m_clk),
4754 CLK_LIST(cci_m_clk),
4755};
4756
4757static int msm_clock_debug_probe(struct platform_device *pdev)
4758{
4759 int ret;
4760 struct resource *res;
4761 bool compat_bin = false, compat_bin2 = false;
4762 bool compat_bin3 = false;
4763 bool compat_bin4 = false;
4764
4765 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4766 "qcom,cc-debug-8937");
4767
4768 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4769 "qcom,cc-debug-8917");
4770
4771 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4772 "qcom,cc-debug-8940");
4773
4774 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4775 "qcom,cc-debug-8920");
4776
4777 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4778 if (!res) {
4779 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4780 return -EINVAL;
4781 }
4782
4783 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4784 if (!meas_base) {
4785 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4786 return -ENOMEM;
4787 }
4788
4789 clk_ops_debug_mux = clk_ops_gen_mux;
4790 clk_ops_debug_mux.get_rate = measure_get_rate;
4791
4792 if (compat_bin2)
4793 gcc_debug_mux_8937.post_div = 0x3;
4794
4795 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4796 ret = of_msm_clock_register(pdev->dev.of_node,
4797 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4798 else
4799 ret = of_msm_clock_register(pdev->dev.of_node,
4800 msm_clocks_measure_8937,
4801 ARRAY_SIZE(msm_clocks_measure_8937));
4802 if (ret) {
4803 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4804 return ret;
4805 }
4806
4807 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4808 return ret;
4809}
4810
4811static const struct of_device_id msm_clock_debug_match_table[] = {
4812 { .compatible = "qcom,cc-debug-8952" },
4813 { .compatible = "qcom,cc-debug-8937" },
4814 { .compatible = "qcom,cc-debug-8917" },
4815 { .compatible = "qcom,cc-debug-8940" },
4816 { .compatible = "qcom,cc-debug-8920" },
4817 {}
4818};
4819
4820static struct platform_driver msm_clock_debug_driver = {
4821 .probe = msm_clock_debug_probe,
4822 .driver = {
4823 .name = "qcom,cc-debug-8952",
4824 .of_match_table = msm_clock_debug_match_table,
4825 .owner = THIS_MODULE,
4826 },
4827};
4828
4829static int __init msm_clock_debug_init(void)
4830{
4831 return platform_driver_register(&msm_clock_debug_driver);
4832}
4833
4834/* MDSS DSI_PHY_PLL */
4835static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4836 CLK_LIST(ext_pclk0_clk_src),
4837 CLK_LIST(ext_byte0_clk_src),
4838 CLK_LIST(byte0_clk_src),
4839 CLK_LIST(pclk0_clk_src),
4840 CLK_LIST(gcc_mdss_pclk0_clk),
4841 CLK_LIST(gcc_mdss_byte0_clk),
4842 CLK_LIST(mdss_mdp_vote_clk),
4843 CLK_LIST(mdss_rotator_vote_clk),
4844};
4845
4846static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4847 CLK_LIST(ext_pclk1_clk_src),
4848 CLK_LIST(ext_byte1_clk_src),
4849 CLK_LIST(byte1_clk_src),
4850 CLK_LIST(pclk1_clk_src),
4851 CLK_LIST(gcc_mdss_pclk1_clk),
4852 CLK_LIST(gcc_mdss_byte1_clk),
4853};
4854
4855static int msm_gcc_mdss_probe(struct platform_device *pdev)
4856{
4857 int ret = 0;
4858 struct clk *curr_p;
4859 bool compat_bin = false;
4860
4861 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4862 "qcom,gcc-mdss-8937");
4863 if (!compat_bin)
4864 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4865 "qcom,gcc-mdss-8940");
4866
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4867 if (!compat_bin)
4868 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4869 "qcom,gcc-mdss-sdm439");
4870
4871 if (!compat_bin)
4872 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4873 "qcom,gcc-mdss-sdm429");
4874
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4875 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4876 "pclk0_src");
4877 if (IS_ERR(curr_p)) {
4878 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4879 return PTR_ERR(curr_p);
4880 }
4881
4882 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4883 "byte0_src");
4884 if (IS_ERR(curr_p)) {
4885 dev_err(&pdev->dev, "Failed to get byte source.\n");
4886 ret = PTR_ERR(curr_p);
4887 goto byte0_fail;
4888 }
4889
4890 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4891 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4892
4893 if (compat_bin) {
4894 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4895 "pclk1_src");
4896 if (IS_ERR(curr_p)) {
4897 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4898 ret = PTR_ERR(curr_p);
4899 goto fail;
4900 }
4901
4902 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4903 "byte1_src");
4904 if (IS_ERR(curr_p)) {
4905 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4906 ret = PTR_ERR(curr_p);
4907 goto byte1_fail;
4908 }
4909
4910 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4911 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4912 }
4913
4914 ret = of_msm_clock_register(pdev->dev.of_node,
4915 msm_clocks_gcc_mdss_common,
4916 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4917 if (ret)
4918 goto fail;
4919
4920 if (compat_bin) {
4921 ret = of_msm_clock_register(pdev->dev.of_node,
4922 msm_clocks_gcc_mdss_8937,
4923 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4924 if (ret)
4925 goto fail_8937;
4926 }
4927
4928 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4929
4930 return ret;
4931fail_8937:
4932 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4933byte1_fail:
4934 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4935fail:
4936 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4937byte0_fail:
4938 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4939 return ret;
4940
4941}
4942
4943static const struct of_device_id msm_clock_mdss_match_table[] = {
4944 { .compatible = "qcom,gcc-mdss-8952" },
4945 { .compatible = "qcom,gcc-mdss-8937" },
4946 { .compatible = "qcom,gcc-mdss-8917" },
4947 { .compatible = "qcom,gcc-mdss-8940" },
4948 { .compatible = "qcom,gcc-mdss-8920" },
Padmanabhan Komanduru1853d7f2018-04-09 21:50:30 +0530[diff] [blame]4949 { .compatible = "qcom,gcc-mdss-sdm439" },
4950 { .compatible = "qcom,gcc-mdss-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4951 {}
4952};
4953
4954static struct platform_driver msm_clock_gcc_mdss_driver = {
4955 .probe = msm_gcc_mdss_probe,
4956 .driver = {
4957 .name = "gcc-mdss-8952",
4958 .of_match_table = msm_clock_mdss_match_table,
4959 .owner = THIS_MODULE,
4960 },
4961};
4962
4963static int __init msm_gcc_mdss_init(void)
4964{
4965 return platform_driver_register(&msm_clock_gcc_mdss_driver);
4966}
4967arch_initcall(msm_gcc_init);
4968fs_initcall_sync(msm_gcc_mdss_init);
4969late_initcall(msm_clock_debug_init);