blob: a9c30bcb65b85393d18532c53beab31645fe325d [file] [log] [blame]
Zhu Yib481de92007-09-25 17:54:57 -07001/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
Zhu Yib481de92007-09-25 17:54:57 -070038#include <linux/etherdevice.h>
Zhu Yi12342c42007-12-20 11:27:32 +080039#include <asm/unaligned.h>
Zhu Yib481de92007-09-25 17:54:57 -070040
Zhu Yib481de92007-09-25 17:54:57 -070041#include "iwl-4965.h"
42#include "iwl-helpers.h"
43
Christoph Hellwigbb8c0932008-01-27 16:41:47 -080044static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv);
Christoph Hellwig416e1432007-10-25 17:15:49 +080045
Zhu Yib481de92007-09-25 17:54:57 -070046#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_SISO_##s##M_PLCP, \
49 IWL_RATE_MIMO_##s##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
56 IWL_RATE_##np##M_INDEX }
57
58/*
59 * Parameter order:
60 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -080066const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
Zhu Yib481de92007-09-25 17:54:57 -070067 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
71 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
79 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
80};
81
Ron Rindjunskyfe01b472008-01-28 14:07:24 +020082#ifdef CONFIG_IWL4965_HT
83
84static const u16 default_tid_to_tx_fifo[] = {
85 IWL_TX_FIFO_AC1,
86 IWL_TX_FIFO_AC0,
87 IWL_TX_FIFO_AC0,
88 IWL_TX_FIFO_AC1,
89 IWL_TX_FIFO_AC2,
90 IWL_TX_FIFO_AC2,
91 IWL_TX_FIFO_AC3,
92 IWL_TX_FIFO_AC3,
93 IWL_TX_FIFO_NONE,
94 IWL_TX_FIFO_NONE,
95 IWL_TX_FIFO_NONE,
96 IWL_TX_FIFO_NONE,
97 IWL_TX_FIFO_NONE,
98 IWL_TX_FIFO_NONE,
99 IWL_TX_FIFO_NONE,
100 IWL_TX_FIFO_NONE,
101 IWL_TX_FIFO_AC3
102};
103
104#endif /*CONFIG_IWL4965_HT */
105
Zhu Yib481de92007-09-25 17:54:57 -0700106static int is_fat_channel(__le32 rxon_flags)
107{
108 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
109 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
110}
111
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800112static u8 is_single_stream(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700113{
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800114#ifdef CONFIG_IWL4965_HT
Ron Rindjunskyfd105e72007-11-26 16:14:39 +0200115 if (!priv->current_ht_config.is_ht ||
116 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
Zhu Yib481de92007-09-25 17:54:57 -0700117 (priv->ps_mode == IWL_MIMO_PS_STATIC))
118 return 1;
119#else
120 return 1;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800121#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -0700122 return 0;
123}
124
125/*
126 * Determine how many receiver/antenna chains to use.
127 * More provides better reception via diversity. Fewer saves power.
128 * MIMO (dual stream) requires at least 2, but works better with 3.
129 * This does not determine *which* chains to use, just how many.
130 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800131static int iwl4965_get_rx_chain_counter(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -0700132 u8 *idle_state, u8 *rx_state)
133{
134 u8 is_single = is_single_stream(priv);
135 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
136
137 /* # of Rx chains to use when expecting MIMO. */
138 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
139 *rx_state = 2;
140 else
141 *rx_state = 3;
142
143 /* # Rx chains when idling and maybe trying to save power */
144 switch (priv->ps_mode) {
145 case IWL_MIMO_PS_STATIC:
146 case IWL_MIMO_PS_DYNAMIC:
147 *idle_state = (is_cam) ? 2 : 1;
148 break;
149 case IWL_MIMO_PS_NONE:
150 *idle_state = (is_cam) ? *rx_state : 1;
151 break;
152 default:
153 *idle_state = 1;
154 break;
155 }
156
157 return 0;
158}
159
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800160int iwl4965_hw_rxq_stop(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700161{
162 int rc;
163 unsigned long flags;
164
165 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800166 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700167 if (rc) {
168 spin_unlock_irqrestore(&priv->lock, flags);
169 return rc;
170 }
171
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800172 /* stop Rx DMA */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800173 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
174 rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700175 (1 << 24), 1000);
176 if (rc < 0)
177 IWL_ERROR("Can't stop Rx DMA.\n");
178
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800179 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700180 spin_unlock_irqrestore(&priv->lock, flags);
181
182 return 0;
183}
184
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800185u8 iwl4965_hw_find_station(struct iwl4965_priv *priv, const u8 *addr)
Zhu Yib481de92007-09-25 17:54:57 -0700186{
187 int i;
188 int start = 0;
189 int ret = IWL_INVALID_STATION;
190 unsigned long flags;
Joe Perches0795af52007-10-03 17:59:30 -0700191 DECLARE_MAC_BUF(mac);
Zhu Yib481de92007-09-25 17:54:57 -0700192
193 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
194 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
195 start = IWL_STA_ID;
196
197 if (is_broadcast_ether_addr(addr))
198 return IWL4965_BROADCAST_ID;
199
200 spin_lock_irqsave(&priv->sta_lock, flags);
201 for (i = start; i < priv->hw_setting.max_stations; i++)
202 if ((priv->stations[i].used) &&
203 (!compare_ether_addr
204 (priv->stations[i].sta.sta.addr, addr))) {
205 ret = i;
206 goto out;
207 }
208
John W. Linvillea50e2e32007-09-27 17:00:29 -0400209 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
Joe Perches0795af52007-10-03 17:59:30 -0700210 print_mac(mac, addr), priv->num_stations);
Zhu Yib481de92007-09-25 17:54:57 -0700211
212 out:
213 spin_unlock_irqrestore(&priv->sta_lock, flags);
214 return ret;
215}
216
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800217static int iwl4965_nic_set_pwr_src(struct iwl4965_priv *priv, int pwr_max)
Zhu Yib481de92007-09-25 17:54:57 -0700218{
Tomas Winklerd8609652007-10-25 17:15:35 +0800219 int ret;
Zhu Yib481de92007-09-25 17:54:57 -0700220 unsigned long flags;
221
222 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800223 ret = iwl4965_grab_nic_access(priv);
Tomas Winklerd8609652007-10-25 17:15:35 +0800224 if (ret) {
Zhu Yib481de92007-09-25 17:54:57 -0700225 spin_unlock_irqrestore(&priv->lock, flags);
Tomas Winklerd8609652007-10-25 17:15:35 +0800226 return ret;
Zhu Yib481de92007-09-25 17:54:57 -0700227 }
228
229 if (!pwr_max) {
230 u32 val;
231
Tomas Winklerd8609652007-10-25 17:15:35 +0800232 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
Zhu Yib481de92007-09-25 17:54:57 -0700233 &val);
234
235 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800236 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700237 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
238 ~APMG_PS_CTRL_MSK_PWR_SRC);
239 } else
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800240 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700241 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
242 ~APMG_PS_CTRL_MSK_PWR_SRC);
243
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800244 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700245 spin_unlock_irqrestore(&priv->lock, flags);
246
Tomas Winklerd8609652007-10-25 17:15:35 +0800247 return ret;
Zhu Yib481de92007-09-25 17:54:57 -0700248}
249
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800250static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
Zhu Yib481de92007-09-25 17:54:57 -0700251{
252 int rc;
253 unsigned long flags;
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200254 unsigned int rb_size;
Zhu Yib481de92007-09-25 17:54:57 -0700255
256 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800257 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700258 if (rc) {
259 spin_unlock_irqrestore(&priv->lock, flags);
260 return rc;
261 }
262
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200263 if (iwl4965_param_amsdu_size_8K)
264 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
265 else
266 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
267
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800268 /* Stop Rx DMA */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800269 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
Zhu Yib481de92007-09-25 17:54:57 -0700270
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800271 /* Reset driver's Rx queue write index */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800272 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800273
274 /* Tell device where to find RBD circular buffer in DRAM */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800275 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700276 rxq->dma_addr >> 8);
277
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800278 /* Tell device where in DRAM to update its Rx status */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800279 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700280 (priv->hw_setting.shared_phys +
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800281 offsetof(struct iwl4965_shared, val0)) >> 4);
Zhu Yib481de92007-09-25 17:54:57 -0700282
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800283 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800284 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700285 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
286 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +0200287 rb_size |
Zhu Yib481de92007-09-25 17:54:57 -0700288 /*0x10 << 4 | */
289 (RX_QUEUE_SIZE_LOG <<
290 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
291
292 /*
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800293 * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
Zhu Yib481de92007-09-25 17:54:57 -0700294 */
295
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800296 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700297 spin_unlock_irqrestore(&priv->lock, flags);
298
299 return 0;
300}
301
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800302/* Tell 4965 where to find the "keep warm" buffer */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800303static int iwl4965_kw_init(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700304{
305 unsigned long flags;
306 int rc;
307
308 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800309 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700310 if (rc)
311 goto out;
312
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800313 iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700314 priv->kw.dma_addr >> 4);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800315 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700316out:
317 spin_unlock_irqrestore(&priv->lock, flags);
318 return rc;
319}
320
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800321static int iwl4965_kw_alloc(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700322{
323 struct pci_dev *dev = priv->pci_dev;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800324 struct iwl4965_kw *kw = &priv->kw;
Zhu Yib481de92007-09-25 17:54:57 -0700325
326 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
327 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
328 if (!kw->v_addr)
329 return -ENOMEM;
330
331 return 0;
332}
333
334#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
335 ? # x " " : "")
336
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800337/**
338 * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv.
339 *
340 * Does not set up a command, or touch hardware.
341 */
Johannes Berg8318d782008-01-24 19:38:38 +0100342int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv,
343 enum ieee80211_band band, u16 channel,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800344 const struct iwl4965_eeprom_channel *eeprom_ch,
Zhu Yib481de92007-09-25 17:54:57 -0700345 u8 fat_extension_channel)
346{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800347 struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -0700348
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800349 ch_info = (struct iwl4965_channel_info *)
Johannes Berg8318d782008-01-24 19:38:38 +0100350 iwl4965_get_channel_info(priv, band, channel);
Zhu Yib481de92007-09-25 17:54:57 -0700351
352 if (!is_channel_valid(ch_info))
353 return -1;
354
355 IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
356 " %ddBm): Ad-Hoc %ssupported\n",
357 ch_info->channel,
358 is_channel_a_band(ch_info) ?
359 "5.2" : "2.4",
360 CHECK_AND_PRINT(IBSS),
361 CHECK_AND_PRINT(ACTIVE),
362 CHECK_AND_PRINT(RADAR),
363 CHECK_AND_PRINT(WIDE),
364 CHECK_AND_PRINT(NARROW),
365 CHECK_AND_PRINT(DFS),
366 eeprom_ch->flags,
367 eeprom_ch->max_power_avg,
368 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
369 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
370 "" : "not ");
371
372 ch_info->fat_eeprom = *eeprom_ch;
373 ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
374 ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
375 ch_info->fat_min_power = 0;
376 ch_info->fat_scan_power = eeprom_ch->max_power_avg;
377 ch_info->fat_flags = eeprom_ch->flags;
378 ch_info->fat_extension_channel = fat_extension_channel;
379
380 return 0;
381}
382
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800383/**
384 * iwl4965_kw_free - Free the "keep warm" buffer
385 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800386static void iwl4965_kw_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700387{
388 struct pci_dev *dev = priv->pci_dev;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800389 struct iwl4965_kw *kw = &priv->kw;
Zhu Yib481de92007-09-25 17:54:57 -0700390
391 if (kw->v_addr) {
392 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
393 memset(kw, 0, sizeof(*kw));
394 }
395}
396
397/**
398 * iwl4965_txq_ctx_reset - Reset TX queue context
399 * Destroys all DMA structures and initialise them again
400 *
401 * @param priv
402 * @return error code
403 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800404static int iwl4965_txq_ctx_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700405{
406 int rc = 0;
407 int txq_id, slots_num;
408 unsigned long flags;
409
410 iwl4965_kw_free(priv);
411
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800412 /* Free all tx/cmd queues and keep-warm buffer */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800413 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700414
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800415 /* Alloc keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -0700416 rc = iwl4965_kw_alloc(priv);
417 if (rc) {
418 IWL_ERROR("Keep Warm allocation failed");
419 goto error_kw;
420 }
421
422 spin_lock_irqsave(&priv->lock, flags);
423
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800424 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700425 if (unlikely(rc)) {
426 IWL_ERROR("TX reset failed");
427 spin_unlock_irqrestore(&priv->lock, flags);
428 goto error_reset;
429 }
430
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800431 /* Turn off all Tx DMA channels */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800432 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
433 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700434 spin_unlock_irqrestore(&priv->lock, flags);
435
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800436 /* Tell 4965 where to find the keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -0700437 rc = iwl4965_kw_init(priv);
438 if (rc) {
439 IWL_ERROR("kw_init failed\n");
440 goto error_reset;
441 }
442
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800443 /* Alloc and init all (default 16) Tx queues,
444 * including the command queue (#4) */
Zhu Yib481de92007-09-25 17:54:57 -0700445 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
446 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
447 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800448 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
Zhu Yib481de92007-09-25 17:54:57 -0700449 txq_id);
450 if (rc) {
451 IWL_ERROR("Tx %d queue init failed\n", txq_id);
452 goto error;
453 }
454 }
455
456 return rc;
457
458 error:
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800459 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700460 error_reset:
461 iwl4965_kw_free(priv);
462 error_kw:
463 return rc;
464}
465
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800466int iwl4965_hw_nic_init(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700467{
468 int rc;
469 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800470 struct iwl4965_rx_queue *rxq = &priv->rxq;
Zhu Yib481de92007-09-25 17:54:57 -0700471 u8 rev_id;
472 u32 val;
473 u8 val_link;
474
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800475 iwl4965_power_init_handle(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700476
477 /* nic_init */
478 spin_lock_irqsave(&priv->lock, flags);
479
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800480 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
Zhu Yib481de92007-09-25 17:54:57 -0700481 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
482
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800483 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
484 rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
Zhu Yib481de92007-09-25 17:54:57 -0700485 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
486 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
487 if (rc < 0) {
488 spin_unlock_irqrestore(&priv->lock, flags);
489 IWL_DEBUG_INFO("Failed to init the card\n");
490 return rc;
491 }
492
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800493 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700494 if (rc) {
495 spin_unlock_irqrestore(&priv->lock, flags);
496 return rc;
497 }
498
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800499 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
Zhu Yib481de92007-09-25 17:54:57 -0700500
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800501 iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700502 APMG_CLK_VAL_DMA_CLK_RQT |
503 APMG_CLK_VAL_BSM_CLK_RQT);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800504 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
Zhu Yib481de92007-09-25 17:54:57 -0700505
506 udelay(20);
507
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800508 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700509 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
510
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800511 iwl4965_release_nic_access(priv);
512 iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
Zhu Yib481de92007-09-25 17:54:57 -0700513 spin_unlock_irqrestore(&priv->lock, flags);
514
515 /* Determine HW type */
516 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
517 if (rc)
518 return rc;
519
520 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
521
522 iwl4965_nic_set_pwr_src(priv, 1);
523 spin_lock_irqsave(&priv->lock, flags);
524
525 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
526 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
527 /* Enable No Snoop field */
528 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
529 val & ~(1 << 11));
530 }
531
532 spin_unlock_irqrestore(&priv->lock, flags);
533
Zhu Yib481de92007-09-25 17:54:57 -0700534 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
535 IWL_ERROR("Older EEPROM detected! Aborting.\n");
536 return -EINVAL;
537 }
538
539 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
540
541 /* disable L1 entry -- workaround for pre-B1 */
542 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
543
544 spin_lock_irqsave(&priv->lock, flags);
545
546 /* set CSR_HW_CONFIG_REG for uCode use */
547
Tomas Winkler9f6adf22008-02-19 14:05:33 -0800548 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
549 CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R |
550 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
551 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
Zhu Yib481de92007-09-25 17:54:57 -0700552
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800553 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700554 if (rc < 0) {
555 spin_unlock_irqrestore(&priv->lock, flags);
556 IWL_DEBUG_INFO("Failed to init the card\n");
557 return rc;
558 }
559
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800560 iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
561 iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700562 APMG_PS_CTRL_VAL_RESET_REQ);
563 udelay(5);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800564 iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700565 APMG_PS_CTRL_VAL_RESET_REQ);
566
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800567 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700568 spin_unlock_irqrestore(&priv->lock, flags);
569
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800570 iwl4965_hw_card_show_info(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700571
572 /* end nic_init */
573
574 /* Allocate the RX queue, or reset if it is already allocated */
575 if (!rxq->bd) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800576 rc = iwl4965_rx_queue_alloc(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700577 if (rc) {
578 IWL_ERROR("Unable to initialize Rx queue\n");
579 return -ENOMEM;
580 }
581 } else
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800582 iwl4965_rx_queue_reset(priv, rxq);
Zhu Yib481de92007-09-25 17:54:57 -0700583
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800584 iwl4965_rx_replenish(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700585
586 iwl4965_rx_init(priv, rxq);
587
588 spin_lock_irqsave(&priv->lock, flags);
589
590 rxq->need_update = 1;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800591 iwl4965_rx_queue_update_write_ptr(priv, rxq);
Zhu Yib481de92007-09-25 17:54:57 -0700592
593 spin_unlock_irqrestore(&priv->lock, flags);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800594
595 /* Allocate and init all Tx and Command queues */
Zhu Yib481de92007-09-25 17:54:57 -0700596 rc = iwl4965_txq_ctx_reset(priv);
597 if (rc)
598 return rc;
599
600 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
601 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
602
603 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
604 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
605
606 set_bit(STATUS_INIT, &priv->status);
607
608 return 0;
609}
610
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800611int iwl4965_hw_nic_stop_master(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700612{
613 int rc = 0;
614 u32 reg_val;
615 unsigned long flags;
616
617 spin_lock_irqsave(&priv->lock, flags);
618
619 /* set stop master bit */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800620 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
Zhu Yib481de92007-09-25 17:54:57 -0700621
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800622 reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
Zhu Yib481de92007-09-25 17:54:57 -0700623
624 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
625 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
626 IWL_DEBUG_INFO("Card in power save, master is already "
627 "stopped\n");
628 else {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800629 rc = iwl4965_poll_bit(priv, CSR_RESET,
Zhu Yib481de92007-09-25 17:54:57 -0700630 CSR_RESET_REG_FLAG_MASTER_DISABLED,
631 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
632 if (rc < 0) {
633 spin_unlock_irqrestore(&priv->lock, flags);
634 return rc;
635 }
636 }
637
638 spin_unlock_irqrestore(&priv->lock, flags);
639 IWL_DEBUG_INFO("stop master\n");
640
641 return rc;
642}
643
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800644/**
645 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
646 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800647void iwl4965_hw_txq_ctx_stop(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700648{
649
650 int txq_id;
651 unsigned long flags;
652
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800653 /* Stop each Tx DMA channel, and wait for it to be idle */
Zhu Yib481de92007-09-25 17:54:57 -0700654 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
655 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800656 if (iwl4965_grab_nic_access(priv)) {
Zhu Yib481de92007-09-25 17:54:57 -0700657 spin_unlock_irqrestore(&priv->lock, flags);
658 continue;
659 }
660
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800661 iwl4965_write_direct32(priv,
Zhu Yib481de92007-09-25 17:54:57 -0700662 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
663 0x0);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800664 iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700665 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
666 (txq_id), 200);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800667 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700668 spin_unlock_irqrestore(&priv->lock, flags);
669 }
670
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +0800671 /* Deallocate memory for all Tx queues */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800672 iwl4965_hw_txq_ctx_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700673}
674
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800675int iwl4965_hw_nic_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700676{
677 int rc = 0;
678 unsigned long flags;
679
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800680 iwl4965_hw_nic_stop_master(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700681
682 spin_lock_irqsave(&priv->lock, flags);
683
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800684 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
Zhu Yib481de92007-09-25 17:54:57 -0700685
686 udelay(10);
687
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800688 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
689 rc = iwl4965_poll_bit(priv, CSR_RESET,
Zhu Yib481de92007-09-25 17:54:57 -0700690 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
691 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
692
693 udelay(10);
694
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800695 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700696 if (!rc) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800697 iwl4965_write_prph(priv, APMG_CLK_EN_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700698 APMG_CLK_VAL_DMA_CLK_RQT |
699 APMG_CLK_VAL_BSM_CLK_RQT);
700
701 udelay(10);
702
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800703 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
Zhu Yib481de92007-09-25 17:54:57 -0700704 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
705
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800706 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700707 }
708
709 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
710 wake_up_interruptible(&priv->wait_command_queue);
711
712 spin_unlock_irqrestore(&priv->lock, flags);
713
714 return rc;
715
716}
717
718#define REG_RECALIB_PERIOD (60)
719
720/**
721 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
722 *
723 * This callback is provided in order to queue the statistics_work
724 * in work_queue context (v. softirq)
725 *
726 * This timer function is continually reset to execute within
727 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
728 * was received. We need to ensure we receive the statistics in order
729 * to update the temperature used for calibrating the TXPOWER. However,
730 * we can't send the statistics command from softirq context (which
731 * is the context which timers run at) so we have to queue off the
732 * statistics_work to actually send the command to the hardware.
733 */
734static void iwl4965_bg_statistics_periodic(unsigned long data)
735{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800736 struct iwl4965_priv *priv = (struct iwl4965_priv *)data;
Zhu Yib481de92007-09-25 17:54:57 -0700737
738 queue_work(priv->workqueue, &priv->statistics_work);
739}
740
741/**
742 * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
743 *
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800744 * This is queued by iwl4965_bg_statistics_periodic.
Zhu Yib481de92007-09-25 17:54:57 -0700745 */
746static void iwl4965_bg_statistics_work(struct work_struct *work)
747{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800748 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -0700749 statistics_work);
750
751 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
752 return;
753
754 mutex_lock(&priv->mutex);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800755 iwl4965_send_statistics_request(priv);
Zhu Yib481de92007-09-25 17:54:57 -0700756 mutex_unlock(&priv->mutex);
757}
758
759#define CT_LIMIT_CONST 259
760#define TM_CT_KILL_THRESHOLD 110
761
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800762void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -0700763{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800764 struct iwl4965_ct_kill_config cmd;
Zhu Yib481de92007-09-25 17:54:57 -0700765 u32 R1, R2, R3;
766 u32 temp_th;
767 u32 crit_temperature;
768 unsigned long flags;
769 int rc = 0;
770
771 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800772 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
Zhu Yib481de92007-09-25 17:54:57 -0700773 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
774 spin_unlock_irqrestore(&priv->lock, flags);
775
776 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
777 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
778 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
779 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
780 } else {
781 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
782 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
783 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
784 }
785
786 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
787
788 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
789 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800790 rc = iwl4965_send_cmd_pdu(priv,
Zhu Yib481de92007-09-25 17:54:57 -0700791 REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
792 if (rc)
793 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
794 else
795 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
796}
797
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +0800798#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -0700799
800/* "false alarms" are signals that our DSP tries to lock onto,
801 * but then determines that they are either noise, or transmissions
802 * from a distant wireless network (also "noise", really) that get
803 * "stepped on" by stronger transmissions within our own network.
804 * This algorithm attempts to set a sensitivity level that is high
805 * enough to receive all of our own network traffic, but not so
806 * high that our DSP gets too busy trying to lock onto non-network
807 * activity/noise. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800808static int iwl4965_sens_energy_cck(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -0700809 u32 norm_fa,
810 u32 rx_enable_time,
811 struct statistics_general_data *rx_info)
812{
813 u32 max_nrg_cck = 0;
814 int i = 0;
815 u8 max_silence_rssi = 0;
816 u32 silence_ref = 0;
817 u8 silence_rssi_a = 0;
818 u8 silence_rssi_b = 0;
819 u8 silence_rssi_c = 0;
820 u32 val;
821
822 /* "false_alarms" values below are cross-multiplications to assess the
823 * numbers of false alarms within the measured period of actual Rx
824 * (Rx is off when we're txing), vs the min/max expected false alarms
825 * (some should be expected if rx is sensitive enough) in a
826 * hypothetical listening period of 200 time units (TU), 204.8 msec:
827 *
828 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
829 *
830 * */
831 u32 false_alarms = norm_fa * 200 * 1024;
832 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
833 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800834 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -0700835
836 data = &(priv->sensitivity_data);
837
838 data->nrg_auto_corr_silence_diff = 0;
839
840 /* Find max silence rssi among all 3 receivers.
841 * This is background noise, which may include transmissions from other
842 * networks, measured during silence before our network's beacon */
843 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800844 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700845 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800846 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700847 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
Reinette Chatre8a1b0242008-01-14 17:46:25 -0800848 ALL_BAND_FILTER) >> 8);
Zhu Yib481de92007-09-25 17:54:57 -0700849
850 val = max(silence_rssi_b, silence_rssi_c);
851 max_silence_rssi = max(silence_rssi_a, (u8) val);
852
853 /* Store silence rssi in 20-beacon history table */
854 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
855 data->nrg_silence_idx++;
856 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
857 data->nrg_silence_idx = 0;
858
859 /* Find max silence rssi across 20 beacon history */
860 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
861 val = data->nrg_silence_rssi[i];
862 silence_ref = max(silence_ref, val);
863 }
864 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
865 silence_rssi_a, silence_rssi_b, silence_rssi_c,
866 silence_ref);
867
868 /* Find max rx energy (min value!) among all 3 receivers,
869 * measured during beacon frame.
870 * Save it in 10-beacon history table. */
871 i = data->nrg_energy_idx;
872 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
873 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
874
875 data->nrg_energy_idx++;
876 if (data->nrg_energy_idx >= 10)
877 data->nrg_energy_idx = 0;
878
879 /* Find min rx energy (max value) across 10 beacon history.
880 * This is the minimum signal level that we want to receive well.
881 * Add backoff (margin so we don't miss slightly lower energy frames).
882 * This establishes an upper bound (min value) for energy threshold. */
883 max_nrg_cck = data->nrg_value[0];
884 for (i = 1; i < 10; i++)
885 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
886 max_nrg_cck += 6;
887
888 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
889 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
890 rx_info->beacon_energy_c, max_nrg_cck - 6);
891
892 /* Count number of consecutive beacons with fewer-than-desired
893 * false alarms. */
894 if (false_alarms < min_false_alarms)
895 data->num_in_cck_no_fa++;
896 else
897 data->num_in_cck_no_fa = 0;
898 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
899 data->num_in_cck_no_fa);
900
901 /* If we got too many false alarms this time, reduce sensitivity */
902 if (false_alarms > max_false_alarms) {
903 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
904 false_alarms, max_false_alarms);
905 IWL_DEBUG_CALIB("... reducing sensitivity\n");
906 data->nrg_curr_state = IWL_FA_TOO_MANY;
907
908 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
909 /* Store for "fewer than desired" on later beacon */
910 data->nrg_silence_ref = silence_ref;
911
912 /* increase energy threshold (reduce nrg value)
913 * to decrease sensitivity */
914 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
915 data->nrg_th_cck = data->nrg_th_cck
916 - NRG_STEP_CCK;
917 }
918
919 /* increase auto_corr values to decrease sensitivity */
920 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
921 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
922 else {
923 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
924 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
925 }
926 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
927 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
928
929 /* Else if we got fewer than desired, increase sensitivity */
930 } else if (false_alarms < min_false_alarms) {
931 data->nrg_curr_state = IWL_FA_TOO_FEW;
932
933 /* Compare silence level with silence level for most recent
934 * healthy number or too many false alarms */
935 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
936 (s32)silence_ref;
937
938 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
939 false_alarms, min_false_alarms,
940 data->nrg_auto_corr_silence_diff);
941
942 /* Increase value to increase sensitivity, but only if:
943 * 1a) previous beacon did *not* have *too many* false alarms
944 * 1b) AND there's a significant difference in Rx levels
945 * from a previous beacon with too many, or healthy # FAs
946 * OR 2) We've seen a lot of beacons (100) with too few
947 * false alarms */
948 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
949 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
950 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
951
952 IWL_DEBUG_CALIB("... increasing sensitivity\n");
953 /* Increase nrg value to increase sensitivity */
954 val = data->nrg_th_cck + NRG_STEP_CCK;
955 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
956
957 /* Decrease auto_corr values to increase sensitivity */
958 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
959 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
960
961 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
962 data->auto_corr_cck_mrc =
963 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
964
965 } else
966 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
967
968 /* Else we got a healthy number of false alarms, keep status quo */
969 } else {
970 IWL_DEBUG_CALIB(" FA in safe zone\n");
971 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
972
973 /* Store for use in "fewer than desired" with later beacon */
974 data->nrg_silence_ref = silence_ref;
975
976 /* If previous beacon had too many false alarms,
977 * give it some extra margin by reducing sensitivity again
978 * (but don't go below measured energy of desired Rx) */
979 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
980 IWL_DEBUG_CALIB("... increasing margin\n");
981 data->nrg_th_cck -= NRG_MARGIN;
982 }
983 }
984
985 /* Make sure the energy threshold does not go above the measured
986 * energy of the desired Rx signals (reduced by backoff margin),
987 * or else we might start missing Rx frames.
988 * Lower value is higher energy, so we use max()!
989 */
990 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
991 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
992
993 data->nrg_prev_state = data->nrg_curr_state;
994
995 return 0;
996}
997
998
Christoph Hellwigbb8c0932008-01-27 16:41:47 -0800999static int iwl4965_sens_auto_corr_ofdm(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07001000 u32 norm_fa,
1001 u32 rx_enable_time)
1002{
1003 u32 val;
1004 u32 false_alarms = norm_fa * 200 * 1024;
1005 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1006 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001007 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001008
1009 data = &(priv->sensitivity_data);
1010
1011 /* If we got too many false alarms this time, reduce sensitivity */
1012 if (false_alarms > max_false_alarms) {
1013
1014 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1015 false_alarms, max_false_alarms);
1016
1017 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1018 data->auto_corr_ofdm =
1019 min((u32)AUTO_CORR_MAX_OFDM, val);
1020
1021 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1022 data->auto_corr_ofdm_mrc =
1023 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1024
1025 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1026 data->auto_corr_ofdm_x1 =
1027 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1028
1029 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1030 data->auto_corr_ofdm_mrc_x1 =
1031 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1032 }
1033
1034 /* Else if we got fewer than desired, increase sensitivity */
1035 else if (false_alarms < min_false_alarms) {
1036
1037 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1038 false_alarms, min_false_alarms);
1039
1040 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1041 data->auto_corr_ofdm =
1042 max((u32)AUTO_CORR_MIN_OFDM, val);
1043
1044 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1045 data->auto_corr_ofdm_mrc =
1046 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1047
1048 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1049 data->auto_corr_ofdm_x1 =
1050 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1051
1052 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1053 data->auto_corr_ofdm_mrc_x1 =
1054 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1055 }
1056
1057 else
1058 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1059 min_false_alarms, false_alarms, max_false_alarms);
1060
1061 return 0;
1062}
1063
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001064static int iwl4965_sensitivity_callback(struct iwl4965_priv *priv,
1065 struct iwl4965_cmd *cmd, struct sk_buff *skb)
Zhu Yib481de92007-09-25 17:54:57 -07001066{
1067 /* We didn't cache the SKB; let the caller free it */
1068 return 1;
1069}
1070
1071/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001072static int iwl4965_sensitivity_write(struct iwl4965_priv *priv, u8 flags)
Zhu Yib481de92007-09-25 17:54:57 -07001073{
1074 int rc = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001075 struct iwl4965_sensitivity_cmd cmd ;
1076 struct iwl4965_sensitivity_data *data = NULL;
1077 struct iwl4965_host_cmd cmd_out = {
Zhu Yib481de92007-09-25 17:54:57 -07001078 .id = SENSITIVITY_CMD,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001079 .len = sizeof(struct iwl4965_sensitivity_cmd),
Zhu Yib481de92007-09-25 17:54:57 -07001080 .meta.flags = flags,
1081 .data = &cmd,
1082 };
1083
1084 data = &(priv->sensitivity_data);
1085
1086 memset(&cmd, 0, sizeof(cmd));
1087
1088 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1089 cpu_to_le16((u16)data->auto_corr_ofdm);
1090 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1091 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1092 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1093 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1094 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1095 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1096
1097 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1098 cpu_to_le16((u16)data->auto_corr_cck);
1099 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1100 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1101
1102 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1103 cpu_to_le16((u16)data->nrg_th_cck);
1104 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1105 cpu_to_le16((u16)data->nrg_th_ofdm);
1106
1107 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1108 __constant_cpu_to_le16(190);
1109 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1110 __constant_cpu_to_le16(390);
1111 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1112 __constant_cpu_to_le16(62);
1113
1114 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1115 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1116 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1117 data->nrg_th_ofdm);
1118
1119 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1120 data->auto_corr_cck, data->auto_corr_cck_mrc,
1121 data->nrg_th_cck);
1122
Ben Cahillf7d09d72007-11-29 11:09:51 +08001123 /* Update uCode's "work" table, and copy it to DSP */
Zhu Yib481de92007-09-25 17:54:57 -07001124 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1125
1126 if (flags & CMD_ASYNC)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001127 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
Zhu Yib481de92007-09-25 17:54:57 -07001128
1129 /* Don't send command to uCode if nothing has changed */
1130 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1131 sizeof(u16)*HD_TABLE_SIZE)) {
1132 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1133 return 0;
1134 }
1135
1136 /* Copy table for comparison next time */
1137 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1138 sizeof(u16)*HD_TABLE_SIZE);
1139
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001140 rc = iwl4965_send_cmd(priv, &cmd_out);
Zhu Yib481de92007-09-25 17:54:57 -07001141 if (!rc) {
1142 IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
1143 return rc;
1144 }
1145
1146 return 0;
1147}
1148
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001149void iwl4965_init_sensitivity(struct iwl4965_priv *priv, u8 flags, u8 force)
Zhu Yib481de92007-09-25 17:54:57 -07001150{
1151 int rc = 0;
1152 int i;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001153 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001154
1155 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1156
1157 if (force)
1158 memset(&(priv->sensitivity_tbl[0]), 0,
1159 sizeof(u16)*HD_TABLE_SIZE);
1160
1161 /* Clear driver's sensitivity algo data */
1162 data = &(priv->sensitivity_data);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001163 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
Zhu Yib481de92007-09-25 17:54:57 -07001164
1165 data->num_in_cck_no_fa = 0;
1166 data->nrg_curr_state = IWL_FA_TOO_MANY;
1167 data->nrg_prev_state = IWL_FA_TOO_MANY;
1168 data->nrg_silence_ref = 0;
1169 data->nrg_silence_idx = 0;
1170 data->nrg_energy_idx = 0;
1171
1172 for (i = 0; i < 10; i++)
1173 data->nrg_value[i] = 0;
1174
1175 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1176 data->nrg_silence_rssi[i] = 0;
1177
1178 data->auto_corr_ofdm = 90;
1179 data->auto_corr_ofdm_mrc = 170;
1180 data->auto_corr_ofdm_x1 = 105;
1181 data->auto_corr_ofdm_mrc_x1 = 220;
1182 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1183 data->auto_corr_cck_mrc = 200;
1184 data->nrg_th_cck = 100;
1185 data->nrg_th_ofdm = 100;
1186
1187 data->last_bad_plcp_cnt_ofdm = 0;
1188 data->last_fa_cnt_ofdm = 0;
1189 data->last_bad_plcp_cnt_cck = 0;
1190 data->last_fa_cnt_cck = 0;
1191
1192 /* Clear prior Sensitivity command data to force send to uCode */
1193 if (force)
1194 memset(&(priv->sensitivity_tbl[0]), 0,
1195 sizeof(u16)*HD_TABLE_SIZE);
1196
1197 rc |= iwl4965_sensitivity_write(priv, flags);
1198 IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
1199
1200 return;
1201}
1202
1203
1204/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1205 * Called after every association, but this runs only once!
1206 * ... once chain noise is calibrated the first time, it's good forever. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001207void iwl4965_chain_noise_reset(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001208{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001209 struct iwl4965_chain_noise_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001210 int rc = 0;
1211
1212 data = &(priv->chain_noise_data);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001213 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
1214 struct iwl4965_calibration_cmd cmd;
Zhu Yib481de92007-09-25 17:54:57 -07001215
1216 memset(&cmd, 0, sizeof(cmd));
1217 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1218 cmd.diff_gain_a = 0;
1219 cmd.diff_gain_b = 0;
1220 cmd.diff_gain_c = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001221 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
Zhu Yib481de92007-09-25 17:54:57 -07001222 sizeof(cmd), &cmd);
1223 msleep(4);
1224 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1225 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1226 }
1227 return;
1228}
1229
1230/*
1231 * Accumulate 20 beacons of signal and noise statistics for each of
1232 * 3 receivers/antennas/rx-chains, then figure out:
1233 * 1) Which antennas are connected.
1234 * 2) Differential rx gain settings to balance the 3 receivers.
1235 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001236static void iwl4965_noise_calibration(struct iwl4965_priv *priv,
1237 struct iwl4965_notif_statistics *stat_resp)
Zhu Yib481de92007-09-25 17:54:57 -07001238{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001239 struct iwl4965_chain_noise_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001240 int rc = 0;
1241
1242 u32 chain_noise_a;
1243 u32 chain_noise_b;
1244 u32 chain_noise_c;
1245 u32 chain_sig_a;
1246 u32 chain_sig_b;
1247 u32 chain_sig_c;
1248 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1249 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1250 u32 max_average_sig;
1251 u16 max_average_sig_antenna_i;
1252 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1253 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1254 u16 i = 0;
1255 u16 chan_num = INITIALIZATION_VALUE;
1256 u32 band = INITIALIZATION_VALUE;
1257 u32 active_chains = 0;
1258 unsigned long flags;
1259 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1260
1261 data = &(priv->chain_noise_data);
1262
1263 /* Accumulate just the first 20 beacons after the first association,
1264 * then we're done forever. */
1265 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1266 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1267 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1268 return;
1269 }
1270
1271 spin_lock_irqsave(&priv->lock, flags);
1272 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1273 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1274 spin_unlock_irqrestore(&priv->lock, flags);
1275 return;
1276 }
1277
1278 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1279 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1280
1281 /* Make sure we accumulate data for just the associated channel
1282 * (even if scanning). */
1283 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1284 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1285 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1286 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1287 chan_num, band);
1288 spin_unlock_irqrestore(&priv->lock, flags);
1289 return;
1290 }
1291
1292 /* Accumulate beacon statistics values across 20 beacons */
1293 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1294 IN_BAND_FILTER;
1295 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1296 IN_BAND_FILTER;
1297 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1298 IN_BAND_FILTER;
1299
1300 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1301 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1302 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1303
1304 spin_unlock_irqrestore(&priv->lock, flags);
1305
1306 data->beacon_count++;
1307
1308 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1309 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1310 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1311
1312 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1313 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1314 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1315
1316 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1317 data->beacon_count);
1318 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1319 chain_sig_a, chain_sig_b, chain_sig_c);
1320 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1321 chain_noise_a, chain_noise_b, chain_noise_c);
1322
1323 /* If this is the 20th beacon, determine:
1324 * 1) Disconnected antennas (using signal strengths)
1325 * 2) Differential gain (using silence noise) to balance receivers */
1326 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1327
1328 /* Analyze signal for disconnected antenna */
1329 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1330 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1331 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1332
1333 if (average_sig[0] >= average_sig[1]) {
1334 max_average_sig = average_sig[0];
1335 max_average_sig_antenna_i = 0;
1336 active_chains = (1 << max_average_sig_antenna_i);
1337 } else {
1338 max_average_sig = average_sig[1];
1339 max_average_sig_antenna_i = 1;
1340 active_chains = (1 << max_average_sig_antenna_i);
1341 }
1342
1343 if (average_sig[2] >= max_average_sig) {
1344 max_average_sig = average_sig[2];
1345 max_average_sig_antenna_i = 2;
1346 active_chains = (1 << max_average_sig_antenna_i);
1347 }
1348
1349 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1350 average_sig[0], average_sig[1], average_sig[2]);
1351 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1352 max_average_sig, max_average_sig_antenna_i);
1353
1354 /* Compare signal strengths for all 3 receivers. */
1355 for (i = 0; i < NUM_RX_CHAINS; i++) {
1356 if (i != max_average_sig_antenna_i) {
1357 s32 rssi_delta = (max_average_sig -
1358 average_sig[i]);
1359
1360 /* If signal is very weak, compared with
1361 * strongest, mark it as disconnected. */
1362 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1363 data->disconn_array[i] = 1;
1364 else
1365 active_chains |= (1 << i);
1366 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1367 "disconn_array[i] = %d\n",
1368 i, rssi_delta, data->disconn_array[i]);
1369 }
1370 }
1371
1372 /*If both chains A & B are disconnected -
1373 * connect B and leave A as is */
1374 if (data->disconn_array[CHAIN_A] &&
1375 data->disconn_array[CHAIN_B]) {
1376 data->disconn_array[CHAIN_B] = 0;
1377 active_chains |= (1 << CHAIN_B);
1378 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1379 "W/A - declare B as connected\n");
1380 }
1381
1382 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1383 active_chains);
1384
1385 /* Save for use within RXON, TX, SCAN commands, etc. */
1386 priv->valid_antenna = active_chains;
1387
1388 /* Analyze noise for rx balance */
1389 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1390 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1391 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1392
1393 for (i = 0; i < NUM_RX_CHAINS; i++) {
1394 if (!(data->disconn_array[i]) &&
1395 (average_noise[i] <= min_average_noise)) {
1396 /* This means that chain i is active and has
1397 * lower noise values so far: */
1398 min_average_noise = average_noise[i];
1399 min_average_noise_antenna_i = i;
1400 }
1401 }
1402
1403 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1404
1405 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1406 average_noise[0], average_noise[1],
1407 average_noise[2]);
1408
1409 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1410 min_average_noise, min_average_noise_antenna_i);
1411
1412 for (i = 0; i < NUM_RX_CHAINS; i++) {
1413 s32 delta_g = 0;
1414
1415 if (!(data->disconn_array[i]) &&
1416 (data->delta_gain_code[i] ==
1417 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1418 delta_g = average_noise[i] - min_average_noise;
1419 data->delta_gain_code[i] = (u8)((delta_g *
1420 10) / 15);
1421 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1422 data->delta_gain_code[i])
1423 data->delta_gain_code[i] =
1424 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1425
1426 data->delta_gain_code[i] =
1427 (data->delta_gain_code[i] | (1 << 2));
1428 } else
1429 data->delta_gain_code[i] = 0;
1430 }
1431 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1432 data->delta_gain_code[0],
1433 data->delta_gain_code[1],
1434 data->delta_gain_code[2]);
1435
1436 /* Differential gain gets sent to uCode only once */
1437 if (!data->radio_write) {
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001438 struct iwl4965_calibration_cmd cmd;
Zhu Yib481de92007-09-25 17:54:57 -07001439 data->radio_write = 1;
1440
1441 memset(&cmd, 0, sizeof(cmd));
1442 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1443 cmd.diff_gain_a = data->delta_gain_code[0];
1444 cmd.diff_gain_b = data->delta_gain_code[1];
1445 cmd.diff_gain_c = data->delta_gain_code[2];
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001446 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
Zhu Yib481de92007-09-25 17:54:57 -07001447 sizeof(cmd), &cmd);
1448 if (rc)
1449 IWL_DEBUG_CALIB("fail sending cmd "
1450 "REPLY_PHY_CALIBRATION_CMD \n");
1451
1452 /* TODO we might want recalculate
1453 * rx_chain in rxon cmd */
1454
1455 /* Mark so we run this algo only once! */
1456 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1457 }
1458 data->chain_noise_a = 0;
1459 data->chain_noise_b = 0;
1460 data->chain_noise_c = 0;
1461 data->chain_signal_a = 0;
1462 data->chain_signal_b = 0;
1463 data->chain_signal_c = 0;
1464 data->beacon_count = 0;
1465 }
1466 return;
1467}
1468
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001469static void iwl4965_sensitivity_calibration(struct iwl4965_priv *priv,
1470 struct iwl4965_notif_statistics *resp)
Zhu Yib481de92007-09-25 17:54:57 -07001471{
1472 int rc = 0;
1473 u32 rx_enable_time;
1474 u32 fa_cck;
1475 u32 fa_ofdm;
1476 u32 bad_plcp_cck;
1477 u32 bad_plcp_ofdm;
1478 u32 norm_fa_ofdm;
1479 u32 norm_fa_cck;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001480 struct iwl4965_sensitivity_data *data = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001481 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1482 struct statistics_rx *statistics = &(resp->rx);
1483 unsigned long flags;
1484 struct statistics_general_data statis;
1485
1486 data = &(priv->sensitivity_data);
1487
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001488 if (!iwl4965_is_associated(priv)) {
Zhu Yib481de92007-09-25 17:54:57 -07001489 IWL_DEBUG_CALIB("<< - not associated\n");
1490 return;
1491 }
1492
1493 spin_lock_irqsave(&priv->lock, flags);
1494 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1495 IWL_DEBUG_CALIB("<< invalid data.\n");
1496 spin_unlock_irqrestore(&priv->lock, flags);
1497 return;
1498 }
1499
1500 /* Extract Statistics: */
1501 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1502 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1503 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1504 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1505 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1506
1507 statis.beacon_silence_rssi_a =
1508 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1509 statis.beacon_silence_rssi_b =
1510 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1511 statis.beacon_silence_rssi_c =
1512 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1513 statis.beacon_energy_a =
1514 le32_to_cpu(statistics->general.beacon_energy_a);
1515 statis.beacon_energy_b =
1516 le32_to_cpu(statistics->general.beacon_energy_b);
1517 statis.beacon_energy_c =
1518 le32_to_cpu(statistics->general.beacon_energy_c);
1519
1520 spin_unlock_irqrestore(&priv->lock, flags);
1521
1522 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1523
1524 if (!rx_enable_time) {
1525 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1526 return;
1527 }
1528
1529 /* These statistics increase monotonically, and do not reset
1530 * at each beacon. Calculate difference from last value, or just
1531 * use the new statistics value if it has reset or wrapped around. */
1532 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1533 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1534 else {
1535 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1536 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1537 }
1538
1539 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1540 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1541 else {
1542 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1543 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1544 }
1545
1546 if (data->last_fa_cnt_ofdm > fa_ofdm)
1547 data->last_fa_cnt_ofdm = fa_ofdm;
1548 else {
1549 fa_ofdm -= data->last_fa_cnt_ofdm;
1550 data->last_fa_cnt_ofdm += fa_ofdm;
1551 }
1552
1553 if (data->last_fa_cnt_cck > fa_cck)
1554 data->last_fa_cnt_cck = fa_cck;
1555 else {
1556 fa_cck -= data->last_fa_cnt_cck;
1557 data->last_fa_cnt_cck += fa_cck;
1558 }
1559
1560 /* Total aborted signal locks */
1561 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1562 norm_fa_cck = fa_cck + bad_plcp_cck;
1563
1564 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1565 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1566
1567 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1568 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
1569 rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
1570
1571 return;
1572}
1573
1574static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1575{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001576 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -07001577 sensitivity_work);
1578
1579 mutex_lock(&priv->mutex);
1580
1581 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1582 test_bit(STATUS_SCANNING, &priv->status)) {
1583 mutex_unlock(&priv->mutex);
1584 return;
1585 }
1586
1587 if (priv->start_calib) {
1588 iwl4965_noise_calibration(priv, &priv->statistics);
1589
1590 if (priv->sensitivity_data.state ==
1591 IWL_SENS_CALIB_NEED_REINIT) {
1592 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1593 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1594 } else
1595 iwl4965_sensitivity_calibration(priv,
1596 &priv->statistics);
1597 }
1598
1599 mutex_unlock(&priv->mutex);
1600 return;
1601}
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001602#endif /*CONFIG_IWL4965_SENSITIVITY*/
Zhu Yib481de92007-09-25 17:54:57 -07001603
1604static void iwl4965_bg_txpower_work(struct work_struct *work)
1605{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001606 struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
Zhu Yib481de92007-09-25 17:54:57 -07001607 txpower_work);
1608
1609 /* If a scan happened to start before we got here
1610 * then just return; the statistics notification will
1611 * kick off another scheduled work to compensate for
1612 * any temperature delta we missed here. */
1613 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1614 test_bit(STATUS_SCANNING, &priv->status))
1615 return;
1616
1617 mutex_lock(&priv->mutex);
1618
1619 /* Regardless of if we are assocaited, we must reconfigure the
1620 * TX power since frames can be sent on non-radar channels while
1621 * not associated */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001622 iwl4965_hw_reg_send_txpower(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001623
1624 /* Update last_temperature to keep is_calib_needed from running
1625 * when it isn't needed... */
1626 priv->last_temperature = priv->temperature;
1627
1628 mutex_unlock(&priv->mutex);
1629}
1630
1631/*
1632 * Acquire priv->lock before calling this function !
1633 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001634static void iwl4965_set_wr_ptrs(struct iwl4965_priv *priv, int txq_id, u32 index)
Zhu Yib481de92007-09-25 17:54:57 -07001635{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001636 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
Zhu Yib481de92007-09-25 17:54:57 -07001637 (index & 0xff) | (txq_id << 8));
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001638 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
Zhu Yib481de92007-09-25 17:54:57 -07001639}
1640
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001641/**
1642 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1643 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1644 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1645 *
1646 * NOTE: Acquire priv->lock before calling this function !
Zhu Yib481de92007-09-25 17:54:57 -07001647 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001648static void iwl4965_tx_queue_set_status(struct iwl4965_priv *priv,
1649 struct iwl4965_tx_queue *txq,
Zhu Yib481de92007-09-25 17:54:57 -07001650 int tx_fifo_id, int scd_retry)
1651{
1652 int txq_id = txq->q.id;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001653
1654 /* Find out whether to activate Tx queue */
Zhu Yib481de92007-09-25 17:54:57 -07001655 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1656
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001657 /* Set up and activate */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001658 iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
Zhu Yib481de92007-09-25 17:54:57 -07001659 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1660 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1661 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1662 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1663 SCD_QUEUE_STTS_REG_MSK);
1664
1665 txq->sched_retry = scd_retry;
1666
1667 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001668 active ? "Activate" : "Deactivate",
Zhu Yib481de92007-09-25 17:54:57 -07001669 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1670}
1671
1672static const u16 default_queue_to_tx_fifo[] = {
1673 IWL_TX_FIFO_AC3,
1674 IWL_TX_FIFO_AC2,
1675 IWL_TX_FIFO_AC1,
1676 IWL_TX_FIFO_AC0,
1677 IWL_CMD_FIFO_NUM,
1678 IWL_TX_FIFO_HCCA_1,
1679 IWL_TX_FIFO_HCCA_2
1680};
1681
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001682static inline void iwl4965_txq_ctx_activate(struct iwl4965_priv *priv, int txq_id)
Zhu Yib481de92007-09-25 17:54:57 -07001683{
1684 set_bit(txq_id, &priv->txq_ctx_active_msk);
1685}
1686
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001687static inline void iwl4965_txq_ctx_deactivate(struct iwl4965_priv *priv, int txq_id)
Zhu Yib481de92007-09-25 17:54:57 -07001688{
1689 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1690}
1691
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001692int iwl4965_alive_notify(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001693{
1694 u32 a;
1695 int i = 0;
1696 unsigned long flags;
1697 int rc;
1698
1699 spin_lock_irqsave(&priv->lock, flags);
1700
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001701#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07001702 memset(&(priv->sensitivity_data), 0,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001703 sizeof(struct iwl4965_sensitivity_data));
Zhu Yib481de92007-09-25 17:54:57 -07001704 memset(&(priv->chain_noise_data), 0,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001705 sizeof(struct iwl4965_chain_noise_data));
Zhu Yib481de92007-09-25 17:54:57 -07001706 for (i = 0; i < NUM_RX_CHAINS; i++)
1707 priv->chain_noise_data.delta_gain_code[i] =
1708 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08001709#endif /* CONFIG_IWL4965_SENSITIVITY*/
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001710 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001711 if (rc) {
1712 spin_unlock_irqrestore(&priv->lock, flags);
1713 return rc;
1714 }
1715
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001716 /* Clear 4965's internal Tx Scheduler data base */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001717 priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
Zhu Yib481de92007-09-25 17:54:57 -07001718 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1719 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001720 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001721 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001722 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001723 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001724 iwl4965_write_targ_mem(priv, a, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001725
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001726 /* Tel 4965 where to find Tx byte count tables */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001727 iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
Zhu Yib481de92007-09-25 17:54:57 -07001728 (priv->hw_setting.shared_phys +
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001729 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001730
1731 /* Disable chain mode for all queues */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001732 iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
Zhu Yib481de92007-09-25 17:54:57 -07001733
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001734 /* Initialize each Tx queue (including the command queue) */
Zhu Yib481de92007-09-25 17:54:57 -07001735 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001736
1737 /* TFD circular buffer read/write indexes */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001738 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1739 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001740
1741 /* Max Tx Window size for Scheduler-ACK mode */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001742 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07001743 SCD_CONTEXT_QUEUE_OFFSET(i),
1744 (SCD_WIN_SIZE <<
1745 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1746 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001747
1748 /* Frame limit */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001749 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07001750 SCD_CONTEXT_QUEUE_OFFSET(i) +
1751 sizeof(u32),
1752 (SCD_FRAME_LIMIT <<
1753 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1754 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1755
1756 }
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001757 iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
Zhu Yib481de92007-09-25 17:54:57 -07001758 (1 << priv->hw_setting.max_txq_num) - 1);
1759
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001760 /* Activate all Tx DMA/FIFO channels */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001761 iwl4965_write_prph(priv, KDR_SCD_TXFACT,
Zhu Yib481de92007-09-25 17:54:57 -07001762 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1763
1764 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001765
1766 /* Map each Tx/cmd queue to its corresponding fifo */
Zhu Yib481de92007-09-25 17:54:57 -07001767 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1768 int ac = default_queue_to_tx_fifo[i];
1769 iwl4965_txq_ctx_activate(priv, i);
1770 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1771 }
1772
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001773 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07001774 spin_unlock_irqrestore(&priv->lock, flags);
1775
1776 return 0;
1777}
1778
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001779/**
1780 * iwl4965_hw_set_hw_setting
1781 *
1782 * Called when initializing driver
1783 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001784int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001785{
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001786 /* Allocate area for Tx byte count tables and Rx queue status */
Zhu Yib481de92007-09-25 17:54:57 -07001787 priv->hw_setting.shared_virt =
1788 pci_alloc_consistent(priv->pci_dev,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001789 sizeof(struct iwl4965_shared),
Zhu Yib481de92007-09-25 17:54:57 -07001790 &priv->hw_setting.shared_phys);
1791
1792 if (!priv->hw_setting.shared_virt)
1793 return -1;
1794
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001795 memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
Zhu Yib481de92007-09-25 17:54:57 -07001796
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001797 priv->hw_setting.max_txq_num = iwl4965_param_queues_num;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001798 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
Zhu Yib481de92007-09-25 17:54:57 -07001799 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
1800 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02001801 if (iwl4965_param_amsdu_size_8K)
1802 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1803 else
1804 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1805 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
Zhu Yib481de92007-09-25 17:54:57 -07001806 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
1807 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
Tomas Winkler3e82a822008-02-13 11:32:31 -08001808
1809 priv->hw_setting.tx_ant_num = 2;
1810
Zhu Yib481de92007-09-25 17:54:57 -07001811 return 0;
1812}
1813
1814/**
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001815 * iwl4965_hw_txq_ctx_free - Free TXQ Context
Zhu Yib481de92007-09-25 17:54:57 -07001816 *
1817 * Destroy all TX DMA queues and structures
1818 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001819void iwl4965_hw_txq_ctx_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07001820{
1821 int txq_id;
1822
1823 /* Tx queues */
1824 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001825 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
Zhu Yib481de92007-09-25 17:54:57 -07001826
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001827 /* Keep-warm buffer */
Zhu Yib481de92007-09-25 17:54:57 -07001828 iwl4965_kw_free(priv);
1829}
1830
1831/**
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001832 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
Zhu Yib481de92007-09-25 17:54:57 -07001833 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001834 * Does NOT advance any TFD circular buffer read/write indexes
1835 * Does NOT free the TFD itself (which is within circular buffer)
Zhu Yib481de92007-09-25 17:54:57 -07001836 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001837int iwl4965_hw_txq_free_tfd(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
Zhu Yib481de92007-09-25 17:54:57 -07001838{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001839 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1840 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
Zhu Yib481de92007-09-25 17:54:57 -07001841 struct pci_dev *dev = priv->pci_dev;
1842 int i;
1843 int counter = 0;
1844 int index, is_odd;
1845
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001846 /* Host command buffers stay mapped in memory, nothing to clean */
Zhu Yib481de92007-09-25 17:54:57 -07001847 if (txq->q.id == IWL_CMD_QUEUE_NUM)
Zhu Yib481de92007-09-25 17:54:57 -07001848 return 0;
1849
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001850 /* Sanity check on number of chunks */
Zhu Yib481de92007-09-25 17:54:57 -07001851 counter = IWL_GET_BITS(*bd, num_tbs);
1852 if (counter > MAX_NUM_OF_TBS) {
1853 IWL_ERROR("Too many chunks: %i\n", counter);
1854 /* @todo issue fatal error, it is quite serious situation */
1855 return 0;
1856 }
1857
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001858 /* Unmap chunks, if any.
1859 * TFD info for odd chunks is different format than for even chunks. */
Zhu Yib481de92007-09-25 17:54:57 -07001860 for (i = 0; i < counter; i++) {
1861 index = i / 2;
1862 is_odd = i & 0x1;
1863
1864 if (is_odd)
1865 pci_unmap_single(
1866 dev,
1867 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1868 (IWL_GET_BITS(bd->pa[index],
1869 tb2_addr_hi20) << 16),
1870 IWL_GET_BITS(bd->pa[index], tb2_len),
1871 PCI_DMA_TODEVICE);
1872
1873 else if (i > 0)
1874 pci_unmap_single(dev,
1875 le32_to_cpu(bd->pa[index].tb1_addr),
1876 IWL_GET_BITS(bd->pa[index], tb1_len),
1877 PCI_DMA_TODEVICE);
1878
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001879 /* Free SKB, if any, for this chunk */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08001880 if (txq->txb[txq->q.read_ptr].skb[i]) {
1881 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
Zhu Yib481de92007-09-25 17:54:57 -07001882
1883 dev_kfree_skb(skb);
Tomas Winklerfc4b6852007-10-25 17:15:24 +08001884 txq->txb[txq->q.read_ptr].skb[i] = NULL;
Zhu Yib481de92007-09-25 17:54:57 -07001885 }
1886 }
1887 return 0;
1888}
1889
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001890int iwl4965_hw_reg_set_txpower(struct iwl4965_priv *priv, s8 power)
Zhu Yib481de92007-09-25 17:54:57 -07001891{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001892 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
Zhu Yib481de92007-09-25 17:54:57 -07001893 return -EINVAL;
1894}
1895
1896static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1897{
1898 s32 sign = 1;
1899
1900 if (num < 0) {
1901 sign = -sign;
1902 num = -num;
1903 }
1904 if (denom < 0) {
1905 sign = -sign;
1906 denom = -denom;
1907 }
1908 *res = 1;
1909 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1910
1911 return 1;
1912}
1913
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08001914/**
1915 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1916 *
1917 * Determines power supply voltage compensation for txpower calculations.
1918 * Returns number of 1/2-dB steps to subtract from gain table index,
1919 * to compensate for difference between power supply voltage during
1920 * factory measurements, vs. current power supply voltage.
1921 *
1922 * Voltage indication is higher for lower voltage.
1923 * Lower voltage requires more gain (lower gain table index).
1924 */
Zhu Yib481de92007-09-25 17:54:57 -07001925static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1926 s32 current_voltage)
1927{
1928 s32 comp = 0;
1929
1930 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1931 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1932 return 0;
1933
1934 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1935 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1936
1937 if (current_voltage > eeprom_voltage)
1938 comp *= 2;
1939 if ((comp < -2) || (comp > 2))
1940 comp = 0;
1941
1942 return comp;
1943}
1944
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001945static const struct iwl4965_channel_info *
Johannes Berg8318d782008-01-24 19:38:38 +01001946iwl4965_get_channel_txpower_info(struct iwl4965_priv *priv,
1947 enum ieee80211_band band, u16 channel)
Zhu Yib481de92007-09-25 17:54:57 -07001948{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001949 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07001950
Johannes Berg8318d782008-01-24 19:38:38 +01001951 ch_info = iwl4965_get_channel_info(priv, band, channel);
Zhu Yib481de92007-09-25 17:54:57 -07001952
1953 if (!is_channel_valid(ch_info))
1954 return NULL;
1955
1956 return ch_info;
1957}
1958
1959static s32 iwl4965_get_tx_atten_grp(u16 channel)
1960{
1961 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1962 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1963 return CALIB_CH_GROUP_5;
1964
1965 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1966 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1967 return CALIB_CH_GROUP_1;
1968
1969 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1970 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1971 return CALIB_CH_GROUP_2;
1972
1973 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1974 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1975 return CALIB_CH_GROUP_3;
1976
1977 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1978 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1979 return CALIB_CH_GROUP_4;
1980
1981 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1982 return -1;
1983}
1984
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08001985static u32 iwl4965_get_sub_band(const struct iwl4965_priv *priv, u32 channel)
Zhu Yib481de92007-09-25 17:54:57 -07001986{
1987 s32 b = -1;
1988
1989 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1990 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
1991 continue;
1992
1993 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
1994 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
1995 break;
1996 }
1997
1998 return b;
1999}
2000
2001static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2002{
2003 s32 val;
2004
2005 if (x2 == x1)
2006 return y1;
2007 else {
2008 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2009 return val + y2;
2010 }
2011}
2012
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002013/**
2014 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2015 *
2016 * Interpolates factory measurements from the two sample channels within a
2017 * sub-band, to apply to channel of interest. Interpolation is proportional to
2018 * differences in channel frequencies, which is proportional to differences
2019 * in channel number.
2020 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002021static int iwl4965_interpolate_chan(struct iwl4965_priv *priv, u32 channel,
2022 struct iwl4965_eeprom_calib_ch_info *chan_info)
Zhu Yib481de92007-09-25 17:54:57 -07002023{
2024 s32 s = -1;
2025 u32 c;
2026 u32 m;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002027 const struct iwl4965_eeprom_calib_measure *m1;
2028 const struct iwl4965_eeprom_calib_measure *m2;
2029 struct iwl4965_eeprom_calib_measure *omeas;
Zhu Yib481de92007-09-25 17:54:57 -07002030 u32 ch_i1;
2031 u32 ch_i2;
2032
2033 s = iwl4965_get_sub_band(priv, channel);
2034 if (s >= EEPROM_TX_POWER_BANDS) {
2035 IWL_ERROR("Tx Power can not find channel %d ", channel);
2036 return -1;
2037 }
2038
2039 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2040 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2041 chan_info->ch_num = (u8) channel;
2042
2043 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2044 channel, s, ch_i1, ch_i2);
2045
2046 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2047 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2048 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2049 measurements[c][m]);
2050 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2051 measurements[c][m]);
2052 omeas = &(chan_info->measurements[c][m]);
2053
2054 omeas->actual_pow =
2055 (u8) iwl4965_interpolate_value(channel, ch_i1,
2056 m1->actual_pow,
2057 ch_i2,
2058 m2->actual_pow);
2059 omeas->gain_idx =
2060 (u8) iwl4965_interpolate_value(channel, ch_i1,
2061 m1->gain_idx, ch_i2,
2062 m2->gain_idx);
2063 omeas->temperature =
2064 (u8) iwl4965_interpolate_value(channel, ch_i1,
2065 m1->temperature,
2066 ch_i2,
2067 m2->temperature);
2068 omeas->pa_det =
2069 (s8) iwl4965_interpolate_value(channel, ch_i1,
2070 m1->pa_det, ch_i2,
2071 m2->pa_det);
2072
2073 IWL_DEBUG_TXPOWER
2074 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2075 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2076 IWL_DEBUG_TXPOWER
2077 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2078 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2079 IWL_DEBUG_TXPOWER
2080 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2081 m1->pa_det, m2->pa_det, omeas->pa_det);
2082 IWL_DEBUG_TXPOWER
2083 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2084 m1->temperature, m2->temperature,
2085 omeas->temperature);
2086 }
2087 }
2088
2089 return 0;
2090}
2091
2092/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2093 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2094static s32 back_off_table[] = {
2095 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2096 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2097 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2098 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2099 10 /* CCK */
2100};
2101
2102/* Thermal compensation values for txpower for various frequency ranges ...
2103 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002104static struct iwl4965_txpower_comp_entry {
Zhu Yib481de92007-09-25 17:54:57 -07002105 s32 degrees_per_05db_a;
2106 s32 degrees_per_05db_a_denom;
2107} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2108 {9, 2}, /* group 0 5.2, ch 34-43 */
2109 {4, 1}, /* group 1 5.2, ch 44-70 */
2110 {4, 1}, /* group 2 5.2, ch 71-124 */
2111 {4, 1}, /* group 3 5.2, ch 125-200 */
2112 {3, 1} /* group 4 2.4, ch all */
2113};
2114
2115static s32 get_min_power_index(s32 rate_power_index, u32 band)
2116{
2117 if (!band) {
2118 if ((rate_power_index & 7) <= 4)
2119 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2120 }
2121 return MIN_TX_GAIN_INDEX;
2122}
2123
2124struct gain_entry {
2125 u8 dsp;
2126 u8 radio;
2127};
2128
2129static const struct gain_entry gain_table[2][108] = {
2130 /* 5.2GHz power gain index table */
2131 {
2132 {123, 0x3F}, /* highest txpower */
2133 {117, 0x3F},
2134 {110, 0x3F},
2135 {104, 0x3F},
2136 {98, 0x3F},
2137 {110, 0x3E},
2138 {104, 0x3E},
2139 {98, 0x3E},
2140 {110, 0x3D},
2141 {104, 0x3D},
2142 {98, 0x3D},
2143 {110, 0x3C},
2144 {104, 0x3C},
2145 {98, 0x3C},
2146 {110, 0x3B},
2147 {104, 0x3B},
2148 {98, 0x3B},
2149 {110, 0x3A},
2150 {104, 0x3A},
2151 {98, 0x3A},
2152 {110, 0x39},
2153 {104, 0x39},
2154 {98, 0x39},
2155 {110, 0x38},
2156 {104, 0x38},
2157 {98, 0x38},
2158 {110, 0x37},
2159 {104, 0x37},
2160 {98, 0x37},
2161 {110, 0x36},
2162 {104, 0x36},
2163 {98, 0x36},
2164 {110, 0x35},
2165 {104, 0x35},
2166 {98, 0x35},
2167 {110, 0x34},
2168 {104, 0x34},
2169 {98, 0x34},
2170 {110, 0x33},
2171 {104, 0x33},
2172 {98, 0x33},
2173 {110, 0x32},
2174 {104, 0x32},
2175 {98, 0x32},
2176 {110, 0x31},
2177 {104, 0x31},
2178 {98, 0x31},
2179 {110, 0x30},
2180 {104, 0x30},
2181 {98, 0x30},
2182 {110, 0x25},
2183 {104, 0x25},
2184 {98, 0x25},
2185 {110, 0x24},
2186 {104, 0x24},
2187 {98, 0x24},
2188 {110, 0x23},
2189 {104, 0x23},
2190 {98, 0x23},
2191 {110, 0x22},
2192 {104, 0x18},
2193 {98, 0x18},
2194 {110, 0x17},
2195 {104, 0x17},
2196 {98, 0x17},
2197 {110, 0x16},
2198 {104, 0x16},
2199 {98, 0x16},
2200 {110, 0x15},
2201 {104, 0x15},
2202 {98, 0x15},
2203 {110, 0x14},
2204 {104, 0x14},
2205 {98, 0x14},
2206 {110, 0x13},
2207 {104, 0x13},
2208 {98, 0x13},
2209 {110, 0x12},
2210 {104, 0x08},
2211 {98, 0x08},
2212 {110, 0x07},
2213 {104, 0x07},
2214 {98, 0x07},
2215 {110, 0x06},
2216 {104, 0x06},
2217 {98, 0x06},
2218 {110, 0x05},
2219 {104, 0x05},
2220 {98, 0x05},
2221 {110, 0x04},
2222 {104, 0x04},
2223 {98, 0x04},
2224 {110, 0x03},
2225 {104, 0x03},
2226 {98, 0x03},
2227 {110, 0x02},
2228 {104, 0x02},
2229 {98, 0x02},
2230 {110, 0x01},
2231 {104, 0x01},
2232 {98, 0x01},
2233 {110, 0x00},
2234 {104, 0x00},
2235 {98, 0x00},
2236 {93, 0x00},
2237 {88, 0x00},
2238 {83, 0x00},
2239 {78, 0x00},
2240 },
2241 /* 2.4GHz power gain index table */
2242 {
2243 {110, 0x3f}, /* highest txpower */
2244 {104, 0x3f},
2245 {98, 0x3f},
2246 {110, 0x3e},
2247 {104, 0x3e},
2248 {98, 0x3e},
2249 {110, 0x3d},
2250 {104, 0x3d},
2251 {98, 0x3d},
2252 {110, 0x3c},
2253 {104, 0x3c},
2254 {98, 0x3c},
2255 {110, 0x3b},
2256 {104, 0x3b},
2257 {98, 0x3b},
2258 {110, 0x3a},
2259 {104, 0x3a},
2260 {98, 0x3a},
2261 {110, 0x39},
2262 {104, 0x39},
2263 {98, 0x39},
2264 {110, 0x38},
2265 {104, 0x38},
2266 {98, 0x38},
2267 {110, 0x37},
2268 {104, 0x37},
2269 {98, 0x37},
2270 {110, 0x36},
2271 {104, 0x36},
2272 {98, 0x36},
2273 {110, 0x35},
2274 {104, 0x35},
2275 {98, 0x35},
2276 {110, 0x34},
2277 {104, 0x34},
2278 {98, 0x34},
2279 {110, 0x33},
2280 {104, 0x33},
2281 {98, 0x33},
2282 {110, 0x32},
2283 {104, 0x32},
2284 {98, 0x32},
2285 {110, 0x31},
2286 {104, 0x31},
2287 {98, 0x31},
2288 {110, 0x30},
2289 {104, 0x30},
2290 {98, 0x30},
2291 {110, 0x6},
2292 {104, 0x6},
2293 {98, 0x6},
2294 {110, 0x5},
2295 {104, 0x5},
2296 {98, 0x5},
2297 {110, 0x4},
2298 {104, 0x4},
2299 {98, 0x4},
2300 {110, 0x3},
2301 {104, 0x3},
2302 {98, 0x3},
2303 {110, 0x2},
2304 {104, 0x2},
2305 {98, 0x2},
2306 {110, 0x1},
2307 {104, 0x1},
2308 {98, 0x1},
2309 {110, 0x0},
2310 {104, 0x0},
2311 {98, 0x0},
2312 {97, 0},
2313 {96, 0},
2314 {95, 0},
2315 {94, 0},
2316 {93, 0},
2317 {92, 0},
2318 {91, 0},
2319 {90, 0},
2320 {89, 0},
2321 {88, 0},
2322 {87, 0},
2323 {86, 0},
2324 {85, 0},
2325 {84, 0},
2326 {83, 0},
2327 {82, 0},
2328 {81, 0},
2329 {80, 0},
2330 {79, 0},
2331 {78, 0},
2332 {77, 0},
2333 {76, 0},
2334 {75, 0},
2335 {74, 0},
2336 {73, 0},
2337 {72, 0},
2338 {71, 0},
2339 {70, 0},
2340 {69, 0},
2341 {68, 0},
2342 {67, 0},
2343 {66, 0},
2344 {65, 0},
2345 {64, 0},
2346 {63, 0},
2347 {62, 0},
2348 {61, 0},
2349 {60, 0},
2350 {59, 0},
2351 }
2352};
2353
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002354static int iwl4965_fill_txpower_tbl(struct iwl4965_priv *priv, u8 band, u16 channel,
Zhu Yib481de92007-09-25 17:54:57 -07002355 u8 is_fat, u8 ctrl_chan_high,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002356 struct iwl4965_tx_power_db *tx_power_tbl)
Zhu Yib481de92007-09-25 17:54:57 -07002357{
2358 u8 saturation_power;
2359 s32 target_power;
2360 s32 user_target_power;
2361 s32 power_limit;
2362 s32 current_temp;
2363 s32 reg_limit;
2364 s32 current_regulatory;
2365 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2366 int i;
2367 int c;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002368 const struct iwl4965_channel_info *ch_info = NULL;
2369 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2370 const struct iwl4965_eeprom_calib_measure *measurement;
Zhu Yib481de92007-09-25 17:54:57 -07002371 s16 voltage;
2372 s32 init_voltage;
2373 s32 voltage_compensation;
2374 s32 degrees_per_05db_num;
2375 s32 degrees_per_05db_denom;
2376 s32 factory_temp;
2377 s32 temperature_comp[2];
2378 s32 factory_gain_index[2];
2379 s32 factory_actual_pwr[2];
2380 s32 power_index;
2381
2382 /* Sanity check requested level (dBm) */
2383 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2384 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2385 priv->user_txpower_limit);
2386 return -EINVAL;
2387 }
2388 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2389 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2390 priv->user_txpower_limit);
2391 return -EINVAL;
2392 }
2393
2394 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2395 * are used for indexing into txpower table) */
2396 user_target_power = 2 * priv->user_txpower_limit;
2397
2398 /* Get current (RXON) channel, band, width */
2399 ch_info =
Johannes Berg8318d782008-01-24 19:38:38 +01002400 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
Zhu Yib481de92007-09-25 17:54:57 -07002401
2402 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2403 is_fat);
2404
2405 if (!ch_info)
2406 return -EINVAL;
2407
2408 /* get txatten group, used to select 1) thermal txpower adjustment
2409 * and 2) mimo txpower balance between Tx chains. */
2410 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2411 if (txatten_grp < 0)
2412 return -EINVAL;
2413
2414 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2415 channel, txatten_grp);
2416
2417 if (is_fat) {
2418 if (ctrl_chan_high)
2419 channel -= 2;
2420 else
2421 channel += 2;
2422 }
2423
2424 /* hardware txpower limits ...
2425 * saturation (clipping distortion) txpowers are in half-dBm */
2426 if (band)
2427 saturation_power = priv->eeprom.calib_info.saturation_power24;
2428 else
2429 saturation_power = priv->eeprom.calib_info.saturation_power52;
2430
2431 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2432 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2433 if (band)
2434 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2435 else
2436 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2437 }
2438
2439 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2440 * max_power_avg values are in dBm, convert * 2 */
2441 if (is_fat)
2442 reg_limit = ch_info->fat_max_power_avg * 2;
2443 else
2444 reg_limit = ch_info->max_power_avg * 2;
2445
2446 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2447 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2448 if (band)
2449 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2450 else
2451 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2452 }
2453
2454 /* Interpolate txpower calibration values for this channel,
2455 * based on factory calibration tests on spaced channels. */
2456 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2457
2458 /* calculate tx gain adjustment based on power supply voltage */
2459 voltage = priv->eeprom.calib_info.voltage;
2460 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2461 voltage_compensation =
2462 iwl4965_get_voltage_compensation(voltage, init_voltage);
2463
2464 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2465 init_voltage,
2466 voltage, voltage_compensation);
2467
2468 /* get current temperature (Celsius) */
2469 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2470 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2471 current_temp = KELVIN_TO_CELSIUS(current_temp);
2472
2473 /* select thermal txpower adjustment params, based on channel group
2474 * (same frequency group used for mimo txatten adjustment) */
2475 degrees_per_05db_num =
2476 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2477 degrees_per_05db_denom =
2478 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2479
2480 /* get per-chain txpower values from factory measurements */
2481 for (c = 0; c < 2; c++) {
2482 measurement = &ch_eeprom_info.measurements[c][1];
2483
2484 /* txgain adjustment (in half-dB steps) based on difference
2485 * between factory and current temperature */
2486 factory_temp = measurement->temperature;
2487 iwl4965_math_div_round((current_temp - factory_temp) *
2488 degrees_per_05db_denom,
2489 degrees_per_05db_num,
2490 &temperature_comp[c]);
2491
2492 factory_gain_index[c] = measurement->gain_idx;
2493 factory_actual_pwr[c] = measurement->actual_pow;
2494
2495 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2496 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2497 "curr tmp %d, comp %d steps\n",
2498 factory_temp, current_temp,
2499 temperature_comp[c]);
2500
2501 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2502 factory_gain_index[c],
2503 factory_actual_pwr[c]);
2504 }
2505
2506 /* for each of 33 bit-rates (including 1 for CCK) */
2507 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2508 u8 is_mimo_rate;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002509 union iwl4965_tx_power_dual_stream tx_power;
Zhu Yib481de92007-09-25 17:54:57 -07002510
2511 /* for mimo, reduce each chain's txpower by half
2512 * (3dB, 6 steps), so total output power is regulatory
2513 * compliant. */
2514 if (i & 0x8) {
2515 current_regulatory = reg_limit -
2516 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2517 is_mimo_rate = 1;
2518 } else {
2519 current_regulatory = reg_limit;
2520 is_mimo_rate = 0;
2521 }
2522
2523 /* find txpower limit, either hardware or regulatory */
2524 power_limit = saturation_power - back_off_table[i];
2525 if (power_limit > current_regulatory)
2526 power_limit = current_regulatory;
2527
2528 /* reduce user's txpower request if necessary
2529 * for this rate on this channel */
2530 target_power = user_target_power;
2531 if (target_power > power_limit)
2532 target_power = power_limit;
2533
2534 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2535 i, saturation_power - back_off_table[i],
2536 current_regulatory, user_target_power,
2537 target_power);
2538
2539 /* for each of 2 Tx chains (radio transmitters) */
2540 for (c = 0; c < 2; c++) {
2541 s32 atten_value;
2542
2543 if (is_mimo_rate)
2544 atten_value =
2545 (s32)le32_to_cpu(priv->card_alive_init.
2546 tx_atten[txatten_grp][c]);
2547 else
2548 atten_value = 0;
2549
2550 /* calculate index; higher index means lower txpower */
2551 power_index = (u8) (factory_gain_index[c] -
2552 (target_power -
2553 factory_actual_pwr[c]) -
2554 temperature_comp[c] -
2555 voltage_compensation +
2556 atten_value);
2557
2558/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2559 power_index); */
2560
2561 if (power_index < get_min_power_index(i, band))
2562 power_index = get_min_power_index(i, band);
2563
2564 /* adjust 5 GHz index to support negative indexes */
2565 if (!band)
2566 power_index += 9;
2567
2568 /* CCK, rate 32, reduce txpower for CCK */
2569 if (i == POWER_TABLE_CCK_ENTRY)
2570 power_index +=
2571 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2572
2573 /* stay within the table! */
2574 if (power_index > 107) {
2575 IWL_WARNING("txpower index %d > 107\n",
2576 power_index);
2577 power_index = 107;
2578 }
2579 if (power_index < 0) {
2580 IWL_WARNING("txpower index %d < 0\n",
2581 power_index);
2582 power_index = 0;
2583 }
2584
2585 /* fill txpower command for this rate/chain */
2586 tx_power.s.radio_tx_gain[c] =
2587 gain_table[band][power_index].radio;
2588 tx_power.s.dsp_predis_atten[c] =
2589 gain_table[band][power_index].dsp;
2590
2591 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2592 "gain 0x%02x dsp %d\n",
2593 c, atten_value, power_index,
2594 tx_power.s.radio_tx_gain[c],
2595 tx_power.s.dsp_predis_atten[c]);
2596 }/* for each chain */
2597
2598 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2599
2600 }/* for each rate */
2601
2602 return 0;
2603}
2604
2605/**
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002606 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
Zhu Yib481de92007-09-25 17:54:57 -07002607 *
2608 * Uses the active RXON for channel, band, and characteristics (fat, high)
2609 * The power limit is taken from priv->user_txpower_limit.
2610 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002611int iwl4965_hw_reg_send_txpower(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002612{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002613 struct iwl4965_txpowertable_cmd cmd = { 0 };
Zhu Yib481de92007-09-25 17:54:57 -07002614 int rc = 0;
2615 u8 band = 0;
2616 u8 is_fat = 0;
2617 u8 ctrl_chan_high = 0;
2618
2619 if (test_bit(STATUS_SCANNING, &priv->status)) {
2620 /* If this gets hit a lot, switch it to a BUG() and catch
2621 * the stack trace to find out who is calling this during
2622 * a scan. */
2623 IWL_WARNING("TX Power requested while scanning!\n");
2624 return -EAGAIN;
2625 }
2626
Johannes Berg8318d782008-01-24 19:38:38 +01002627 band = priv->band == IEEE80211_BAND_2GHZ;
Zhu Yib481de92007-09-25 17:54:57 -07002628
2629 is_fat = is_fat_channel(priv->active_rxon.flags);
2630
2631 if (is_fat &&
2632 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2633 ctrl_chan_high = 1;
2634
2635 cmd.band = band;
2636 cmd.channel = priv->active_rxon.channel;
2637
2638 rc = iwl4965_fill_txpower_tbl(priv, band,
2639 le16_to_cpu(priv->active_rxon.channel),
2640 is_fat, ctrl_chan_high, &cmd.tx_power);
2641 if (rc)
2642 return rc;
2643
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002644 rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
Zhu Yib481de92007-09-25 17:54:57 -07002645 return rc;
2646}
2647
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002648int iwl4965_hw_channel_switch(struct iwl4965_priv *priv, u16 channel)
Zhu Yib481de92007-09-25 17:54:57 -07002649{
2650 int rc;
2651 u8 band = 0;
2652 u8 is_fat = 0;
2653 u8 ctrl_chan_high = 0;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002654 struct iwl4965_channel_switch_cmd cmd = { 0 };
2655 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07002656
Johannes Berg8318d782008-01-24 19:38:38 +01002657 band = priv->band == IEEE80211_BAND_2GHZ;
Zhu Yib481de92007-09-25 17:54:57 -07002658
Johannes Berg8318d782008-01-24 19:38:38 +01002659 ch_info = iwl4965_get_channel_info(priv, priv->band, channel);
Zhu Yib481de92007-09-25 17:54:57 -07002660
2661 is_fat = is_fat_channel(priv->staging_rxon.flags);
2662
2663 if (is_fat &&
2664 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2665 ctrl_chan_high = 1;
2666
2667 cmd.band = band;
2668 cmd.expect_beacon = 0;
2669 cmd.channel = cpu_to_le16(channel);
2670 cmd.rxon_flags = priv->active_rxon.flags;
2671 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2672 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2673 if (ch_info)
2674 cmd.expect_beacon = is_channel_radar(ch_info);
2675 else
2676 cmd.expect_beacon = 1;
2677
2678 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2679 ctrl_chan_high, &cmd.tx_power);
2680 if (rc) {
2681 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2682 return rc;
2683 }
2684
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002685 rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
Zhu Yib481de92007-09-25 17:54:57 -07002686 return rc;
2687}
2688
2689#define RTS_HCCA_RETRY_LIMIT 3
2690#define RTS_DFAULT_RETRY_LIMIT 60
2691
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002692void iwl4965_hw_build_tx_cmd_rate(struct iwl4965_priv *priv,
2693 struct iwl4965_cmd *cmd,
Zhu Yib481de92007-09-25 17:54:57 -07002694 struct ieee80211_tx_control *ctrl,
2695 struct ieee80211_hdr *hdr, int sta_id,
2696 int is_hcca)
2697{
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002698 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
Zhu Yib481de92007-09-25 17:54:57 -07002699 u8 rts_retry_limit = 0;
2700 u8 data_retry_limit = 0;
Zhu Yib481de92007-09-25 17:54:57 -07002701 u16 fc = le16_to_cpu(hdr->frame_control);
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002702 u8 rate_plcp;
2703 u16 rate_flags = 0;
Johannes Berg8318d782008-01-24 19:38:38 +01002704 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
Zhu Yib481de92007-09-25 17:54:57 -07002705
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002706 rate_plcp = iwl4965_rates[rate_idx].plcp;
Zhu Yib481de92007-09-25 17:54:57 -07002707
2708 rts_retry_limit = (is_hcca) ?
2709 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2710
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002711 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2712 rate_flags |= RATE_MCS_CCK_MSK;
2713
2714
Zhu Yib481de92007-09-25 17:54:57 -07002715 if (ieee80211_is_probe_response(fc)) {
2716 data_retry_limit = 3;
2717 if (data_retry_limit < rts_retry_limit)
2718 rts_retry_limit = data_retry_limit;
2719 } else
2720 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2721
2722 if (priv->data_retry_limit != -1)
2723 data_retry_limit = priv->data_retry_limit;
2724
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002725
2726 if (ieee80211_is_data(fc)) {
2727 tx->initial_rate_index = 0;
2728 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2729 } else {
Zhu Yib481de92007-09-25 17:54:57 -07002730 switch (fc & IEEE80211_FCTL_STYPE) {
2731 case IEEE80211_STYPE_AUTH:
2732 case IEEE80211_STYPE_DEAUTH:
2733 case IEEE80211_STYPE_ASSOC_REQ:
2734 case IEEE80211_STYPE_REASSOC_REQ:
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002735 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2736 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2737 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
Zhu Yib481de92007-09-25 17:54:57 -07002738 }
2739 break;
2740 default:
2741 break;
2742 }
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002743
2744 /* Alternate between antenna A and B for successive frames */
2745 if (priv->use_ant_b_for_management_frame) {
2746 priv->use_ant_b_for_management_frame = 0;
2747 rate_flags |= RATE_MCS_ANT_B_MSK;
2748 } else {
2749 priv->use_ant_b_for_management_frame = 1;
2750 rate_flags |= RATE_MCS_ANT_A_MSK;
2751 }
Zhu Yib481de92007-09-25 17:54:57 -07002752 }
2753
Tomas Winkler87e4f7d2008-01-14 17:46:16 -08002754 tx->rts_retry_limit = rts_retry_limit;
2755 tx->data_retry_limit = data_retry_limit;
2756 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
Zhu Yib481de92007-09-25 17:54:57 -07002757}
2758
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002759int iwl4965_hw_get_rx_read(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002760{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002761 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
Zhu Yib481de92007-09-25 17:54:57 -07002762
2763 return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
2764}
2765
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002766int iwl4965_hw_get_temperature(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002767{
2768 return priv->temperature;
2769}
2770
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002771unsigned int iwl4965_hw_get_beacon_cmd(struct iwl4965_priv *priv,
2772 struct iwl4965_frame *frame, u8 rate)
Zhu Yib481de92007-09-25 17:54:57 -07002773{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002774 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
Zhu Yib481de92007-09-25 17:54:57 -07002775 unsigned int frame_size;
2776
2777 tx_beacon_cmd = &frame->u.beacon;
2778 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2779
2780 tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
2781 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2782
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002783 frame_size = iwl4965_fill_beacon_frame(priv,
Zhu Yib481de92007-09-25 17:54:57 -07002784 tx_beacon_cmd->frame,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002785 iwl4965_broadcast_addr,
Zhu Yib481de92007-09-25 17:54:57 -07002786 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2787
2788 BUG_ON(frame_size > MAX_MPDU_SIZE);
2789 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2790
2791 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2792 tx_beacon_cmd->tx.rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002793 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
Zhu Yib481de92007-09-25 17:54:57 -07002794 else
2795 tx_beacon_cmd->tx.rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002796 iwl4965_hw_set_rate_n_flags(rate, 0);
Zhu Yib481de92007-09-25 17:54:57 -07002797
2798 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2799 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2800 return (sizeof(*tx_beacon_cmd) + frame_size);
2801}
2802
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002803/*
2804 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2805 * given Tx queue, and enable the DMA channel used for that queue.
2806 *
2807 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2808 * channels supported in hardware.
2809 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002810int iwl4965_hw_tx_queue_init(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
Zhu Yib481de92007-09-25 17:54:57 -07002811{
2812 int rc;
2813 unsigned long flags;
2814 int txq_id = txq->q.id;
2815
2816 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002817 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07002818 if (rc) {
2819 spin_unlock_irqrestore(&priv->lock, flags);
2820 return rc;
2821 }
2822
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002823 /* Circular buffer (TFD queue in DRAM) physical base address */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002824 iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
Zhu Yib481de92007-09-25 17:54:57 -07002825 txq->q.dma_addr >> 8);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002826
2827 /* Enable DMA channel, using same id as for TFD queue */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002828 iwl4965_write_direct32(
Zhu Yib481de92007-09-25 17:54:57 -07002829 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2830 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2831 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002832 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07002833 spin_unlock_irqrestore(&priv->lock, flags);
2834
2835 return 0;
2836}
2837
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002838int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl4965_priv *priv, void *ptr,
Zhu Yib481de92007-09-25 17:54:57 -07002839 dma_addr_t addr, u16 len)
2840{
2841 int index, is_odd;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002842 struct iwl4965_tfd_frame *tfd = ptr;
Zhu Yib481de92007-09-25 17:54:57 -07002843 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2844
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002845 /* Each TFD can point to a maximum 20 Tx buffers */
Zhu Yib481de92007-09-25 17:54:57 -07002846 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2847 IWL_ERROR("Error can not send more than %d chunks\n",
2848 MAX_NUM_OF_TBS);
2849 return -EINVAL;
2850 }
2851
2852 index = num_tbs / 2;
2853 is_odd = num_tbs & 0x1;
2854
2855 if (!is_odd) {
2856 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2857 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
Tomas Winkler6a218f62008-01-14 17:46:15 -08002858 iwl_get_dma_hi_address(addr));
Zhu Yib481de92007-09-25 17:54:57 -07002859 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2860 } else {
2861 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2862 (u32) (addr & 0xffff));
2863 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2864 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2865 }
2866
2867 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2868
2869 return 0;
2870}
2871
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002872static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002873{
2874 u16 hw_version = priv->eeprom.board_revision_4965;
2875
2876 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2877 ((hw_version >> 8) & 0x0F),
2878 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2879
2880 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2881 priv->eeprom.board_pba_number_4965);
2882}
2883
2884#define IWL_TX_CRC_SIZE 4
2885#define IWL_TX_DELIMITER_SIZE 4
2886
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002887/**
2888 * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
2889 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002890int iwl4965_tx_queue_update_wr_ptr(struct iwl4965_priv *priv,
2891 struct iwl4965_tx_queue *txq, u16 byte_cnt)
Zhu Yib481de92007-09-25 17:54:57 -07002892{
2893 int len;
2894 int txq_id = txq->q.id;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002895 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
Zhu Yib481de92007-09-25 17:54:57 -07002896
2897 if (txq->need_update == 0)
2898 return 0;
2899
2900 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2901
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002902 /* Set up byte count within first 256 entries */
Zhu Yib481de92007-09-25 17:54:57 -07002903 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002904 tfd_offset[txq->q.write_ptr], byte_cnt, len);
Zhu Yib481de92007-09-25 17:54:57 -07002905
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002906 /* If within first 64 entries, duplicate at end */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002907 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
Zhu Yib481de92007-09-25 17:54:57 -07002908 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
Tomas Winklerfc4b6852007-10-25 17:15:24 +08002909 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
Zhu Yib481de92007-09-25 17:54:57 -07002910 byte_cnt, len);
2911
2912 return 0;
2913}
2914
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002915/**
2916 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2917 *
2918 * Selects how many and which Rx receivers/antennas/chains to use.
2919 * This should not be used for scan command ... it puts data in wrong place.
2920 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002921void iwl4965_set_rxon_chain(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002922{
2923 u8 is_single = is_single_stream(priv);
2924 u8 idle_state, rx_state;
2925
2926 priv->staging_rxon.rx_chain = 0;
2927 rx_state = idle_state = 3;
2928
2929 /* Tell uCode which antennas are actually connected.
2930 * Before first association, we assume all antennas are connected.
2931 * Just after first association, iwl4965_noise_calibration()
2932 * checks which antennas actually *are* connected. */
2933 priv->staging_rxon.rx_chain |=
2934 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2935
2936 /* How many receivers should we use? */
2937 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2938 priv->staging_rxon.rx_chain |=
2939 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2940 priv->staging_rxon.rx_chain |=
2941 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2942
2943 if (!is_single && (rx_state >= 2) &&
2944 !test_bit(STATUS_POWER_PMI, &priv->status))
2945 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2946 else
2947 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2948
2949 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2950}
2951
Zhu Yib481de92007-09-25 17:54:57 -07002952/**
2953 * sign_extend - Sign extend a value using specified bit as sign-bit
2954 *
2955 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2956 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2957 *
2958 * @param oper value to sign extend
2959 * @param index 0 based bit index (0<=index<32) to sign bit
2960 */
2961static s32 sign_extend(u32 oper, int index)
2962{
2963 u8 shift = 31 - index;
2964
2965 return (s32)(oper << shift) >> shift;
2966}
2967
2968/**
2969 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2970 * @statistics: Provides the temperature reading from the uCode
2971 *
2972 * A return of <0 indicates bogus data in the statistics
2973 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08002974int iwl4965_get_temperature(const struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07002975{
2976 s32 temperature;
2977 s32 vt;
2978 s32 R1, R2, R3;
2979 u32 R4;
2980
2981 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2982 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2983 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2984 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2985 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2986 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2987 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2988 } else {
2989 IWL_DEBUG_TEMP("Running temperature calibration\n");
2990 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2991 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2992 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2993 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2994 }
2995
2996 /*
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08002997 * Temperature is only 23 bits, so sign extend out to 32.
Zhu Yib481de92007-09-25 17:54:57 -07002998 *
2999 * NOTE If we haven't received a statistics notification yet
3000 * with an updated temperature, use R4 provided to us in the
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003001 * "initialize" ALIVE response.
3002 */
Zhu Yib481de92007-09-25 17:54:57 -07003003 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3004 vt = sign_extend(R4, 23);
3005 else
3006 vt = sign_extend(
3007 le32_to_cpu(priv->statistics.general.temperature), 23);
3008
3009 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3010 R1, R2, R3, vt);
3011
3012 if (R3 == R1) {
3013 IWL_ERROR("Calibration conflict R1 == R3\n");
3014 return -1;
3015 }
3016
3017 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3018 * Add offset to center the adjustment around 0 degrees Centigrade. */
3019 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3020 temperature /= (R3 - R1);
3021 temperature = (temperature * 97) / 100 +
3022 TEMPERATURE_CALIB_KELVIN_OFFSET;
3023
3024 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3025 KELVIN_TO_CELSIUS(temperature));
3026
3027 return temperature;
3028}
3029
3030/* Adjust Txpower only if temperature variance is greater than threshold. */
3031#define IWL_TEMPERATURE_THRESHOLD 3
3032
3033/**
3034 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3035 *
3036 * If the temperature changed has changed sufficiently, then a recalibration
3037 * is needed.
3038 *
3039 * Assumes caller will replace priv->last_temperature once calibration
3040 * executed.
3041 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003042static int iwl4965_is_temp_calib_needed(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003043{
3044 int temp_diff;
3045
3046 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3047 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3048 return 0;
3049 }
3050
3051 temp_diff = priv->temperature - priv->last_temperature;
3052
3053 /* get absolute value */
3054 if (temp_diff < 0) {
3055 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3056 temp_diff = -temp_diff;
3057 } else if (temp_diff == 0)
3058 IWL_DEBUG_POWER("Same temp, \n");
3059 else
3060 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3061
3062 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3063 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3064 return 0;
3065 }
3066
3067 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3068
3069 return 1;
3070}
3071
3072/* Calculate noise level, based on measurements during network silence just
3073 * before arriving beacon. This measurement can be done only if we know
3074 * exactly when to expect beacons, therefore only when we're associated. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003075static void iwl4965_rx_calc_noise(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07003076{
3077 struct statistics_rx_non_phy *rx_info
3078 = &(priv->statistics.rx.general);
3079 int num_active_rx = 0;
3080 int total_silence = 0;
3081 int bcn_silence_a =
3082 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3083 int bcn_silence_b =
3084 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3085 int bcn_silence_c =
3086 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3087
3088 if (bcn_silence_a) {
3089 total_silence += bcn_silence_a;
3090 num_active_rx++;
3091 }
3092 if (bcn_silence_b) {
3093 total_silence += bcn_silence_b;
3094 num_active_rx++;
3095 }
3096 if (bcn_silence_c) {
3097 total_silence += bcn_silence_c;
3098 num_active_rx++;
3099 }
3100
3101 /* Average among active antennas */
3102 if (num_active_rx)
3103 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3104 else
3105 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3106
3107 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3108 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3109 priv->last_rx_noise);
3110}
3111
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003112void iwl4965_hw_rx_statistics(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003113{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003114 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003115 int change;
3116 s32 temp;
3117
3118 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3119 (int)sizeof(priv->statistics), pkt->len);
3120
3121 change = ((priv->statistics.general.temperature !=
3122 pkt->u.stats.general.temperature) ||
3123 ((priv->statistics.flag &
3124 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3125 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3126
3127 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3128
3129 set_bit(STATUS_STATISTICS, &priv->status);
3130
3131 /* Reschedule the statistics timer to occur in
3132 * REG_RECALIB_PERIOD seconds to ensure we get a
3133 * thermal update even if the uCode doesn't give
3134 * us one */
3135 mod_timer(&priv->statistics_periodic, jiffies +
3136 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3137
3138 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3139 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3140 iwl4965_rx_calc_noise(priv);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003141#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07003142 queue_work(priv->workqueue, &priv->sensitivity_work);
3143#endif
3144 }
3145
3146 /* If the hardware hasn't reported a change in
3147 * temperature then don't bother computing a
3148 * calibrated temperature value */
3149 if (!change)
3150 return;
3151
3152 temp = iwl4965_get_temperature(priv);
3153 if (temp < 0)
3154 return;
3155
3156 if (priv->temperature != temp) {
3157 if (priv->temperature)
3158 IWL_DEBUG_TEMP("Temperature changed "
3159 "from %dC to %dC\n",
3160 KELVIN_TO_CELSIUS(priv->temperature),
3161 KELVIN_TO_CELSIUS(temp));
3162 else
3163 IWL_DEBUG_TEMP("Temperature "
3164 "initialized to %dC\n",
3165 KELVIN_TO_CELSIUS(temp));
3166 }
3167
3168 priv->temperature = temp;
3169 set_bit(STATUS_TEMPERATURE, &priv->status);
3170
3171 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3172 iwl4965_is_temp_calib_needed(priv))
3173 queue_work(priv->workqueue, &priv->txpower_work);
3174}
3175
Zhu Yi12342c42007-12-20 11:27:32 +08003176static void iwl4965_add_radiotap(struct iwl4965_priv *priv,
3177 struct sk_buff *skb,
3178 struct iwl4965_rx_phy_res *rx_start,
3179 struct ieee80211_rx_status *stats,
3180 u32 ampdu_status)
3181{
3182 s8 signal = stats->ssi;
3183 s8 noise = 0;
Johannes Berg8318d782008-01-24 19:38:38 +01003184 int rate = stats->rate_idx;
Zhu Yi12342c42007-12-20 11:27:32 +08003185 u64 tsf = stats->mactime;
3186 __le16 phy_flags_hw = rx_start->phy_flags;
3187 struct iwl4965_rt_rx_hdr {
3188 struct ieee80211_radiotap_header rt_hdr;
3189 __le64 rt_tsf; /* TSF */
3190 u8 rt_flags; /* radiotap packet flags */
3191 u8 rt_rate; /* rate in 500kb/s */
3192 __le16 rt_channelMHz; /* channel in MHz */
3193 __le16 rt_chbitmask; /* channel bitfield */
3194 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3195 s8 rt_dbmnoise;
3196 u8 rt_antenna; /* antenna number */
3197 } __attribute__ ((packed)) *iwl4965_rt;
3198
3199 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3200 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3201 if (net_ratelimit())
3202 printk(KERN_ERR "not enough headroom [%d] for "
Miguel Botón01c20982008-01-04 23:34:35 +01003203 "radiotap head [%zd]\n",
Zhu Yi12342c42007-12-20 11:27:32 +08003204 skb_headroom(skb), sizeof(*iwl4965_rt));
3205 return;
3206 }
3207
3208 /* put radiotap header in front of 802.11 header and data */
3209 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3210
3211 /* initialise radiotap header */
3212 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3213 iwl4965_rt->rt_hdr.it_pad = 0;
3214
3215 /* total header + data */
3216 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3217 &iwl4965_rt->rt_hdr.it_len);
3218
3219 /* Indicate all the fields we add to the radiotap header */
3220 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3221 (1 << IEEE80211_RADIOTAP_FLAGS) |
3222 (1 << IEEE80211_RADIOTAP_RATE) |
3223 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3224 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3225 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3226 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3227 &iwl4965_rt->rt_hdr.it_present);
3228
3229 /* Zero the flags, we'll add to them as we go */
3230 iwl4965_rt->rt_flags = 0;
3231
3232 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3233
3234 iwl4965_rt->rt_dbmsignal = signal;
3235 iwl4965_rt->rt_dbmnoise = noise;
3236
3237 /* Convert the channel frequency and set the flags */
3238 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3239 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3240 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3241 IEEE80211_CHAN_5GHZ),
3242 &iwl4965_rt->rt_chbitmask);
3243 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3244 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3245 IEEE80211_CHAN_2GHZ),
3246 &iwl4965_rt->rt_chbitmask);
3247 else /* 802.11g */
3248 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3249 IEEE80211_CHAN_2GHZ),
3250 &iwl4965_rt->rt_chbitmask);
3251
Zhu Yi12342c42007-12-20 11:27:32 +08003252 if (rate == -1)
3253 iwl4965_rt->rt_rate = 0;
3254 else
3255 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3256
3257 /*
3258 * "antenna number"
3259 *
3260 * It seems that the antenna field in the phy flags value
3261 * is actually a bitfield. This is undefined by radiotap,
3262 * it wants an actual antenna number but I always get "7"
3263 * for most legacy frames I receive indicating that the
3264 * same frame was received on all three RX chains.
3265 *
3266 * I think this field should be removed in favour of a
3267 * new 802.11n radiotap field "RX chains" that is defined
3268 * as a bitmask.
3269 */
3270 iwl4965_rt->rt_antenna =
3271 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
3272
3273 /* set the preamble flag if appropriate */
3274 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3275 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3276
3277 stats->flag |= RX_FLAG_RADIOTAP;
3278}
3279
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003280static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data,
Zhu Yib481de92007-09-25 17:54:57 -07003281 int include_phy,
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003282 struct iwl4965_rx_mem_buffer *rxb,
Zhu Yib481de92007-09-25 17:54:57 -07003283 struct ieee80211_rx_status *stats)
3284{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003285 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003286 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3287 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3288 struct ieee80211_hdr *hdr;
3289 u16 len;
3290 __le32 *rx_end;
3291 unsigned int skblen;
3292 u32 ampdu_status;
3293
3294 if (!include_phy && priv->last_phy_res[0])
3295 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3296
3297 if (!rx_start) {
3298 IWL_ERROR("MPDU frame without a PHY data\n");
3299 return;
3300 }
3301 if (include_phy) {
3302 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3303 rx_start->cfg_phy_cnt);
3304
3305 len = le16_to_cpu(rx_start->byte_count);
3306
3307 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3308 sizeof(struct iwl4965_rx_phy_res) +
3309 rx_start->cfg_phy_cnt + len);
3310
3311 } else {
3312 struct iwl4965_rx_mpdu_res_start *amsdu =
3313 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3314
3315 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3316 sizeof(struct iwl4965_rx_mpdu_res_start));
3317 len = le16_to_cpu(amsdu->byte_count);
3318 rx_start->byte_count = amsdu->byte_count;
3319 rx_end = (__le32 *) (((u8 *) hdr) + len);
3320 }
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02003321 if (len > priv->hw_setting.max_pkt_size || len < 16) {
Zhu Yi12342c42007-12-20 11:27:32 +08003322 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
Zhu Yib481de92007-09-25 17:54:57 -07003323 return;
3324 }
3325
3326 ampdu_status = le32_to_cpu(*rx_end);
3327 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3328
3329 /* start from MAC */
3330 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3331 skb_put(rxb->skb, len); /* end where data ends */
3332
3333 /* We only process data packets if the interface is open */
3334 if (unlikely(!priv->is_open)) {
3335 IWL_DEBUG_DROP_LIMIT
3336 ("Dropping packet while interface is not open.\n");
3337 return;
3338 }
3339
Zhu Yib481de92007-09-25 17:54:57 -07003340 stats->flag = 0;
3341 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3342
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003343 if (iwl4965_param_hwcrypto)
3344 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
Zhu Yib481de92007-09-25 17:54:57 -07003345
Zhu Yi12342c42007-12-20 11:27:32 +08003346 if (priv->add_radiotap)
3347 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3348
Zhu Yib481de92007-09-25 17:54:57 -07003349 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3350 priv->alloc_rxb_skb--;
3351 rxb->skb = NULL;
3352#ifdef LED
3353 priv->led_packets += len;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003354 iwl4965_setup_activity_timer(priv);
Zhu Yib481de92007-09-25 17:54:57 -07003355#endif
3356}
3357
3358/* Calc max signal level (dBm) among 3 possible receivers */
3359static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3360{
3361 /* data from PHY/DSP regarding signal strength, etc.,
3362 * contents are always there, not configurable by host. */
3363 struct iwl4965_rx_non_cfg_phy *ncphy =
3364 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3365 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3366 >> IWL_AGC_DB_POS;
3367
3368 u32 valid_antennae =
3369 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3370 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3371 u8 max_rssi = 0;
3372 u32 i;
3373
3374 /* Find max rssi among 3 possible receivers.
3375 * These values are measured by the digital signal processor (DSP).
3376 * They should stay fairly constant even as the signal strength varies,
3377 * if the radio's automatic gain control (AGC) is working right.
3378 * AGC value (see below) will provide the "interesting" info. */
3379 for (i = 0; i < 3; i++)
3380 if (valid_antennae & (1 << i))
3381 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3382
3383 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3384 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3385 max_rssi, agc);
3386
3387 /* dBm = max_rssi dB - agc dB - constant.
3388 * Higher AGC (higher radio gain) means lower signal. */
3389 return (max_rssi - agc - IWL_RSSI_OFFSET);
3390}
3391
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003392#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003393
3394/* Parsed Information Elements */
3395struct ieee802_11_elems {
3396 u8 *ds_params;
3397 u8 ds_params_len;
3398 u8 *tim;
3399 u8 tim_len;
3400 u8 *ibss_params;
3401 u8 ibss_params_len;
3402 u8 *erp_info;
3403 u8 erp_info_len;
3404 u8 *ht_cap_param;
3405 u8 ht_cap_param_len;
3406 u8 *ht_extra_param;
3407 u8 ht_extra_param_len;
3408};
3409
3410static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
3411{
3412 size_t left = len;
3413 u8 *pos = start;
3414 int unknown = 0;
3415
3416 memset(elems, 0, sizeof(*elems));
3417
3418 while (left >= 2) {
3419 u8 id, elen;
3420
3421 id = *pos++;
3422 elen = *pos++;
3423 left -= 2;
3424
3425 if (elen > left)
3426 return -1;
3427
3428 switch (id) {
3429 case WLAN_EID_DS_PARAMS:
3430 elems->ds_params = pos;
3431 elems->ds_params_len = elen;
3432 break;
3433 case WLAN_EID_TIM:
3434 elems->tim = pos;
3435 elems->tim_len = elen;
3436 break;
3437 case WLAN_EID_IBSS_PARAMS:
3438 elems->ibss_params = pos;
3439 elems->ibss_params_len = elen;
3440 break;
3441 case WLAN_EID_ERP_INFO:
3442 elems->erp_info = pos;
3443 elems->erp_info_len = elen;
3444 break;
3445 case WLAN_EID_HT_CAPABILITY:
3446 elems->ht_cap_param = pos;
3447 elems->ht_cap_param_len = elen;
3448 break;
3449 case WLAN_EID_HT_EXTRA_INFO:
3450 elems->ht_extra_param = pos;
3451 elems->ht_extra_param_len = elen;
3452 break;
3453 default:
3454 unknown++;
3455 break;
3456 }
3457
3458 left -= elen;
3459 pos += elen;
3460 }
3461
3462 return 0;
3463}
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003464
Tomas Winkler78330fd2008-02-06 02:37:18 +02003465void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info,
3466 enum ieee80211_band band)
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003467{
3468 ht_info->cap = 0;
3469 memset(ht_info->supp_mcs_set, 0, 16);
3470
3471 ht_info->ht_supported = 1;
3472
Tomas Winkler78330fd2008-02-06 02:37:18 +02003473 if (band == IEEE80211_BAND_5GHZ) {
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003474 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3475 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3476 ht_info->supp_mcs_set[4] = 0x01;
3477 }
3478 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3479 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3480 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3481 (IWL_MIMO_PS_NONE << 2));
Ron Rindjunsky9ee1ba42007-11-26 16:14:42 +02003482 if (iwl4965_param_amsdu_size_8K) {
3483 printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
3484 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3485 }
Ron Rindjunsky326eeee2007-11-26 16:14:37 +02003486
3487 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3488 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3489
3490 ht_info->supp_mcs_set[0] = 0xFF;
3491 ht_info->supp_mcs_set[1] = 0xFF;
3492}
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003493#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07003494
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003495static void iwl4965_sta_modify_ps_wake(struct iwl4965_priv *priv, int sta_id)
Zhu Yib481de92007-09-25 17:54:57 -07003496{
3497 unsigned long flags;
3498
3499 spin_lock_irqsave(&priv->sta_lock, flags);
3500 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3501 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3502 priv->stations[sta_id].sta.sta.modify_mask = 0;
3503 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3504 spin_unlock_irqrestore(&priv->sta_lock, flags);
3505
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003506 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07003507}
3508
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003509static void iwl4965_update_ps_mode(struct iwl4965_priv *priv, u16 ps_bit, u8 *addr)
Zhu Yib481de92007-09-25 17:54:57 -07003510{
3511 /* FIXME: need locking over ps_status ??? */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003512 u8 sta_id = iwl4965_hw_find_station(priv, addr);
Zhu Yib481de92007-09-25 17:54:57 -07003513
3514 if (sta_id != IWL_INVALID_STATION) {
3515 u8 sta_awake = priv->stations[sta_id].
3516 ps_status == STA_PS_STATUS_WAKE;
3517
3518 if (sta_awake && ps_bit)
3519 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3520 else if (!sta_awake && !ps_bit) {
3521 iwl4965_sta_modify_ps_wake(priv, sta_id);
3522 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3523 }
3524 }
3525}
3526
Mohamed Abbas7878a5a2007-11-29 11:10:13 +08003527#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
3528
Zhu Yib481de92007-09-25 17:54:57 -07003529/* Called for REPLY_4965_RX (legacy ABG frames), or
3530 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003531static void iwl4965_rx_reply_rx(struct iwl4965_priv *priv,
3532 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003533{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003534 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003535 /* Use phy data (Rx signal strength, etc.) contained within
3536 * this rx packet for legacy frames,
3537 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3538 int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
3539 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3540 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3541 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3542 __le32 *rx_end;
3543 unsigned int len = 0;
3544 struct ieee80211_hdr *header;
3545 u16 fc;
3546 struct ieee80211_rx_status stats = {
3547 .mactime = le64_to_cpu(rx_start->timestamp),
Johannes Berg8318d782008-01-24 19:38:38 +01003548 .freq = ieee80211chan2mhz(le16_to_cpu(rx_start->channel)),
3549 .band =
Zhu Yib481de92007-09-25 17:54:57 -07003550 (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
Johannes Berg8318d782008-01-24 19:38:38 +01003551 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ,
Zhu Yib481de92007-09-25 17:54:57 -07003552 .antenna = 0,
Mohamed Abbas2c28b362008-01-31 21:46:41 -08003553 .rate_idx = iwl4965_rate_index_from_plcp(
Johannes Berg8318d782008-01-24 19:38:38 +01003554 le32_to_cpu(rx_start->rate_n_flags)),
Zhu Yib481de92007-09-25 17:54:57 -07003555 .flag = 0,
Zhu Yib481de92007-09-25 17:54:57 -07003556 };
3557 u8 network_packet;
3558
3559 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3560 IWL_DEBUG_DROP
3561 ("dsp size out of range [0,20]: "
3562 "%d/n", rx_start->cfg_phy_cnt);
3563 return;
3564 }
3565 if (!include_phy) {
3566 if (priv->last_phy_res[0])
3567 rx_start = (struct iwl4965_rx_phy_res *)
3568 &priv->last_phy_res[1];
3569 else
3570 rx_start = NULL;
3571 }
3572
3573 if (!rx_start) {
3574 IWL_ERROR("MPDU frame without a PHY data\n");
3575 return;
3576 }
3577
3578 if (include_phy) {
3579 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3580 + rx_start->cfg_phy_cnt);
3581
3582 len = le16_to_cpu(rx_start->byte_count);
3583 rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt +
3584 sizeof(struct iwl4965_rx_phy_res) + len);
3585 } else {
3586 struct iwl4965_rx_mpdu_res_start *amsdu =
3587 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3588
3589 header = (void *)(pkt->u.raw +
3590 sizeof(struct iwl4965_rx_mpdu_res_start));
3591 len = le16_to_cpu(amsdu->byte_count);
3592 rx_end = (__le32 *) (pkt->u.raw +
3593 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3594 }
3595
3596 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3597 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3598 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3599 le32_to_cpu(*rx_end));
3600 return;
3601 }
3602
3603 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3604
Zhu Yib481de92007-09-25 17:54:57 -07003605 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3606 stats.ssi = iwl4965_calc_rssi(rx_start);
3607
3608 /* Meaningful noise values are available only from beacon statistics,
3609 * which are gathered only when associated, and indicate noise
3610 * only for the associated network channel ...
3611 * Ignore these noise values while scanning (other channels) */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003612 if (iwl4965_is_associated(priv) &&
Zhu Yib481de92007-09-25 17:54:57 -07003613 !test_bit(STATUS_SCANNING, &priv->status)) {
3614 stats.noise = priv->last_rx_noise;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003615 stats.signal = iwl4965_calc_sig_qual(stats.ssi, stats.noise);
Zhu Yib481de92007-09-25 17:54:57 -07003616 } else {
3617 stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003618 stats.signal = iwl4965_calc_sig_qual(stats.ssi, 0);
Zhu Yib481de92007-09-25 17:54:57 -07003619 }
3620
3621 /* Reset beacon noise level if not associated. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003622 if (!iwl4965_is_associated(priv))
Zhu Yib481de92007-09-25 17:54:57 -07003623 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3624
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003625#ifdef CONFIG_IWL4965_DEBUG
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003626 /* TODO: Parts of iwl4965_report_frame are broken for 4965 */
3627 if (iwl4965_debug_level & (IWL_DL_RX))
Zhu Yib481de92007-09-25 17:54:57 -07003628 /* Set "1" to report good data frames in groups of 100 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003629 iwl4965_report_frame(priv, pkt, header, 1);
Zhu Yib481de92007-09-25 17:54:57 -07003630
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003631 if (iwl4965_debug_level & (IWL_DL_RX | IWL_DL_STATS))
Zhu Yib481de92007-09-25 17:54:57 -07003632 IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n",
3633 stats.ssi, stats.noise, stats.signal,
3634 (long unsigned int)le64_to_cpu(rx_start->timestamp));
3635#endif
3636
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003637 network_packet = iwl4965_is_network_packet(priv, header);
Zhu Yib481de92007-09-25 17:54:57 -07003638 if (network_packet) {
3639 priv->last_rx_rssi = stats.ssi;
3640 priv->last_beacon_time = priv->ucode_beacon_time;
3641 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3642 }
3643
3644 fc = le16_to_cpu(header->frame_control);
3645 switch (fc & IEEE80211_FCTL_FTYPE) {
3646 case IEEE80211_FTYPE_MGMT:
3647
3648 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3649 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3650 header->addr2);
3651 switch (fc & IEEE80211_FCTL_STYPE) {
3652 case IEEE80211_STYPE_PROBE_RESP:
3653 case IEEE80211_STYPE_BEACON:
3654 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
3655 !compare_ether_addr(header->addr2, priv->bssid)) ||
3656 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
3657 !compare_ether_addr(header->addr3, priv->bssid))) {
3658 struct ieee80211_mgmt *mgmt =
3659 (struct ieee80211_mgmt *)header;
3660 u64 timestamp =
3661 le64_to_cpu(mgmt->u.beacon.timestamp);
3662
3663 priv->timestamp0 = timestamp & 0xFFFFFFFF;
3664 priv->timestamp1 =
3665 (timestamp >> 32) & 0xFFFFFFFF;
3666 priv->beacon_int = le16_to_cpu(
3667 mgmt->u.beacon.beacon_int);
3668 if (priv->call_post_assoc_from_beacon &&
3669 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
3670 priv->call_post_assoc_from_beacon = 0;
3671 queue_work(priv->workqueue,
3672 &priv->post_associate.work);
3673 }
3674 }
3675 break;
3676
3677 case IEEE80211_STYPE_ACTION:
3678 break;
3679
3680 /*
Johannes Berg471b3ef2007-12-28 14:32:58 +01003681 * TODO: Use the new callback function from
3682 * mac80211 instead of sniffing these packets.
Zhu Yib481de92007-09-25 17:54:57 -07003683 */
3684 case IEEE80211_STYPE_ASSOC_RESP:
3685 case IEEE80211_STYPE_REASSOC_RESP:
mabbas052c4b92007-10-25 17:15:43 +08003686 if (network_packet) {
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003687#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003688 u8 *pos = NULL;
3689 struct ieee802_11_elems elems;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003690#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07003691 struct ieee80211_mgmt *mgnt =
3692 (struct ieee80211_mgmt *)header;
3693
Mohamed Abbas7878a5a2007-11-29 11:10:13 +08003694 /* We have just associated, give some
3695 * time for the 4-way handshake if
3696 * any. Don't start scan too early. */
3697 priv->next_scan_jiffies = jiffies +
3698 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
3699
Zhu Yib481de92007-09-25 17:54:57 -07003700 priv->assoc_id = (~((1 << 15) | (1 << 14))
3701 & le16_to_cpu(mgnt->u.assoc_resp.aid));
3702 priv->assoc_capability =
3703 le16_to_cpu(
3704 mgnt->u.assoc_resp.capab_info);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003705#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003706 pos = mgnt->u.assoc_resp.variable;
3707 if (!parse_elems(pos,
3708 len - (pos - (u8 *) mgnt),
3709 &elems)) {
3710 if (elems.ht_extra_param &&
3711 elems.ht_cap_param)
3712 break;
3713 }
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003714#endif /*CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07003715 /* assoc_id is 0 no association */
3716 if (!priv->assoc_id)
3717 break;
3718 if (priv->beacon_int)
3719 queue_work(priv->workqueue,
3720 &priv->post_associate.work);
3721 else
3722 priv->call_post_assoc_from_beacon = 1;
3723 }
3724
3725 break;
3726
3727 case IEEE80211_STYPE_PROBE_REQ:
3728 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003729 !iwl4965_is_associated(priv)) {
Joe Perches0795af52007-10-03 17:59:30 -07003730 DECLARE_MAC_BUF(mac1);
3731 DECLARE_MAC_BUF(mac2);
3732 DECLARE_MAC_BUF(mac3);
3733
Zhu Yib481de92007-09-25 17:54:57 -07003734 IWL_DEBUG_DROP("Dropping (non network): "
Joe Perches0795af52007-10-03 17:59:30 -07003735 "%s, %s, %s\n",
3736 print_mac(mac1, header->addr1),
3737 print_mac(mac2, header->addr2),
3738 print_mac(mac3, header->addr3));
Zhu Yib481de92007-09-25 17:54:57 -07003739 return;
3740 }
3741 }
3742 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats);
3743 break;
3744
3745 case IEEE80211_FTYPE_CTL:
Ron Rindjunsky9ab46172007-12-25 17:00:38 +02003746#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003747 switch (fc & IEEE80211_FCTL_STYPE) {
3748 case IEEE80211_STYPE_BACK_REQ:
3749 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3750 iwl4965_handle_data_packet(priv, 0, include_phy,
3751 rxb, &stats);
3752 break;
3753 default:
3754 break;
3755 }
3756#endif
Zhu Yib481de92007-09-25 17:54:57 -07003757 break;
3758
Joe Perches0795af52007-10-03 17:59:30 -07003759 case IEEE80211_FTYPE_DATA: {
3760 DECLARE_MAC_BUF(mac1);
3761 DECLARE_MAC_BUF(mac2);
3762 DECLARE_MAC_BUF(mac3);
3763
Zhu Yib481de92007-09-25 17:54:57 -07003764 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3765 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3766 header->addr2);
3767
3768 if (unlikely(!network_packet))
3769 IWL_DEBUG_DROP("Dropping (non network): "
Joe Perches0795af52007-10-03 17:59:30 -07003770 "%s, %s, %s\n",
3771 print_mac(mac1, header->addr1),
3772 print_mac(mac2, header->addr2),
3773 print_mac(mac3, header->addr3));
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003774 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
Joe Perches0795af52007-10-03 17:59:30 -07003775 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3776 print_mac(mac1, header->addr1),
3777 print_mac(mac2, header->addr2),
3778 print_mac(mac3, header->addr3));
Zhu Yib481de92007-09-25 17:54:57 -07003779 else
3780 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3781 &stats);
3782 break;
Joe Perches0795af52007-10-03 17:59:30 -07003783 }
Zhu Yib481de92007-09-25 17:54:57 -07003784 default:
3785 break;
3786
3787 }
3788}
3789
3790/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3791 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003792static void iwl4965_rx_reply_rx_phy(struct iwl4965_priv *priv,
3793 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003794{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003795 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
Zhu Yib481de92007-09-25 17:54:57 -07003796 priv->last_phy_res[0] = 1;
3797 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3798 sizeof(struct iwl4965_rx_phy_res));
3799}
3800
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003801static void iwl4965_rx_missed_beacon_notif(struct iwl4965_priv *priv,
3802 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07003803
3804{
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003805#ifdef CONFIG_IWL4965_SENSITIVITY
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003806 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3807 struct iwl4965_missed_beacon_notif *missed_beacon;
Zhu Yib481de92007-09-25 17:54:57 -07003808
3809 missed_beacon = &pkt->u.missed_beacon;
3810 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3811 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3812 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3813 le32_to_cpu(missed_beacon->total_missed_becons),
3814 le32_to_cpu(missed_beacon->num_recvd_beacons),
3815 le32_to_cpu(missed_beacon->num_expected_beacons));
3816 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
3817 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
3818 queue_work(priv->workqueue, &priv->sensitivity_work);
3819 }
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003820#endif /*CONFIG_IWL4965_SENSITIVITY*/
Zhu Yib481de92007-09-25 17:54:57 -07003821}
3822
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08003823#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07003824
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003825/**
3826 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3827 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003828static void iwl4965_sta_modify_enable_tid_tx(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07003829 int sta_id, int tid)
3830{
3831 unsigned long flags;
3832
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003833 /* Remove "disable" flag, to enable Tx for this TID */
Zhu Yib481de92007-09-25 17:54:57 -07003834 spin_lock_irqsave(&priv->sta_lock, flags);
3835 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3836 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3837 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3838 spin_unlock_irqrestore(&priv->sta_lock, flags);
3839
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003840 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07003841}
3842
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003843/**
3844 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3845 *
3846 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3847 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3848 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003849static int iwl4965_tx_status_reply_compressed_ba(struct iwl4965_priv *priv,
3850 struct iwl4965_ht_agg *agg,
3851 struct iwl4965_compressed_ba_resp*
Zhu Yib481de92007-09-25 17:54:57 -07003852 ba_resp)
3853
3854{
3855 int i, sh, ack;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003856 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3857 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3858 u64 bitmap;
3859 int successes = 0;
3860 struct ieee80211_tx_status *tx_status;
Zhu Yib481de92007-09-25 17:54:57 -07003861
3862 if (unlikely(!agg->wait_for_ba)) {
3863 IWL_ERROR("Received BA when not expected\n");
3864 return -EINVAL;
3865 }
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003866
3867 /* Mark that the expected block-ack response arrived */
Zhu Yib481de92007-09-25 17:54:57 -07003868 agg->wait_for_ba = 0;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003869 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003870
3871 /* Calculate shift to align block-ack bits with our Tx window bits */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003872 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
Ian Schram01ebd062007-10-25 17:15:22 +08003873 if (sh < 0) /* tbw something is wrong with indices */
Zhu Yib481de92007-09-25 17:54:57 -07003874 sh += 0x100;
3875
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003876 /* don't use 64-bit values for now */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003877 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
Zhu Yib481de92007-09-25 17:54:57 -07003878
3879 if (agg->frame_count > (64 - sh)) {
3880 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3881 return -1;
3882 }
3883
3884 /* check for success or failure according to the
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003885 * transmitted bitmap and block-ack bitmap */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003886 bitmap &= agg->bitmap;
Zhu Yib481de92007-09-25 17:54:57 -07003887
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003888 /* For each frame attempted in aggregation,
3889 * update driver's record of tx frame's status. */
Zhu Yib481de92007-09-25 17:54:57 -07003890 for (i = 0; i < agg->frame_count ; i++) {
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003891 ack = bitmap & (1 << i);
3892 successes += !!ack;
Zhu Yib481de92007-09-25 17:54:57 -07003893 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003894 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3895 agg->start_idx + i);
Zhu Yib481de92007-09-25 17:54:57 -07003896 }
3897
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003898 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3899 tx_status->flags = IEEE80211_TX_STATUS_ACK;
Ron Rindjunsky99556432008-01-28 14:07:25 +02003900 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3901 tx_status->ampdu_ack_map = successes;
3902 tx_status->ampdu_ack_len = agg->frame_count;
Tomas Winkler78330fd2008-02-06 02:37:18 +02003903 /* FIXME Wrong rate
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003904 tx_status->control.tx_rate = agg->rate_n_flags;
Tomas Winkler78330fd2008-02-06 02:37:18 +02003905 */
Zhu Yib481de92007-09-25 17:54:57 -07003906
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02003907 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", bitmap);
3908
3909 return 0;
3910}
3911
3912/**
3913 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3914 */
3915static void iwl4965_tx_queue_stop_scheduler(struct iwl4965_priv *priv,
3916 u16 txq_id)
3917{
3918 /* Simply stop the queue, but don't change any configuration;
3919 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3920 iwl4965_write_prph(priv,
3921 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
3922 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3923 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3924}
3925
3926/**
3927 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3928 */
3929static int iwl4965_tx_queue_agg_disable(struct iwl4965_priv *priv, u16 txq_id,
3930 u16 ssn_idx, u8 tx_fifo)
3931{
3932 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3933 IWL_WARNING("queue number too small: %d, must be > %d\n",
3934 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3935 return -EINVAL;
3936 }
3937
3938 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3939
3940 iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3941
3942 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3943 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3944 /* supposes that ssn_idx is valid (!= 0xFFF) */
3945 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3946
3947 iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
3948 iwl4965_txq_ctx_deactivate(priv, txq_id);
3949 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3950
3951 return 0;
3952}
3953
3954int iwl4965_check_empty_hw_queue(struct iwl4965_priv *priv, int sta_id,
3955 u8 tid, int txq_id)
3956{
3957 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3958 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3959 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3960
3961 switch (priv->stations[sta_id].tid[tid].agg.state) {
3962 case IWL_EMPTYING_HW_QUEUE_DELBA:
3963 /* We are reclaiming the last packet of the */
3964 /* aggregated HW queue */
3965 if (txq_id == tid_data->agg.txq_id &&
3966 q->read_ptr == q->write_ptr) {
3967 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3968 int tx_fifo = default_tid_to_tx_fifo[tid];
3969 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3970 iwl4965_tx_queue_agg_disable(priv, txq_id,
3971 ssn, tx_fifo);
3972 tid_data->agg.state = IWL_AGG_OFF;
3973 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3974 }
3975 break;
3976 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3977 /* We are reclaiming the last packet of the queue */
3978 if (tid_data->tfds_in_queue == 0) {
3979 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3980 tid_data->agg.state = IWL_AGG_ON;
3981 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3982 }
3983 break;
3984 }
Zhu Yib481de92007-09-25 17:54:57 -07003985 return 0;
3986}
3987
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003988/**
3989 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3990 * @index -- current index
3991 * @n_bd -- total number of entries in queue (s/b power of 2)
3992 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08003993static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
Zhu Yib481de92007-09-25 17:54:57 -07003994{
3995 return (index == 0) ? n_bd - 1 : index - 1;
3996}
3997
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08003998/**
3999 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4000 *
4001 * Handles block-acknowledge notification from device, which reports success
4002 * of frames sent via aggregation.
4003 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004004static void iwl4965_rx_reply_compressed_ba(struct iwl4965_priv *priv,
4005 struct iwl4965_rx_mem_buffer *rxb)
Zhu Yib481de92007-09-25 17:54:57 -07004006{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004007 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4008 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
Zhu Yib481de92007-09-25 17:54:57 -07004009 int index;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004010 struct iwl4965_tx_queue *txq = NULL;
4011 struct iwl4965_ht_agg *agg;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004012 DECLARE_MAC_BUF(mac);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004013
4014 /* "flow" corresponds to Tx queue */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004015 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004016
4017 /* "ssn" is start of block-ack Tx window, corresponds to index
4018 * (in Tx queue's circular buffer) of first TFD/frame in window */
Zhu Yib481de92007-09-25 17:54:57 -07004019 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4020
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004021 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
Zhu Yib481de92007-09-25 17:54:57 -07004022 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4023 return;
4024 }
4025
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004026 txq = &priv->txq[scd_flow];
Zhu Yib481de92007-09-25 17:54:57 -07004027 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004028
4029 /* Find index just before block-ack window */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004030 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
Zhu Yib481de92007-09-25 17:54:57 -07004031
Ian Schram01ebd062007-10-25 17:15:22 +08004032 /* TODO: Need to get this copy more safely - now good for debug */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004033
Joe Perches0795af52007-10-03 17:59:30 -07004034 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4035 "sta_id = %d\n",
Zhu Yib481de92007-09-25 17:54:57 -07004036 agg->wait_for_ba,
Joe Perches0795af52007-10-03 17:59:30 -07004037 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
Zhu Yib481de92007-09-25 17:54:57 -07004038 ba_resp->sta_id);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004039 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
Zhu Yib481de92007-09-25 17:54:57 -07004040 "%d, scd_ssn = %d\n",
4041 ba_resp->tid,
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004042 ba_resp->seq_ctl,
4043 ba_resp->bitmap,
Zhu Yib481de92007-09-25 17:54:57 -07004044 ba_resp->scd_flow,
4045 ba_resp->scd_ssn);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004046 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
Zhu Yib481de92007-09-25 17:54:57 -07004047 agg->start_idx,
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004048 agg->bitmap);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004049
4050 /* Update driver's record of ACK vs. not for each frame in window */
Zhu Yib481de92007-09-25 17:54:57 -07004051 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004052
4053 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4054 * block-ack window (we assume that they've been successfully
4055 * transmitted ... if not, it's too late anyway). */
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004056 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4057 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4058 priv->stations[ba_resp->sta_id].
4059 tid[ba_resp->tid].tfds_in_queue -= freed;
4060 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4061 priv->mac80211_registered &&
4062 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4063 ieee80211_wake_queue(priv->hw, scd_flow);
4064 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4065 ba_resp->tid, scd_flow);
4066 }
Zhu Yib481de92007-09-25 17:54:57 -07004067}
4068
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004069/**
4070 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4071 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004072static int iwl4965_tx_queue_set_q2ratid(struct iwl4965_priv *priv, u16 ra_tid,
Zhu Yib481de92007-09-25 17:54:57 -07004073 u16 txq_id)
4074{
4075 u32 tbl_dw_addr;
4076 u32 tbl_dw;
4077 u16 scd_q2ratid;
4078
4079 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4080
4081 tbl_dw_addr = priv->scd_base_addr +
4082 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4083
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004084 tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
Zhu Yib481de92007-09-25 17:54:57 -07004085
4086 if (txq_id & 0x1)
4087 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4088 else
4089 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4090
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004091 iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
Zhu Yib481de92007-09-25 17:54:57 -07004092
4093 return 0;
4094}
4095
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004096
Zhu Yib481de92007-09-25 17:54:57 -07004097/**
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004098 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4099 *
4100 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4101 * i.e. it must be one of the higher queues used for aggregation
Zhu Yib481de92007-09-25 17:54:57 -07004102 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004103static int iwl4965_tx_queue_agg_enable(struct iwl4965_priv *priv, int txq_id,
Zhu Yib481de92007-09-25 17:54:57 -07004104 int tx_fifo, int sta_id, int tid,
4105 u16 ssn_idx)
4106{
4107 unsigned long flags;
4108 int rc;
4109 u16 ra_tid;
4110
4111 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4112 IWL_WARNING("queue number too small: %d, must be > %d\n",
4113 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4114
4115 ra_tid = BUILD_RAxTID(sta_id, tid);
4116
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004117 /* Modify device's station table to Tx this TID */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004118 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
Zhu Yib481de92007-09-25 17:54:57 -07004119
4120 spin_lock_irqsave(&priv->lock, flags);
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004121 rc = iwl4965_grab_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004122 if (rc) {
4123 spin_unlock_irqrestore(&priv->lock, flags);
4124 return rc;
4125 }
4126
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004127 /* Stop this Tx queue before configuring it */
Zhu Yib481de92007-09-25 17:54:57 -07004128 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4129
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004130 /* Map receiver-address / traffic-ID to this queue */
Zhu Yib481de92007-09-25 17:54:57 -07004131 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4132
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004133 /* Set this queue as a chain-building queue */
Reinette Chatre8a1b0242008-01-14 17:46:25 -08004134 iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
Zhu Yib481de92007-09-25 17:54:57 -07004135
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004136 /* Place first TFD at index corresponding to start sequence number.
4137 * Assumes that ssn_idx is valid (!= 0xFFF) */
Tomas Winklerfc4b6852007-10-25 17:15:24 +08004138 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4139 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
Zhu Yib481de92007-09-25 17:54:57 -07004140 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4141
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004142 /* Set up Tx window size and frame limit for this queue */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004143 iwl4965_write_targ_mem(priv,
Zhu Yib481de92007-09-25 17:54:57 -07004144 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4145 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4146 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4147
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004148 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
Zhu Yib481de92007-09-25 17:54:57 -07004149 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4150 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4151 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4152
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004153 iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
Zhu Yib481de92007-09-25 17:54:57 -07004154
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004155 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
Zhu Yib481de92007-09-25 17:54:57 -07004156 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4157
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004158 iwl4965_release_nic_access(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004159 spin_unlock_irqrestore(&priv->lock, flags);
4160
4161 return 0;
4162}
4163
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004164#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004165
4166/**
4167 * iwl4965_add_station - Initialize a station's hardware rate table
4168 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004169 * The uCode's station table contains a table of fallback rates
Zhu Yib481de92007-09-25 17:54:57 -07004170 * for automatic fallback during transmission.
4171 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004172 * NOTE: This sets up a default set of values. These will be replaced later
4173 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4174 * rc80211_simple.
Zhu Yib481de92007-09-25 17:54:57 -07004175 *
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004176 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4177 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4178 * which requires station table entry to exist).
Zhu Yib481de92007-09-25 17:54:57 -07004179 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004180void iwl4965_add_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
Zhu Yib481de92007-09-25 17:54:57 -07004181{
4182 int i, r;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004183 struct iwl4965_link_quality_cmd link_cmd = {
Zhu Yib481de92007-09-25 17:54:57 -07004184 .reserved1 = 0,
4185 };
4186 u16 rate_flags;
4187
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004188 /* Set up the rate scaling to start at selected rate, fall back
4189 * all the way down to 1M in IEEE order, and then spin on 1M */
Zhu Yib481de92007-09-25 17:54:57 -07004190 if (is_ap)
4191 r = IWL_RATE_54M_INDEX;
Johannes Berg8318d782008-01-24 19:38:38 +01004192 else if (priv->band == IEEE80211_BAND_5GHZ)
Zhu Yib481de92007-09-25 17:54:57 -07004193 r = IWL_RATE_6M_INDEX;
4194 else
4195 r = IWL_RATE_1M_INDEX;
4196
4197 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4198 rate_flags = 0;
4199 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4200 rate_flags |= RATE_MCS_CCK_MSK;
4201
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004202 /* Use Tx antenna B only */
Zhu Yib481de92007-09-25 17:54:57 -07004203 rate_flags |= RATE_MCS_ANT_B_MSK;
4204 rate_flags &= ~RATE_MCS_ANT_A_MSK;
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004205
Zhu Yib481de92007-09-25 17:54:57 -07004206 link_cmd.rs_table[i].rate_n_flags =
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004207 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4208 r = iwl4965_get_prev_ieee_rate(r);
Zhu Yib481de92007-09-25 17:54:57 -07004209 }
4210
4211 link_cmd.general_params.single_stream_ant_msk = 2;
4212 link_cmd.general_params.dual_stream_ant_msk = 3;
4213 link_cmd.agg_params.agg_dis_start_th = 3;
4214 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4215
4216 /* Update the rate scaling for control frame Tx to AP */
4217 link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
4218
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004219 iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
Zhu Yib481de92007-09-25 17:54:57 -07004220 &link_cmd);
4221}
4222
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004223#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004224
Johannes Berg8318d782008-01-24 19:38:38 +01004225static u8 iwl4965_is_channel_extension(struct iwl4965_priv *priv,
4226 enum ieee80211_band band,
Tomas Winkler78330fd2008-02-06 02:37:18 +02004227 u16 channel, u8 extension_chan_offset)
Zhu Yib481de92007-09-25 17:54:57 -07004228{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004229 const struct iwl4965_channel_info *ch_info;
Zhu Yib481de92007-09-25 17:54:57 -07004230
Johannes Berg8318d782008-01-24 19:38:38 +01004231 ch_info = iwl4965_get_channel_info(priv, band, channel);
Zhu Yib481de92007-09-25 17:54:57 -07004232 if (!is_channel_valid(ch_info))
4233 return 0;
4234
4235 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)
4236 return 0;
4237
4238 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4239 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4240 return 1;
4241
4242 return 0;
4243}
4244
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004245static u8 iwl4965_is_fat_tx_allowed(struct iwl4965_priv *priv,
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004246 struct ieee80211_ht_info *sta_ht_inf)
Zhu Yib481de92007-09-25 17:54:57 -07004247{
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004248 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
Zhu Yib481de92007-09-25 17:54:57 -07004249
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004250 if ((!iwl_ht_conf->is_ht) ||
4251 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
4252 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO))
Zhu Yib481de92007-09-25 17:54:57 -07004253 return 0;
4254
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004255 if (sta_ht_inf) {
4256 if ((!sta_ht_inf->ht_supported) ||
Roel Kluin194c7ca2008-02-02 20:48:48 +01004257 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004258 return 0;
4259 }
Zhu Yib481de92007-09-25 17:54:57 -07004260
Tomas Winkler78330fd2008-02-06 02:37:18 +02004261 return (iwl4965_is_channel_extension(priv, priv->band,
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004262 iwl_ht_conf->control_channel,
4263 iwl_ht_conf->extension_chan_offset));
Zhu Yib481de92007-09-25 17:54:57 -07004264}
4265
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004266void iwl4965_set_rxon_ht(struct iwl4965_priv *priv, struct iwl_ht_info *ht_info)
Zhu Yib481de92007-09-25 17:54:57 -07004267{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004268 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
Zhu Yib481de92007-09-25 17:54:57 -07004269 u32 val;
4270
4271 if (!ht_info->is_ht)
4272 return;
4273
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004274 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004275 if (iwl4965_is_fat_tx_allowed(priv, NULL))
Zhu Yib481de92007-09-25 17:54:57 -07004276 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4277 else
4278 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4279 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4280
4281 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4282 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4283 le16_to_cpu(rxon->channel),
4284 ht_info->control_channel);
4285 rxon->channel = cpu_to_le16(ht_info->control_channel);
4286 return;
4287 }
4288
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004289 /* Note: control channel is opposite of extension channel */
Zhu Yib481de92007-09-25 17:54:57 -07004290 switch (ht_info->extension_chan_offset) {
4291 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4292 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4293 break;
4294 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4295 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4296 break;
4297 case IWL_EXT_CHANNEL_OFFSET_AUTO:
4298 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4299 break;
4300 default:
4301 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4302 break;
4303 }
4304
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004305 val = ht_info->ht_protection;
Zhu Yib481de92007-09-25 17:54:57 -07004306
4307 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4308
Zhu Yib481de92007-09-25 17:54:57 -07004309 iwl4965_set_rxon_chain(priv);
4310
4311 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4312 "rxon flags 0x%X operation mode :0x%X "
4313 "extension channel offset 0x%x "
4314 "control chan %d\n",
Ron Rindjunskyfd105e72007-11-26 16:14:39 +02004315 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4316 le32_to_cpu(rxon->flags), ht_info->ht_protection,
Zhu Yib481de92007-09-25 17:54:57 -07004317 ht_info->extension_chan_offset,
4318 ht_info->control_channel);
4319 return;
4320}
4321
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004322void iwl4965_set_ht_add_station(struct iwl4965_priv *priv, u8 index,
4323 struct ieee80211_ht_info *sta_ht_inf)
Zhu Yib481de92007-09-25 17:54:57 -07004324{
4325 __le32 sta_flags;
Tomas Winklere53cfe02008-01-30 22:05:13 -08004326 u8 mimo_ps_mode;
Zhu Yib481de92007-09-25 17:54:57 -07004327
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004328 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
Zhu Yib481de92007-09-25 17:54:57 -07004329 goto done;
4330
Tomas Winklere53cfe02008-01-30 22:05:13 -08004331 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4332
Zhu Yib481de92007-09-25 17:54:57 -07004333 sta_flags = priv->stations[index].sta.station_flags;
4334
Tomas Winklere53cfe02008-01-30 22:05:13 -08004335 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4336
4337 switch (mimo_ps_mode) {
4338 case WLAN_HT_CAP_MIMO_PS_STATIC:
4339 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4340 break;
4341 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
Zhu Yib481de92007-09-25 17:54:57 -07004342 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
Tomas Winklere53cfe02008-01-30 22:05:13 -08004343 break;
4344 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4345 break;
4346 default:
4347 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4348 break;
4349 }
Zhu Yib481de92007-09-25 17:54:57 -07004350
4351 sta_flags |= cpu_to_le32(
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004352 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
Zhu Yib481de92007-09-25 17:54:57 -07004353
4354 sta_flags |= cpu_to_le32(
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004355 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
Zhu Yib481de92007-09-25 17:54:57 -07004356
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004357 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
Zhu Yib481de92007-09-25 17:54:57 -07004358 sta_flags |= STA_FLG_FAT_EN_MSK;
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004359 else
Tomas Winklere53cfe02008-01-30 22:05:13 -08004360 sta_flags &= ~STA_FLG_FAT_EN_MSK;
Ron Rindjunsky67d62032007-11-26 16:14:40 +02004361
Zhu Yib481de92007-09-25 17:54:57 -07004362 priv->stations[index].sta.station_flags = sta_flags;
4363 done:
4364 return;
4365}
4366
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004367static void iwl4965_sta_modify_add_ba_tid(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07004368 int sta_id, int tid, u16 ssn)
4369{
4370 unsigned long flags;
4371
4372 spin_lock_irqsave(&priv->sta_lock, flags);
4373 priv->stations[sta_id].sta.station_flags_msk = 0;
4374 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4375 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4376 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4377 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4378 spin_unlock_irqrestore(&priv->sta_lock, flags);
4379
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004380 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07004381}
4382
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004383static void iwl4965_sta_modify_del_ba_tid(struct iwl4965_priv *priv,
Zhu Yib481de92007-09-25 17:54:57 -07004384 int sta_id, int tid)
4385{
4386 unsigned long flags;
4387
4388 spin_lock_irqsave(&priv->sta_lock, flags);
4389 priv->stations[sta_id].sta.station_flags_msk = 0;
4390 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4391 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4392 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4393 spin_unlock_irqrestore(&priv->sta_lock, flags);
4394
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004395 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
Zhu Yib481de92007-09-25 17:54:57 -07004396}
4397
Cahill, Ben M8b6eaea2007-11-29 11:09:54 +08004398/*
4399 * Find first available (lowest unused) Tx Queue, mark it "active".
4400 * Called only when finding queue for aggregation.
4401 * Should never return anything < 7, because they should already
4402 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4403 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004404static int iwl4965_txq_ctx_activate_free(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004405{
4406 int txq_id;
4407
4408 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4409 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4410 return txq_id;
4411 return -1;
4412}
4413
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004414static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4415 u16 tid, u16 *start_seq_num)
Zhu Yib481de92007-09-25 17:54:57 -07004416{
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004417 struct iwl4965_priv *priv = hw->priv;
Zhu Yib481de92007-09-25 17:54:57 -07004418 int sta_id;
4419 int tx_fifo;
4420 int txq_id;
4421 int ssn = -1;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004422 int rc = 0;
Zhu Yib481de92007-09-25 17:54:57 -07004423 unsigned long flags;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004424 struct iwl4965_tid_data *tid_data;
Joe Perches0795af52007-10-03 17:59:30 -07004425 DECLARE_MAC_BUF(mac);
Zhu Yib481de92007-09-25 17:54:57 -07004426
4427 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4428 tx_fifo = default_tid_to_tx_fifo[tid];
4429 else
4430 return -EINVAL;
4431
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004432 IWL_WARNING("%s on da = %s tid = %d\n",
4433 __func__, print_mac(mac, da), tid);
Zhu Yib481de92007-09-25 17:54:57 -07004434
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004435 sta_id = iwl4965_hw_find_station(priv, da);
Zhu Yib481de92007-09-25 17:54:57 -07004436 if (sta_id == IWL_INVALID_STATION)
4437 return -ENXIO;
4438
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004439 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4440 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4441 return -ENXIO;
4442 }
4443
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004444 txq_id = iwl4965_txq_ctx_activate_free(priv);
Zhu Yib481de92007-09-25 17:54:57 -07004445 if (txq_id == -1)
4446 return -ENXIO;
4447
4448 spin_lock_irqsave(&priv->sta_lock, flags);
4449 tid_data = &priv->stations[sta_id].tid[tid];
4450 ssn = SEQ_TO_SN(tid_data->seq_number);
4451 tid_data->agg.txq_id = txq_id;
4452 spin_unlock_irqrestore(&priv->sta_lock, flags);
4453
4454 *start_seq_num = ssn;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004455 rc = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
Zhu Yib481de92007-09-25 17:54:57 -07004456 sta_id, tid, ssn);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004457 if (rc)
4458 return rc;
4459
4460 rc = 0;
4461 if (tid_data->tfds_in_queue == 0) {
4462 printk(KERN_ERR "HW queue is empty\n");
4463 tid_data->agg.state = IWL_AGG_ON;
4464 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4465 } else {
4466 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4467 tid_data->tfds_in_queue);
4468 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4469 }
4470 return rc;
Zhu Yib481de92007-09-25 17:54:57 -07004471}
4472
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004473static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4474 u16 tid)
Zhu Yib481de92007-09-25 17:54:57 -07004475{
4476
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004477 struct iwl4965_priv *priv = hw->priv;
Zhu Yib481de92007-09-25 17:54:57 -07004478 int tx_fifo_id, txq_id, sta_id, ssn = -1;
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004479 struct iwl4965_tid_data *tid_data;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004480 int rc, write_ptr, read_ptr;
4481 unsigned long flags;
Joe Perches0795af52007-10-03 17:59:30 -07004482 DECLARE_MAC_BUF(mac);
4483
Zhu Yib481de92007-09-25 17:54:57 -07004484 if (!da) {
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004485 IWL_ERROR("da = NULL\n");
Zhu Yib481de92007-09-25 17:54:57 -07004486 return -EINVAL;
4487 }
4488
4489 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4490 tx_fifo_id = default_tid_to_tx_fifo[tid];
4491 else
4492 return -EINVAL;
4493
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004494 sta_id = iwl4965_hw_find_station(priv, da);
Zhu Yib481de92007-09-25 17:54:57 -07004495
4496 if (sta_id == IWL_INVALID_STATION)
4497 return -ENXIO;
4498
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004499 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4500 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4501
Zhu Yib481de92007-09-25 17:54:57 -07004502 tid_data = &priv->stations[sta_id].tid[tid];
4503 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4504 txq_id = tid_data->agg.txq_id;
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004505 write_ptr = priv->txq[txq_id].q.write_ptr;
4506 read_ptr = priv->txq[txq_id].q.read_ptr;
Zhu Yib481de92007-09-25 17:54:57 -07004507
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004508 /* The queue is not empty */
4509 if (write_ptr != read_ptr) {
4510 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4511 priv->stations[sta_id].tid[tid].agg.state =
4512 IWL_EMPTYING_HW_QUEUE_DELBA;
4513 return 0;
4514 }
4515
4516 IWL_DEBUG_HT("HW queue empty\n");;
4517 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4518
4519 spin_lock_irqsave(&priv->lock, flags);
4520 rc = iwl4965_grab_nic_access(priv);
4521 if (rc) {
4522 spin_unlock_irqrestore(&priv->lock, flags);
4523 return rc;
4524 }
Zhu Yib481de92007-09-25 17:54:57 -07004525 rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004526 iwl4965_release_nic_access(priv);
4527 spin_unlock_irqrestore(&priv->lock, flags);
4528
Zhu Yib481de92007-09-25 17:54:57 -07004529 if (rc)
4530 return rc;
4531
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004532 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
4533
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004534 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
Ron Rindjunskyfe01b472008-01-28 14:07:24 +02004535 print_mac(mac, da), tid);
Zhu Yib481de92007-09-25 17:54:57 -07004536
4537 return 0;
4538}
4539
Ron Rindjunsky8114fcf2008-01-28 14:07:23 +02004540int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4541 enum ieee80211_ampdu_mlme_action action,
4542 const u8 *addr, u16 tid, u16 *ssn)
4543{
4544 struct iwl4965_priv *priv = hw->priv;
4545 int sta_id;
4546 DECLARE_MAC_BUF(mac);
4547
4548 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4549 print_mac(mac, addr), tid);
4550 sta_id = iwl4965_hw_find_station(priv, addr);
4551 switch (action) {
4552 case IEEE80211_AMPDU_RX_START:
4553 IWL_DEBUG_HT("start Rx\n");
4554 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4555 break;
4556 case IEEE80211_AMPDU_RX_STOP:
4557 IWL_DEBUG_HT("stop Rx\n");
4558 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4559 break;
4560 case IEEE80211_AMPDU_TX_START:
4561 IWL_DEBUG_HT("start Tx\n");
4562 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4563 case IEEE80211_AMPDU_TX_STOP:
4564 IWL_DEBUG_HT("stop Tx\n");
4565 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4566 default:
4567 IWL_DEBUG_HT("unknown\n");
4568 return -EINVAL;
4569 break;
4570 }
4571 return 0;
4572}
4573
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004574#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004575
4576/* Set up 4965-specific Rx frame reply handlers */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004577void iwl4965_hw_rx_handler_setup(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004578{
4579 /* Legacy Rx frames */
4580 priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
4581
4582 /* High-throughput (HT) Rx frames */
4583 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4584 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4585
4586 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4587 iwl4965_rx_missed_beacon_notif;
4588
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004589#ifdef CONFIG_IWL4965_HT
Zhu Yib481de92007-09-25 17:54:57 -07004590 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004591#endif /* CONFIG_IWL4965_HT */
Zhu Yib481de92007-09-25 17:54:57 -07004592}
4593
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004594void iwl4965_hw_setup_deferred_work(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004595{
4596 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4597 INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
Christoph Hellwigc8b0e6e2007-10-25 17:15:51 +08004598#ifdef CONFIG_IWL4965_SENSITIVITY
Zhu Yib481de92007-09-25 17:54:57 -07004599 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4600#endif
Zhu Yib481de92007-09-25 17:54:57 -07004601 init_timer(&priv->statistics_periodic);
4602 priv->statistics_periodic.data = (unsigned long)priv;
4603 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4604}
4605
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004606void iwl4965_hw_cancel_deferred_work(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004607{
4608 del_timer_sync(&priv->statistics_periodic);
4609
4610 cancel_delayed_work(&priv->init_alive_start);
4611}
4612
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004613struct pci_device_id iwl4965_hw_card_ids[] = {
Zhu Yi3567c112007-11-06 22:06:24 -08004614 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4229)},
4615 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4230)},
Zhu Yib481de92007-09-25 17:54:57 -07004616 {0}
4617};
4618
Ben Cahill796083c2007-11-29 11:09:45 +08004619/*
4620 * The device's EEPROM semaphore prevents conflicts between driver and uCode
4621 * when accessing the EEPROM; each access is a series of pulses to/from the
4622 * EEPROM chip, not a single event, so even reads could conflict if they
4623 * weren't arbitrated by the semaphore.
4624 */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004625int iwl4965_eeprom_acquire_semaphore(struct iwl4965_priv *priv)
Zhu Yib481de92007-09-25 17:54:57 -07004626{
4627 u16 count;
4628 int rc;
4629
4630 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
Ben Cahill796083c2007-11-29 11:09:45 +08004631 /* Request semaphore */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004632 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -07004633 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
Ben Cahill796083c2007-11-29 11:09:45 +08004634
4635 /* See if we got it */
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004636 rc = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
Zhu Yib481de92007-09-25 17:54:57 -07004637 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
4638 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
4639 EEPROM_SEM_TIMEOUT);
4640 if (rc >= 0) {
Ian Schram91e17472007-10-25 17:15:23 +08004641 IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
Zhu Yib481de92007-09-25 17:54:57 -07004642 count+1);
4643 return rc;
4644 }
4645 }
4646
4647 return rc;
4648}
4649
Christoph Hellwigbb8c0932008-01-27 16:41:47 -08004650MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);