blob: 086682e51c242ec381a6debd4d0a0763a7408175 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020052#include <linux/dcbnl.h>
Jiri Pirkoc4745502016-02-26 17:32:26 +010053#include <net/devlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020054#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
251static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
252{
253 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
260static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
261 bool enable)
262{
263 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
264 char svpe_pl[MLXSW_REG_SVPE_LEN];
265
266 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
267 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
268}
269
270int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
271 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
272 u16 vid)
273{
274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
275 char svfa_pl[MLXSW_REG_SVFA_LEN];
276
277 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
278 fid, vid);
279 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
280}
281
282static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
283 u16 vid, bool learn_enable)
284{
285 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
286 char *spvmlr_pl;
287 int err;
288
289 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
290 if (!spvmlr_pl)
291 return -ENOMEM;
292 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
293 learn_enable);
294 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
295 kfree(spvmlr_pl);
296 return err;
297}
298
299static int
300mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
301{
302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
303 char sspr_pl[MLXSW_REG_SSPR_LEN];
304
305 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
306 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
307}
308
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200309static int __mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
310 u8 local_port, u8 *p_module,
311 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200312{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200313 char pmlp_pl[MLXSW_REG_PMLP_LEN];
314 int err;
315
Ido Schimmel558c2d52016-02-26 17:32:29 +0100316 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200317 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
318 if (err)
319 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100320 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
321 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200322 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200323 return 0;
324}
325
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200326static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
327 u8 local_port, u8 *p_module,
328 u8 *p_width)
329{
330 u8 lane;
331
332 return __mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, p_module,
333 p_width, &lane);
334}
335
Ido Schimmel18f1e702016-02-26 17:32:31 +0100336static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
337 u8 module, u8 width, u8 lane)
338{
339 char pmlp_pl[MLXSW_REG_PMLP_LEN];
340 int i;
341
342 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
343 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
344 for (i = 0; i < width; i++) {
345 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
346 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
347 }
348
349 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
350}
351
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100352static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
353{
354 char pmlp_pl[MLXSW_REG_PMLP_LEN];
355
356 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
357 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
358 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
359}
360
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200361static int mlxsw_sp_port_open(struct net_device *dev)
362{
363 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
364 int err;
365
366 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
367 if (err)
368 return err;
369 netif_start_queue(dev);
370 return 0;
371}
372
373static int mlxsw_sp_port_stop(struct net_device *dev)
374{
375 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
376
377 netif_stop_queue(dev);
378 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
379}
380
381static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
382 struct net_device *dev)
383{
384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
385 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
386 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
387 const struct mlxsw_tx_info tx_info = {
388 .local_port = mlxsw_sp_port->local_port,
389 .is_emad = false,
390 };
391 u64 len;
392 int err;
393
394 if (mlxsw_core_skb_transmit_busy(mlxsw_sp, &tx_info))
395 return NETDEV_TX_BUSY;
396
397 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
398 struct sk_buff *skb_orig = skb;
399
400 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
401 if (!skb) {
402 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
403 dev_kfree_skb_any(skb_orig);
404 return NETDEV_TX_OK;
405 }
406 }
407
408 if (eth_skb_pad(skb)) {
409 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
410 return NETDEV_TX_OK;
411 }
412
413 mlxsw_sp_txhdr_construct(skb, &tx_info);
414 len = skb->len;
415 /* Due to a race we might fail here because of a full queue. In that
416 * unlikely case we simply drop the packet.
417 */
418 err = mlxsw_core_skb_transmit(mlxsw_sp, skb, &tx_info);
419
420 if (!err) {
421 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
422 u64_stats_update_begin(&pcpu_stats->syncp);
423 pcpu_stats->tx_packets++;
424 pcpu_stats->tx_bytes += len;
425 u64_stats_update_end(&pcpu_stats->syncp);
426 } else {
427 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
428 dev_kfree_skb_any(skb);
429 }
430 return NETDEV_TX_OK;
431}
432
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100433static void mlxsw_sp_set_rx_mode(struct net_device *dev)
434{
435}
436
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200437static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
438{
439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
440 struct sockaddr *addr = p;
441 int err;
442
443 if (!is_valid_ether_addr(addr->sa_data))
444 return -EADDRNOTAVAIL;
445
446 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
447 if (err)
448 return err;
449 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
450 return 0;
451}
452
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200453static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
454 bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200455{
456 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
457
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200458 if (pause_en) {
459 u16 pg_pause_size = pg_size + MLXSW_SP_PAUSE_DELAY;
460
461 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
462 pg_pause_size, pg_size);
463 } else {
464 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
465 }
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200466}
467
468int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200469 u8 *prio_tc, bool pause_en)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200470{
471 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200472 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200473 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200474
475 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
476 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
477 if (err)
478 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200479
480 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
481 bool configure = false;
482
483 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
484 if (prio_tc[j] == i) {
485 configure = true;
486 break;
487 }
488 }
489
490 if (!configure)
491 continue;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200492 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200493 }
494
Ido Schimmelff6551e2016-04-06 17:10:03 +0200495 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
496}
497
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200498static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200499 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200500{
501 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
502 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
503 u8 *prio_tc;
504
505 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
506
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200507 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
508 pause_en);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200509}
510
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200511static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
512{
513 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200514 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200515 int err;
516
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200517 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200518 if (err)
519 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200520 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
521 if (err)
522 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200523 dev->mtu = mtu;
524 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200525
526err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200527 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200528 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200529}
530
531static struct rtnl_link_stats64 *
532mlxsw_sp_port_get_stats64(struct net_device *dev,
533 struct rtnl_link_stats64 *stats)
534{
535 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
536 struct mlxsw_sp_port_pcpu_stats *p;
537 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
538 u32 tx_dropped = 0;
539 unsigned int start;
540 int i;
541
542 for_each_possible_cpu(i) {
543 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
544 do {
545 start = u64_stats_fetch_begin_irq(&p->syncp);
546 rx_packets = p->rx_packets;
547 rx_bytes = p->rx_bytes;
548 tx_packets = p->tx_packets;
549 tx_bytes = p->tx_bytes;
550 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
551
552 stats->rx_packets += rx_packets;
553 stats->rx_bytes += rx_bytes;
554 stats->tx_packets += tx_packets;
555 stats->tx_bytes += tx_bytes;
556 /* tx_dropped is u32, updated without syncp protection. */
557 tx_dropped += p->tx_dropped;
558 }
559 stats->tx_dropped = tx_dropped;
560 return stats;
561}
562
563int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
564 u16 vid_end, bool is_member, bool untagged)
565{
566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
567 char *spvm_pl;
568 int err;
569
570 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
571 if (!spvm_pl)
572 return -ENOMEM;
573
574 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
575 vid_end, is_member, untagged);
576 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
577 kfree(spvm_pl);
578 return err;
579}
580
581static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
582{
583 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
584 u16 vid, last_visited_vid;
585 int err;
586
587 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
588 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
589 vid);
590 if (err) {
591 last_visited_vid = vid;
592 goto err_port_vid_to_fid_set;
593 }
594 }
595
596 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
597 if (err) {
598 last_visited_vid = VLAN_N_VID;
599 goto err_port_vid_to_fid_set;
600 }
601
602 return 0;
603
604err_port_vid_to_fid_set:
605 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
606 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
607 vid);
608 return err;
609}
610
611static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
612{
613 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
614 u16 vid;
615 int err;
616
617 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
618 if (err)
619 return err;
620
621 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
622 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
623 vid, vid);
624 if (err)
625 return err;
626 }
627
628 return 0;
629}
630
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100631static struct mlxsw_sp_vfid *
632mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
633{
634 struct mlxsw_sp_vfid *vfid;
635
636 list_for_each_entry(vfid, &mlxsw_sp->port_vfids.list, list) {
637 if (vfid->vid == vid)
638 return vfid;
639 }
640
641 return NULL;
642}
643
644static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
645{
646 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
647 MLXSW_SP_VFID_PORT_MAX);
648}
649
650static int __mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp, u16 vfid)
651{
652 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
653 char sfmr_pl[MLXSW_REG_SFMR_LEN];
654
655 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_CREATE_FID, fid, 0);
656 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
657}
658
659static void __mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp, u16 vfid)
660{
661 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
662 char sfmr_pl[MLXSW_REG_SFMR_LEN];
663
664 mlxsw_reg_sfmr_pack(sfmr_pl, MLXSW_REG_SFMR_OP_DESTROY_FID, fid, 0);
665 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
666}
667
668static struct mlxsw_sp_vfid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
669 u16 vid)
670{
671 struct device *dev = mlxsw_sp->bus_info->dev;
672 struct mlxsw_sp_vfid *vfid;
673 u16 n_vfid;
674 int err;
675
676 n_vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
677 if (n_vfid == MLXSW_SP_VFID_PORT_MAX) {
678 dev_err(dev, "No available vFIDs\n");
679 return ERR_PTR(-ERANGE);
680 }
681
682 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
683 if (err) {
684 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
685 return ERR_PTR(err);
686 }
687
688 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
689 if (!vfid)
690 goto err_allocate_vfid;
691
692 vfid->vfid = n_vfid;
693 vfid->vid = vid;
694
695 list_add(&vfid->list, &mlxsw_sp->port_vfids.list);
696 set_bit(n_vfid, mlxsw_sp->port_vfids.mapped);
697
698 return vfid;
699
700err_allocate_vfid:
701 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
702 return ERR_PTR(-ENOMEM);
703}
704
705static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
706 struct mlxsw_sp_vfid *vfid)
707{
708 clear_bit(vfid->vfid, mlxsw_sp->port_vfids.mapped);
709 list_del(&vfid->list);
710
711 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
712
713 kfree(vfid);
714}
715
716static struct mlxsw_sp_port *
717mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port,
718 struct mlxsw_sp_vfid *vfid)
719{
720 struct mlxsw_sp_port *mlxsw_sp_vport;
721
722 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
723 if (!mlxsw_sp_vport)
724 return NULL;
725
726 /* dev will be set correctly after the VLAN device is linked
727 * with the real device. In case of bridge SELF invocation, dev
728 * will remain as is.
729 */
730 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
731 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
732 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
733 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100734 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
735 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100736 mlxsw_sp_vport->vport.vfid = vfid;
737 mlxsw_sp_vport->vport.vid = vfid->vid;
738
739 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
740
741 return mlxsw_sp_vport;
742}
743
744static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
745{
746 list_del(&mlxsw_sp_vport->vport.list);
747 kfree(mlxsw_sp_vport);
748}
749
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200750int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
751 u16 vid)
752{
753 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
754 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100755 struct mlxsw_sp_port *mlxsw_sp_vport;
756 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200757 int err;
758
759 /* VLAN 0 is added to HW filter when device goes up, but it is
760 * reserved in our case, so simply return.
761 */
762 if (!vid)
763 return 0;
764
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100765 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200766 netdev_warn(dev, "VID=%d already configured\n", vid);
767 return 0;
768 }
769
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100770 vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
771 if (!vfid) {
772 vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
773 if (IS_ERR(vfid)) {
774 netdev_err(dev, "Failed to create vFID for VID=%d\n",
775 vid);
776 return PTR_ERR(vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200777 }
778 }
779
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100780 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vfid);
781 if (!mlxsw_sp_vport) {
782 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
783 err = -ENOMEM;
784 goto err_port_vport_create;
785 }
786
787 if (!vfid->nr_vports) {
788 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid,
Ido Schimmel19ae6122015-12-15 16:03:39 +0100789 true, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100790 if (err) {
791 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
792 vfid->vfid);
793 goto err_vport_flood_set;
794 }
795 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200796
797 /* When adding the first VLAN interface on a bridged port we need to
798 * transition all the active 802.1Q bridge VLANs to use explicit
799 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
800 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100801 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200802 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
803 if (err) {
804 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100805 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200806 }
807 }
808
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100809 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200810 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100811 true,
812 mlxsw_sp_vfid_to_fid(vfid->vfid),
813 vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814 if (err) {
815 netdev_err(dev, "Failed to map {Port, VID=%d} to vFID=%d\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100816 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200817 goto err_port_vid_to_fid_set;
818 }
819
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100820 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821 if (err) {
822 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
823 goto err_port_vid_learning_set;
824 }
825
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100826 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200827 if (err) {
828 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
829 vid);
830 goto err_port_add_vid;
831 }
832
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100833 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200834 MLXSW_REG_SPMS_STATE_FORWARDING);
835 if (err) {
836 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
837 goto err_port_stp_state_set;
838 }
839
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100840 vfid->nr_vports++;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200841
842 return 0;
843
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200844err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100845 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200846err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100847 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848err_port_vid_learning_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100849 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200850 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100851 mlxsw_sp_vfid_to_fid(vfid->vfid), vid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200852err_port_vid_to_fid_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100853 if (list_is_singular(&mlxsw_sp_port->vports_list))
854 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
855err_port_vp_mode_trans:
856 if (!vfid->nr_vports)
Ido Schimmel19ae6122015-12-15 16:03:39 +0100857 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
858 false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100859err_vport_flood_set:
860 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
861err_port_vport_create:
862 if (!vfid->nr_vports)
863 mlxsw_sp_vfid_destroy(mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200864 return err;
865}
866
867int mlxsw_sp_port_kill_vid(struct net_device *dev,
868 __be16 __always_unused proto, u16 vid)
869{
870 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100871 struct mlxsw_sp_port *mlxsw_sp_vport;
872 struct mlxsw_sp_vfid *vfid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873 int err;
874
875 /* VLAN 0 is removed from HW filter when device goes down, but
876 * it is reserved in our case, so simply return.
877 */
878 if (!vid)
879 return 0;
880
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100881 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
882 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200883 netdev_warn(dev, "VID=%d does not exist\n", vid);
884 return 0;
885 }
886
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100887 vfid = mlxsw_sp_vport->vport.vfid;
888
889 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 MLXSW_REG_SPMS_STATE_DISCARDING);
891 if (err) {
892 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
893 return err;
894 }
895
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100896 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897 if (err) {
898 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
899 vid);
900 return err;
901 }
902
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100903 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200904 if (err) {
905 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
906 return err;
907 }
908
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100909 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200910 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100911 false,
912 mlxsw_sp_vfid_to_fid(vfid->vfid),
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200913 vid);
914 if (err) {
915 netdev_err(dev, "Failed to invalidate {Port, VID=%d} to vFID=%d mapping\n",
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100916 vid, vfid->vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200917 return err;
918 }
919
920 /* When removing the last VLAN interface on a bridged port we need to
921 * transition all active 802.1Q bridge VLANs to use VID to FID
922 * mappings and set port's mode to VLAN mode.
923 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100924 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200925 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
926 if (err) {
927 netdev_err(dev, "Failed to set to VLAN mode\n");
928 return err;
929 }
930 }
931
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100932 vfid->nr_vports--;
933 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
934
935 /* Destroy the vFID if no vPorts are assigned to it anymore. */
936 if (!vfid->nr_vports)
937 mlxsw_sp_vfid_destroy(mlxsw_sp_port->mlxsw_sp, vfid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200938
939 return 0;
940}
941
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200942static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
943 size_t len)
944{
945 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
946 u8 module, width, lane;
947 int err;
948
949 err = __mlxsw_sp_port_module_info_get(mlxsw_sp_port->mlxsw_sp,
950 mlxsw_sp_port->local_port,
951 &module, &width, &lane);
952 if (err) {
953 netdev_err(dev, "Failed to retrieve module information\n");
954 return err;
955 }
956
957 if (!mlxsw_sp_port->split)
958 err = snprintf(name, len, "p%d", module + 1);
959 else
960 err = snprintf(name, len, "p%ds%d", module + 1,
961 lane / width);
962
963 if (err >= len)
964 return -EINVAL;
965
966 return 0;
967}
968
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200969static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
970 .ndo_open = mlxsw_sp_port_open,
971 .ndo_stop = mlxsw_sp_port_stop,
972 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100973 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200974 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
975 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
976 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
977 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
978 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
979 .ndo_fdb_add = switchdev_port_fdb_add,
980 .ndo_fdb_del = switchdev_port_fdb_del,
981 .ndo_fdb_dump = switchdev_port_fdb_dump,
982 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
983 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
984 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200985 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200986};
987
988static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
989 struct ethtool_drvinfo *drvinfo)
990{
991 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
992 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
993
994 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
995 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
996 sizeof(drvinfo->version));
997 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
998 "%d.%d.%d",
999 mlxsw_sp->bus_info->fw_rev.major,
1000 mlxsw_sp->bus_info->fw_rev.minor,
1001 mlxsw_sp->bus_info->fw_rev.subminor);
1002 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1003 sizeof(drvinfo->bus_info));
1004}
1005
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001006static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1007 struct ethtool_pauseparam *pause)
1008{
1009 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1010
1011 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1012 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1013}
1014
1015static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1016 struct ethtool_pauseparam *pause)
1017{
1018 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1019
1020 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1021 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1022 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1023
1024 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1025 pfcc_pl);
1026}
1027
1028static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1029 struct ethtool_pauseparam *pause)
1030{
1031 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1032 bool pause_en = pause->tx_pause || pause->rx_pause;
1033 int err;
1034
1035 if (pause->autoneg) {
1036 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1037 return -EINVAL;
1038 }
1039
1040 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1041 if (err) {
1042 netdev_err(dev, "Failed to configure port's headroom\n");
1043 return err;
1044 }
1045
1046 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1047 if (err) {
1048 netdev_err(dev, "Failed to set PAUSE parameters\n");
1049 goto err_port_pause_configure;
1050 }
1051
1052 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1053 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1054
1055 return 0;
1056
1057err_port_pause_configure:
1058 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1059 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1060 return err;
1061}
1062
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001063struct mlxsw_sp_port_hw_stats {
1064 char str[ETH_GSTRING_LEN];
1065 u64 (*getter)(char *payload);
1066};
1067
1068static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1069 {
1070 .str = "a_frames_transmitted_ok",
1071 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1072 },
1073 {
1074 .str = "a_frames_received_ok",
1075 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1076 },
1077 {
1078 .str = "a_frame_check_sequence_errors",
1079 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1080 },
1081 {
1082 .str = "a_alignment_errors",
1083 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1084 },
1085 {
1086 .str = "a_octets_transmitted_ok",
1087 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1088 },
1089 {
1090 .str = "a_octets_received_ok",
1091 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1092 },
1093 {
1094 .str = "a_multicast_frames_xmitted_ok",
1095 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1096 },
1097 {
1098 .str = "a_broadcast_frames_xmitted_ok",
1099 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1100 },
1101 {
1102 .str = "a_multicast_frames_received_ok",
1103 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1104 },
1105 {
1106 .str = "a_broadcast_frames_received_ok",
1107 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1108 },
1109 {
1110 .str = "a_in_range_length_errors",
1111 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1112 },
1113 {
1114 .str = "a_out_of_range_length_field",
1115 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1116 },
1117 {
1118 .str = "a_frame_too_long_errors",
1119 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1120 },
1121 {
1122 .str = "a_symbol_error_during_carrier",
1123 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1124 },
1125 {
1126 .str = "a_mac_control_frames_transmitted",
1127 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1128 },
1129 {
1130 .str = "a_mac_control_frames_received",
1131 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1132 },
1133 {
1134 .str = "a_unsupported_opcodes_received",
1135 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1136 },
1137 {
1138 .str = "a_pause_mac_ctrl_frames_received",
1139 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1140 },
1141 {
1142 .str = "a_pause_mac_ctrl_frames_xmitted",
1143 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1144 },
1145};
1146
1147#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1148
1149static void mlxsw_sp_port_get_strings(struct net_device *dev,
1150 u32 stringset, u8 *data)
1151{
1152 u8 *p = data;
1153 int i;
1154
1155 switch (stringset) {
1156 case ETH_SS_STATS:
1157 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1158 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1159 ETH_GSTRING_LEN);
1160 p += ETH_GSTRING_LEN;
1161 }
1162 break;
1163 }
1164}
1165
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001166static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1167 enum ethtool_phys_id_state state)
1168{
1169 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1171 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1172 bool active;
1173
1174 switch (state) {
1175 case ETHTOOL_ID_ACTIVE:
1176 active = true;
1177 break;
1178 case ETHTOOL_ID_INACTIVE:
1179 active = false;
1180 break;
1181 default:
1182 return -EOPNOTSUPP;
1183 }
1184
1185 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1186 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1187}
1188
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001189static void mlxsw_sp_port_get_stats(struct net_device *dev,
1190 struct ethtool_stats *stats, u64 *data)
1191{
1192 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1193 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1194 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1195 int i;
1196 int err;
1197
1198 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port);
1199 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1200 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1201 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1202}
1203
1204static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1205{
1206 switch (sset) {
1207 case ETH_SS_STATS:
1208 return MLXSW_SP_PORT_HW_STATS_LEN;
1209 default:
1210 return -EOPNOTSUPP;
1211 }
1212}
1213
1214struct mlxsw_sp_port_link_mode {
1215 u32 mask;
1216 u32 supported;
1217 u32 advertised;
1218 u32 speed;
1219};
1220
1221static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1222 {
1223 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1224 .supported = SUPPORTED_100baseT_Full,
1225 .advertised = ADVERTISED_100baseT_Full,
1226 .speed = 100,
1227 },
1228 {
1229 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1230 .speed = 100,
1231 },
1232 {
1233 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1234 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1235 .supported = SUPPORTED_1000baseKX_Full,
1236 .advertised = ADVERTISED_1000baseKX_Full,
1237 .speed = 1000,
1238 },
1239 {
1240 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1241 .supported = SUPPORTED_10000baseT_Full,
1242 .advertised = ADVERTISED_10000baseT_Full,
1243 .speed = 10000,
1244 },
1245 {
1246 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1247 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1248 .supported = SUPPORTED_10000baseKX4_Full,
1249 .advertised = ADVERTISED_10000baseKX4_Full,
1250 .speed = 10000,
1251 },
1252 {
1253 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1254 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1255 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1256 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1257 .supported = SUPPORTED_10000baseKR_Full,
1258 .advertised = ADVERTISED_10000baseKR_Full,
1259 .speed = 10000,
1260 },
1261 {
1262 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1263 .supported = SUPPORTED_20000baseKR2_Full,
1264 .advertised = ADVERTISED_20000baseKR2_Full,
1265 .speed = 20000,
1266 },
1267 {
1268 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1269 .supported = SUPPORTED_40000baseCR4_Full,
1270 .advertised = ADVERTISED_40000baseCR4_Full,
1271 .speed = 40000,
1272 },
1273 {
1274 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1275 .supported = SUPPORTED_40000baseKR4_Full,
1276 .advertised = ADVERTISED_40000baseKR4_Full,
1277 .speed = 40000,
1278 },
1279 {
1280 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1281 .supported = SUPPORTED_40000baseSR4_Full,
1282 .advertised = ADVERTISED_40000baseSR4_Full,
1283 .speed = 40000,
1284 },
1285 {
1286 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1287 .supported = SUPPORTED_40000baseLR4_Full,
1288 .advertised = ADVERTISED_40000baseLR4_Full,
1289 .speed = 40000,
1290 },
1291 {
1292 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1293 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1294 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1295 .speed = 25000,
1296 },
1297 {
1298 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1299 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1300 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1301 .speed = 50000,
1302 },
1303 {
1304 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1305 .supported = SUPPORTED_56000baseKR4_Full,
1306 .advertised = ADVERTISED_56000baseKR4_Full,
1307 .speed = 56000,
1308 },
1309 {
1310 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1311 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1312 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1313 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1314 .speed = 100000,
1315 },
1316};
1317
1318#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1319
1320static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1321{
1322 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1323 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1324 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1325 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1328 return SUPPORTED_FIBRE;
1329
1330 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1331 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1332 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1333 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1334 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1335 return SUPPORTED_Backplane;
1336 return 0;
1337}
1338
1339static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1340{
1341 u32 modes = 0;
1342 int i;
1343
1344 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1345 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1346 modes |= mlxsw_sp_port_link_mode[i].supported;
1347 }
1348 return modes;
1349}
1350
1351static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1352{
1353 u32 modes = 0;
1354 int i;
1355
1356 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1357 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1358 modes |= mlxsw_sp_port_link_mode[i].advertised;
1359 }
1360 return modes;
1361}
1362
1363static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1364 struct ethtool_cmd *cmd)
1365{
1366 u32 speed = SPEED_UNKNOWN;
1367 u8 duplex = DUPLEX_UNKNOWN;
1368 int i;
1369
1370 if (!carrier_ok)
1371 goto out;
1372
1373 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1374 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1375 speed = mlxsw_sp_port_link_mode[i].speed;
1376 duplex = DUPLEX_FULL;
1377 break;
1378 }
1379 }
1380out:
1381 ethtool_cmd_speed_set(cmd, speed);
1382 cmd->duplex = duplex;
1383}
1384
1385static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1386{
1387 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1388 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1389 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1390 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1391 return PORT_FIBRE;
1392
1393 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1394 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1395 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1396 return PORT_DA;
1397
1398 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1399 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1400 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1401 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1402 return PORT_NONE;
1403
1404 return PORT_OTHER;
1405}
1406
1407static int mlxsw_sp_port_get_settings(struct net_device *dev,
1408 struct ethtool_cmd *cmd)
1409{
1410 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1411 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1412 char ptys_pl[MLXSW_REG_PTYS_LEN];
1413 u32 eth_proto_cap;
1414 u32 eth_proto_admin;
1415 u32 eth_proto_oper;
1416 int err;
1417
1418 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1419 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1420 if (err) {
1421 netdev_err(dev, "Failed to get proto");
1422 return err;
1423 }
1424 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1425 &eth_proto_admin, &eth_proto_oper);
1426
1427 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1428 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1429 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1430 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1431 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1432 eth_proto_oper, cmd);
1433
1434 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1435 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1436 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1437
1438 cmd->transceiver = XCVR_INTERNAL;
1439 return 0;
1440}
1441
1442static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1443{
1444 u32 ptys_proto = 0;
1445 int i;
1446
1447 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1448 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1449 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1450 }
1451 return ptys_proto;
1452}
1453
1454static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1455{
1456 u32 ptys_proto = 0;
1457 int i;
1458
1459 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1460 if (speed == mlxsw_sp_port_link_mode[i].speed)
1461 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1462 }
1463 return ptys_proto;
1464}
1465
Ido Schimmel18f1e702016-02-26 17:32:31 +01001466static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1467{
1468 u32 ptys_proto = 0;
1469 int i;
1470
1471 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1472 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1473 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1474 }
1475 return ptys_proto;
1476}
1477
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001478static int mlxsw_sp_port_set_settings(struct net_device *dev,
1479 struct ethtool_cmd *cmd)
1480{
1481 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1482 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1483 char ptys_pl[MLXSW_REG_PTYS_LEN];
1484 u32 speed;
1485 u32 eth_proto_new;
1486 u32 eth_proto_cap;
1487 u32 eth_proto_admin;
1488 bool is_up;
1489 int err;
1490
1491 speed = ethtool_cmd_speed(cmd);
1492
1493 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1494 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1495 mlxsw_sp_to_ptys_speed(speed);
1496
1497 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1498 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1499 if (err) {
1500 netdev_err(dev, "Failed to get proto");
1501 return err;
1502 }
1503 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1504
1505 eth_proto_new = eth_proto_new & eth_proto_cap;
1506 if (!eth_proto_new) {
1507 netdev_err(dev, "Not supported proto admin requested");
1508 return -EINVAL;
1509 }
1510 if (eth_proto_new == eth_proto_admin)
1511 return 0;
1512
1513 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1514 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1515 if (err) {
1516 netdev_err(dev, "Failed to set proto admin");
1517 return err;
1518 }
1519
1520 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1521 if (err) {
1522 netdev_err(dev, "Failed to get oper status");
1523 return err;
1524 }
1525 if (!is_up)
1526 return 0;
1527
1528 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1529 if (err) {
1530 netdev_err(dev, "Failed to set admin status");
1531 return err;
1532 }
1533
1534 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1535 if (err) {
1536 netdev_err(dev, "Failed to set admin status");
1537 return err;
1538 }
1539
1540 return 0;
1541}
1542
1543static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1544 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1545 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001546 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1547 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001548 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001549 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001550 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1551 .get_sset_count = mlxsw_sp_port_get_sset_count,
1552 .get_settings = mlxsw_sp_port_get_settings,
1553 .set_settings = mlxsw_sp_port_set_settings,
1554};
1555
Ido Schimmel18f1e702016-02-26 17:32:31 +01001556static int
1557mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1558{
1559 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1560 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1561 char ptys_pl[MLXSW_REG_PTYS_LEN];
1562 u32 eth_proto_admin;
1563
1564 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1565 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1566 eth_proto_admin);
1567 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1568}
1569
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001570int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1571 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1572 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001573{
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 char qeec_pl[MLXSW_REG_QEEC_LEN];
1576
1577 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1578 next_index);
1579 mlxsw_reg_qeec_de_set(qeec_pl, true);
1580 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1581 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1583}
1584
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001585int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 enum mlxsw_reg_qeec_hr hr, u8 index,
1587 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001588{
1589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1590 char qeec_pl[MLXSW_REG_QEEC_LEN];
1591
1592 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1593 next_index);
1594 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1595 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1596 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1597}
1598
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001599int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1600 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001601{
1602 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1603 char qtct_pl[MLXSW_REG_QTCT_LEN];
1604
1605 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1606 tclass);
1607 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1608}
1609
1610static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1611{
1612 int err, i;
1613
1614 /* Setup the elements hierarcy, so that each TC is linked to
1615 * one subgroup, which are all member in the same group.
1616 */
1617 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1618 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1619 0);
1620 if (err)
1621 return err;
1622 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1623 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1624 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1625 0, false, 0);
1626 if (err)
1627 return err;
1628 }
1629 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1630 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1631 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1632 false, 0);
1633 if (err)
1634 return err;
1635 }
1636
1637 /* Make sure the max shaper is disabled in all hierarcies that
1638 * support it.
1639 */
1640 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1641 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1642 MLXSW_REG_QEEC_MAS_DIS);
1643 if (err)
1644 return err;
1645 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1646 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1647 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1648 i, 0,
1649 MLXSW_REG_QEEC_MAS_DIS);
1650 if (err)
1651 return err;
1652 }
1653 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1654 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1655 MLXSW_REG_QEEC_HIERARCY_TC,
1656 i, i,
1657 MLXSW_REG_QEEC_MAS_DIS);
1658 if (err)
1659 return err;
1660 }
1661
1662 /* Map all priorities to traffic class 0. */
1663 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1664 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1665 if (err)
1666 return err;
1667 }
1668
1669 return 0;
1670}
1671
Ido Schimmel18f1e702016-02-26 17:32:31 +01001672static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1673 bool split, u8 module, u8 width)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001674{
Jiri Pirkoc4745502016-02-26 17:32:26 +01001675 struct devlink *devlink = priv_to_devlink(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001676 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirkoc4745502016-02-26 17:32:26 +01001677 struct devlink_port *devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001678 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001679 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001680 int err;
1681
1682 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1683 if (!dev)
1684 return -ENOMEM;
1685 mlxsw_sp_port = netdev_priv(dev);
1686 mlxsw_sp_port->dev = dev;
1687 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1688 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001689 mlxsw_sp_port->split = split;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001690 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1691 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1692 if (!mlxsw_sp_port->active_vlans) {
1693 err = -ENOMEM;
1694 goto err_port_active_vlans_alloc;
1695 }
Elad Razfc1273a2016-01-06 13:01:11 +01001696 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1697 if (!mlxsw_sp_port->untagged_vlans) {
1698 err = -ENOMEM;
1699 goto err_port_untagged_vlans_alloc;
1700 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001701 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001702
1703 mlxsw_sp_port->pcpu_stats =
1704 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1705 if (!mlxsw_sp_port->pcpu_stats) {
1706 err = -ENOMEM;
1707 goto err_alloc_stats;
1708 }
1709
1710 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1711 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1712
1713 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1714 if (err) {
1715 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1716 mlxsw_sp_port->local_port);
1717 goto err_dev_addr_init;
1718 }
1719
1720 netif_carrier_off(dev);
1721
1722 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1723 NETIF_F_HW_VLAN_CTAG_FILTER;
1724
1725 /* Each packet needs to have a Tx header (metadata) on top all other
1726 * headers.
1727 */
1728 dev->hard_header_len += MLXSW_TXHDR_LEN;
1729
Jiri Pirkoc4745502016-02-26 17:32:26 +01001730 devlink_port = &mlxsw_sp_port->devlink_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001731 if (mlxsw_sp_port->split)
1732 devlink_port_split_set(devlink_port, module);
Jiri Pirkoc4745502016-02-26 17:32:26 +01001733 err = devlink_port_register(devlink, devlink_port, local_port);
1734 if (err) {
1735 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register devlink port\n",
1736 mlxsw_sp_port->local_port);
1737 goto err_devlink_port_register;
1738 }
1739
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001740 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1741 if (err) {
1742 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1743 mlxsw_sp_port->local_port);
1744 goto err_port_system_port_mapping_set;
1745 }
1746
1747 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1748 if (err) {
1749 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1750 mlxsw_sp_port->local_port);
1751 goto err_port_swid_set;
1752 }
1753
Ido Schimmel18f1e702016-02-26 17:32:31 +01001754 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1755 if (err) {
1756 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1757 mlxsw_sp_port->local_port);
1758 goto err_port_speed_by_width_set;
1759 }
1760
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001761 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1762 if (err) {
1763 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1764 mlxsw_sp_port->local_port);
1765 goto err_port_mtu_set;
1766 }
1767
1768 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1769 if (err)
1770 goto err_port_admin_status_set;
1771
1772 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1773 if (err) {
1774 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1775 mlxsw_sp_port->local_port);
1776 goto err_port_buffers_init;
1777 }
1778
Ido Schimmel90183b92016-04-06 17:10:08 +02001779 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1780 if (err) {
1781 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1782 mlxsw_sp_port->local_port);
1783 goto err_port_ets_init;
1784 }
1785
Ido Schimmelf00817d2016-04-06 17:10:09 +02001786 /* ETS and buffers must be initialized before DCB. */
1787 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1788 if (err) {
1789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1790 mlxsw_sp_port->local_port);
1791 goto err_port_dcb_init;
1792 }
1793
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001794 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1795 err = register_netdev(dev);
1796 if (err) {
1797 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1798 mlxsw_sp_port->local_port);
1799 goto err_register_netdev;
1800 }
1801
Jiri Pirkoc4745502016-02-26 17:32:26 +01001802 devlink_port_type_eth_set(devlink_port, dev);
1803
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001804 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1805 if (err)
1806 goto err_port_vlan_init;
1807
1808 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1809 return 0;
1810
1811err_port_vlan_init:
1812 unregister_netdev(dev);
1813err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001814err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001815err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001816err_port_buffers_init:
1817err_port_admin_status_set:
1818err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001819err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001820err_port_swid_set:
1821err_port_system_port_mapping_set:
Jiri Pirkoc4745502016-02-26 17:32:26 +01001822 devlink_port_unregister(&mlxsw_sp_port->devlink_port);
1823err_devlink_port_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001824err_dev_addr_init:
1825 free_percpu(mlxsw_sp_port->pcpu_stats);
1826err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001827 kfree(mlxsw_sp_port->untagged_vlans);
1828err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001829 kfree(mlxsw_sp_port->active_vlans);
1830err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001831 free_netdev(dev);
1832 return err;
1833}
1834
Ido Schimmel18f1e702016-02-26 17:32:31 +01001835static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
1836 bool split, u8 module, u8 width, u8 lane)
1837{
1838 int err;
1839
1840 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1841 lane);
1842 if (err)
1843 return err;
1844
1845 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split, module,
1846 width);
1847 if (err)
1848 goto err_port_create;
1849
1850 return 0;
1851
1852err_port_create:
1853 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port);
1854 return err;
1855}
1856
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001857static void mlxsw_sp_port_vports_fini(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001858{
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001859 struct net_device *dev = mlxsw_sp_port->dev;
1860 struct mlxsw_sp_port *mlxsw_sp_vport, *tmp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001861
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001862 list_for_each_entry_safe(mlxsw_sp_vport, tmp,
1863 &mlxsw_sp_port->vports_list, vport.list) {
1864 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
1865
1866 /* vPorts created for VLAN devices should already be gone
1867 * by now, since we unregistered the port netdev.
1868 */
1869 WARN_ON(is_vlan_dev(mlxsw_sp_vport->dev));
1870 mlxsw_sp_port_kill_vid(dev, 0, vid);
1871 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001872}
1873
1874static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1875{
1876 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
Jiri Pirkoc4745502016-02-26 17:32:26 +01001877 struct devlink_port *devlink_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001878
1879 if (!mlxsw_sp_port)
1880 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001881 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirkoc4745502016-02-26 17:32:26 +01001882 devlink_port = &mlxsw_sp_port->devlink_port;
1883 devlink_port_type_clear(devlink_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001884 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001885 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Jiri Pirkoc4745502016-02-26 17:32:26 +01001886 devlink_port_unregister(devlink_port);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001887 mlxsw_sp_port_vports_fini(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001888 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001889 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1890 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001891 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001892 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001893 kfree(mlxsw_sp_port->active_vlans);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001894 free_netdev(mlxsw_sp_port->dev);
1895}
1896
1897static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1898{
1899 int i;
1900
1901 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1902 mlxsw_sp_port_remove(mlxsw_sp, i);
1903 kfree(mlxsw_sp->ports);
1904}
1905
1906static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1907{
1908 size_t alloc_size;
Ido Schimmel558c2d52016-02-26 17:32:29 +01001909 u8 module, width;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001910 int i;
1911 int err;
1912
1913 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1914 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1915 if (!mlxsw_sp->ports)
1916 return -ENOMEM;
1917
1918 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001919 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
1920 &width);
1921 if (err)
1922 goto err_port_module_info_get;
1923 if (!width)
1924 continue;
1925 mlxsw_sp->port_to_module[i] = module;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001926 err = __mlxsw_sp_port_create(mlxsw_sp, i, false, module, width);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001927 if (err)
1928 goto err_port_create;
1929 }
1930 return 0;
1931
1932err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001933err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001934 for (i--; i >= 1; i--)
1935 mlxsw_sp_port_remove(mlxsw_sp, i);
1936 kfree(mlxsw_sp->ports);
1937 return err;
1938}
1939
Ido Schimmel18f1e702016-02-26 17:32:31 +01001940static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1941{
1942 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1943
1944 return local_port - offset;
1945}
1946
1947static int mlxsw_sp_port_split(void *priv, u8 local_port, unsigned int count)
1948{
1949 struct mlxsw_sp *mlxsw_sp = priv;
1950 struct mlxsw_sp_port *mlxsw_sp_port;
1951 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1952 u8 module, cur_width, base_port;
1953 int i;
1954 int err;
1955
1956 mlxsw_sp_port = mlxsw_sp->ports[local_port];
1957 if (!mlxsw_sp_port) {
1958 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
1959 local_port);
1960 return -EINVAL;
1961 }
1962
1963 if (count != 2 && count != 4) {
1964 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
1965 return -EINVAL;
1966 }
1967
1968 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
1969 &cur_width);
1970 if (err) {
1971 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
1972 return err;
1973 }
1974
1975 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
1976 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
1977 return -EINVAL;
1978 }
1979
1980 /* Make sure we have enough slave (even) ports for the split. */
1981 if (count == 2) {
1982 base_port = local_port;
1983 if (mlxsw_sp->ports[base_port + 1]) {
1984 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1985 return -EINVAL;
1986 }
1987 } else {
1988 base_port = mlxsw_sp_cluster_base_port_get(local_port);
1989 if (mlxsw_sp->ports[base_port + 1] ||
1990 mlxsw_sp->ports[base_port + 3]) {
1991 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
1992 return -EINVAL;
1993 }
1994 }
1995
1996 for (i = 0; i < count; i++)
1997 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1998
1999 for (i = 0; i < count; i++) {
2000 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
2001 module, width, i * width);
2002 if (err) {
2003 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split port\n");
2004 goto err_port_create;
2005 }
2006 }
2007
2008 return 0;
2009
2010err_port_create:
2011 for (i--; i >= 0; i--)
2012 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2013 for (i = 0; i < count / 2; i++) {
2014 module = mlxsw_sp->port_to_module[base_port + i * 2];
2015 mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
2016 module, MLXSW_PORT_MODULE_MAX_WIDTH, 0);
2017 }
2018 return err;
2019}
2020
2021static int mlxsw_sp_port_unsplit(void *priv, u8 local_port)
2022{
2023 struct mlxsw_sp *mlxsw_sp = priv;
2024 struct mlxsw_sp_port *mlxsw_sp_port;
2025 u8 module, cur_width, base_port;
2026 unsigned int count;
2027 int i;
2028 int err;
2029
2030 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2031 if (!mlxsw_sp_port) {
2032 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2033 local_port);
2034 return -EINVAL;
2035 }
2036
2037 if (!mlxsw_sp_port->split) {
2038 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2039 return -EINVAL;
2040 }
2041
2042 err = mlxsw_sp_port_module_info_get(mlxsw_sp, local_port, &module,
2043 &cur_width);
2044 if (err) {
2045 netdev_err(mlxsw_sp_port->dev, "Failed to get port's width\n");
2046 return err;
2047 }
2048 count = cur_width == 1 ? 4 : 2;
2049
2050 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2051
2052 /* Determine which ports to remove. */
2053 if (count == 2 && local_port >= base_port + 2)
2054 base_port = base_port + 2;
2055
2056 for (i = 0; i < count; i++)
2057 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2058
2059 for (i = 0; i < count / 2; i++) {
2060 module = mlxsw_sp->port_to_module[base_port + i * 2];
2061 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * 2, false,
2062 module, MLXSW_PORT_MODULE_MAX_WIDTH,
2063 0);
2064 if (err)
2065 dev_err(mlxsw_sp->bus_info->dev, "Failed to reinstantiate port\n");
2066 }
2067
2068 return 0;
2069}
2070
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002071static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2072 char *pude_pl, void *priv)
2073{
2074 struct mlxsw_sp *mlxsw_sp = priv;
2075 struct mlxsw_sp_port *mlxsw_sp_port;
2076 enum mlxsw_reg_pude_oper_status status;
2077 u8 local_port;
2078
2079 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2080 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2081 if (!mlxsw_sp_port) {
2082 dev_warn(mlxsw_sp->bus_info->dev, "Port %d: Link event received for non-existent port\n",
2083 local_port);
2084 return;
2085 }
2086
2087 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2088 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2089 netdev_info(mlxsw_sp_port->dev, "link up\n");
2090 netif_carrier_on(mlxsw_sp_port->dev);
2091 } else {
2092 netdev_info(mlxsw_sp_port->dev, "link down\n");
2093 netif_carrier_off(mlxsw_sp_port->dev);
2094 }
2095}
2096
2097static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2098 .func = mlxsw_sp_pude_event_func,
2099 .trap_id = MLXSW_TRAP_ID_PUDE,
2100};
2101
2102static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2103 enum mlxsw_event_trap_id trap_id)
2104{
2105 struct mlxsw_event_listener *el;
2106 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2107 int err;
2108
2109 switch (trap_id) {
2110 case MLXSW_TRAP_ID_PUDE:
2111 el = &mlxsw_sp_pude_event;
2112 break;
2113 }
2114 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2115 if (err)
2116 return err;
2117
2118 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2119 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2120 if (err)
2121 goto err_event_trap_set;
2122
2123 return 0;
2124
2125err_event_trap_set:
2126 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2127 return err;
2128}
2129
2130static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2131 enum mlxsw_event_trap_id trap_id)
2132{
2133 struct mlxsw_event_listener *el;
2134
2135 switch (trap_id) {
2136 case MLXSW_TRAP_ID_PUDE:
2137 el = &mlxsw_sp_pude_event;
2138 break;
2139 }
2140 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2141}
2142
2143static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2144 void *priv)
2145{
2146 struct mlxsw_sp *mlxsw_sp = priv;
2147 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2148 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2149
2150 if (unlikely(!mlxsw_sp_port)) {
2151 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2152 local_port);
2153 return;
2154 }
2155
2156 skb->dev = mlxsw_sp_port->dev;
2157
2158 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2159 u64_stats_update_begin(&pcpu_stats->syncp);
2160 pcpu_stats->rx_packets++;
2161 pcpu_stats->rx_bytes += skb->len;
2162 u64_stats_update_end(&pcpu_stats->syncp);
2163
2164 skb->protocol = eth_type_trans(skb, skb->dev);
2165 netif_receive_skb(skb);
2166}
2167
2168static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2169 {
2170 .func = mlxsw_sp_rx_listener_func,
2171 .local_port = MLXSW_PORT_DONT_CARE,
2172 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2173 },
2174 /* Traps for specific L2 packet types, not trapped as FDB MC */
2175 {
2176 .func = mlxsw_sp_rx_listener_func,
2177 .local_port = MLXSW_PORT_DONT_CARE,
2178 .trap_id = MLXSW_TRAP_ID_STP,
2179 },
2180 {
2181 .func = mlxsw_sp_rx_listener_func,
2182 .local_port = MLXSW_PORT_DONT_CARE,
2183 .trap_id = MLXSW_TRAP_ID_LACP,
2184 },
2185 {
2186 .func = mlxsw_sp_rx_listener_func,
2187 .local_port = MLXSW_PORT_DONT_CARE,
2188 .trap_id = MLXSW_TRAP_ID_EAPOL,
2189 },
2190 {
2191 .func = mlxsw_sp_rx_listener_func,
2192 .local_port = MLXSW_PORT_DONT_CARE,
2193 .trap_id = MLXSW_TRAP_ID_LLDP,
2194 },
2195 {
2196 .func = mlxsw_sp_rx_listener_func,
2197 .local_port = MLXSW_PORT_DONT_CARE,
2198 .trap_id = MLXSW_TRAP_ID_MMRP,
2199 },
2200 {
2201 .func = mlxsw_sp_rx_listener_func,
2202 .local_port = MLXSW_PORT_DONT_CARE,
2203 .trap_id = MLXSW_TRAP_ID_MVRP,
2204 },
2205 {
2206 .func = mlxsw_sp_rx_listener_func,
2207 .local_port = MLXSW_PORT_DONT_CARE,
2208 .trap_id = MLXSW_TRAP_ID_RPVST,
2209 },
2210 {
2211 .func = mlxsw_sp_rx_listener_func,
2212 .local_port = MLXSW_PORT_DONT_CARE,
2213 .trap_id = MLXSW_TRAP_ID_DHCP,
2214 },
2215 {
2216 .func = mlxsw_sp_rx_listener_func,
2217 .local_port = MLXSW_PORT_DONT_CARE,
2218 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2219 },
2220 {
2221 .func = mlxsw_sp_rx_listener_func,
2222 .local_port = MLXSW_PORT_DONT_CARE,
2223 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2224 },
2225 {
2226 .func = mlxsw_sp_rx_listener_func,
2227 .local_port = MLXSW_PORT_DONT_CARE,
2228 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2229 },
2230 {
2231 .func = mlxsw_sp_rx_listener_func,
2232 .local_port = MLXSW_PORT_DONT_CARE,
2233 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2234 },
2235 {
2236 .func = mlxsw_sp_rx_listener_func,
2237 .local_port = MLXSW_PORT_DONT_CARE,
2238 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2239 },
2240};
2241
2242static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2243{
2244 char htgt_pl[MLXSW_REG_HTGT_LEN];
2245 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2246 int i;
2247 int err;
2248
2249 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2250 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2251 if (err)
2252 return err;
2253
2254 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2255 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2256 if (err)
2257 return err;
2258
2259 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2260 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2261 &mlxsw_sp_rx_listener[i],
2262 mlxsw_sp);
2263 if (err)
2264 goto err_rx_listener_register;
2265
2266 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2267 mlxsw_sp_rx_listener[i].trap_id);
2268 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2269 if (err)
2270 goto err_rx_trap_set;
2271 }
2272 return 0;
2273
2274err_rx_trap_set:
2275 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2276 &mlxsw_sp_rx_listener[i],
2277 mlxsw_sp);
2278err_rx_listener_register:
2279 for (i--; i >= 0; i--) {
2280 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2281 mlxsw_sp_rx_listener[i].trap_id);
2282 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2283
2284 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2285 &mlxsw_sp_rx_listener[i],
2286 mlxsw_sp);
2287 }
2288 return err;
2289}
2290
2291static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2292{
2293 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2294 int i;
2295
2296 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2297 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
2298 mlxsw_sp_rx_listener[i].trap_id);
2299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2300
2301 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2302 &mlxsw_sp_rx_listener[i],
2303 mlxsw_sp);
2304 }
2305}
2306
2307static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2308 enum mlxsw_reg_sfgc_type type,
2309 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2310{
2311 enum mlxsw_flood_table_type table_type;
2312 enum mlxsw_sp_flood_table flood_table;
2313 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2314
Ido Schimmel19ae6122015-12-15 16:03:39 +01002315 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002316 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002317 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002318 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002319
2320 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2321 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2322 else
2323 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324
2325 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2326 flood_table);
2327 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2328}
2329
2330static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2331{
2332 int type, err;
2333
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002334 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2335 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2336 continue;
2337
2338 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2339 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2340 if (err)
2341 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002342
2343 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2344 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2345 if (err)
2346 return err;
2347 }
2348
2349 return 0;
2350}
2351
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002352static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2353{
2354 char slcr_pl[MLXSW_REG_SLCR_LEN];
2355
2356 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2357 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2358 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2359 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2360 MLXSW_REG_SLCR_LAG_HASH_SIP |
2361 MLXSW_REG_SLCR_LAG_HASH_DIP |
2362 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2363 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2364 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2365 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2366}
2367
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002368static int mlxsw_sp_init(void *priv, struct mlxsw_core *mlxsw_core,
2369 const struct mlxsw_bus_info *mlxsw_bus_info)
2370{
2371 struct mlxsw_sp *mlxsw_sp = priv;
2372 int err;
2373
2374 mlxsw_sp->core = mlxsw_core;
2375 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002376 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002377 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002378 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002379
2380 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2381 if (err) {
2382 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2383 return err;
2384 }
2385
2386 err = mlxsw_sp_ports_create(mlxsw_sp);
2387 if (err) {
2388 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002389 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002390 }
2391
2392 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2393 if (err) {
2394 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
2395 goto err_event_register;
2396 }
2397
2398 err = mlxsw_sp_traps_init(mlxsw_sp);
2399 if (err) {
2400 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2401 goto err_rx_listener_register;
2402 }
2403
2404 err = mlxsw_sp_flood_init(mlxsw_sp);
2405 if (err) {
2406 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2407 goto err_flood_init;
2408 }
2409
2410 err = mlxsw_sp_buffers_init(mlxsw_sp);
2411 if (err) {
2412 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2413 goto err_buffers_init;
2414 }
2415
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002416 err = mlxsw_sp_lag_init(mlxsw_sp);
2417 if (err) {
2418 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2419 goto err_lag_init;
2420 }
2421
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2423 if (err) {
2424 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2425 goto err_switchdev_init;
2426 }
2427
2428 return 0;
2429
2430err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002431err_lag_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002432err_buffers_init:
2433err_flood_init:
2434 mlxsw_sp_traps_fini(mlxsw_sp);
2435err_rx_listener_register:
2436 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2437err_event_register:
2438 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002439 return err;
2440}
2441
2442static void mlxsw_sp_fini(void *priv)
2443{
2444 struct mlxsw_sp *mlxsw_sp = priv;
2445
2446 mlxsw_sp_switchdev_fini(mlxsw_sp);
2447 mlxsw_sp_traps_fini(mlxsw_sp);
2448 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2449 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002450}
2451
2452static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2453 .used_max_vepa_channels = 1,
2454 .max_vepa_channels = 0,
2455 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002456 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002457 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002458 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002459 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002460 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002461 .used_max_pgt = 1,
2462 .max_pgt = 0,
2463 .used_max_system_port = 1,
2464 .max_system_port = 64,
2465 .used_max_vlan_groups = 1,
2466 .max_vlan_groups = 127,
2467 .used_max_regions = 1,
2468 .max_regions = 400,
2469 .used_flood_tables = 1,
2470 .used_flood_mode = 1,
2471 .flood_mode = 3,
2472 .max_fid_offset_flood_tables = 2,
2473 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002474 .max_fid_flood_tables = 2,
2475 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002476 .used_max_ib_mc = 1,
2477 .max_ib_mc = 0,
2478 .used_max_pkey = 1,
2479 .max_pkey = 0,
2480 .swid_config = {
2481 {
2482 .used_type = 1,
2483 .type = MLXSW_PORT_SWID_TYPE_ETH,
2484 }
2485 },
2486};
2487
2488static struct mlxsw_driver mlxsw_sp_driver = {
2489 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2490 .owner = THIS_MODULE,
2491 .priv_size = sizeof(struct mlxsw_sp),
2492 .init = mlxsw_sp_init,
2493 .fini = mlxsw_sp_fini,
Ido Schimmel18f1e702016-02-26 17:32:31 +01002494 .port_split = mlxsw_sp_port_split,
2495 .port_unsplit = mlxsw_sp_port_unsplit,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002496 .txhdr_construct = mlxsw_sp_txhdr_construct,
2497 .txhdr_len = MLXSW_TXHDR_LEN,
2498 .profile = &mlxsw_sp_config_profile,
2499};
2500
Ido Schimmel039c49a2016-01-27 15:20:18 +01002501static int
2502mlxsw_sp_port_fdb_flush_by_port(const struct mlxsw_sp_port *mlxsw_sp_port)
2503{
2504 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2505 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2506
2507 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT);
2508 mlxsw_reg_sfdf_system_port_set(sfdf_pl, mlxsw_sp_port->local_port);
2509
2510 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2511}
2512
2513static int
2514mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2515 u16 fid)
2516{
2517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2518 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2519
2520 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2521 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2522 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2523 mlxsw_sp_port->local_port);
2524
2525 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2526}
2527
2528static int
2529mlxsw_sp_port_fdb_flush_by_lag_id(const struct mlxsw_sp_port *mlxsw_sp_port)
2530{
2531 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2532 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2533
2534 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG);
2535 mlxsw_reg_sfdf_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2536
2537 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2538}
2539
2540static int
2541mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2542 u16 fid)
2543{
2544 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2545 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2546
2547 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2548 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2549 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2550
2551 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2552}
2553
2554static int
2555__mlxsw_sp_port_fdb_flush(const struct mlxsw_sp_port *mlxsw_sp_port)
2556{
2557 int err, last_err = 0;
2558 u16 vid;
2559
2560 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2561 err = mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, vid);
2562 if (err)
2563 last_err = err;
2564 }
2565
2566 return last_err;
2567}
2568
2569static int
2570__mlxsw_sp_port_fdb_flush_lagged(const struct mlxsw_sp_port *mlxsw_sp_port)
2571{
2572 int err, last_err = 0;
2573 u16 vid;
2574
2575 for (vid = 1; vid < VLAN_N_VID - 1; vid++) {
2576 err = mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port, vid);
2577 if (err)
2578 last_err = err;
2579 }
2580
2581 return last_err;
2582}
2583
2584static int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port)
2585{
2586 if (!list_empty(&mlxsw_sp_port->vports_list))
2587 if (mlxsw_sp_port->lagged)
2588 return __mlxsw_sp_port_fdb_flush_lagged(mlxsw_sp_port);
2589 else
2590 return __mlxsw_sp_port_fdb_flush(mlxsw_sp_port);
2591 else
2592 if (mlxsw_sp_port->lagged)
2593 return mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port);
2594 else
2595 return mlxsw_sp_port_fdb_flush_by_port(mlxsw_sp_port);
2596}
2597
2598static int mlxsw_sp_vport_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_vport)
2599{
2600 u16 vfid = mlxsw_sp_vport_vfid_get(mlxsw_sp_vport);
2601 u16 fid = mlxsw_sp_vfid_to_fid(vfid);
2602
2603 if (mlxsw_sp_vport->lagged)
2604 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_vport,
2605 fid);
2606 else
2607 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_vport, fid);
2608}
2609
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002610static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2611{
2612 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2613}
2614
2615static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port)
2616{
2617 struct net_device *dev = mlxsw_sp_port->dev;
2618 int err;
2619
2620 /* When port is not bridged untagged packets are tagged with
2621 * PVID=VID=1, thereby creating an implicit VLAN interface in
2622 * the device. Remove it and let bridge code take care of its
2623 * own VLANs.
2624 */
2625 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002626 if (err)
2627 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002628
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002629 mlxsw_sp_port->learning = 1;
2630 mlxsw_sp_port->learning_sync = 1;
2631 mlxsw_sp_port->uc_flood = 1;
2632 mlxsw_sp_port->bridged = 1;
2633
2634 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002635}
2636
Ido Schimmel039c49a2016-01-27 15:20:18 +01002637static int mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2638 bool flush_fdb)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002639{
2640 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002641
Ido Schimmel039c49a2016-01-27 15:20:18 +01002642 if (flush_fdb && mlxsw_sp_port_fdb_flush(mlxsw_sp_port))
2643 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
2644
Ido Schimmel28a01d22016-02-18 11:30:02 +01002645 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2646
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002647 mlxsw_sp_port->learning = 0;
2648 mlxsw_sp_port->learning_sync = 0;
2649 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002650 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002651
2652 /* Add implicit VLAN interface in the device, so that untagged
2653 * packets will be classified to the default vFID.
2654 */
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002655 return mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002656}
2657
2658static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2659 struct net_device *br_dev)
2660{
2661 return !mlxsw_sp->master_bridge.dev ||
2662 mlxsw_sp->master_bridge.dev == br_dev;
2663}
2664
2665static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2666 struct net_device *br_dev)
2667{
2668 mlxsw_sp->master_bridge.dev = br_dev;
2669 mlxsw_sp->master_bridge.ref_count++;
2670}
2671
2672static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp,
2673 struct net_device *br_dev)
2674{
2675 if (--mlxsw_sp->master_bridge.ref_count == 0)
2676 mlxsw_sp->master_bridge.dev = NULL;
2677}
2678
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002679static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002680{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002681 char sldr_pl[MLXSW_REG_SLDR_LEN];
2682
2683 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2684 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2685}
2686
2687static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2688{
2689 char sldr_pl[MLXSW_REG_SLDR_LEN];
2690
2691 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2692 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2693}
2694
2695static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2696 u16 lag_id, u8 port_index)
2697{
2698 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2699 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2700
2701 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2702 lag_id, port_index);
2703 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2704}
2705
2706static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2707 u16 lag_id)
2708{
2709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2710 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2711
2712 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2713 lag_id);
2714 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2715}
2716
2717static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2718 u16 lag_id)
2719{
2720 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2721 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2722
2723 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2724 lag_id);
2725 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2726}
2727
2728static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2729 u16 lag_id)
2730{
2731 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2732 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2733
2734 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2735 lag_id);
2736 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2737}
2738
2739static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2740 struct net_device *lag_dev,
2741 u16 *p_lag_id)
2742{
2743 struct mlxsw_sp_upper *lag;
2744 int free_lag_id = -1;
2745 int i;
2746
2747 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2748 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2749 if (lag->ref_count) {
2750 if (lag->dev == lag_dev) {
2751 *p_lag_id = i;
2752 return 0;
2753 }
2754 } else if (free_lag_id < 0) {
2755 free_lag_id = i;
2756 }
2757 }
2758 if (free_lag_id < 0)
2759 return -EBUSY;
2760 *p_lag_id = free_lag_id;
2761 return 0;
2762}
2763
2764static bool
2765mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2766 struct net_device *lag_dev,
2767 struct netdev_lag_upper_info *lag_upper_info)
2768{
2769 u16 lag_id;
2770
2771 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2772 return false;
2773 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2774 return false;
2775 return true;
2776}
2777
2778static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2779 u16 lag_id, u8 *p_port_index)
2780{
2781 int i;
2782
2783 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2784 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2785 *p_port_index = i;
2786 return 0;
2787 }
2788 }
2789 return -EBUSY;
2790}
2791
2792static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2793 struct net_device *lag_dev)
2794{
2795 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2796 struct mlxsw_sp_upper *lag;
2797 u16 lag_id;
2798 u8 port_index;
2799 int err;
2800
2801 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2802 if (err)
2803 return err;
2804 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2805 if (!lag->ref_count) {
2806 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2807 if (err)
2808 return err;
2809 lag->dev = lag_dev;
2810 }
2811
2812 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
2813 if (err)
2814 return err;
2815 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
2816 if (err)
2817 goto err_col_port_add;
2818 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
2819 if (err)
2820 goto err_col_port_enable;
2821
2822 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
2823 mlxsw_sp_port->local_port);
2824 mlxsw_sp_port->lag_id = lag_id;
2825 mlxsw_sp_port->lagged = 1;
2826 lag->ref_count++;
2827 return 0;
2828
2829err_col_port_add:
2830 if (!lag->ref_count)
2831 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2832err_col_port_enable:
2833 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
2834 return err;
2835}
2836
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002837static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01002838 struct net_device *br_dev,
2839 bool flush_fdb);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002840
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002841static int mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
2842 struct net_device *lag_dev)
2843{
2844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002845 struct mlxsw_sp_port *mlxsw_sp_vport;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002846 struct mlxsw_sp_upper *lag;
2847 u16 lag_id = mlxsw_sp_port->lag_id;
2848 int err;
2849
2850 if (!mlxsw_sp_port->lagged)
2851 return 0;
2852 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2853 WARN_ON(lag->ref_count == 0);
2854
2855 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
2856 if (err)
2857 return err;
Dan Carpenter82a06422015-12-09 13:33:51 +03002858 err = mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002859 if (err)
2860 return err;
2861
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002862 /* In case we leave a LAG device that has bridges built on top,
2863 * then their teardown sequence is never issued and we need to
2864 * invoke the necessary cleanup routines ourselves.
2865 */
2866 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
2867 vport.list) {
2868 struct net_device *br_dev;
2869
2870 if (!mlxsw_sp_vport->bridged)
2871 continue;
2872
2873 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002874 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, false);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002875 }
2876
2877 if (mlxsw_sp_port->bridged) {
2878 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002879 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, false);
Ido Schimmel912b1c82016-03-07 15:15:29 +01002880 mlxsw_sp_master_bridge_dec(mlxsw_sp, NULL);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01002881 }
2882
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002883 if (lag->ref_count == 1) {
Ido Schimmel039c49a2016-01-27 15:20:18 +01002884 if (mlxsw_sp_port_fdb_flush_by_lag_id(mlxsw_sp_port))
2885 netdev_err(mlxsw_sp_port->dev, "Failed to flush FDB\n");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002886 err = mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
2887 if (err)
2888 return err;
2889 }
2890
2891 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
2892 mlxsw_sp_port->local_port);
2893 mlxsw_sp_port->lagged = 0;
2894 lag->ref_count--;
2895 return 0;
2896}
2897
Jiri Pirko74581202015-12-03 12:12:30 +01002898static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2899 u16 lag_id)
2900{
2901 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2902 char sldr_pl[MLXSW_REG_SLDR_LEN];
2903
2904 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
2905 mlxsw_sp_port->local_port);
2906 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2907}
2908
2909static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2910 u16 lag_id)
2911{
2912 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2913 char sldr_pl[MLXSW_REG_SLDR_LEN];
2914
2915 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
2916 mlxsw_sp_port->local_port);
2917 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2918}
2919
2920static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
2921 bool lag_tx_enabled)
2922{
2923 if (lag_tx_enabled)
2924 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
2925 mlxsw_sp_port->lag_id);
2926 else
2927 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
2928 mlxsw_sp_port->lag_id);
2929}
2930
2931static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
2932 struct netdev_lag_lower_state_info *info)
2933{
2934 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
2935}
2936
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002937static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
2938 struct net_device *vlan_dev)
2939{
2940 struct mlxsw_sp_port *mlxsw_sp_vport;
2941 u16 vid = vlan_dev_vlan_id(vlan_dev);
2942
2943 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2944 if (!mlxsw_sp_vport) {
2945 WARN_ON(!mlxsw_sp_vport);
2946 return -EINVAL;
2947 }
2948
2949 mlxsw_sp_vport->dev = vlan_dev;
2950
2951 return 0;
2952}
2953
2954static int mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
2955 struct net_device *vlan_dev)
2956{
2957 struct mlxsw_sp_port *mlxsw_sp_vport;
2958 u16 vid = vlan_dev_vlan_id(vlan_dev);
2959
2960 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
2961 if (!mlxsw_sp_vport) {
2962 WARN_ON(!mlxsw_sp_vport);
2963 return -EINVAL;
2964 }
2965
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002966 /* When removing a VLAN device while still bridged we should first
2967 * remove it from the bridge, as we receive the bridge's notification
2968 * when the vPort is already gone.
2969 */
2970 if (mlxsw_sp_vport->bridged) {
2971 struct net_device *br_dev;
2972
2973 br_dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002974 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport, br_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002975 }
2976
Ido Schimmel9589a7b52015-12-15 16:03:43 +01002977 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
2978
2979 return 0;
2980}
2981
Jiri Pirko74581202015-12-03 12:12:30 +01002982static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
2983 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002984{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002985 struct netdev_notifier_changeupper_info *info;
2986 struct mlxsw_sp_port *mlxsw_sp_port;
2987 struct net_device *upper_dev;
2988 struct mlxsw_sp *mlxsw_sp;
2989 int err;
2990
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002991 mlxsw_sp_port = netdev_priv(dev);
2992 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2993 info = ptr;
2994
2995 switch (event) {
2996 case NETDEV_PRECHANGEUPPER:
2997 upper_dev = info->upper_dev;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002998 if (!info->master || !info->linking)
2999 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003000 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003001 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003002 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
3003 return NOTIFY_BAD;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003004 if (netif_is_lag_master(upper_dev) &&
3005 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3006 info->upper_info))
3007 return NOTIFY_BAD;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003008 break;
3009 case NETDEV_CHANGEUPPER:
3010 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003011 if (is_vlan_dev(upper_dev)) {
3012 if (info->linking) {
3013 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3014 upper_dev);
3015 if (err) {
3016 netdev_err(dev, "Failed to link VLAN device\n");
3017 return NOTIFY_BAD;
3018 }
3019 } else {
3020 err = mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3021 upper_dev);
3022 if (err) {
3023 netdev_err(dev, "Failed to unlink VLAN device\n");
3024 return NOTIFY_BAD;
3025 }
3026 }
3027 } else if (netif_is_bridge_master(upper_dev)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003028 if (info->linking) {
3029 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port);
Ido Schimmel78124072016-01-04 10:42:24 +01003030 if (err) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003031 netdev_err(dev, "Failed to join bridge\n");
Ido Schimmel78124072016-01-04 10:42:24 +01003032 return NOTIFY_BAD;
3033 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003034 mlxsw_sp_master_bridge_inc(mlxsw_sp, upper_dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003035 } else {
Ido Schimmel039c49a2016-01-27 15:20:18 +01003036 err = mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
3037 true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003038 mlxsw_sp_master_bridge_dec(mlxsw_sp, upper_dev);
Ido Schimmel78124072016-01-04 10:42:24 +01003039 if (err) {
3040 netdev_err(dev, "Failed to leave bridge\n");
3041 return NOTIFY_BAD;
3042 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003043 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003044 } else if (netif_is_lag_master(upper_dev)) {
3045 if (info->linking) {
3046 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3047 upper_dev);
3048 if (err) {
3049 netdev_err(dev, "Failed to join link aggregation\n");
3050 return NOTIFY_BAD;
3051 }
3052 } else {
3053 err = mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3054 upper_dev);
3055 if (err) {
3056 netdev_err(dev, "Failed to leave link aggregation\n");
3057 return NOTIFY_BAD;
3058 }
3059 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003060 }
3061 break;
3062 }
3063
3064 return NOTIFY_DONE;
3065}
3066
Jiri Pirko74581202015-12-03 12:12:30 +01003067static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3068 unsigned long event, void *ptr)
3069{
3070 struct netdev_notifier_changelowerstate_info *info;
3071 struct mlxsw_sp_port *mlxsw_sp_port;
3072 int err;
3073
3074 mlxsw_sp_port = netdev_priv(dev);
3075 info = ptr;
3076
3077 switch (event) {
3078 case NETDEV_CHANGELOWERSTATE:
3079 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3080 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3081 info->lower_state_info);
3082 if (err)
3083 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3084 }
3085 break;
3086 }
3087
3088 return NOTIFY_DONE;
3089}
3090
3091static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3092 unsigned long event, void *ptr)
3093{
3094 switch (event) {
3095 case NETDEV_PRECHANGEUPPER:
3096 case NETDEV_CHANGEUPPER:
3097 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3098 case NETDEV_CHANGELOWERSTATE:
3099 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3100 }
3101
3102 return NOTIFY_DONE;
3103}
3104
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003105static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3106 unsigned long event, void *ptr)
3107{
3108 struct net_device *dev;
3109 struct list_head *iter;
3110 int ret;
3111
3112 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3113 if (mlxsw_sp_port_dev_check(dev)) {
3114 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3115 if (ret == NOTIFY_BAD)
3116 return ret;
3117 }
3118 }
3119
3120 return NOTIFY_DONE;
3121}
3122
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003123static struct mlxsw_sp_vfid *
3124mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3125 const struct net_device *br_dev)
3126{
3127 struct mlxsw_sp_vfid *vfid;
3128
3129 list_for_each_entry(vfid, &mlxsw_sp->br_vfids.list, list) {
3130 if (vfid->br_dev == br_dev)
3131 return vfid;
3132 }
3133
3134 return NULL;
3135}
3136
3137static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3138{
3139 return vfid - MLXSW_SP_VFID_PORT_MAX;
3140}
3141
3142static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3143{
3144 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3145}
3146
3147static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3148{
3149 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3150 MLXSW_SP_VFID_BR_MAX);
3151}
3152
3153static struct mlxsw_sp_vfid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3154 struct net_device *br_dev)
3155{
3156 struct device *dev = mlxsw_sp->bus_info->dev;
3157 struct mlxsw_sp_vfid *vfid;
3158 u16 n_vfid;
3159 int err;
3160
3161 n_vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3162 if (n_vfid == MLXSW_SP_VFID_MAX) {
3163 dev_err(dev, "No available vFIDs\n");
3164 return ERR_PTR(-ERANGE);
3165 }
3166
3167 err = __mlxsw_sp_vfid_create(mlxsw_sp, n_vfid);
3168 if (err) {
3169 dev_err(dev, "Failed to create vFID=%d\n", n_vfid);
3170 return ERR_PTR(err);
3171 }
3172
3173 vfid = kzalloc(sizeof(*vfid), GFP_KERNEL);
3174 if (!vfid)
3175 goto err_allocate_vfid;
3176
3177 vfid->vfid = n_vfid;
3178 vfid->br_dev = br_dev;
3179
3180 list_add(&vfid->list, &mlxsw_sp->br_vfids.list);
3181 set_bit(mlxsw_sp_vfid_to_br_vfid(n_vfid), mlxsw_sp->br_vfids.mapped);
3182
3183 return vfid;
3184
3185err_allocate_vfid:
3186 __mlxsw_sp_vfid_destroy(mlxsw_sp, n_vfid);
3187 return ERR_PTR(-ENOMEM);
3188}
3189
3190static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
3191 struct mlxsw_sp_vfid *vfid)
3192{
3193 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid->vfid);
3194
3195 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
3196 list_del(&vfid->list);
3197
3198 __mlxsw_sp_vfid_destroy(mlxsw_sp, vfid->vfid);
3199
3200 kfree(vfid);
3201}
3202
3203static int mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003204 struct net_device *br_dev,
3205 bool flush_fdb)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003206{
3207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3208 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3209 struct net_device *dev = mlxsw_sp_vport->dev;
3210 struct mlxsw_sp_vfid *vfid, *new_vfid;
3211 int err;
3212
3213 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3214 if (!vfid) {
3215 WARN_ON(!vfid);
3216 return -EINVAL;
3217 }
3218
3219 /* We need a vFID to go back to after leaving the bridge's vFID. */
3220 new_vfid = mlxsw_sp_vfid_find(mlxsw_sp, vid);
3221 if (!new_vfid) {
3222 new_vfid = mlxsw_sp_vfid_create(mlxsw_sp, vid);
3223 if (IS_ERR(new_vfid)) {
3224 netdev_err(dev, "Failed to create vFID for VID=%d\n",
3225 vid);
3226 return PTR_ERR(new_vfid);
3227 }
3228 }
3229
3230 /* Invalidate existing {Port, VID} to vFID mapping and create a new
3231 * one for the new vFID.
3232 */
3233 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3234 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3235 false,
3236 mlxsw_sp_vfid_to_fid(vfid->vfid),
3237 vid);
3238 if (err) {
3239 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3240 vfid->vfid);
3241 goto err_port_vid_to_fid_invalidate;
3242 }
3243
3244 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3245 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3246 true,
3247 mlxsw_sp_vfid_to_fid(new_vfid->vfid),
3248 vid);
3249 if (err) {
3250 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3251 new_vfid->vfid);
3252 goto err_port_vid_to_fid_validate;
3253 }
3254
3255 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3256 if (err) {
3257 netdev_err(dev, "Failed to disable learning\n");
3258 goto err_port_vid_learning_set;
3259 }
3260
3261 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false,
3262 false);
3263 if (err) {
3264 netdev_err(dev, "Failed clear to clear flooding\n");
3265 goto err_vport_flood_set;
3266 }
3267
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003268 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3269 MLXSW_REG_SPMS_STATE_FORWARDING);
3270 if (err) {
3271 netdev_err(dev, "Failed to set STP state\n");
3272 goto err_port_stp_state_set;
3273 }
3274
Ido Schimmel039c49a2016-01-27 15:20:18 +01003275 if (flush_fdb && mlxsw_sp_vport_fdb_flush(mlxsw_sp_vport))
3276 netdev_err(dev, "Failed to flush FDB\n");
3277
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003278 /* Switch between the vFIDs and destroy the old one if needed. */
3279 new_vfid->nr_vports++;
3280 mlxsw_sp_vport->vport.vfid = new_vfid;
3281 vfid->nr_vports--;
3282 if (!vfid->nr_vports)
3283 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3284
3285 mlxsw_sp_vport->learning = 0;
3286 mlxsw_sp_vport->learning_sync = 0;
3287 mlxsw_sp_vport->uc_flood = 0;
3288 mlxsw_sp_vport->bridged = 0;
3289
3290 return 0;
3291
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003292err_port_stp_state_set:
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003293err_vport_flood_set:
3294err_port_vid_learning_set:
3295err_port_vid_to_fid_validate:
3296err_port_vid_to_fid_invalidate:
3297 /* Rollback vFID only if new. */
3298 if (!new_vfid->nr_vports)
3299 mlxsw_sp_vfid_destroy(mlxsw_sp, new_vfid);
3300 return err;
3301}
3302
3303static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3304 struct net_device *br_dev)
3305{
3306 struct mlxsw_sp_vfid *old_vfid = mlxsw_sp_vport->vport.vfid;
3307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_vport->mlxsw_sp;
3308 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3309 struct net_device *dev = mlxsw_sp_vport->dev;
3310 struct mlxsw_sp_vfid *vfid;
3311 int err;
3312
3313 vfid = mlxsw_sp_br_vfid_find(mlxsw_sp, br_dev);
3314 if (!vfid) {
3315 vfid = mlxsw_sp_br_vfid_create(mlxsw_sp, br_dev);
3316 if (IS_ERR(vfid)) {
3317 netdev_err(dev, "Failed to create bridge vFID\n");
3318 return PTR_ERR(vfid);
3319 }
3320 }
3321
3322 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, true, false);
3323 if (err) {
3324 netdev_err(dev, "Failed to setup flooding for vFID=%d\n",
3325 vfid->vfid);
3326 goto err_port_flood_set;
3327 }
3328
3329 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3330 if (err) {
3331 netdev_err(dev, "Failed to enable learning\n");
3332 goto err_port_vid_learning_set;
3333 }
3334
3335 /* We need to invalidate existing {Port, VID} to vFID mapping and
3336 * create a new one for the bridge's vFID.
3337 */
3338 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3339 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3340 false,
3341 mlxsw_sp_vfid_to_fid(old_vfid->vfid),
3342 vid);
3343 if (err) {
3344 netdev_err(dev, "Failed to invalidate {Port, VID} to vFID=%d mapping\n",
3345 old_vfid->vfid);
3346 goto err_port_vid_to_fid_invalidate;
3347 }
3348
3349 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3350 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
3351 true,
3352 mlxsw_sp_vfid_to_fid(vfid->vfid),
3353 vid);
3354 if (err) {
3355 netdev_err(dev, "Failed to map {Port, VID} to vFID=%d\n",
3356 vfid->vfid);
3357 goto err_port_vid_to_fid_validate;
3358 }
3359
3360 /* Switch between the vFIDs and destroy the old one if needed. */
3361 vfid->nr_vports++;
3362 mlxsw_sp_vport->vport.vfid = vfid;
3363 old_vfid->nr_vports--;
3364 if (!old_vfid->nr_vports)
3365 mlxsw_sp_vfid_destroy(mlxsw_sp, old_vfid);
3366
3367 mlxsw_sp_vport->learning = 1;
3368 mlxsw_sp_vport->learning_sync = 1;
3369 mlxsw_sp_vport->uc_flood = 1;
3370 mlxsw_sp_vport->bridged = 1;
3371
3372 return 0;
3373
3374err_port_vid_to_fid_validate:
3375 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport,
3376 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, false,
3377 mlxsw_sp_vfid_to_fid(old_vfid->vfid), vid);
3378err_port_vid_to_fid_invalidate:
3379 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3380err_port_vid_learning_set:
3381 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, vfid->vfid, false, false);
3382err_port_flood_set:
3383 if (!vfid->nr_vports)
3384 mlxsw_sp_br_vfid_destroy(mlxsw_sp, vfid);
3385 return err;
3386}
3387
3388static bool
3389mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3390 const struct net_device *br_dev)
3391{
3392 struct mlxsw_sp_port *mlxsw_sp_vport;
3393
3394 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3395 vport.list) {
3396 if (mlxsw_sp_vport_br_get(mlxsw_sp_vport) == br_dev)
3397 return false;
3398 }
3399
3400 return true;
3401}
3402
3403static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3404 unsigned long event, void *ptr,
3405 u16 vid)
3406{
3407 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3408 struct netdev_notifier_changeupper_info *info = ptr;
3409 struct mlxsw_sp_port *mlxsw_sp_vport;
3410 struct net_device *upper_dev;
3411 int err;
3412
3413 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3414
3415 switch (event) {
3416 case NETDEV_PRECHANGEUPPER:
3417 upper_dev = info->upper_dev;
3418 if (!info->master || !info->linking)
3419 break;
3420 if (!netif_is_bridge_master(upper_dev))
3421 return NOTIFY_BAD;
3422 /* We can't have multiple VLAN interfaces configured on
3423 * the same port and being members in the same bridge.
3424 */
3425 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3426 upper_dev))
3427 return NOTIFY_BAD;
3428 break;
3429 case NETDEV_CHANGEUPPER:
3430 upper_dev = info->upper_dev;
3431 if (!info->master)
3432 break;
3433 if (info->linking) {
3434 if (!mlxsw_sp_vport) {
3435 WARN_ON(!mlxsw_sp_vport);
3436 return NOTIFY_BAD;
3437 }
3438 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3439 upper_dev);
3440 if (err) {
3441 netdev_err(dev, "Failed to join bridge\n");
3442 return NOTIFY_BAD;
3443 }
3444 } else {
3445 /* We ignore bridge's unlinking notifications if vPort
3446 * is gone, since we already left the bridge when the
3447 * VLAN device was unlinked from the real device.
3448 */
3449 if (!mlxsw_sp_vport)
3450 return NOTIFY_DONE;
3451 err = mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003452 upper_dev, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003453 if (err) {
3454 netdev_err(dev, "Failed to leave bridge\n");
3455 return NOTIFY_BAD;
3456 }
3457 }
3458 }
3459
3460 return NOTIFY_DONE;
3461}
3462
Ido Schimmel272c4472015-12-15 16:03:47 +01003463static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3464 unsigned long event, void *ptr,
3465 u16 vid)
3466{
3467 struct net_device *dev;
3468 struct list_head *iter;
3469 int ret;
3470
3471 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3472 if (mlxsw_sp_port_dev_check(dev)) {
3473 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3474 vid);
3475 if (ret == NOTIFY_BAD)
3476 return ret;
3477 }
3478 }
3479
3480 return NOTIFY_DONE;
3481}
3482
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003483static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3484 unsigned long event, void *ptr)
3485{
3486 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3487 u16 vid = vlan_dev_vlan_id(vlan_dev);
3488
Ido Schimmel272c4472015-12-15 16:03:47 +01003489 if (mlxsw_sp_port_dev_check(real_dev))
3490 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3491 vid);
3492 else if (netif_is_lag_master(real_dev))
3493 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3494 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003495
Ido Schimmel272c4472015-12-15 16:03:47 +01003496 return NOTIFY_DONE;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003497}
3498
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003499static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3500 unsigned long event, void *ptr)
3501{
3502 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3503
3504 if (mlxsw_sp_port_dev_check(dev))
3505 return mlxsw_sp_netdevice_port_event(dev, event, ptr);
3506
3507 if (netif_is_lag_master(dev))
3508 return mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3509
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003510 if (is_vlan_dev(dev))
3511 return mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
3512
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003513 return NOTIFY_DONE;
3514}
3515
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003516static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3517 .notifier_call = mlxsw_sp_netdevice_event,
3518};
3519
3520static int __init mlxsw_sp_module_init(void)
3521{
3522 int err;
3523
3524 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3525 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3526 if (err)
3527 goto err_core_driver_register;
3528 return 0;
3529
3530err_core_driver_register:
3531 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3532 return err;
3533}
3534
3535static void __exit mlxsw_sp_module_exit(void)
3536{
3537 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3538 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3539}
3540
3541module_init(mlxsw_sp_module_init);
3542module_exit(mlxsw_sp_module_exit);
3543
3544MODULE_LICENSE("Dual BSD/GPL");
3545MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3546MODULE_DESCRIPTION("Mellanox Spectrum driver");
3547MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);