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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _S2IO_H
14#define _S2IO_H
15
16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20
21#ifndef BOOL
22#define BOOL int
23#endif
24
25#ifndef TRUE
26#define TRUE 1
27#define FALSE 0
28#endif
29
30#undef SUCCESS
31#define SUCCESS 0
32#define FAILURE -1
Sivakumar Subramani19a60522007-01-31 13:30:49 -050033#define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
34#define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -050035#define S2IO_BIT_RESET 1
36#define S2IO_BIT_SET 2
Ananda Rajubd1034f2006-04-21 19:20:22 -040037#define CHECKBIT(value, nbit) (value & (1 << nbit))
38
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070039/* Maximum time to flicker LED when asked to identify NIC using ethtool */
40#define MAX_FLICKER_TIME 60000 /* 60 Secs */
41
Linus Torvalds1da177e2005-04-16 15:20:36 -070042/* Maximum outstanding splits to be configured into xena. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050043enum {
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 XENA_ONE_SPLIT_TRANSACTION = 0,
45 XENA_TWO_SPLIT_TRANSACTION = 1,
46 XENA_THREE_SPLIT_TRANSACTION = 2,
47 XENA_FOUR_SPLIT_TRANSACTION = 3,
48 XENA_EIGHT_SPLIT_TRANSACTION = 4,
49 XENA_TWELVE_SPLIT_TRANSACTION = 5,
50 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
51 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050052};
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
54
55/* OS concerned variables and constants */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070056#define WATCH_DOG_TIMEOUT 15*HZ
57#define EFILL 0x1234
58#define ALIGN_SIZE 127
59#define PCIX_COMMAND_REGISTER 0x62
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61/*
62 * Debug related variables.
63 */
64/* different debug levels. */
65#define ERR_DBG 0
66#define INIT_DBG 1
67#define INFO_DBG 2
68#define TX_DBG 3
69#define INTR_DBG 4
70
71/* Global variable that defines the present debug level of the driver. */
Adrian Bunk26df54b2006-01-14 03:09:40 +010072static int debug_level = ERR_DBG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070073
74/* DEBUG message print. */
75#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
76
77/* Protocol assist features of the NIC */
78#define L3_CKSUM_OK 0xFFFF
79#define L4_CKSUM_OK 0xFFFF
80#define S2IO_JUMBO_SIZE 9600
81
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070082/* Driver statistics maintained by driver */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050083struct swStat {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070084 unsigned long long single_ecc_errs;
85 unsigned long long double_ecc_errs;
Ananda Rajubd1034f2006-04-21 19:20:22 -040086 unsigned long long parity_err_cnt;
87 unsigned long long serious_err_cnt;
88 unsigned long long soft_reset_cnt;
89 unsigned long long fifo_full_cnt;
90 unsigned long long ring_full_cnt;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -050091 /* LRO statistics */
92 unsigned long long clubbed_frms_cnt;
93 unsigned long long sending_both;
94 unsigned long long outof_sequence_pkts;
95 unsigned long long flush_max_pkts;
96 unsigned long long sum_avg_pkts_aggregated;
97 unsigned long long num_aggregations;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -050098};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070099
Ananda Rajubd1034f2006-04-21 19:20:22 -0400100/* Xpak releated alarm and warnings */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500101struct xpakStat {
Ananda Rajubd1034f2006-04-21 19:20:22 -0400102 u64 alarm_transceiver_temp_high;
103 u64 alarm_transceiver_temp_low;
104 u64 alarm_laser_bias_current_high;
105 u64 alarm_laser_bias_current_low;
106 u64 alarm_laser_output_power_high;
107 u64 alarm_laser_output_power_low;
108 u64 warn_transceiver_temp_high;
109 u64 warn_transceiver_temp_low;
110 u64 warn_laser_bias_current_high;
111 u64 warn_laser_bias_current_low;
112 u64 warn_laser_output_power_high;
113 u64 warn_laser_output_power_low;
114 u64 xpak_regs_stat;
115 u32 xpak_timer_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500116};
Ananda Rajubd1034f2006-04-21 19:20:22 -0400117
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119/* The statistics block of Xena */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500120struct stat_block {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121/* Tx MAC statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400122 __le32 tmac_data_octets;
123 __le32 tmac_frms;
124 __le64 tmac_drop_frms;
125 __le32 tmac_bcst_frms;
126 __le32 tmac_mcst_frms;
127 __le64 tmac_pause_ctrl_frms;
128 __le32 tmac_ucst_frms;
129 __le32 tmac_ttl_octets;
130 __le32 tmac_any_err_frms;
131 __le32 tmac_nucst_frms;
132 __le64 tmac_ttl_less_fb_octets;
133 __le64 tmac_vld_ip_octets;
134 __le32 tmac_drop_ip;
135 __le32 tmac_vld_ip;
136 __le32 tmac_rst_tcp;
137 __le32 tmac_icmp;
138 __le64 tmac_tcp;
139 __le32 reserved_0;
140 __le32 tmac_udp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142/* Rx MAC Statistics counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400143 __le32 rmac_data_octets;
144 __le32 rmac_vld_frms;
145 __le64 rmac_fcs_err_frms;
146 __le64 rmac_drop_frms;
147 __le32 rmac_vld_bcst_frms;
148 __le32 rmac_vld_mcst_frms;
149 __le32 rmac_out_rng_len_err_frms;
150 __le32 rmac_in_rng_len_err_frms;
151 __le64 rmac_long_frms;
152 __le64 rmac_pause_ctrl_frms;
153 __le64 rmac_unsup_ctrl_frms;
154 __le32 rmac_accepted_ucst_frms;
155 __le32 rmac_ttl_octets;
156 __le32 rmac_discarded_frms;
157 __le32 rmac_accepted_nucst_frms;
158 __le32 reserved_1;
159 __le32 rmac_drop_events;
160 __le64 rmac_ttl_less_fb_octets;
161 __le64 rmac_ttl_frms;
162 __le64 reserved_2;
163 __le32 rmac_usized_frms;
164 __le32 reserved_3;
165 __le32 rmac_frag_frms;
166 __le32 rmac_osized_frms;
167 __le32 reserved_4;
168 __le32 rmac_jabber_frms;
169 __le64 rmac_ttl_64_frms;
170 __le64 rmac_ttl_65_127_frms;
171 __le64 reserved_5;
172 __le64 rmac_ttl_128_255_frms;
173 __le64 rmac_ttl_256_511_frms;
174 __le64 reserved_6;
175 __le64 rmac_ttl_512_1023_frms;
176 __le64 rmac_ttl_1024_1518_frms;
177 __le32 rmac_ip;
178 __le32 reserved_7;
179 __le64 rmac_ip_octets;
180 __le32 rmac_drop_ip;
181 __le32 rmac_hdr_err_ip;
182 __le32 reserved_8;
183 __le32 rmac_icmp;
184 __le64 rmac_tcp;
185 __le32 rmac_err_drp_udp;
186 __le32 rmac_udp;
187 __le64 rmac_xgmii_err_sym;
188 __le64 rmac_frms_q0;
189 __le64 rmac_frms_q1;
190 __le64 rmac_frms_q2;
191 __le64 rmac_frms_q3;
192 __le64 rmac_frms_q4;
193 __le64 rmac_frms_q5;
194 __le64 rmac_frms_q6;
195 __le64 rmac_frms_q7;
196 __le16 rmac_full_q3;
197 __le16 rmac_full_q2;
198 __le16 rmac_full_q1;
199 __le16 rmac_full_q0;
200 __le16 rmac_full_q7;
201 __le16 rmac_full_q6;
202 __le16 rmac_full_q5;
203 __le16 rmac_full_q4;
204 __le32 reserved_9;
205 __le32 rmac_pause_cnt;
206 __le64 rmac_xgmii_data_err_cnt;
207 __le64 rmac_xgmii_ctrl_err_cnt;
208 __le32 rmac_err_tcp;
209 __le32 rmac_accepted_ip;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210
211/* PCI/PCI-X Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400212 __le32 new_rd_req_cnt;
213 __le32 rd_req_cnt;
214 __le32 rd_rtry_cnt;
215 __le32 new_rd_req_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217/* PCI/PCI-X Write/Read transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400218 __le32 wr_req_cnt;
219 __le32 wr_rtry_rd_ack_cnt;
220 __le32 new_wr_req_rtry_cnt;
221 __le32 new_wr_req_cnt;
222 __le32 wr_disc_cnt;
223 __le32 wr_rtry_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225/* PCI/PCI-X Write / DMA Transaction statistics. */
Al Viro107c3a72006-08-13 15:38:04 -0400226 __le32 txp_wr_cnt;
227 __le32 rd_rtry_wr_ack_cnt;
228 __le32 txd_wr_cnt;
229 __le32 txd_rd_cnt;
230 __le32 rxd_wr_cnt;
231 __le32 rxd_rd_cnt;
232 __le32 rxf_wr_cnt;
233 __le32 txf_rd_cnt;
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700234
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700235/* Tx MAC statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400236 __le32 tmac_data_octets_oflow;
237 __le32 tmac_frms_oflow;
238 __le32 tmac_bcst_frms_oflow;
239 __le32 tmac_mcst_frms_oflow;
240 __le32 tmac_ucst_frms_oflow;
241 __le32 tmac_ttl_octets_oflow;
242 __le32 tmac_any_err_frms_oflow;
243 __le32 tmac_nucst_frms_oflow;
244 __le64 tmac_vlan_frms;
245 __le32 tmac_drop_ip_oflow;
246 __le32 tmac_vld_ip_oflow;
247 __le32 tmac_rst_tcp_oflow;
248 __le32 tmac_icmp_oflow;
249 __le32 tpa_unknown_protocol;
250 __le32 tmac_udp_oflow;
251 __le32 reserved_10;
252 __le32 tpa_parse_failure;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700253
254/* Rx MAC Statistics overflow counters. */
Al Viro107c3a72006-08-13 15:38:04 -0400255 __le32 rmac_data_octets_oflow;
256 __le32 rmac_vld_frms_oflow;
257 __le32 rmac_vld_bcst_frms_oflow;
258 __le32 rmac_vld_mcst_frms_oflow;
259 __le32 rmac_accepted_ucst_frms_oflow;
260 __le32 rmac_ttl_octets_oflow;
261 __le32 rmac_discarded_frms_oflow;
262 __le32 rmac_accepted_nucst_frms_oflow;
263 __le32 rmac_usized_frms_oflow;
264 __le32 rmac_drop_events_oflow;
265 __le32 rmac_frag_frms_oflow;
266 __le32 rmac_osized_frms_oflow;
267 __le32 rmac_ip_oflow;
268 __le32 rmac_jabber_frms_oflow;
269 __le32 rmac_icmp_oflow;
270 __le32 rmac_drop_ip_oflow;
271 __le32 rmac_err_drp_udp_oflow;
272 __le32 rmac_udp_oflow;
273 __le32 reserved_11;
274 __le32 rmac_pause_cnt_oflow;
275 __le64 rmac_ttl_1519_4095_frms;
276 __le64 rmac_ttl_4096_8191_frms;
277 __le64 rmac_ttl_8192_max_frms;
278 __le64 rmac_ttl_gt_max_frms;
279 __le64 rmac_osized_alt_frms;
280 __le64 rmac_jabber_alt_frms;
281 __le64 rmac_gt_max_alt_frms;
282 __le64 rmac_vlan_frms;
283 __le32 rmac_len_discard;
284 __le32 rmac_fcs_discard;
285 __le32 rmac_pf_discard;
286 __le32 rmac_da_discard;
287 __le32 rmac_red_discard;
288 __le32 rmac_rts_discard;
289 __le32 reserved_12;
290 __le32 rmac_ingm_full_discard;
291 __le32 reserved_13;
292 __le32 rmac_accepted_ip_oflow;
293 __le32 reserved_14;
294 __le32 link_fault_cnt;
Ananda Rajubd1034f2006-04-21 19:20:22 -0400295 u8 buffer[20];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500296 struct swStat sw_stat;
297 struct xpakStat xpak_stat;
298};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700300/*
301 * Structures representing different init time configuration
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 * parameters of the NIC.
303 */
304
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700305#define MAX_TX_FIFOS 8
306#define MAX_RX_RINGS 8
307
308/* FIFO mappings for all possible number of fifos configured */
Adrian Bunk26df54b2006-01-14 03:09:40 +0100309static int fifo_map[][MAX_TX_FIFOS] = {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700310 {0, 0, 0, 0, 0, 0, 0, 0},
311 {0, 0, 0, 0, 1, 1, 1, 1},
312 {0, 0, 0, 1, 1, 1, 2, 2},
313 {0, 0, 1, 1, 2, 2, 3, 3},
314 {0, 0, 1, 1, 2, 2, 3, 4},
315 {0, 0, 1, 1, 2, 3, 4, 5},
316 {0, 0, 1, 2, 3, 4, 5, 6},
317 {0, 1, 2, 3, 4, 5, 6, 7},
318};
319
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320/* Maintains Per FIFO related information. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500321struct tx_fifo_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700322#define MAX_AVAILABLE_TXDS 8192
323 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
324/* Priority definition */
325#define TX_FIFO_PRI_0 0 /*Highest */
326#define TX_FIFO_PRI_1 1
327#define TX_FIFO_PRI_2 2
328#define TX_FIFO_PRI_3 3
329#define TX_FIFO_PRI_4 4
330#define TX_FIFO_PRI_5 5
331#define TX_FIFO_PRI_6 6
332#define TX_FIFO_PRI_7 7 /*lowest */
333 u8 fifo_priority; /* specifies pointer level for FIFO */
334 /* user should not set twos fifos with same pri */
335 u8 f_no_snoop;
336#define NO_SNOOP_TXD 0x01
337#define NO_SNOOP_TXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500338};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339
340
341/* Maintains per Ring related information */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500342struct rx_ring_config {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 u32 num_rxd; /*No of RxDs per Rx Ring */
344#define RX_RING_PRI_0 0 /* highest */
345#define RX_RING_PRI_1 1
346#define RX_RING_PRI_2 2
347#define RX_RING_PRI_3 3
348#define RX_RING_PRI_4 4
349#define RX_RING_PRI_5 5
350#define RX_RING_PRI_6 6
351#define RX_RING_PRI_7 7 /* lowest */
352
353 u8 ring_priority; /*Specifies service priority of ring */
354 /* OSM should not set any two rings with same priority */
355 u8 ring_org; /*Organization of ring */
356#define RING_ORG_BUFF1 0x01
357#define RX_RING_ORG_BUFF3 0x03
358#define RX_RING_ORG_BUFF5 0x05
359
360 u8 f_no_snoop;
361#define NO_SNOOP_RXD 0x01
362#define NO_SNOOP_RXD_BUFFER 0x02
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500363};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700365/* This structure provides contains values of the tunable parameters
366 * of the H/W
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 */
368struct config_param {
369/* Tx Side */
370 u32 tx_fifo_num; /*Number of Tx FIFOs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700372 u8 fifo_mapping[MAX_TX_FIFOS];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500373 struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
375 u64 tx_intr_type;
376 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
377
378/* Rx Side */
379 u32 rx_ring_num; /*Number of receive rings */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380#define MAX_RX_BLOCKS_PER_RING 150
381
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500382 struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
raghavendra.koushik@neterion.comb6e3f982005-08-03 12:38:01 -0700383 u8 bimodal; /*Flag for setting bimodal interrupts*/
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
385#define HEADER_ETHERNET_II_802_3_SIZE 14
386#define HEADER_802_2_SIZE 3
387#define HEADER_SNAP_SIZE 5
388#define HEADER_VLAN_SIZE 4
389
390#define MIN_MTU 46
391#define MAX_PYLD 1500
392#define MAX_MTU (MAX_PYLD+18)
393#define MAX_MTU_VLAN (MAX_PYLD+22)
394#define MAX_PYLD_JUMBO 9600
395#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
396#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700397 u16 bus_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398};
399
400/* Structure representing MAC Addrs */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500401struct mac_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700402 u8 mac_addr[ETH_ALEN];
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500403};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
405/* Structure that represent every FIFO element in the BAR1
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700406 * Address location.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500408struct TxFIFO_element {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 u64 TxDL_Pointer;
410
411 u64 List_Control;
412#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
413#define TX_FIFO_FIRST_LIST BIT(14)
414#define TX_FIFO_LAST_LIST BIT(15)
415#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
416#define TX_FIFO_SPECIAL_FUNC BIT(23)
417#define TX_FIFO_DS_NO_SNOOP BIT(31)
418#define TX_FIFO_BUFF_NO_SNOOP BIT(30)
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500419};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421/* Tx descriptor structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500422struct TxD {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 u64 Control_1;
424/* bit mask */
425#define TXD_LIST_OWN_XENA BIT(7)
426#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
427#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
428#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
429#define TXD_GATHER_CODE (BIT(22) | BIT(23))
430#define TXD_GATHER_CODE_FIRST BIT(22)
431#define TXD_GATHER_CODE_LAST BIT(23)
432#define TXD_TCP_LSO_EN BIT(30)
433#define TXD_UDP_COF_EN BIT(31)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500434#define TXD_UFO_EN BIT(31) | BIT(30)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500436#define TXD_UFO_MSS(val) vBIT(val,34,14)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
438
439 u64 Control_2;
440#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
441#define TXD_TX_CKO_IPV4_EN BIT(5)
442#define TXD_TX_CKO_TCP_EN BIT(6)
443#define TXD_TX_CKO_UDP_EN BIT(7)
444#define TXD_VLAN_ENABLE BIT(15)
445#define TXD_VLAN_TAG(val) vBIT(val,16,16)
446#define TXD_INT_NUMBER(val) vBIT(val,34,6)
447#define TXD_INT_TYPE_PER_LIST BIT(47)
448#define TXD_INT_TYPE_UTILZ BIT(46)
449#define TXD_SET_MARKER vBIT(0x6,0,4)
450
451 u64 Buffer_Pointer;
452 u64 Host_Control; /* reserved for host */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500453};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
455/* Structure to hold the phy and virt addr of every TxDL. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500456struct list_info_hold {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457 dma_addr_t list_phy_addr;
458 void *list_virt_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500459};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460
Ananda Rajuda6971d2005-10-31 16:55:31 -0500461/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500462struct RxD_t {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463 u64 Host_Control; /* reserved for host */
464 u64 Control_1;
465#define RXD_OWN_XENA BIT(7)
466#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
467#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
468#define RXD_FRAME_PROTO_IPV4 BIT(27)
469#define RXD_FRAME_PROTO_IPV6 BIT(28)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700470#define RXD_FRAME_IP_FRAG BIT(29)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471#define RXD_FRAME_PROTO_TCP BIT(30)
472#define RXD_FRAME_PROTO_UDP BIT(31)
473#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
474#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
475#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
476
477 u64 Control_2;
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700478#define THE_RXD_MARK 0x3
479#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
480#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
481
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
483#define SET_VLAN_TAG(val) vBIT(val,48,16)
484#define SET_NUM_TAG(val) vBIT(val,16,32)
485
Ananda Rajuda6971d2005-10-31 16:55:31 -0500486
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500487};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500488/* Rx descriptor structure for 1 buffer mode */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500489struct RxD1 {
490 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500491
492#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
493#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
494#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
495 (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
496 u64 Buffer0_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500497};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500498/* Rx descriptor structure for 3 or 2 buffer mode */
499
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500500struct RxD3 {
501 struct RxD_t h;
Ananda Rajuda6971d2005-10-31 16:55:31 -0500502
503#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
504#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
505#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
506#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
507#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
508#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
509#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
510 (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
511#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
512 (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
513#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
514 (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515#define BUF0_LEN 40
516#define BUF1_LEN 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517
518 u64 Buffer0_ptr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519 u64 Buffer1_ptr;
520 u64 Buffer2_ptr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500521};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500522
Linus Torvalds1da177e2005-04-16 15:20:36 -0700523
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700524/* Structure that represents the Rx descriptor block which contains
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 * 128 Rx descriptors.
526 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500527struct RxD_block {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500528#define MAX_RXDS_PER_BLOCK_1 127
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500529 struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530
531 u64 reserved_0;
532#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700533 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 * Rxd in this blk */
535 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
536 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700537 * the upper 32 bits should
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538 * be 0 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500539};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541#define SIZE_OF_BLOCK 4096
542
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500543#define RXD_MODE_1 0 /* One Buffer mode */
544#define RXD_MODE_3A 1 /* Three Buffer mode */
545#define RXD_MODE_3B 2 /* Two Buffer mode */
Ananda Rajuda6971d2005-10-31 16:55:31 -0500546
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700547/* Structure to hold virtual addresses of Buf0 and Buf1 in
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548 * 2buf mode. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500549struct buffAdd {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700550 void *ba_0_org;
551 void *ba_1_org;
552 void *ba_0;
553 void *ba_1;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500554};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
556/* Structure which stores all the MAC control parameters */
557
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700558/* This structure stores the offset of the RxD in the ring
559 * from which the Rx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 * up the RxDs for processing.
561 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500562struct rx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 u32 block_index;
564 u32 offset;
565 u32 ring_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500566};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500568struct rx_curr_put_info {
569 u32 block_index;
570 u32 offset;
571 u32 ring_len;
572};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573
574/* This structure stores the offset of the TxDl in the FIFO
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700575 * from which the Tx Interrupt processor can start picking
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576 * up the TxDLs for send complete interrupt processing.
577 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500578struct tx_curr_get_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 u32 offset;
580 u32 fifo_len;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500581};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500583struct tx_curr_put_info {
584 u32 offset;
585 u32 fifo_len;
586};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500588struct rxd_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500589 void *virt_addr;
590 dma_addr_t dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500591};
Ananda Rajuda6971d2005-10-31 16:55:31 -0500592
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700593/* Structure that holds the Phy and virt addresses of the Blocks */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500594struct rx_block_info {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500595 void *block_virt_addr;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700596 dma_addr_t block_dma_addr;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500597 struct rxd_info *rxds;
598};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700599
600/* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500601struct ring_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700602 /* The ring number */
603 int ring_no;
604
605 /*
606 * Place holders for the virtual and physical addresses of
607 * all the Rx Blocks
608 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500609 struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700610 int block_count;
611 int pkt_cnt;
612
613 /*
614 * Put pointer info which indictes which RxD has to be replenished
615 * with a new buffer.
616 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500617 struct rx_curr_put_info rx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700618
619 /*
620 * Get pointer info which indictes which is the last RxD that was
621 * processed by the driver.
622 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500623 struct rx_curr_get_info rx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700624
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700625 /* Index to the absolute position of the put pointer of Rx ring */
626 int put_pos;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700627
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700628 /* Buffer Address store. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500629 struct buffAdd **ba;
630 struct s2io_nic *nic;
631};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700632
633/* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500634struct fifo_info {
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700635 /* FIFO number */
636 int fifo_no;
637
638 /* Maximum TxDs per TxDL */
639 int max_txds;
640
641 /* Place holder of all the TX List's Phy and Virt addresses. */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500642 struct list_info_hold *list_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700643
644 /*
645 * Current offset within the tx FIFO where driver would write
646 * new Tx frame
647 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500648 struct tx_curr_put_info tx_curr_put_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700649
650 /*
651 * Current offset within tx FIFO from where the driver would start freeing
652 * the buffers
653 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500654 struct tx_curr_get_info tx_curr_get_info;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700655
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500656 struct s2io_nic *nic;
657};
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700658
Adrian Bunk47bdd712006-06-30 18:25:18 +0200659/* Information related to the Tx and Rx FIFOs and Rings of Xena
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660 * is maintained in this structure.
661 */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500662struct mac_info {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663/* tx side stuff */
664 /* logical pointer of start of each Tx FIFO */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500665 struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700667 /* Fifo specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500668 struct fifo_info fifos[MAX_TX_FIFOS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700669
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700670 /* Save virtual address of TxD page with zero DMA addr(if any) */
671 void *zerodma_virt_addr;
672
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700673/* rx side stuff */
674 /* Ring specific structure */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500675 struct ring_info rings[MAX_RX_RINGS];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700676
677 u16 rmac_pause_time;
678 u16 mc_pause_threshold_q0q3;
679 u16 mc_pause_threshold_q4q7;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680
681 void *stats_mem; /* orignal pointer to allocated mem */
682 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
683 u32 stats_mem_sz;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500684 struct stat_block *stats_info; /* Logical address of the stat block */
685};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686
687/* structure representing the user defined MAC addresses */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500688struct usr_addr {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 char addr[ETH_ALEN];
690 int usage_cnt;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500691};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693/* Default Tunable parameters of the NIC. */
Ananda Raju9dc737a2006-04-21 19:05:41 -0400694#define DEFAULT_FIFO_0_LEN 4096
695#define DEFAULT_FIFO_1_7_LEN 512
Ananda Rajuc92ca042006-04-21 19:18:03 -0400696#define SMALL_BLK_CNT 30
697#define LARGE_BLK_CNT 100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400699/*
700 * Structure to keep track of the MSI-X vectors and the corresponding
701 * argument registered against each vector
702 */
703#define MAX_REQUESTED_MSI_X 17
704struct s2io_msix_entry
705{
706 u16 vector;
707 u16 entry;
708 void *arg;
709
710 u8 type;
711#define MSIX_FIFO_TYPE 1
712#define MSIX_RING_TYPE 2
713
714 u8 in_use;
715#define MSIX_REGISTERED_SUCCESS 0xAA
716};
717
718struct msix_info_st {
719 u64 addr;
720 u64 data;
721};
722
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500723/* Data structure to represent a LRO session */
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500724struct lro {
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500725 struct sk_buff *parent;
Ananda Raju75c30b12006-07-24 19:55:09 -0400726 struct sk_buff *last_frag;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500727 u8 *l2h;
728 struct iphdr *iph;
729 struct tcphdr *tcph;
730 u32 tcp_next_seq;
Al Virobd4f3ae2007-02-09 16:40:15 +0000731 __be32 tcp_ack;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500732 int total_len;
733 int frags_len;
734 int sg_num;
735 int in_use;
Al Virobd4f3ae2007-02-09 16:40:15 +0000736 __be16 window;
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500737 u32 cur_tsval;
738 u32 cur_tsecr;
739 u8 saw_ts;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500740};
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500741
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742/* Structure representing one instance of the NIC */
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700743struct s2io_nic {
Ananda Rajuda6971d2005-10-31 16:55:31 -0500744 int rxd_mode;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700745 /*
746 * Count of packets to be processed in a given iteration, it will be indicated
747 * by the quota field of the device structure when NAPI is enabled.
748 */
749 int pkts_to_process;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700750 struct net_device *dev;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500751 struct mac_info mac_control;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700752 struct config_param config;
753 struct pci_dev *pdev;
754 void __iomem *bar0;
755 void __iomem *bar1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700756#define MAX_MAC_SUPPORTED 16
757#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
758
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500759 struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
760 struct mac_addr pre_mac_addr[MAX_MAC_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
762 struct net_device_stats stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763 int high_dma_flag;
764 int device_close_flag;
765 int device_enabled_once;
766
Ananda Rajuc92ca042006-04-21 19:18:03 -0400767 char name[60];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 struct tasklet_struct task;
769 volatile unsigned long tasklet_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700771 /* Timer that handles I/O errors/exceptions */
772 struct timer_list alarm_timer;
773
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700774 /* Space to back up the PCI config space */
775 u32 config_space[256 / sizeof(u32)];
776
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777 atomic_t rx_bufs_left[MAX_RX_RINGS];
778
779 spinlock_t tx_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780 spinlock_t put_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
782#define PROMISC 1
783#define ALL_MULTI 2
784
785#define MAX_ADDRS_SUPPORTED 64
786 u16 usr_addr_count;
787 u16 mc_addr_count;
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500788 struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789
790 u16 m_cast_flg;
791 u16 all_multi_pos;
792 u16 promisc_flg;
793
794 u16 tx_pkt_count;
795 u16 rx_pkt_count;
796 u16 tx_err_count;
797 u16 rx_err_count;
798
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 /* Id timer, used to blink NIC to physically identify NIC. */
800 struct timer_list id_timer;
801
802 /* Restart timer, used to restart NIC if the device is stuck and
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700803 * a schedule task that will set the correct Link state once the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 * NIC's PHY has stabilized after a state change.
805 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806 struct work_struct rst_timer_task;
807 struct work_struct set_link_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700809 /* Flag that can be used to turn on or turn off the Rx checksum
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 * offload feature.
811 */
812 int rx_csum;
813
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700814 /* after blink, the adapter must be restored with original
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 * values.
816 */
817 u64 adapt_ctrl_org;
818
819 /* Last known link state. */
820 u16 last_link_state;
821#define LINK_DOWN 1
822#define LINK_UP 2
823
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824 int task_flag;
825#define CARD_DOWN 1
826#define CARD_UP 2
827 atomic_t card_state;
828 volatile unsigned long link_state;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700829 struct vlan_group *vlgrp;
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400830#define MSIX_FLG 0xA5
831 struct msix_entry *entries;
832 struct s2io_msix_entry *s2io_entries;
Ananda Rajue6a8fee2006-07-06 23:58:23 -0700833 char desc[MAX_REQUESTED_MSI_X][25];
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400834
Ananda Rajuc92ca042006-04-21 19:18:03 -0400835 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
836
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400837 struct msix_info_st msix_info[0x3f];
838
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700839#define XFRAME_I_DEVICE 1
840#define XFRAME_II_DEVICE 2
841 u8 device_type;
raghavendra.koushik@neterion.combe3a6b02005-08-03 12:35:55 -0700842
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500843#define MAX_LRO_SESSIONS 32
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500844 struct lro lro0_n[MAX_LRO_SESSIONS];
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -0500845 unsigned long clubbed_frms_cnt;
846 unsigned long sending_both;
847 u8 lro;
848 u16 lro_max_aggr_per_sess;
849
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400850#define INTA 0
851#define MSI 1
852#define MSI_X 2
853 u8 intr_type;
854
raghavendra.koushik@neterion.com7ba013a2005-08-03 12:29:20 -0700855 spinlock_t rx_lock;
856 atomic_t isr_cnt;
Ananda Rajufed5ecc2005-11-14 15:25:08 -0500857 u64 *ufo_in_band_v;
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500858#define VPD_STRING_LEN 80
859 u8 product_name[VPD_STRING_LEN];
860 u8 serial_num[VPD_STRING_LEN];
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700861};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862
863#define RESET_ERROR 1;
864#define CMD_ERROR 2;
865
866/* OS related system calls */
867#ifndef readq
868static inline u64 readq(void __iomem *addr)
869{
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700870 u64 ret = 0;
871 ret = readl(addr + 4);
Andrew Morton7ef24b62005-08-25 17:14:46 -0700872 ret <<= 32;
873 ret |= readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875 return ret;
876}
877#endif
878
879#ifndef writeq
880static inline void writeq(u64 val, void __iomem *addr)
881{
882 writel((u32) (val), addr);
883 writel((u32) (val >> 32), (addr + 4));
884}
Ananda Rajuc92ca042006-04-21 19:18:03 -0400885#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700886
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400887/*
888 * Some registers have to be written in a particular order to
889 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
890 * is used to perform such ordered writes. Defines UF (Upper First)
Ananda Rajuc92ca042006-04-21 19:18:03 -0400891 * and LF (Lower First) will be used to specify the required write order.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 */
893#define UF 1
894#define LF 2
895static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
896{
Ananda Rajuc92ca042006-04-21 19:18:03 -0400897 u32 ret;
898
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899 if (order == LF) {
900 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400901 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400903 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904 } else {
905 writel((u32) (val >> 32), (addr + 4));
Ananda Rajuc92ca042006-04-21 19:18:03 -0400906 ret = readl(addr + 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 writel((u32) (val), addr);
Ananda Rajuc92ca042006-04-21 19:18:03 -0400908 ret = readl(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909 }
910}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911
912/* Interrupt related values of Xena */
913
914#define ENABLE_INTRS 1
915#define DISABLE_INTRS 2
916
917/* Highest level interrupt blocks */
918#define TX_PIC_INTR (0x0001<<0)
919#define TX_DMA_INTR (0x0001<<1)
920#define TX_MAC_INTR (0x0001<<2)
921#define TX_XGXS_INTR (0x0001<<3)
922#define TX_TRAFFIC_INTR (0x0001<<4)
923#define RX_PIC_INTR (0x0001<<5)
924#define RX_DMA_INTR (0x0001<<6)
925#define RX_MAC_INTR (0x0001<<7)
926#define RX_XGXS_INTR (0x0001<<8)
927#define RX_TRAFFIC_INTR (0x0001<<9)
928#define MC_INTR (0x0001<<10)
929#define ENA_ALL_INTRS ( TX_PIC_INTR | \
930 TX_DMA_INTR | \
931 TX_MAC_INTR | \
932 TX_XGXS_INTR | \
933 TX_TRAFFIC_INTR | \
934 RX_PIC_INTR | \
935 RX_DMA_INTR | \
936 RX_MAC_INTR | \
937 RX_XGXS_INTR | \
938 RX_TRAFFIC_INTR | \
939 MC_INTR )
940
941/* Interrupt masks for the general interrupt mask register */
942#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
943
944#define TXPIC_INT_M BIT(0)
945#define TXDMA_INT_M BIT(1)
946#define TXMAC_INT_M BIT(2)
947#define TXXGXS_INT_M BIT(3)
948#define TXTRAFFIC_INT_M BIT(8)
949#define PIC_RX_INT_M BIT(32)
950#define RXDMA_INT_M BIT(33)
951#define RXMAC_INT_M BIT(34)
952#define MC_INT_M BIT(35)
953#define RXXGXS_INT_M BIT(36)
954#define RXTRAFFIC_INT_M BIT(40)
955
956/* PIC level Interrupts TODO*/
957
958/* DMA level Inressupts */
959#define TXDMA_PFC_INT_M BIT(0)
960#define TXDMA_PCC_INT_M BIT(2)
961
962/* PFC block interrupts */
963#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
964
965/* PCC block interrupts. */
966#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
967 PCC_FB_ECC Error. */
968
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -0700969#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700970/*
971 * Prototype declaration.
972 */
973static int __devinit s2io_init_nic(struct pci_dev *pdev,
974 const struct pci_device_id *pre);
975static void __devexit s2io_rem_nic(struct pci_dev *pdev);
976static int init_shared_mem(struct s2io_nic *sp);
977static void free_shared_mem(struct s2io_nic *sp);
978static int init_nic(struct s2io_nic *nic);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500979static void rx_intr_handler(struct ring_info *ring_data);
980static void tx_intr_handler(struct fifo_info *fifo_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981static void alarm_intr_handler(struct s2io_nic *sp);
982
983static int s2io_starter(void);
Sivakumar Subramani19a60522007-01-31 13:30:49 -0500984static void s2io_closer(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985static void s2io_tx_watchdog(struct net_device *dev);
986static void s2io_tasklet(unsigned long dev_addr);
987static void s2io_set_multicast(struct net_device *dev);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500988static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
989static void s2io_link(struct s2io_nic * sp, int link);
990static void s2io_reset(struct s2io_nic * sp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991static int s2io_poll(struct net_device *dev, int *budget);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500992static void s2io_init_pci(struct s2io_nic * sp);
Adrian Bunk26df54b2006-01-14 03:09:40 +0100993static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
raghavendra.koushik@neterion.com25fff882005-08-03 12:34:11 -0700994static void s2io_alarm_handle(unsigned long data);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -0500995static int s2io_enable_msi(struct s2io_nic *nic);
David Howells7d12e782006-10-05 14:55:46 +0100996static irqreturn_t s2io_msi_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400997static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +0100998s2io_msix_ring_handle(int irq, void *dev_id);
Ravinandan Arakalicc6e7c42005-10-04 06:41:24 -0400999static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01001000s2io_msix_fifo_handle(int irq, void *dev_id);
1001static irqreturn_t s2io_isr(int irq, void *dev_id);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001002static int verify_xena_quiescence(struct s2io_nic *sp);
Jeff Garzik7282d492006-09-13 14:30:00 -04001003static const struct ethtool_ops netdev_ethtool_ops;
David Howellsc4028952006-11-22 14:57:56 +00001004static void s2io_set_link(struct work_struct *work);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001005static int s2io_set_swapper(struct s2io_nic * sp);
1006static void s2io_card_down(struct s2io_nic *nic);
1007static int s2io_card_up(struct s2io_nic *nic);
Adrian Bunk26df54b2006-01-14 03:09:40 +01001008static int get_xena_rev_id(struct pci_dev *pdev);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001009static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
1010 int bit_state);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001011static int s2io_add_isr(struct s2io_nic * sp);
1012static void s2io_rem_isr(struct s2io_nic * sp);
Sivakumar Subramani19a60522007-01-31 13:30:49 -05001013
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001014static void restore_xmsi_data(struct s2io_nic *nic);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001015
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001016static int
1017s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
1018 struct RxD_t *rxdp, struct s2io_nic *sp);
1019static void clear_lro_session(struct lro *lro);
Ravinandan Arakali7d3d04392006-01-25 14:53:07 -05001020static void queue_rx_frame(struct sk_buff *skb);
Ralf Baechle1ee6dd72007-01-31 14:09:29 -05001021static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
1022static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
1023 struct sk_buff *skb, u32 tcp_len);
Sivakumar Subramani9fc93a42007-02-24 01:57:32 -05001024static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
Ananda Rajub41477f2006-07-24 19:52:49 -04001025
Ananda Raju75c30b12006-07-24 19:55:09 -04001026#define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
1027#define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
1028#define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
1029
Ananda Rajub41477f2006-07-24 19:52:49 -04001030#define S2IO_PARM_INT(X, def_val) \
1031 static unsigned int X = def_val;\
1032 module_param(X , uint, 0);
1033
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034#endif /* _S2IO_H */