blob: b9daa0bf32a46375784c2f6ade582ba4c46c4a74 [file] [log] [blame]
Shawn Guofba311f2010-12-18 21:39:31 +08001/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
Thierry Reding641d0342013-01-21 11:09:01 +010023#include <linux/err.h>
Shawn Guofba311f2010-12-18 21:39:31 +080024#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/irq.h>
Shawn Guo0b76c542012-08-20 16:43:32 +080028#include <linux/irqdomain.h>
Shawn Guo4052d452012-05-04 14:29:22 +080029#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
Shawn Guo8d7cf832011-06-06 09:37:58 -060032#include <linux/platform_device.h>
33#include <linux/slab.h>
Linus Walleij0f4630f2015-12-04 14:02:58 +010034#include <linux/gpio/driver.h>
35/* FIXME: for gpio_get_value(), replace this by direct register read */
36#include <linux/gpio.h>
Paul Gortmakerbb207ef2011-07-03 13:38:09 -040037#include <linux/module.h>
Shawn Guofba311f2010-12-18 21:39:31 +080038
Shawn Guo8d7cf832011-06-06 09:37:58 -060039#define MXS_SET 0x4
40#define MXS_CLR 0x8
Shawn Guofba311f2010-12-18 21:39:31 +080041
Shawn Guo164387d2012-05-03 23:32:52 +080042#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
43#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
44#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
45#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
46#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
47#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
48#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
49#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
Shawn Guofba311f2010-12-18 21:39:31 +080050
51#define GPIO_INT_FALL_EDGE 0x0
52#define GPIO_INT_LOW_LEV 0x1
53#define GPIO_INT_RISE_EDGE 0x2
54#define GPIO_INT_HIGH_LEV 0x3
55#define GPIO_INT_LEV_MASK (1 << 0)
56#define GPIO_INT_POL_MASK (1 << 1)
57
Shawn Guo164387d2012-05-03 23:32:52 +080058enum mxs_gpio_id {
59 IMX23_GPIO,
60 IMX28_GPIO,
61};
62
Grant Likely7b2fa572011-06-06 09:37:58 -060063struct mxs_gpio_port {
64 void __iomem *base;
65 int id;
66 int irq;
Shawn Guo0b76c542012-08-20 16:43:32 +080067 struct irq_domain *domain;
Linus Walleij0f4630f2015-12-04 14:02:58 +010068 struct gpio_chip gc;
Shawn Guo164387d2012-05-03 23:32:52 +080069 enum mxs_gpio_id devid;
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010070 u32 both_edges;
Grant Likely7b2fa572011-06-06 09:37:58 -060071};
72
Shawn Guo164387d2012-05-03 23:32:52 +080073static inline int is_imx23_gpio(struct mxs_gpio_port *port)
74{
75 return port->devid == IMX23_GPIO;
76}
77
78static inline int is_imx28_gpio(struct mxs_gpio_port *port)
79{
80 return port->devid == IMX28_GPIO;
81}
82
Shawn Guofba311f2010-12-18 21:39:31 +080083/* Note: This driver assumes 32 GPIOs are handled in one register */
84
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +010085static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
Shawn Guofba311f2010-12-18 21:39:31 +080086{
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010087 u32 val;
Shawn Guo0b76c542012-08-20 16:43:32 +080088 u32 pin_mask = 1 << d->hwirq;
Shawn Guo498c17c2011-06-07 22:00:54 +080089 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
90 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +080091 void __iomem *pin_addr;
92 int edge;
93
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010094 port->both_edges &= ~pin_mask;
Shawn Guofba311f2010-12-18 21:39:31 +080095 switch (type) {
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010096 case IRQ_TYPE_EDGE_BOTH:
Linus Walleij0f4630f2015-12-04 14:02:58 +010097 val = gpio_get_value(port->gc.base + d->hwirq);
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +010098 if (val)
99 edge = GPIO_INT_FALL_EDGE;
100 else
101 edge = GPIO_INT_RISE_EDGE;
102 port->both_edges |= pin_mask;
103 break;
Shawn Guofba311f2010-12-18 21:39:31 +0800104 case IRQ_TYPE_EDGE_RISING:
105 edge = GPIO_INT_RISE_EDGE;
106 break;
107 case IRQ_TYPE_EDGE_FALLING:
108 edge = GPIO_INT_FALL_EDGE;
109 break;
110 case IRQ_TYPE_LEVEL_LOW:
111 edge = GPIO_INT_LOW_LEV;
112 break;
113 case IRQ_TYPE_LEVEL_HIGH:
114 edge = GPIO_INT_HIGH_LEV;
115 break;
116 default:
117 return -EINVAL;
118 }
119
120 /* set level or edge */
Shawn Guo164387d2012-05-03 23:32:52 +0800121 pin_addr = port->base + PINCTRL_IRQLEV(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800122 if (edge & GPIO_INT_LEV_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600123 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800124 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600125 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800126
127 /* set polarity */
Shawn Guo164387d2012-05-03 23:32:52 +0800128 pin_addr = port->base + PINCTRL_IRQPOL(port);
Shawn Guofba311f2010-12-18 21:39:31 +0800129 if (edge & GPIO_INT_POL_MASK)
Shawn Guo8d7cf832011-06-06 09:37:58 -0600130 writel(pin_mask, pin_addr + MXS_SET);
Shawn Guofba311f2010-12-18 21:39:31 +0800131 else
Shawn Guo8d7cf832011-06-06 09:37:58 -0600132 writel(pin_mask, pin_addr + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800133
Shawn Guo0b76c542012-08-20 16:43:32 +0800134 writel(pin_mask,
Shawn Guo164387d2012-05-03 23:32:52 +0800135 port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guofba311f2010-12-18 21:39:31 +0800136
137 return 0;
138}
139
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +0100140static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
141{
142 u32 bit, val, edge;
143 void __iomem *pin_addr;
144
145 bit = 1 << gpio;
146
147 pin_addr = port->base + PINCTRL_IRQPOL(port);
148 val = readl(pin_addr);
149 edge = val & bit;
150
151 if (edge)
152 writel(bit, pin_addr + MXS_CLR);
153 else
154 writel(bit, pin_addr + MXS_SET);
155}
156
Shawn Guofba311f2010-12-18 21:39:31 +0800157/* MXS has one interrupt *per* gpio port */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200158static void mxs_gpio_irq_handler(struct irq_desc *desc)
Shawn Guofba311f2010-12-18 21:39:31 +0800159{
160 u32 irq_stat;
Jiang Liu476f8b42015-06-04 12:13:15 +0800161 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
Shawn Guofba311f2010-12-18 21:39:31 +0800162
Uwe Kleine-König1f6b5dd2011-01-25 16:54:22 +0100163 desc->irq_data.chip->irq_ack(&desc->irq_data);
164
Shawn Guo164387d2012-05-03 23:32:52 +0800165 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
166 readl(port->base + PINCTRL_IRQEN(port));
Shawn Guofba311f2010-12-18 21:39:31 +0800167
168 while (irq_stat != 0) {
169 int irqoffset = fls(irq_stat) - 1;
Gwenhael Goavec-Merou66d79902013-01-29 09:16:33 +0100170 if (port->both_edges & (1 << irqoffset))
171 mxs_flip_edge(port, irqoffset);
172
Shawn Guo0b76c542012-08-20 16:43:32 +0800173 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
Shawn Guofba311f2010-12-18 21:39:31 +0800174 irq_stat &= ~(1 << irqoffset);
175 }
176}
177
178/*
179 * Set interrupt number "irq" in the GPIO as a wake-up source.
180 * While system is running, all registered GPIO interrupts need to have
181 * wake-up enabled. When system is suspended, only selected GPIO interrupts
182 * need to have wake-up enabled.
183 * @param irq interrupt source number
184 * @param enable enable as wake-up if equal to non-zero
185 * @return This function returns 0 on success.
186 */
Uwe Kleine-Königbf0c11182011-02-18 21:31:41 +0100187static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
Shawn Guofba311f2010-12-18 21:39:31 +0800188{
Shawn Guo498c17c2011-06-07 22:00:54 +0800189 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
190 struct mxs_gpio_port *port = gc->private;
Shawn Guofba311f2010-12-18 21:39:31 +0800191
Shawn Guo61617152011-06-07 22:00:53 +0800192 if (enable)
193 enable_irq_wake(port->irq);
194 else
195 disable_irq_wake(port->irq);
Shawn Guofba311f2010-12-18 21:39:31 +0800196
197 return 0;
198}
199
Peng Fan1bbc5572015-08-23 21:11:53 +0800200static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
Shawn Guo498c17c2011-06-07 22:00:54 +0800201{
202 struct irq_chip_generic *gc;
203 struct irq_chip_type *ct;
204
Shawn Guo0b76c542012-08-20 16:43:32 +0800205 gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
Shawn Guo498c17c2011-06-07 22:00:54 +0800206 port->base, handle_level_irq);
Peng Fan1bbc5572015-08-23 21:11:53 +0800207 if (!gc)
208 return -ENOMEM;
209
Shawn Guo498c17c2011-06-07 22:00:54 +0800210 gc->private = port;
211
212 ct = gc->chip_types;
Shawn Guo591567a2011-07-19 21:16:56 +0800213 ct->chip.irq_ack = irq_gc_ack_set_bit;
Shawn Guo498c17c2011-06-07 22:00:54 +0800214 ct->chip.irq_mask = irq_gc_mask_clr_bit;
215 ct->chip.irq_unmask = irq_gc_mask_set_bit;
216 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
Shawn Guo591567a2011-07-19 21:16:56 +0800217 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
Shawn Guo164387d2012-05-03 23:32:52 +0800218 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
219 ct->regs.mask = PINCTRL_IRQEN(port);
Shawn Guo498c17c2011-06-07 22:00:54 +0800220
Marek Vasuta585f872014-03-24 03:38:10 +0100221 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
222 IRQ_NOREQUEST, 0);
Peng Fan1bbc5572015-08-23 21:11:53 +0800223
224 return 0;
Shawn Guo498c17c2011-06-07 22:00:54 +0800225}
Shawn Guofba311f2010-12-18 21:39:31 +0800226
Shawn Guo06f88a82011-06-06 22:31:29 +0800227static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
Shawn Guofba311f2010-12-18 21:39:31 +0800228{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100229 struct mxs_gpio_port *port = gpiochip_get_data(gc);
Shawn Guofba311f2010-12-18 21:39:31 +0800230
Shawn Guo0b76c542012-08-20 16:43:32 +0800231 return irq_find_mapping(port->domain, offset);
Shawn Guofba311f2010-12-18 21:39:31 +0800232}
233
Janusz Uzyckic8aaa1b2014-11-19 09:55:22 +0100234static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
235{
Linus Walleij0f4630f2015-12-04 14:02:58 +0100236 struct mxs_gpio_port *port = gpiochip_get_data(gc);
Janusz Uzyckic8aaa1b2014-11-19 09:55:22 +0100237 u32 mask = 1 << offset;
238 u32 dir;
239
240 dir = readl(port->base + PINCTRL_DOE(port));
241 return !(dir & mask);
242}
243
Krzysztof Kozlowskif4f79d42015-05-02 00:56:47 +0900244static const struct platform_device_id mxs_gpio_ids[] = {
Shawn Guo164387d2012-05-03 23:32:52 +0800245 {
246 .name = "imx23-gpio",
247 .driver_data = IMX23_GPIO,
248 }, {
249 .name = "imx28-gpio",
250 .driver_data = IMX28_GPIO,
251 }, {
252 /* sentinel */
253 }
254};
255MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
256
Shawn Guo4052d452012-05-04 14:29:22 +0800257static const struct of_device_id mxs_gpio_dt_ids[] = {
258 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
259 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
260 { /* sentinel */ }
261};
262MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
263
Bill Pemberton38363092012-11-19 13:22:34 -0500264static int mxs_gpio_probe(struct platform_device *pdev)
Shawn Guofba311f2010-12-18 21:39:31 +0800265{
Shawn Guo4052d452012-05-04 14:29:22 +0800266 const struct of_device_id *of_id =
267 of_match_device(mxs_gpio_dt_ids, &pdev->dev);
268 struct device_node *np = pdev->dev.of_node;
269 struct device_node *parent;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600270 static void __iomem *base;
271 struct mxs_gpio_port *port;
Shawn Guo0b76c542012-08-20 16:43:32 +0800272 int irq_base;
Shawn Guo498c17c2011-06-07 22:00:54 +0800273 int err;
Shawn Guofba311f2010-12-18 21:39:31 +0800274
Shawn Guo940a4f72012-05-04 10:30:14 +0800275 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600276 if (!port)
277 return -ENOMEM;
Shawn Guofba311f2010-12-18 21:39:31 +0800278
Fabio Estevam99357122013-11-05 17:21:22 -0200279 port->id = of_alias_get_id(np, "gpio");
280 if (port->id < 0)
281 return port->id;
282 port->devid = (enum mxs_gpio_id) of_id->data;
Shawn Guo940a4f72012-05-04 10:30:14 +0800283 port->irq = platform_get_irq(pdev, 0);
284 if (port->irq < 0)
285 return port->irq;
286
Shawn Guo8d7cf832011-06-06 09:37:58 -0600287 /*
288 * map memory region only once, as all the gpio ports
289 * share the same one
290 */
291 if (!base) {
Fabio Estevam99357122013-11-05 17:21:22 -0200292 parent = of_get_parent(np);
293 base = of_iomap(parent, 0);
294 of_node_put(parent);
295 if (!base)
296 return -EADDRNOTAVAIL;
Shawn Guofba311f2010-12-18 21:39:31 +0800297 }
Shawn Guo8d7cf832011-06-06 09:37:58 -0600298 port->base = base;
299
Shawn Guo498c17c2011-06-07 22:00:54 +0800300 /*
301 * select the pin interrupt functionality but initially
302 * disable the interrupts
303 */
Shawn Guo164387d2012-05-03 23:32:52 +0800304 writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
305 writel(0, port->base + PINCTRL_IRQEN(port));
Shawn Guo8d7cf832011-06-06 09:37:58 -0600306
307 /* clear address has to be used to clear IRQSTAT bits */
Shawn Guo164387d2012-05-03 23:32:52 +0800308 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600309
Shawn Guo0b76c542012-08-20 16:43:32 +0800310 irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
311 if (irq_base < 0)
312 return irq_base;
313
314 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
315 &irq_domain_simple_ops, NULL);
316 if (!port->domain) {
317 err = -ENODEV;
318 goto out_irqdesc_free;
319 }
320
Shawn Guo498c17c2011-06-07 22:00:54 +0800321 /* gpio-mxs can be a generic irq chip */
Peng Fan1bbc5572015-08-23 21:11:53 +0800322 err = mxs_gpio_init_gc(port, irq_base);
323 if (err < 0)
324 goto out_irqdomain_remove;
Shawn Guo8d7cf832011-06-06 09:37:58 -0600325
326 /* setup one handler for each entry */
Russell Kinga44735f2015-06-16 23:06:45 +0100327 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
328 port);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600329
Linus Walleij0f4630f2015-12-04 14:02:58 +0100330 err = bgpio_init(&port->gc, &pdev->dev, 4,
Shawn Guo164387d2012-05-03 23:32:52 +0800331 port->base + PINCTRL_DIN(port),
Maxime Ripard90dae4e2013-04-29 16:07:18 +0200332 port->base + PINCTRL_DOUT(port) + MXS_SET,
333 port->base + PINCTRL_DOUT(port) + MXS_CLR,
Linus Torvalds84a442b2012-05-26 12:57:47 -0700334 port->base + PINCTRL_DOE(port), NULL, 0);
Shawn Guo8d7cf832011-06-06 09:37:58 -0600335 if (err)
Linus Walleij0f4630f2015-12-04 14:02:58 +0100336 goto out_irqdomain_remove;
Shawn Guofba311f2010-12-18 21:39:31 +0800337
Linus Walleij0f4630f2015-12-04 14:02:58 +0100338 port->gc.to_irq = mxs_gpio_to_irq;
339 port->gc.get_direction = mxs_gpio_get_direction;
340 port->gc.base = port->id * 32;
Shawn Guo06f88a82011-06-06 22:31:29 +0800341
Linus Walleij0f4630f2015-12-04 14:02:58 +0100342 err = gpiochip_add_data(&port->gc, port);
Shawn Guo0b76c542012-08-20 16:43:32 +0800343 if (err)
Linus Walleij0f4630f2015-12-04 14:02:58 +0100344 goto out_irqdomain_remove;
Shawn Guo06f88a82011-06-06 22:31:29 +0800345
Shawn Guofba311f2010-12-18 21:39:31 +0800346 return 0;
Shawn Guo0b76c542012-08-20 16:43:32 +0800347
Peng Fan1bbc5572015-08-23 21:11:53 +0800348out_irqdomain_remove:
349 irq_domain_remove(port->domain);
Shawn Guo0b76c542012-08-20 16:43:32 +0800350out_irqdesc_free:
351 irq_free_descs(irq_base, 32);
352 return err;
Shawn Guofba311f2010-12-18 21:39:31 +0800353}
354
Shawn Guo8d7cf832011-06-06 09:37:58 -0600355static struct platform_driver mxs_gpio_driver = {
356 .driver = {
357 .name = "gpio-mxs",
Shawn Guo4052d452012-05-04 14:29:22 +0800358 .of_match_table = mxs_gpio_dt_ids,
Shawn Guo8d7cf832011-06-06 09:37:58 -0600359 },
360 .probe = mxs_gpio_probe,
Shawn Guo164387d2012-05-03 23:32:52 +0800361 .id_table = mxs_gpio_ids,
Shawn Guofba311f2010-12-18 21:39:31 +0800362};
Sascha Haueref196602011-01-24 12:57:46 +0100363
Shawn Guo8d7cf832011-06-06 09:37:58 -0600364static int __init mxs_gpio_init(void)
Sascha Haueref196602011-01-24 12:57:46 +0100365{
Shawn Guo8d7cf832011-06-06 09:37:58 -0600366 return platform_driver_register(&mxs_gpio_driver);
Sascha Haueref196602011-01-24 12:57:46 +0100367}
Shawn Guo8d7cf832011-06-06 09:37:58 -0600368postcore_initcall(mxs_gpio_init);
Shawn Guofba311f2010-12-18 21:39:31 +0800369
Shawn Guo8d7cf832011-06-06 09:37:58 -0600370MODULE_AUTHOR("Freescale Semiconductor, "
371 "Daniel Mack <danielncaiaq.de>, "
372 "Juergen Beisert <kernel@pengutronix.de>");
373MODULE_DESCRIPTION("Freescale MXS GPIO");
374MODULE_LICENSE("GPL");