PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Shannon Nelson | 8c47eaa | 2010-01-13 01:49:34 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
| 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe.h" |
| 33 | #include "ixgbe_phy.h" |
Greg Rose | 096a58f | 2010-01-09 02:26:26 +0000 | [diff] [blame] | 34 | #include "ixgbe_mbx.h" |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 35 | |
| 36 | #define IXGBE_82599_MAX_TX_QUEUES 128 |
| 37 | #define IXGBE_82599_MAX_RX_QUEUES 128 |
| 38 | #define IXGBE_82599_RAR_ENTRIES 128 |
| 39 | #define IXGBE_82599_MC_TBL_SIZE 128 |
| 40 | #define IXGBE_82599_VFT_TBL_SIZE 128 |
| 41 | |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 42 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 43 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 44 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); |
| 45 | static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
| 46 | ixgbe_link_speed speed, |
| 47 | bool autoneg, |
| 48 | bool autoneg_wait_to_complete); |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 49 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, |
| 50 | ixgbe_link_speed speed, |
| 51 | bool autoneg, |
| 52 | bool autoneg_wait_to_complete); |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 53 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
| 54 | bool autoneg_wait_to_complete); |
| 55 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 56 | ixgbe_link_speed speed, |
| 57 | bool autoneg, |
| 58 | bool autoneg_wait_to_complete); |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 59 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
| 60 | ixgbe_link_speed speed, |
| 61 | bool autoneg, |
| 62 | bool autoneg_wait_to_complete); |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 63 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 64 | |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 65 | static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 66 | { |
| 67 | struct ixgbe_mac_info *mac = &hw->mac; |
| 68 | if (hw->phy.multispeed_fiber) { |
| 69 | /* Set up dual speed SFP+ support */ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 70 | mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber; |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 71 | mac->ops.disable_tx_laser = |
| 72 | &ixgbe_disable_tx_laser_multispeed_fiber; |
| 73 | mac->ops.enable_tx_laser = |
| 74 | &ixgbe_enable_tx_laser_multispeed_fiber; |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 75 | mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 76 | } else { |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 77 | mac->ops.disable_tx_laser = NULL; |
| 78 | mac->ops.enable_tx_laser = NULL; |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 79 | mac->ops.flap_tx_laser = NULL; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 80 | if ((mac->ops.get_media_type(hw) == |
| 81 | ixgbe_media_type_backplane) && |
| 82 | (hw->phy.smart_speed == ixgbe_smart_speed_auto || |
| 83 | hw->phy.smart_speed == ixgbe_smart_speed_on)) |
| 84 | mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed; |
| 85 | else |
| 86 | mac->ops.setup_link = &ixgbe_setup_mac_link_82599; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 87 | } |
| 88 | } |
| 89 | |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 90 | static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 91 | { |
| 92 | s32 ret_val = 0; |
| 93 | u16 list_offset, data_offset, data_value; |
| 94 | |
| 95 | if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { |
| 96 | ixgbe_init_mac_link_ops_82599(hw); |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 97 | |
| 98 | hw->phy.ops.reset = NULL; |
| 99 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 100 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 101 | &data_offset); |
| 102 | |
| 103 | if (ret_val != 0) |
| 104 | goto setup_sfp_out; |
| 105 | |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 106 | /* PHY config will finish before releasing the semaphore */ |
| 107 | ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 108 | if (ret_val != 0) { |
| 109 | ret_val = IXGBE_ERR_SWFW_SYNC; |
| 110 | goto setup_sfp_out; |
| 111 | } |
| 112 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 113 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 114 | while (data_value != 0xffff) { |
| 115 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); |
| 116 | IXGBE_WRITE_FLUSH(hw); |
| 117 | hw->eeprom.ops.read(hw, ++data_offset, &data_value); |
| 118 | } |
Peter P Waskiewicz Jr | 1479ad4 | 2009-06-04 11:10:17 +0000 | [diff] [blame] | 119 | /* Now restart DSP by setting Restart_AN */ |
| 120 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, |
| 121 | (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART)); |
Peter P Waskiewicz Jr | aa5aec8 | 2009-05-19 09:18:34 +0000 | [diff] [blame] | 122 | |
| 123 | /* Release the semaphore */ |
| 124 | ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); |
| 125 | /* Delay obtaining semaphore again to allow FW access */ |
| 126 | msleep(hw->eeprom.semaphore_delay); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | setup_sfp_out: |
| 130 | return ret_val; |
| 131 | } |
| 132 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 133 | static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw) |
| 134 | { |
| 135 | struct ixgbe_mac_info *mac = &hw->mac; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 136 | |
| 137 | ixgbe_init_mac_link_ops_82599(hw); |
| 138 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 139 | mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; |
| 140 | mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; |
| 141 | mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; |
| 142 | mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; |
| 143 | mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 144 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 145 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | /** |
| 150 | * ixgbe_init_phy_ops_82599 - PHY/SFP specific init |
| 151 | * @hw: pointer to hardware structure |
| 152 | * |
| 153 | * Initialize any function pointers that were not able to be |
| 154 | * set during get_invariants because the PHY/SFP type was |
| 155 | * not known. Perform the SFP init if necessary. |
| 156 | * |
| 157 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 158 | static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 159 | { |
| 160 | struct ixgbe_mac_info *mac = &hw->mac; |
| 161 | struct ixgbe_phy_info *phy = &hw->phy; |
| 162 | s32 ret_val = 0; |
| 163 | |
| 164 | /* Identify the PHY or SFP module */ |
| 165 | ret_val = phy->ops.identify(hw); |
| 166 | |
| 167 | /* Setup function pointers based on detected SFP module and speeds */ |
| 168 | ixgbe_init_mac_link_ops_82599(hw); |
| 169 | |
| 170 | /* If copper media, overwrite with copper function pointers */ |
| 171 | if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { |
| 172 | mac->ops.setup_link = &ixgbe_setup_copper_link_82599; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 173 | mac->ops.get_link_capabilities = |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame^] | 174 | &ixgbe_get_copper_link_capabilities_generic; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | /* Set necessary function pointers based on phy type */ |
| 178 | switch (hw->phy.type) { |
| 179 | case ixgbe_phy_tn: |
| 180 | phy->ops.check_link = &ixgbe_check_phy_link_tnx; |
| 181 | phy->ops.get_firmware_version = |
| 182 | &ixgbe_get_phy_firmware_version_tnx; |
| 183 | break; |
| 184 | default: |
| 185 | break; |
| 186 | } |
| 187 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 188 | return ret_val; |
| 189 | } |
| 190 | |
| 191 | /** |
| 192 | * ixgbe_get_link_capabilities_82599 - Determines link capabilities |
| 193 | * @hw: pointer to hardware structure |
| 194 | * @speed: pointer to link speed |
| 195 | * @negotiation: true when autoneg or autotry is enabled |
| 196 | * |
| 197 | * Determines the link capabilities by reading the AUTOC register. |
| 198 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 199 | static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, |
| 200 | ixgbe_link_speed *speed, |
| 201 | bool *negotiation) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 202 | { |
| 203 | s32 status = 0; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 204 | u32 autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 205 | |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 206 | /* Determine 1G link capabilities off of SFP+ type */ |
| 207 | if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 208 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) { |
| 209 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 210 | *negotiation = true; |
| 211 | goto out; |
| 212 | } |
| 213 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 214 | /* |
| 215 | * Determine link capabilities based on the stored value of AUTOC, |
| 216 | * which represents EEPROM defaults. If AUTOC value has not been |
| 217 | * stored, use the current register value. |
| 218 | */ |
| 219 | if (hw->mac.orig_link_settings_stored) |
| 220 | autoc = hw->mac.orig_autoc; |
| 221 | else |
| 222 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 223 | |
| 224 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 225 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 226 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 227 | *negotiation = false; |
| 228 | break; |
| 229 | |
| 230 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 231 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 232 | *negotiation = false; |
| 233 | break; |
| 234 | |
| 235 | case IXGBE_AUTOC_LMS_1G_AN: |
| 236 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 237 | *negotiation = true; |
| 238 | break; |
| 239 | |
| 240 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 241 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 242 | *negotiation = false; |
| 243 | break; |
| 244 | |
| 245 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 246 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 247 | *speed = IXGBE_LINK_SPEED_UNKNOWN; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 248 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 249 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 250 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 251 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 252 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 253 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 254 | *negotiation = true; |
| 255 | break; |
| 256 | |
| 257 | case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: |
| 258 | *speed = IXGBE_LINK_SPEED_100_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 259 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 260 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 261 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 262 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 263 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 264 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 265 | *negotiation = true; |
| 266 | break; |
| 267 | |
| 268 | case IXGBE_AUTOC_LMS_SGMII_1G_100M: |
| 269 | *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; |
| 270 | *negotiation = false; |
| 271 | break; |
| 272 | |
| 273 | default: |
| 274 | status = IXGBE_ERR_LINK_SETUP; |
| 275 | goto out; |
| 276 | break; |
| 277 | } |
| 278 | |
| 279 | if (hw->phy.multispeed_fiber) { |
| 280 | *speed |= IXGBE_LINK_SPEED_10GB_FULL | |
| 281 | IXGBE_LINK_SPEED_1GB_FULL; |
| 282 | *negotiation = true; |
| 283 | } |
| 284 | |
| 285 | out: |
| 286 | return status; |
| 287 | } |
| 288 | |
| 289 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 290 | * ixgbe_get_media_type_82599 - Get media type |
| 291 | * @hw: pointer to hardware structure |
| 292 | * |
| 293 | * Returns the media type (fiber, copper, backplane) |
| 294 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 295 | static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 296 | { |
| 297 | enum ixgbe_media_type media_type; |
| 298 | |
| 299 | /* Detect if there is a copper PHY attached. */ |
| 300 | if (hw->phy.type == ixgbe_phy_cu_unknown || |
| 301 | hw->phy.type == ixgbe_phy_tn) { |
| 302 | media_type = ixgbe_media_type_copper; |
| 303 | goto out; |
| 304 | } |
| 305 | |
| 306 | switch (hw->device_id) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 307 | case IXGBE_DEV_ID_82599_KX4: |
Don Skidmore | dbfec66 | 2009-10-02 08:58:25 +0000 | [diff] [blame] | 308 | case IXGBE_DEV_ID_82599_KX4_MEZZ: |
Don Skidmore | 312eb93 | 2009-10-02 08:58:04 +0000 | [diff] [blame] | 309 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
Don Skidmore | 74757d4 | 2009-12-08 07:22:23 +0000 | [diff] [blame] | 310 | case IXGBE_DEV_ID_82599_KR: |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 311 | case IXGBE_DEV_ID_82599_XAUI_LOM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 312 | /* Default device ID is mezzanine card KX/KX4 */ |
| 313 | media_type = ixgbe_media_type_backplane; |
| 314 | break; |
| 315 | case IXGBE_DEV_ID_82599_SFP: |
Don Skidmore | 38ad1c8 | 2009-10-08 15:35:58 +0000 | [diff] [blame] | 316 | case IXGBE_DEV_ID_82599_SFP_EM: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 317 | media_type = ixgbe_media_type_fiber; |
| 318 | break; |
Peter P Waskiewicz Jr | 8911184 | 2009-09-14 07:47:49 +0000 | [diff] [blame] | 319 | case IXGBE_DEV_ID_82599_CX4: |
Peter P Waskiewicz Jr | 6b1be19 | 2009-09-14 07:48:10 +0000 | [diff] [blame] | 320 | media_type = ixgbe_media_type_cx4; |
Peter P Waskiewicz Jr | 8911184 | 2009-09-14 07:47:49 +0000 | [diff] [blame] | 321 | break; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 322 | default: |
| 323 | media_type = ixgbe_media_type_unknown; |
| 324 | break; |
| 325 | } |
| 326 | out: |
| 327 | return media_type; |
| 328 | } |
| 329 | |
| 330 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 331 | * ixgbe_start_mac_link_82599 - Setup MAC link settings |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 332 | * @hw: pointer to hardware structure |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 333 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 334 | * |
| 335 | * Configures link settings based on values in the ixgbe_hw struct. |
| 336 | * Restarts the link. Performs autonegotiation if needed. |
| 337 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 338 | static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 339 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 340 | { |
| 341 | u32 autoc_reg; |
| 342 | u32 links_reg; |
| 343 | u32 i; |
| 344 | s32 status = 0; |
| 345 | |
| 346 | /* Restart link */ |
| 347 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 348 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
| 349 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); |
| 350 | |
| 351 | /* Only poll for autoneg to complete if specified to do so */ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 352 | if (autoneg_wait_to_complete) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 353 | if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 354 | IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 355 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 356 | IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 357 | (autoc_reg & IXGBE_AUTOC_LMS_MASK) == |
| 358 | IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 359 | links_reg = 0; /* Just in case Autoneg time = 0 */ |
| 360 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 361 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 362 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 363 | break; |
| 364 | msleep(100); |
| 365 | } |
| 366 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 367 | status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 368 | hw_dbg(hw, "Autoneg did not complete.\n"); |
| 369 | } |
| 370 | } |
| 371 | } |
| 372 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 373 | /* Add delay to filter out noises during initial link setup */ |
| 374 | msleep(50); |
| 375 | |
| 376 | return status; |
| 377 | } |
| 378 | |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 379 | /** |
| 380 | * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser |
| 381 | * @hw: pointer to hardware structure |
| 382 | * |
| 383 | * The base drivers may require better control over SFP+ module |
| 384 | * PHY states. This includes selectively shutting down the Tx |
| 385 | * laser on the PHY, effectively halting physical link. |
| 386 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 387 | static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 388 | { |
| 389 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 390 | |
| 391 | /* Disable tx laser; allow 100us to go dark per spec */ |
| 392 | esdp_reg |= IXGBE_ESDP_SDP3; |
| 393 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 394 | IXGBE_WRITE_FLUSH(hw); |
| 395 | udelay(100); |
| 396 | } |
| 397 | |
| 398 | /** |
| 399 | * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser |
| 400 | * @hw: pointer to hardware structure |
| 401 | * |
| 402 | * The base drivers may require better control over SFP+ module |
| 403 | * PHY states. This includes selectively turning on the Tx |
| 404 | * laser on the PHY, effectively starting physical link. |
| 405 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 406 | static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 407 | { |
| 408 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 409 | |
| 410 | /* Enable tx laser; allow 100ms to light up */ |
| 411 | esdp_reg &= ~IXGBE_ESDP_SDP3; |
| 412 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
| 413 | IXGBE_WRITE_FLUSH(hw); |
| 414 | msleep(100); |
| 415 | } |
| 416 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 417 | /** |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 418 | * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser |
| 419 | * @hw: pointer to hardware structure |
| 420 | * |
| 421 | * When the driver changes the link speeds that it can support, |
| 422 | * it sets autotry_restart to true to indicate that we need to |
| 423 | * initiate a new autotry session with the link partner. To do |
| 424 | * so, we set the speed then disable and re-enable the tx laser, to |
| 425 | * alert the link partner that it also needs to restart autotry on its |
| 426 | * end. This is consistent with true clause 37 autoneg, which also |
| 427 | * involves a loss of signal. |
| 428 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 429 | static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 430 | { |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 431 | hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n"); |
| 432 | |
| 433 | if (hw->mac.autotry_restart) { |
Peter Waskiewicz | 61fac74 | 2010-04-27 00:38:15 +0000 | [diff] [blame] | 434 | ixgbe_disable_tx_laser_multispeed_fiber(hw); |
| 435 | ixgbe_enable_tx_laser_multispeed_fiber(hw); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 436 | hw->mac.autotry_restart = false; |
| 437 | } |
| 438 | } |
| 439 | |
| 440 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 441 | * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 442 | * @hw: pointer to hardware structure |
| 443 | * @speed: new link speed |
| 444 | * @autoneg: true if autonegotiation enabled |
| 445 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 446 | * |
| 447 | * Set the link speed in the AUTOC register and restarts link. |
| 448 | **/ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 449 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, |
| 450 | ixgbe_link_speed speed, |
| 451 | bool autoneg, |
| 452 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 453 | { |
| 454 | s32 status = 0; |
| 455 | ixgbe_link_speed phy_link_speed; |
| 456 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; |
| 457 | u32 speedcnt = 0; |
| 458 | u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); |
| 459 | bool link_up = false; |
| 460 | bool negotiation; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 461 | int i; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 462 | |
| 463 | /* Mask off requested but non-supported speeds */ |
| 464 | hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation); |
| 465 | speed &= phy_link_speed; |
| 466 | |
| 467 | /* |
| 468 | * Try each speed one by one, highest priority first. We do this in |
| 469 | * software because 10gb fiber doesn't support speed autonegotiation. |
| 470 | */ |
| 471 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 472 | speedcnt++; |
| 473 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 474 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 475 | /* If we already have link at this speed, just jump out */ |
| 476 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 477 | |
| 478 | if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up) |
| 479 | goto out; |
| 480 | |
| 481 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 482 | esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); |
| 483 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 484 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 485 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 486 | /* Allow module to change analog characteristics (1G->10G) */ |
| 487 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 488 | |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 489 | status = ixgbe_setup_mac_link_82599(hw, |
| 490 | IXGBE_LINK_SPEED_10GB_FULL, |
| 491 | autoneg, |
| 492 | autoneg_wait_to_complete); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 493 | if (status != 0) |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 494 | return status; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 495 | |
| 496 | /* Flap the tx laser if it has not already been done */ |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 497 | hw->mac.ops.flap_tx_laser(hw); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 498 | |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 499 | /* |
| 500 | * Wait for the controller to acquire link. Per IEEE 802.3ap, |
| 501 | * Section 73.10.2, we may have to wait up to 500ms if KR is |
| 502 | * attempted. 82599 uses the same timing for 10g SFI. |
| 503 | */ |
| 504 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 505 | for (i = 0; i < 5; i++) { |
| 506 | /* Wait for the link partner to also set speed */ |
| 507 | msleep(100); |
| 508 | |
| 509 | /* If we have link, just jump out */ |
| 510 | hw->mac.ops.check_link(hw, &phy_link_speed, |
| 511 | &link_up, false); |
| 512 | if (link_up) |
| 513 | goto out; |
| 514 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 515 | } |
| 516 | |
| 517 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 518 | speedcnt++; |
| 519 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) |
| 520 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 521 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 522 | /* If we already have link at this speed, just jump out */ |
| 523 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 524 | |
| 525 | if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up) |
| 526 | goto out; |
| 527 | |
| 528 | /* Set the module link speed */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 529 | esdp_reg &= ~IXGBE_ESDP_SDP5; |
| 530 | esdp_reg |= IXGBE_ESDP_SDP5_DIR; |
| 531 | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 532 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 533 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 534 | /* Allow module to change analog characteristics (10G->1G) */ |
| 535 | msleep(40); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 536 | |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 537 | status = ixgbe_setup_mac_link_82599(hw, |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 538 | IXGBE_LINK_SPEED_1GB_FULL, |
| 539 | autoneg, |
| 540 | autoneg_wait_to_complete); |
| 541 | if (status != 0) |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 542 | return status; |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 543 | |
| 544 | /* Flap the tx laser if it has not already been done */ |
Mallikarjuna R Chilakala | 1097cd1 | 2010-03-18 14:34:52 +0000 | [diff] [blame] | 545 | hw->mac.ops.flap_tx_laser(hw); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 546 | |
| 547 | /* Wait for the link partner to also set speed */ |
| 548 | msleep(100); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 549 | |
| 550 | /* If we have link, just jump out */ |
| 551 | hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false); |
| 552 | if (link_up) |
| 553 | goto out; |
| 554 | } |
| 555 | |
| 556 | /* |
| 557 | * We didn't get link. Configure back to the highest speed we tried, |
| 558 | * (if there was more than one). We call ourselves back with just the |
| 559 | * single highest speed that the user requested. |
| 560 | */ |
| 561 | if (speedcnt > 1) |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 562 | status = ixgbe_setup_mac_link_multispeed_fiber(hw, |
| 563 | highest_link_speed, |
| 564 | autoneg, |
| 565 | autoneg_wait_to_complete); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 566 | |
| 567 | out: |
Mallikarjuna R Chilakala | c3c7432 | 2009-09-01 13:50:14 +0000 | [diff] [blame] | 568 | /* Set autoneg_advertised value based on input link speed */ |
| 569 | hw->phy.autoneg_advertised = 0; |
| 570 | |
| 571 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 572 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 573 | |
| 574 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 575 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 576 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 577 | return status; |
| 578 | } |
| 579 | |
| 580 | /** |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 581 | * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed |
| 582 | * @hw: pointer to hardware structure |
| 583 | * @speed: new link speed |
| 584 | * @autoneg: true if autonegotiation enabled |
| 585 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 586 | * |
| 587 | * Implements the Intel SmartSpeed algorithm. |
| 588 | **/ |
| 589 | static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, |
| 590 | ixgbe_link_speed speed, bool autoneg, |
| 591 | bool autoneg_wait_to_complete) |
| 592 | { |
| 593 | s32 status = 0; |
| 594 | ixgbe_link_speed link_speed; |
| 595 | s32 i, j; |
| 596 | bool link_up = false; |
| 597 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
Anjali Singhai | c4ee6a5 | 2010-04-27 11:31:25 +0000 | [diff] [blame] | 598 | struct ixgbe_adapter *adapter = hw->back; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 599 | |
| 600 | hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n"); |
| 601 | |
| 602 | /* Set autoneg_advertised value based on input link speed */ |
| 603 | hw->phy.autoneg_advertised = 0; |
| 604 | |
| 605 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 606 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
| 607 | |
| 608 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 609 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 610 | |
| 611 | if (speed & IXGBE_LINK_SPEED_100_FULL) |
| 612 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; |
| 613 | |
| 614 | /* |
| 615 | * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the |
| 616 | * autoneg advertisement if link is unable to be established at the |
| 617 | * highest negotiated rate. This can sometimes happen due to integrity |
| 618 | * issues with the physical media connection. |
| 619 | */ |
| 620 | |
| 621 | /* First, try to get link with full advertisement */ |
| 622 | hw->phy.smart_speed_active = false; |
| 623 | for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { |
| 624 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 625 | autoneg_wait_to_complete); |
| 626 | if (status) |
| 627 | goto out; |
| 628 | |
| 629 | /* |
| 630 | * Wait for the controller to acquire link. Per IEEE 802.3ap, |
| 631 | * Section 73.10.2, we may have to wait up to 500ms if KR is |
| 632 | * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per |
| 633 | * Table 9 in the AN MAS. |
| 634 | */ |
| 635 | for (i = 0; i < 5; i++) { |
| 636 | mdelay(100); |
| 637 | |
| 638 | /* If we have link, just jump out */ |
| 639 | hw->mac.ops.check_link(hw, &link_speed, |
| 640 | &link_up, false); |
| 641 | if (link_up) |
| 642 | goto out; |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | /* |
| 647 | * We didn't get link. If we advertised KR plus one of KX4/KX |
| 648 | * (or BX4/BX), then disable KR and try again. |
| 649 | */ |
| 650 | if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || |
| 651 | ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) |
| 652 | goto out; |
| 653 | |
| 654 | /* Turn SmartSpeed on to disable KR support */ |
| 655 | hw->phy.smart_speed_active = true; |
| 656 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 657 | autoneg_wait_to_complete); |
| 658 | if (status) |
| 659 | goto out; |
| 660 | |
| 661 | /* |
| 662 | * Wait for the controller to acquire link. 600ms will allow for |
| 663 | * the AN link_fail_inhibit_timer as well for multiple cycles of |
| 664 | * parallel detect, both 10g and 1g. This allows for the maximum |
| 665 | * connect attempts as defined in the AN MAS table 73-7. |
| 666 | */ |
| 667 | for (i = 0; i < 6; i++) { |
| 668 | mdelay(100); |
| 669 | |
| 670 | /* If we have link, just jump out */ |
| 671 | hw->mac.ops.check_link(hw, &link_speed, |
| 672 | &link_up, false); |
| 673 | if (link_up) |
| 674 | goto out; |
| 675 | } |
| 676 | |
| 677 | /* We didn't get link. Turn SmartSpeed back off. */ |
| 678 | hw->phy.smart_speed_active = false; |
| 679 | status = ixgbe_setup_mac_link_82599(hw, speed, autoneg, |
| 680 | autoneg_wait_to_complete); |
| 681 | |
| 682 | out: |
Anjali Singhai | c4ee6a5 | 2010-04-27 11:31:25 +0000 | [diff] [blame] | 683 | if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) |
Emil Tantilov | 396e799 | 2010-07-01 20:05:12 +0000 | [diff] [blame] | 684 | e_info(hw, "Smartspeed has downgraded the link speed from " |
Emil Tantilov | 849c454 | 2010-06-03 16:53:41 +0000 | [diff] [blame] | 685 | "the maximum advertised\n"); |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 686 | return status; |
| 687 | } |
| 688 | |
| 689 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 690 | * ixgbe_setup_mac_link_82599 - Set MAC link speed |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 691 | * @hw: pointer to hardware structure |
| 692 | * @speed: new link speed |
| 693 | * @autoneg: true if autonegotiation enabled |
| 694 | * @autoneg_wait_to_complete: true when waiting for completion is needed |
| 695 | * |
| 696 | * Set the link speed in the AUTOC register and restarts link. |
| 697 | **/ |
Emil Tantilov | 5d5b7c3 | 2010-10-12 22:20:59 +0000 | [diff] [blame] | 698 | static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 699 | ixgbe_link_speed speed, bool autoneg, |
| 700 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 701 | { |
| 702 | s32 status = 0; |
| 703 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 704 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 705 | u32 start_autoc = autoc; |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 706 | u32 orig_autoc = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 707 | u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; |
| 708 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 709 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 710 | u32 links_reg; |
| 711 | u32 i; |
| 712 | ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; |
| 713 | |
| 714 | /* Check to see if speed passed in is supported. */ |
| 715 | hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg); |
| 716 | speed &= link_capabilities; |
| 717 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 718 | if (speed == IXGBE_LINK_SPEED_UNKNOWN) { |
| 719 | status = IXGBE_ERR_LINK_SETUP; |
| 720 | goto out; |
| 721 | } |
| 722 | |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 723 | /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ |
| 724 | if (hw->mac.orig_link_settings_stored) |
| 725 | orig_autoc = hw->mac.orig_autoc; |
| 726 | else |
| 727 | orig_autoc = autoc; |
| 728 | |
| 729 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 730 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 731 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 732 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 733 | /* Set KX4/KX/KR support according to speed requested */ |
| 734 | autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); |
| 735 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
PJ Waskiewicz | 1eb99d5 | 2009-04-09 22:28:33 +0000 | [diff] [blame] | 736 | if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 737 | autoc |= IXGBE_AUTOC_KX4_SUPP; |
Don Skidmore | cd7e1f0 | 2009-10-08 15:36:22 +0000 | [diff] [blame] | 738 | if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && |
| 739 | (hw->phy.smart_speed_active == false)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 740 | autoc |= IXGBE_AUTOC_KR_SUPP; |
| 741 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 742 | autoc |= IXGBE_AUTOC_KX_SUPP; |
| 743 | } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && |
| 744 | (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || |
| 745 | link_mode == IXGBE_AUTOC_LMS_1G_AN)) { |
| 746 | /* Switch from 1G SFI to 10G SFI if requested */ |
| 747 | if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && |
| 748 | (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { |
| 749 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 750 | autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; |
| 751 | } |
| 752 | } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && |
| 753 | (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { |
| 754 | /* Switch from 10G SFI to 1G SFI if requested */ |
| 755 | if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && |
| 756 | (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { |
| 757 | autoc &= ~IXGBE_AUTOC_LMS_MASK; |
| 758 | if (autoneg) |
| 759 | autoc |= IXGBE_AUTOC_LMS_1G_AN; |
| 760 | else |
| 761 | autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; |
| 762 | } |
| 763 | } |
| 764 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 765 | if (autoc != start_autoc) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 766 | /* Restart link */ |
| 767 | autoc |= IXGBE_AUTOC_AN_RESTART; |
| 768 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); |
| 769 | |
| 770 | /* Only poll for autoneg to complete if specified to do so */ |
| 771 | if (autoneg_wait_to_complete) { |
| 772 | if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || |
| 773 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || |
| 774 | link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { |
| 775 | links_reg = 0; /*Just in case Autoneg time=0*/ |
| 776 | for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { |
| 777 | links_reg = |
| 778 | IXGBE_READ_REG(hw, IXGBE_LINKS); |
| 779 | if (links_reg & IXGBE_LINKS_KX_AN_COMP) |
| 780 | break; |
| 781 | msleep(100); |
| 782 | } |
| 783 | if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { |
| 784 | status = |
| 785 | IXGBE_ERR_AUTONEG_NOT_COMPLETE; |
| 786 | hw_dbg(hw, "Autoneg did not " |
| 787 | "complete.\n"); |
| 788 | } |
| 789 | } |
| 790 | } |
| 791 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 792 | /* Add delay to filter out noises during initial link setup */ |
| 793 | msleep(50); |
| 794 | } |
| 795 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 796 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 797 | return status; |
| 798 | } |
| 799 | |
| 800 | /** |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 801 | * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 802 | * @hw: pointer to hardware structure |
| 803 | * @speed: new link speed |
| 804 | * @autoneg: true if autonegotiation enabled |
| 805 | * @autoneg_wait_to_complete: true if waiting is needed to complete |
| 806 | * |
| 807 | * Restarts link on PHY and MAC based on settings passed in. |
| 808 | **/ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 809 | static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, |
| 810 | ixgbe_link_speed speed, |
| 811 | bool autoneg, |
| 812 | bool autoneg_wait_to_complete) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 813 | { |
| 814 | s32 status; |
| 815 | |
| 816 | /* Setup the PHY according to input speed */ |
| 817 | status = hw->phy.ops.setup_link_speed(hw, speed, autoneg, |
| 818 | autoneg_wait_to_complete); |
| 819 | /* Set up MAC */ |
Mallikarjuna R Chilakala | 8620a10 | 2009-09-01 13:49:35 +0000 | [diff] [blame] | 820 | ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 821 | |
| 822 | return status; |
| 823 | } |
| 824 | |
| 825 | /** |
| 826 | * ixgbe_reset_hw_82599 - Perform hardware reset |
| 827 | * @hw: pointer to hardware structure |
| 828 | * |
| 829 | * Resets the hardware by resetting the transmit and receive units, masks |
| 830 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) |
| 831 | * reset. |
| 832 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 833 | static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 834 | { |
| 835 | s32 status = 0; |
Greg Rose | c920569 | 2010-01-22 22:46:22 +0000 | [diff] [blame] | 836 | u32 ctrl; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 837 | u32 i; |
| 838 | u32 autoc; |
| 839 | u32 autoc2; |
| 840 | |
| 841 | /* Call adapter stop to disable tx/rx and clear interrupts */ |
| 842 | hw->mac.ops.stop_adapter(hw); |
| 843 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 844 | /* PHY ops must be identified and initialized prior to reset */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 845 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 846 | /* Init PHY and function pointers, perform SFP setup */ |
| 847 | status = hw->phy.ops.init(hw); |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 848 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 849 | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) |
| 850 | goto reset_hw_out; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 851 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 852 | /* Setup SFP module if there is one present. */ |
| 853 | if (hw->phy.sfp_setup_needed) { |
| 854 | status = hw->mac.ops.setup_sfp(hw); |
| 855 | hw->phy.sfp_setup_needed = false; |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 856 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 857 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 858 | /* Reset PHY */ |
| 859 | if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) |
| 860 | hw->phy.ops.reset(hw); |
| 861 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 862 | /* |
| 863 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master |
| 864 | * access and verify no pending requests before reset |
| 865 | */ |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 866 | status = ixgbe_disable_pcie_master(hw); |
| 867 | if (status != 0) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 868 | status = IXGBE_ERR_MASTER_REQUESTS_PENDING; |
| 869 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); |
| 870 | } |
| 871 | |
| 872 | /* |
| 873 | * Issue global reset to the MAC. This needs to be a SW reset. |
| 874 | * If link reset is used, it might reset the MAC when mng is using it |
| 875 | */ |
| 876 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 877 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST)); |
| 878 | IXGBE_WRITE_FLUSH(hw); |
| 879 | |
| 880 | /* Poll for reset bit to self-clear indicating reset is complete */ |
| 881 | for (i = 0; i < 10; i++) { |
| 882 | udelay(1); |
| 883 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); |
| 884 | if (!(ctrl & IXGBE_CTRL_RST)) |
| 885 | break; |
| 886 | } |
| 887 | if (ctrl & IXGBE_CTRL_RST) { |
| 888 | status = IXGBE_ERR_RESET_FAILED; |
| 889 | hw_dbg(hw, "Reset polling failed to complete.\n"); |
| 890 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 891 | |
| 892 | msleep(50); |
| 893 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 894 | /* |
| 895 | * Store the original AUTOC/AUTOC2 values if they have not been |
| 896 | * stored off yet. Otherwise restore the stored original |
| 897 | * values since the reset operation sets back to defaults. |
| 898 | */ |
| 899 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 900 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 901 | if (hw->mac.orig_link_settings_stored == false) { |
| 902 | hw->mac.orig_autoc = autoc; |
| 903 | hw->mac.orig_autoc2 = autoc2; |
| 904 | hw->mac.orig_link_settings_stored = true; |
Jesse Brandeburg | 4df1046 | 2009-03-13 22:15:31 +0000 | [diff] [blame] | 905 | } else { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 906 | if (autoc != hw->mac.orig_autoc) |
| 907 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | |
| 908 | IXGBE_AUTOC_AN_RESTART)); |
| 909 | |
| 910 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != |
| 911 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { |
| 912 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; |
| 913 | autoc2 |= (hw->mac.orig_autoc2 & |
| 914 | IXGBE_AUTOC2_UPPER_MASK); |
| 915 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); |
| 916 | } |
| 917 | } |
| 918 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 919 | /* |
| 920 | * Store MAC address from RAR0, clear receive address registers, and |
| 921 | * clear the multicast table. Also reset num_rar_entries to 128, |
| 922 | * since we modify this value when programming the SAN MAC address. |
| 923 | */ |
| 924 | hw->mac.num_rar_entries = 128; |
| 925 | hw->mac.ops.init_rx_addrs(hw); |
| 926 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 927 | /* Store the permanent mac address */ |
| 928 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); |
| 929 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 930 | /* Store the permanent SAN mac address */ |
| 931 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); |
| 932 | |
Waskiewicz Jr, Peter P | aca6bee | 2009-05-17 12:32:48 +0000 | [diff] [blame] | 933 | /* Add the SAN MAC address to the RAR only if it's a valid address */ |
| 934 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { |
| 935 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, |
| 936 | hw->mac.san_addr, 0, IXGBE_RAH_AV); |
| 937 | |
| 938 | /* Reserve the last RAR for the SAN MAC address */ |
| 939 | hw->mac.num_rar_entries--; |
| 940 | } |
| 941 | |
Yi Zou | 383ff34 | 2009-10-28 18:23:57 +0000 | [diff] [blame] | 942 | /* Store the alternative WWNN/WWPN prefix */ |
| 943 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, |
| 944 | &hw->mac.wwpn_prefix); |
| 945 | |
PJ Waskiewicz | 04f165e | 2009-04-09 22:27:57 +0000 | [diff] [blame] | 946 | reset_hw_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 947 | return status; |
| 948 | } |
| 949 | |
| 950 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 951 | * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables. |
| 952 | * @hw: pointer to hardware structure |
| 953 | **/ |
| 954 | s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) |
| 955 | { |
| 956 | int i; |
| 957 | u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); |
| 958 | fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE; |
| 959 | |
| 960 | /* |
| 961 | * Before starting reinitialization process, |
| 962 | * FDIRCMD.CMD must be zero. |
| 963 | */ |
| 964 | for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) { |
| 965 | if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 966 | IXGBE_FDIRCMD_CMD_MASK)) |
| 967 | break; |
| 968 | udelay(10); |
| 969 | } |
| 970 | if (i >= IXGBE_FDIRCMD_CMD_POLL) { |
| 971 | hw_dbg(hw ,"Flow Director previous command isn't complete, " |
Frans Pop | d6dbee8 | 2010-03-24 07:57:35 +0000 | [diff] [blame] | 972 | "aborting table re-initialization.\n"); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 973 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 974 | } |
| 975 | |
| 976 | IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); |
| 977 | IXGBE_WRITE_FLUSH(hw); |
| 978 | /* |
| 979 | * 82599 adapters flow director init flow cannot be restarted, |
| 980 | * Workaround 82599 silicon errata by performing the following steps |
| 981 | * before re-writing the FDIRCTRL control register with the same value. |
| 982 | * - write 1 to bit 8 of FDIRCMD register & |
| 983 | * - write 0 to bit 8 of FDIRCMD register |
| 984 | */ |
| 985 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 986 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | |
| 987 | IXGBE_FDIRCMD_CLEARHT)); |
| 988 | IXGBE_WRITE_FLUSH(hw); |
| 989 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, |
| 990 | (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & |
| 991 | ~IXGBE_FDIRCMD_CLEARHT)); |
| 992 | IXGBE_WRITE_FLUSH(hw); |
| 993 | /* |
| 994 | * Clear FDIR Hash register to clear any leftover hashes |
| 995 | * waiting to be programmed. |
| 996 | */ |
| 997 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); |
| 998 | IXGBE_WRITE_FLUSH(hw); |
| 999 | |
| 1000 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1001 | IXGBE_WRITE_FLUSH(hw); |
| 1002 | |
| 1003 | /* Poll init-done after we write FDIRCTRL register */ |
| 1004 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1005 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1006 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1007 | break; |
| 1008 | udelay(10); |
| 1009 | } |
| 1010 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) { |
| 1011 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1012 | return IXGBE_ERR_FDIR_REINIT_FAILED; |
| 1013 | } |
| 1014 | |
| 1015 | /* Clear FDIR statistics registers (read to clear) */ |
| 1016 | IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); |
| 1017 | IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); |
| 1018 | IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
| 1019 | IXGBE_READ_REG(hw, IXGBE_FDIRMISS); |
| 1020 | IXGBE_READ_REG(hw, IXGBE_FDIRLEN); |
| 1021 | |
| 1022 | return 0; |
| 1023 | } |
| 1024 | |
| 1025 | /** |
| 1026 | * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters |
| 1027 | * @hw: pointer to hardware structure |
| 1028 | * @pballoc: which mode to allocate filters with |
| 1029 | **/ |
| 1030 | s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1031 | { |
| 1032 | u32 fdirctrl = 0; |
| 1033 | u32 pbsize; |
| 1034 | int i; |
| 1035 | |
| 1036 | /* |
| 1037 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1038 | * must be reduced. The new value is the current size minus |
| 1039 | * flow director memory usage size. |
| 1040 | */ |
| 1041 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1042 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1043 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1044 | |
| 1045 | /* |
| 1046 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
| 1047 | * intialized to zero for non DCB mode otherwise actual total RX PB |
| 1048 | * would be bigger than programmed and filter space would run into |
| 1049 | * the PB 0 region. |
| 1050 | */ |
| 1051 | for (i = 1; i < 8; i++) |
| 1052 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1053 | |
| 1054 | /* Send interrupt when 64 filters are left */ |
| 1055 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1056 | |
| 1057 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1058 | fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT; |
| 1059 | |
| 1060 | switch (pballoc) { |
| 1061 | case IXGBE_FDIR_PBALLOC_64K: |
| 1062 | /* 8k - 1 signature filters */ |
| 1063 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1064 | break; |
| 1065 | case IXGBE_FDIR_PBALLOC_128K: |
| 1066 | /* 16k - 1 signature filters */ |
| 1067 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1068 | break; |
| 1069 | case IXGBE_FDIR_PBALLOC_256K: |
| 1070 | /* 32k - 1 signature filters */ |
| 1071 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1072 | break; |
| 1073 | default: |
| 1074 | /* bad value */ |
| 1075 | return IXGBE_ERR_CONFIG; |
| 1076 | }; |
| 1077 | |
| 1078 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1079 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1080 | |
| 1081 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; |
| 1082 | |
| 1083 | /* Prime the keys for hashing */ |
| 1084 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, |
| 1085 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); |
| 1086 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, |
| 1087 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); |
| 1088 | |
| 1089 | /* |
| 1090 | * Poll init-done after we write the register. Estimated times: |
| 1091 | * 10G: PBALLOC = 11b, timing is 60us |
| 1092 | * 1G: PBALLOC = 11b, timing is 600us |
| 1093 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1094 | * |
| 1095 | * Multiple these timings by 4 if under full Rx load |
| 1096 | * |
| 1097 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1098 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1099 | * this might not finish in our poll time, but we can live with that |
| 1100 | * for now. |
| 1101 | */ |
| 1102 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1103 | IXGBE_WRITE_FLUSH(hw); |
| 1104 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1105 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1106 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1107 | break; |
| 1108 | msleep(1); |
| 1109 | } |
| 1110 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1111 | hw_dbg(hw, "Flow Director Signature poll time exceeded!\n"); |
| 1112 | |
| 1113 | return 0; |
| 1114 | } |
| 1115 | |
| 1116 | /** |
| 1117 | * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters |
| 1118 | * @hw: pointer to hardware structure |
| 1119 | * @pballoc: which mode to allocate filters with |
| 1120 | **/ |
| 1121 | s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc) |
| 1122 | { |
| 1123 | u32 fdirctrl = 0; |
| 1124 | u32 pbsize; |
| 1125 | int i; |
| 1126 | |
| 1127 | /* |
| 1128 | * Before enabling Flow Director, the Rx Packet Buffer size |
| 1129 | * must be reduced. The new value is the current size minus |
| 1130 | * flow director memory usage size. |
| 1131 | */ |
| 1132 | pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc)); |
| 1133 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), |
| 1134 | (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize)); |
| 1135 | |
| 1136 | /* |
| 1137 | * The defaults in the HW for RX PB 1-7 are not zero and so should be |
| 1138 | * intialized to zero for non DCB mode otherwise actual total RX PB |
| 1139 | * would be bigger than programmed and filter space would run into |
| 1140 | * the PB 0 region. |
| 1141 | */ |
| 1142 | for (i = 1; i < 8; i++) |
| 1143 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); |
| 1144 | |
| 1145 | /* Send interrupt when 64 filters are left */ |
| 1146 | fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT; |
| 1147 | |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1148 | /* Initialize the drop queue to Rx queue 127 */ |
| 1149 | fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT); |
| 1150 | |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1151 | switch (pballoc) { |
| 1152 | case IXGBE_FDIR_PBALLOC_64K: |
| 1153 | /* 2k - 1 perfect filters */ |
| 1154 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K; |
| 1155 | break; |
| 1156 | case IXGBE_FDIR_PBALLOC_128K: |
| 1157 | /* 4k - 1 perfect filters */ |
| 1158 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K; |
| 1159 | break; |
| 1160 | case IXGBE_FDIR_PBALLOC_256K: |
| 1161 | /* 8k - 1 perfect filters */ |
| 1162 | fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K; |
| 1163 | break; |
| 1164 | default: |
| 1165 | /* bad value */ |
| 1166 | return IXGBE_ERR_CONFIG; |
| 1167 | }; |
| 1168 | |
| 1169 | /* Turn perfect match filtering on */ |
| 1170 | fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH; |
| 1171 | fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS; |
| 1172 | |
| 1173 | /* Move the flexible bytes to use the ethertype - shift 6 words */ |
| 1174 | fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT); |
| 1175 | |
| 1176 | /* Prime the keys for hashing */ |
| 1177 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, |
| 1178 | htonl(IXGBE_ATR_BUCKET_HASH_KEY)); |
| 1179 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, |
| 1180 | htonl(IXGBE_ATR_SIGNATURE_HASH_KEY)); |
| 1181 | |
| 1182 | /* |
| 1183 | * Poll init-done after we write the register. Estimated times: |
| 1184 | * 10G: PBALLOC = 11b, timing is 60us |
| 1185 | * 1G: PBALLOC = 11b, timing is 600us |
| 1186 | * 100M: PBALLOC = 11b, timing is 6ms |
| 1187 | * |
| 1188 | * Multiple these timings by 4 if under full Rx load |
| 1189 | * |
| 1190 | * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for |
| 1191 | * 1 msec per poll time. If we're at line rate and drop to 100M, then |
| 1192 | * this might not finish in our poll time, but we can live with that |
| 1193 | * for now. |
| 1194 | */ |
| 1195 | |
| 1196 | /* Set the maximum length per hash bucket to 0xA filters */ |
| 1197 | fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT); |
| 1198 | |
| 1199 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); |
| 1200 | IXGBE_WRITE_FLUSH(hw); |
| 1201 | for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) { |
| 1202 | if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & |
| 1203 | IXGBE_FDIRCTRL_INIT_DONE) |
| 1204 | break; |
| 1205 | msleep(1); |
| 1206 | } |
| 1207 | if (i >= IXGBE_FDIR_INIT_DONE_POLL) |
| 1208 | hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n"); |
| 1209 | |
| 1210 | return 0; |
| 1211 | } |
| 1212 | |
| 1213 | |
| 1214 | /** |
| 1215 | * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR |
| 1216 | * @stream: input bitstream to compute the hash on |
| 1217 | * @key: 32-bit hash key |
| 1218 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1219 | static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, |
| 1220 | u32 key) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1221 | { |
| 1222 | /* |
| 1223 | * The algorithm is as follows: |
| 1224 | * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350 |
| 1225 | * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n] |
| 1226 | * and A[n] x B[n] is bitwise AND between same length strings |
| 1227 | * |
| 1228 | * K[n] is 16 bits, defined as: |
| 1229 | * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15] |
| 1230 | * for n modulo 32 < 15, K[n] = |
| 1231 | * K[(n % 32:0) | (31:31 - (14 - (n % 32)))] |
| 1232 | * |
| 1233 | * S[n] is 16 bits, defined as: |
| 1234 | * for n >= 15, S[n] = S[n:n - 15] |
| 1235 | * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))] |
| 1236 | * |
| 1237 | * To simplify for programming, the algorithm is implemented |
| 1238 | * in software this way: |
| 1239 | * |
| 1240 | * Key[31:0], Stream[335:0] |
| 1241 | * |
| 1242 | * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times |
| 1243 | * int_key[350:0] = tmp_key[351:1] |
| 1244 | * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321] |
| 1245 | * |
| 1246 | * hash[15:0] = 0; |
| 1247 | * for (i = 0; i < 351; i++) { |
| 1248 | * if (int_key[i]) |
| 1249 | * hash ^= int_stream[(i + 15):i]; |
| 1250 | * } |
| 1251 | */ |
| 1252 | |
| 1253 | union { |
| 1254 | u64 fill[6]; |
| 1255 | u32 key[11]; |
| 1256 | u8 key_stream[44]; |
| 1257 | } tmp_key; |
| 1258 | |
| 1259 | u8 *stream = (u8 *)atr_input; |
| 1260 | u8 int_key[44]; /* upper-most bit unused */ |
| 1261 | u8 hash_str[46]; /* upper-most 2 bits unused */ |
| 1262 | u16 hash_result = 0; |
| 1263 | int i, j, k, h; |
| 1264 | |
| 1265 | /* |
| 1266 | * Initialize the fill member to prevent warnings |
| 1267 | * on some compilers |
| 1268 | */ |
| 1269 | tmp_key.fill[0] = 0; |
| 1270 | |
| 1271 | /* First load the temporary key stream */ |
| 1272 | for (i = 0; i < 6; i++) { |
| 1273 | u64 fillkey = ((u64)key << 32) | key; |
| 1274 | tmp_key.fill[i] = fillkey; |
| 1275 | } |
| 1276 | |
| 1277 | /* |
| 1278 | * Set the interim key for the hashing. Bit 352 is unused, so we must |
| 1279 | * shift and compensate when building the key. |
| 1280 | */ |
| 1281 | |
| 1282 | int_key[0] = tmp_key.key_stream[0] >> 1; |
| 1283 | for (i = 1, j = 0; i < 44; i++) { |
| 1284 | unsigned int this_key = tmp_key.key_stream[j] << 7; |
| 1285 | j++; |
| 1286 | int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1)); |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * Set the interim bit string for the hashing. Bits 368 and 367 are |
| 1291 | * unused, so shift and compensate when building the string. |
| 1292 | */ |
| 1293 | hash_str[0] = (stream[40] & 0x7f) >> 1; |
| 1294 | for (i = 1, j = 40; i < 46; i++) { |
| 1295 | unsigned int this_str = stream[j] << 7; |
| 1296 | j++; |
| 1297 | if (j > 41) |
| 1298 | j = 0; |
| 1299 | hash_str[i] = (u8)(this_str | (stream[j] >> 1)); |
| 1300 | } |
| 1301 | |
| 1302 | /* |
| 1303 | * Now compute the hash. i is the index into hash_str, j is into our |
| 1304 | * key stream, k is counting the number of bits, and h interates within |
| 1305 | * each byte. |
| 1306 | */ |
| 1307 | for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) { |
| 1308 | for (h = 0; h < 8 && k < 351; h++, k++) { |
| 1309 | if (int_key[j] & (1 << h)) { |
| 1310 | /* |
| 1311 | * Key bit is set, XOR in the current 16-bit |
| 1312 | * string. Example of processing: |
| 1313 | * h = 0, |
| 1314 | * tmp = (hash_str[i - 2] & 0 << 16) | |
| 1315 | * (hash_str[i - 1] & 0xff << 8) | |
| 1316 | * (hash_str[i] & 0xff >> 0) |
| 1317 | * So tmp = hash_str[15 + k:k], since the |
| 1318 | * i + 2 clause rolls off the 16-bit value |
| 1319 | * h = 7, |
| 1320 | * tmp = (hash_str[i - 2] & 0x7f << 9) | |
| 1321 | * (hash_str[i - 1] & 0xff << 1) | |
| 1322 | * (hash_str[i] & 0x80 >> 7) |
| 1323 | */ |
| 1324 | int tmp = (hash_str[i] >> h); |
| 1325 | tmp |= (hash_str[i - 1] << (8 - h)); |
| 1326 | tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1)) |
| 1327 | << (16 - h); |
| 1328 | hash_result ^= (u16)tmp; |
| 1329 | } |
| 1330 | } |
| 1331 | } |
| 1332 | |
| 1333 | return hash_result; |
| 1334 | } |
| 1335 | |
| 1336 | /** |
| 1337 | * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream |
| 1338 | * @input: input stream to modify |
| 1339 | * @vlan: the VLAN id to load |
| 1340 | **/ |
| 1341 | s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan) |
| 1342 | { |
| 1343 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8; |
| 1344 | input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff; |
| 1345 | |
| 1346 | return 0; |
| 1347 | } |
| 1348 | |
| 1349 | /** |
| 1350 | * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address |
| 1351 | * @input: input stream to modify |
| 1352 | * @src_addr: the IP address to load |
| 1353 | **/ |
| 1354 | s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr) |
| 1355 | { |
| 1356 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24; |
| 1357 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] = |
| 1358 | (src_addr >> 16) & 0xff; |
| 1359 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] = |
| 1360 | (src_addr >> 8) & 0xff; |
| 1361 | input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff; |
| 1362 | |
| 1363 | return 0; |
| 1364 | } |
| 1365 | |
| 1366 | /** |
| 1367 | * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address |
| 1368 | * @input: input stream to modify |
| 1369 | * @dst_addr: the IP address to load |
| 1370 | **/ |
| 1371 | s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr) |
| 1372 | { |
| 1373 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24; |
| 1374 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] = |
| 1375 | (dst_addr >> 16) & 0xff; |
| 1376 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] = |
| 1377 | (dst_addr >> 8) & 0xff; |
| 1378 | input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff; |
| 1379 | |
| 1380 | return 0; |
| 1381 | } |
| 1382 | |
| 1383 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1384 | * ixgbe_atr_set_src_port_82599 - Sets the source port |
| 1385 | * @input: input stream to modify |
| 1386 | * @src_port: the source port to load |
| 1387 | **/ |
| 1388 | s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port) |
| 1389 | { |
| 1390 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8; |
| 1391 | input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff; |
| 1392 | |
| 1393 | return 0; |
| 1394 | } |
| 1395 | |
| 1396 | /** |
| 1397 | * ixgbe_atr_set_dst_port_82599 - Sets the destination port |
| 1398 | * @input: input stream to modify |
| 1399 | * @dst_port: the destination port to load |
| 1400 | **/ |
| 1401 | s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port) |
| 1402 | { |
| 1403 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8; |
| 1404 | input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff; |
| 1405 | |
| 1406 | return 0; |
| 1407 | } |
| 1408 | |
| 1409 | /** |
| 1410 | * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes |
| 1411 | * @input: input stream to modify |
| 1412 | * @flex_bytes: the flexible bytes to load |
| 1413 | **/ |
| 1414 | s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte) |
| 1415 | { |
| 1416 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8; |
| 1417 | input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff; |
| 1418 | |
| 1419 | return 0; |
| 1420 | } |
| 1421 | |
| 1422 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1423 | * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type |
| 1424 | * @input: input stream to modify |
| 1425 | * @l4type: the layer 4 type value to load |
| 1426 | **/ |
| 1427 | s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type) |
| 1428 | { |
| 1429 | input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type; |
| 1430 | |
| 1431 | return 0; |
| 1432 | } |
| 1433 | |
| 1434 | /** |
| 1435 | * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream |
| 1436 | * @input: input stream to search |
| 1437 | * @vlan: the VLAN id to load |
| 1438 | **/ |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1439 | static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1440 | { |
| 1441 | *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET]; |
| 1442 | *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8; |
| 1443 | |
| 1444 | return 0; |
| 1445 | } |
| 1446 | |
| 1447 | /** |
| 1448 | * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address |
| 1449 | * @input: input stream to search |
| 1450 | * @src_addr: the IP address to load |
| 1451 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1452 | static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, |
| 1453 | u32 *src_addr) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1454 | { |
| 1455 | *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET]; |
| 1456 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8; |
| 1457 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16; |
| 1458 | *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24; |
| 1459 | |
| 1460 | return 0; |
| 1461 | } |
| 1462 | |
| 1463 | /** |
| 1464 | * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address |
| 1465 | * @input: input stream to search |
| 1466 | * @dst_addr: the IP address to load |
| 1467 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1468 | static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, |
| 1469 | u32 *dst_addr) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1470 | { |
| 1471 | *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET]; |
| 1472 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8; |
| 1473 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16; |
| 1474 | *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24; |
| 1475 | |
| 1476 | return 0; |
| 1477 | } |
| 1478 | |
| 1479 | /** |
| 1480 | * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address |
| 1481 | * @input: input stream to search |
| 1482 | * @src_addr_1: the first 4 bytes of the IP address to load |
| 1483 | * @src_addr_2: the second 4 bytes of the IP address to load |
| 1484 | * @src_addr_3: the third 4 bytes of the IP address to load |
| 1485 | * @src_addr_4: the fourth 4 bytes of the IP address to load |
| 1486 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1487 | static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, |
| 1488 | u32 *src_addr_1, u32 *src_addr_2, |
| 1489 | u32 *src_addr_3, u32 *src_addr_4) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1490 | { |
| 1491 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12]; |
| 1492 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8; |
| 1493 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16; |
| 1494 | *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24; |
| 1495 | |
| 1496 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8]; |
| 1497 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8; |
| 1498 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16; |
| 1499 | *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24; |
| 1500 | |
| 1501 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4]; |
| 1502 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8; |
| 1503 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16; |
| 1504 | *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24; |
| 1505 | |
| 1506 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET]; |
| 1507 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8; |
| 1508 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16; |
| 1509 | *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24; |
| 1510 | |
| 1511 | return 0; |
| 1512 | } |
| 1513 | |
| 1514 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1515 | * ixgbe_atr_get_src_port_82599 - Gets the source port |
| 1516 | * @input: input stream to modify |
| 1517 | * @src_port: the source port to load |
| 1518 | * |
| 1519 | * Even though the input is given in big-endian, the FDIRPORT registers |
| 1520 | * expect the ports to be programmed in little-endian. Hence the need to swap |
| 1521 | * endianness when retrieving the data. This can be confusing since the |
| 1522 | * internal hash engine expects it to be big-endian. |
| 1523 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1524 | static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, |
| 1525 | u16 *src_port) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1526 | { |
| 1527 | *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8; |
| 1528 | *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1]; |
| 1529 | |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | /** |
| 1534 | * ixgbe_atr_get_dst_port_82599 - Gets the destination port |
| 1535 | * @input: input stream to modify |
| 1536 | * @dst_port: the destination port to load |
| 1537 | * |
| 1538 | * Even though the input is given in big-endian, the FDIRPORT registers |
| 1539 | * expect the ports to be programmed in little-endian. Hence the need to swap |
| 1540 | * endianness when retrieving the data. This can be confusing since the |
| 1541 | * internal hash engine expects it to be big-endian. |
| 1542 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1543 | static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, |
| 1544 | u16 *dst_port) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1545 | { |
| 1546 | *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8; |
| 1547 | *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1]; |
| 1548 | |
| 1549 | return 0; |
| 1550 | } |
| 1551 | |
| 1552 | /** |
| 1553 | * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes |
| 1554 | * @input: input stream to modify |
| 1555 | * @flex_bytes: the flexible bytes to load |
| 1556 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1557 | static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, |
| 1558 | u16 *flex_byte) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1559 | { |
| 1560 | *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET]; |
| 1561 | *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8; |
| 1562 | |
| 1563 | return 0; |
| 1564 | } |
| 1565 | |
| 1566 | /** |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1567 | * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type |
| 1568 | * @input: input stream to modify |
| 1569 | * @l4type: the layer 4 type value to load |
| 1570 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1571 | static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, |
| 1572 | u8 *l4type) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1573 | { |
| 1574 | *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET]; |
| 1575 | |
| 1576 | return 0; |
| 1577 | } |
| 1578 | |
| 1579 | /** |
| 1580 | * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter |
| 1581 | * @hw: pointer to hardware structure |
| 1582 | * @stream: input bitstream |
| 1583 | * @queue: queue index to direct traffic to |
| 1584 | **/ |
| 1585 | s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
| 1586 | struct ixgbe_atr_input *input, |
| 1587 | u8 queue) |
| 1588 | { |
| 1589 | u64 fdirhashcmd; |
| 1590 | u64 fdircmd; |
| 1591 | u32 fdirhash; |
| 1592 | u16 bucket_hash, sig_hash; |
| 1593 | u8 l4type; |
| 1594 | |
| 1595 | bucket_hash = ixgbe_atr_compute_hash_82599(input, |
| 1596 | IXGBE_ATR_BUCKET_HASH_KEY); |
| 1597 | |
| 1598 | /* bucket_hash is only 15 bits */ |
| 1599 | bucket_hash &= IXGBE_ATR_HASH_MASK; |
| 1600 | |
| 1601 | sig_hash = ixgbe_atr_compute_hash_82599(input, |
| 1602 | IXGBE_ATR_SIGNATURE_HASH_KEY); |
| 1603 | |
| 1604 | /* Get the l4type in order to program FDIRCMD properly */ |
| 1605 | /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */ |
| 1606 | ixgbe_atr_get_l4type_82599(input, &l4type); |
| 1607 | |
| 1608 | /* |
| 1609 | * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits |
| 1610 | * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. |
| 1611 | */ |
| 1612 | fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; |
| 1613 | |
| 1614 | fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE | |
| 1615 | IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN); |
| 1616 | |
| 1617 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { |
| 1618 | case IXGBE_ATR_L4TYPE_TCP: |
| 1619 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; |
| 1620 | break; |
| 1621 | case IXGBE_ATR_L4TYPE_UDP: |
| 1622 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; |
| 1623 | break; |
| 1624 | case IXGBE_ATR_L4TYPE_SCTP: |
| 1625 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; |
| 1626 | break; |
| 1627 | default: |
| 1628 | hw_dbg(hw, "Error on l4type input\n"); |
| 1629 | return IXGBE_ERR_CONFIG; |
| 1630 | } |
| 1631 | |
| 1632 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) |
| 1633 | fdircmd |= IXGBE_FDIRCMD_IPV6; |
| 1634 | |
| 1635 | fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT); |
| 1636 | fdirhashcmd = ((fdircmd << 32) | fdirhash); |
| 1637 | |
| 1638 | IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); |
| 1639 | |
| 1640 | return 0; |
| 1641 | } |
| 1642 | |
| 1643 | /** |
| 1644 | * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter |
| 1645 | * @hw: pointer to hardware structure |
| 1646 | * @input: input bitstream |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1647 | * @input_masks: bitwise masks for relevant fields |
| 1648 | * @soft_id: software index into the silicon hash tables for filter storage |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1649 | * @queue: queue index to direct traffic to |
| 1650 | * |
| 1651 | * Note that the caller to this function must lock before calling, since the |
| 1652 | * hardware writes must be protected from one another. |
| 1653 | **/ |
| 1654 | s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1655 | struct ixgbe_atr_input *input, |
| 1656 | struct ixgbe_atr_input_masks *input_masks, |
| 1657 | u16 soft_id, u8 queue) |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1658 | { |
| 1659 | u32 fdircmd = 0; |
| 1660 | u32 fdirhash; |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1661 | u32 src_ipv4 = 0, dst_ipv4 = 0; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1662 | u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4; |
| 1663 | u16 src_port, dst_port, vlan_id, flex_bytes; |
| 1664 | u16 bucket_hash; |
| 1665 | u8 l4type; |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1666 | u8 fdirm = 0; |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1667 | |
| 1668 | /* Get our input values */ |
| 1669 | ixgbe_atr_get_l4type_82599(input, &l4type); |
| 1670 | |
| 1671 | /* |
| 1672 | * Check l4type formatting, and bail out before we touch the hardware |
| 1673 | * if there's a configuration issue |
| 1674 | */ |
| 1675 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { |
| 1676 | case IXGBE_ATR_L4TYPE_TCP: |
| 1677 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP; |
| 1678 | break; |
| 1679 | case IXGBE_ATR_L4TYPE_UDP: |
| 1680 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP; |
| 1681 | break; |
| 1682 | case IXGBE_ATR_L4TYPE_SCTP: |
| 1683 | fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP; |
| 1684 | break; |
| 1685 | default: |
| 1686 | hw_dbg(hw, "Error on l4type input\n"); |
| 1687 | return IXGBE_ERR_CONFIG; |
| 1688 | } |
| 1689 | |
| 1690 | bucket_hash = ixgbe_atr_compute_hash_82599(input, |
| 1691 | IXGBE_ATR_BUCKET_HASH_KEY); |
| 1692 | |
| 1693 | /* bucket_hash is only 15 bits */ |
| 1694 | bucket_hash &= IXGBE_ATR_HASH_MASK; |
| 1695 | |
| 1696 | ixgbe_atr_get_vlan_id_82599(input, &vlan_id); |
| 1697 | ixgbe_atr_get_src_port_82599(input, &src_port); |
| 1698 | ixgbe_atr_get_dst_port_82599(input, &dst_port); |
| 1699 | ixgbe_atr_get_flex_byte_82599(input, &flex_bytes); |
| 1700 | |
| 1701 | fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash; |
| 1702 | |
| 1703 | /* Now figure out if we're IPv4 or IPv6 */ |
| 1704 | if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) { |
| 1705 | /* IPv6 */ |
| 1706 | ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2, |
| 1707 | &src_ipv6_3, &src_ipv6_4); |
| 1708 | |
| 1709 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1); |
| 1710 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2); |
| 1711 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3); |
| 1712 | /* The last 4 bytes is the same register as IPv4 */ |
| 1713 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4); |
| 1714 | |
| 1715 | fdircmd |= IXGBE_FDIRCMD_IPV6; |
| 1716 | fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH; |
| 1717 | } else { |
| 1718 | /* IPv4 */ |
| 1719 | ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4); |
| 1720 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1721 | } |
| 1722 | |
| 1723 | ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4); |
| 1724 | IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4); |
| 1725 | |
| 1726 | IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id | |
| 1727 | (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT))); |
| 1728 | IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port | |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1729 | (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT))); |
| 1730 | |
| 1731 | /* |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1732 | * Program the relevant mask registers. L4type cannot be |
| 1733 | * masked out in this implementation. |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1734 | * |
| 1735 | * This also assumes IPv4 only. IPv6 masking isn't supported at this |
| 1736 | * point in time. |
| 1737 | */ |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1738 | IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask); |
| 1739 | IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask); |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1740 | |
| 1741 | switch (l4type & IXGBE_ATR_L4TYPE_MASK) { |
| 1742 | case IXGBE_ATR_L4TYPE_TCP: |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1743 | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask); |
| 1744 | IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, |
| 1745 | (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) | |
| 1746 | (input_masks->dst_port_mask << 16))); |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1747 | break; |
| 1748 | case IXGBE_ATR_L4TYPE_UDP: |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1749 | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask); |
| 1750 | IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, |
| 1751 | (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) | |
| 1752 | (input_masks->src_port_mask << 16))); |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1753 | break; |
| 1754 | default: |
| 1755 | /* this already would have failed above */ |
| 1756 | break; |
| 1757 | } |
| 1758 | |
| 1759 | /* Program the last mask register, FDIRM */ |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1760 | if (input_masks->vlan_id_mask) |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1761 | /* Mask both VLAN and VLANP - bits 0 and 1 */ |
| 1762 | fdirm |= 0x3; |
| 1763 | |
Ben Hutchings | be2902d | 2010-09-16 11:28:07 +0000 | [diff] [blame] | 1764 | if (input_masks->data_mask) |
Peter Waskiewicz | 9a713e7 | 2010-02-10 16:07:54 +0000 | [diff] [blame] | 1765 | /* Flex bytes need masking, so mask the whole thing - bit 4 */ |
| 1766 | fdirm |= 0x10; |
| 1767 | |
| 1768 | /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ |
| 1769 | fdirm |= 0x24; |
| 1770 | |
| 1771 | IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); |
Peter P Waskiewicz Jr | ffff477 | 2009-06-04 16:01:25 +0000 | [diff] [blame] | 1772 | |
| 1773 | fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW; |
| 1774 | fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE; |
| 1775 | fdircmd |= IXGBE_FDIRCMD_LAST; |
| 1776 | fdircmd |= IXGBE_FDIRCMD_QUEUE_EN; |
| 1777 | fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT; |
| 1778 | |
| 1779 | IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); |
| 1780 | IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); |
| 1781 | |
| 1782 | return 0; |
| 1783 | } |
| 1784 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1785 | * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register |
| 1786 | * @hw: pointer to hardware structure |
| 1787 | * @reg: analog register to read |
| 1788 | * @val: read value |
| 1789 | * |
| 1790 | * Performs read operation to Omer analog register specified. |
| 1791 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1792 | static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1793 | { |
| 1794 | u32 core_ctl; |
| 1795 | |
| 1796 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | |
| 1797 | (reg << 8)); |
| 1798 | IXGBE_WRITE_FLUSH(hw); |
| 1799 | udelay(10); |
| 1800 | core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); |
| 1801 | *val = (u8)core_ctl; |
| 1802 | |
| 1803 | return 0; |
| 1804 | } |
| 1805 | |
| 1806 | /** |
| 1807 | * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register |
| 1808 | * @hw: pointer to hardware structure |
| 1809 | * @reg: atlas register to write |
| 1810 | * @val: value to write |
| 1811 | * |
| 1812 | * Performs write operation to Omer analog register specified. |
| 1813 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1814 | static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1815 | { |
| 1816 | u32 core_ctl; |
| 1817 | |
| 1818 | core_ctl = (reg << 8) | val; |
| 1819 | IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); |
| 1820 | IXGBE_WRITE_FLUSH(hw); |
| 1821 | udelay(10); |
| 1822 | |
| 1823 | return 0; |
| 1824 | } |
| 1825 | |
| 1826 | /** |
| 1827 | * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx |
| 1828 | * @hw: pointer to hardware structure |
| 1829 | * |
| 1830 | * Starts the hardware using the generic start_hw function. |
| 1831 | * Then performs device-specific: |
| 1832 | * Clears the rate limiter registers. |
| 1833 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1834 | static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1835 | { |
| 1836 | u32 q_num; |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1837 | s32 ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1838 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1839 | ret_val = ixgbe_start_hw_generic(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1840 | |
| 1841 | /* Clear the rate limiters */ |
| 1842 | for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) { |
| 1843 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num); |
| 1844 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); |
| 1845 | } |
| 1846 | IXGBE_WRITE_FLUSH(hw); |
| 1847 | |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 1848 | /* We need to run link autotry after the driver loads */ |
| 1849 | hw->mac.autotry_restart = true; |
| 1850 | |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 1851 | if (ret_val == 0) |
| 1852 | ret_val = ixgbe_verify_fw_version_82599(hw); |
| 1853 | |
| 1854 | return ret_val; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1855 | } |
| 1856 | |
| 1857 | /** |
| 1858 | * ixgbe_identify_phy_82599 - Get physical layer module |
| 1859 | * @hw: pointer to hardware structure |
| 1860 | * |
| 1861 | * Determines the physical layer module found on the current adapter. |
| 1862 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1863 | static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1864 | { |
| 1865 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 1866 | status = ixgbe_identify_phy_generic(hw); |
| 1867 | if (status != 0) |
| 1868 | status = ixgbe_identify_sfp_module_generic(hw); |
| 1869 | return status; |
| 1870 | } |
| 1871 | |
| 1872 | /** |
| 1873 | * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type |
| 1874 | * @hw: pointer to hardware structure |
| 1875 | * |
| 1876 | * Determines physical layer capabilities of the current configuration. |
| 1877 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1878 | static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1879 | { |
| 1880 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1881 | u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
| 1882 | u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); |
| 1883 | u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; |
| 1884 | u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; |
| 1885 | u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; |
| 1886 | u16 ext_ability = 0; |
PJ Waskiewicz | 1339b9e | 2009-03-13 22:12:29 +0000 | [diff] [blame] | 1887 | u8 comp_codes_10g = 0; |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1888 | u8 comp_codes_1g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1889 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1890 | hw->phy.ops.identify(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1891 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1892 | if (hw->phy.type == ixgbe_phy_tn || |
| 1893 | hw->phy.type == ixgbe_phy_cu_unknown) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1894 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, |
| 1895 | &ext_ability); |
| 1896 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1897 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1898 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1899 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 1900 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1901 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; |
| 1902 | goto out; |
| 1903 | } |
| 1904 | |
| 1905 | switch (autoc & IXGBE_AUTOC_LMS_MASK) { |
| 1906 | case IXGBE_AUTOC_LMS_1G_AN: |
| 1907 | case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: |
| 1908 | if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { |
| 1909 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | |
| 1910 | IXGBE_PHYSICAL_LAYER_1000BASE_BX; |
| 1911 | goto out; |
| 1912 | } else |
| 1913 | /* SFI mode so read SFP module */ |
| 1914 | goto sfp_check; |
| 1915 | break; |
| 1916 | case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: |
| 1917 | if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) |
| 1918 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; |
| 1919 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) |
| 1920 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
Peter P Waskiewicz Jr | 1fcf03e | 2009-05-17 20:58:04 +0000 | [diff] [blame] | 1921 | else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) |
| 1922 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1923 | goto out; |
| 1924 | break; |
| 1925 | case IXGBE_AUTOC_LMS_10G_SERIAL: |
| 1926 | if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { |
| 1927 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1928 | goto out; |
| 1929 | } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) |
| 1930 | goto sfp_check; |
| 1931 | break; |
| 1932 | case IXGBE_AUTOC_LMS_KX4_KX_KR: |
| 1933 | case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: |
| 1934 | if (autoc & IXGBE_AUTOC_KX_SUPP) |
| 1935 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; |
| 1936 | if (autoc & IXGBE_AUTOC_KX4_SUPP) |
| 1937 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; |
| 1938 | if (autoc & IXGBE_AUTOC_KR_SUPP) |
| 1939 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; |
| 1940 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1941 | break; |
| 1942 | default: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1943 | goto out; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1944 | break; |
| 1945 | } |
| 1946 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1947 | sfp_check: |
| 1948 | /* SFP check must be done last since DA modules are sometimes used to |
| 1949 | * test KR mode - we need to id KR mode correctly before SFP module. |
| 1950 | * Call identify_sfp because the pluggable module may have changed */ |
| 1951 | hw->phy.ops.identify_sfp(hw); |
| 1952 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 1953 | goto out; |
| 1954 | |
| 1955 | switch (hw->phy.type) { |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1956 | case ixgbe_phy_sfp_passive_tyco: |
| 1957 | case ixgbe_phy_sfp_passive_unknown: |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1958 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; |
| 1959 | break; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1960 | case ixgbe_phy_sfp_ftl_active: |
| 1961 | case ixgbe_phy_sfp_active_unknown: |
| 1962 | physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; |
| 1963 | break; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1964 | case ixgbe_phy_sfp_avago: |
| 1965 | case ixgbe_phy_sfp_ftl: |
| 1966 | case ixgbe_phy_sfp_intel: |
| 1967 | case ixgbe_phy_sfp_unknown: |
| 1968 | hw->phy.ops.read_i2c_eeprom(hw, |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1969 | IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); |
| 1970 | hw->phy.ops.read_i2c_eeprom(hw, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1971 | IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); |
| 1972 | if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 1973 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; |
| 1974 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 1975 | physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1976 | else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) |
| 1977 | physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1978 | break; |
| 1979 | default: |
| 1980 | break; |
| 1981 | } |
| 1982 | |
| 1983 | out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1984 | return physical_layer; |
| 1985 | } |
| 1986 | |
| 1987 | /** |
| 1988 | * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 |
| 1989 | * @hw: pointer to hardware structure |
| 1990 | * @regval: register value to write to RXCTRL |
| 1991 | * |
| 1992 | * Enables the Rx DMA unit for 82599 |
| 1993 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 1994 | static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1995 | { |
| 1996 | #define IXGBE_MAX_SECRX_POLL 30 |
| 1997 | int i; |
| 1998 | int secrxreg; |
| 1999 | |
| 2000 | /* |
| 2001 | * Workaround for 82599 silicon errata when enabling the Rx datapath. |
| 2002 | * If traffic is incoming before we enable the Rx unit, it could hang |
| 2003 | * the Rx DMA unit. Therefore, make sure the security engine is |
| 2004 | * completely disabled prior to enabling the Rx unit. |
| 2005 | */ |
| 2006 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 2007 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; |
| 2008 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 2009 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { |
| 2010 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); |
| 2011 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) |
| 2012 | break; |
| 2013 | else |
| 2014 | udelay(10); |
| 2015 | } |
| 2016 | |
| 2017 | /* For informational purposes only */ |
| 2018 | if (i >= IXGBE_MAX_SECRX_POLL) |
| 2019 | hw_dbg(hw, "Rx unit being enabled before security " |
| 2020 | "path fully disabled. Continuing with init.\n"); |
| 2021 | |
| 2022 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); |
| 2023 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); |
| 2024 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; |
| 2025 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); |
| 2026 | IXGBE_WRITE_FLUSH(hw); |
| 2027 | |
| 2028 | return 0; |
| 2029 | } |
| 2030 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2031 | /** |
| 2032 | * ixgbe_get_device_caps_82599 - Get additional device capabilities |
| 2033 | * @hw: pointer to hardware structure |
| 2034 | * @device_caps: the EEPROM word with the extra device capabilities |
| 2035 | * |
| 2036 | * This function will read the EEPROM location for the device capabilities, |
| 2037 | * and return the word through device_caps. |
| 2038 | **/ |
Don Skidmore | 7b25cdb | 2009-08-25 04:47:32 +0000 | [diff] [blame] | 2039 | static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps) |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2040 | { |
| 2041 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); |
| 2042 | |
| 2043 | return 0; |
| 2044 | } |
| 2045 | |
PJ Waskiewicz | 0365e6e | 2009-05-17 12:32:25 +0000 | [diff] [blame] | 2046 | /** |
Peter P Waskiewicz Jr | 794caeb | 2009-06-04 16:02:24 +0000 | [diff] [blame] | 2047 | * ixgbe_verify_fw_version_82599 - verify fw version for 82599 |
| 2048 | * @hw: pointer to hardware structure |
| 2049 | * |
| 2050 | * Verifies that installed the firmware version is 0.6 or higher |
| 2051 | * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. |
| 2052 | * |
| 2053 | * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or |
| 2054 | * if the FW version is not supported. |
| 2055 | **/ |
| 2056 | static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) |
| 2057 | { |
| 2058 | s32 status = IXGBE_ERR_EEPROM_VERSION; |
| 2059 | u16 fw_offset, fw_ptp_cfg_offset; |
| 2060 | u16 fw_version = 0; |
| 2061 | |
| 2062 | /* firmware check is only necessary for SFI devices */ |
| 2063 | if (hw->phy.media_type != ixgbe_media_type_fiber) { |
| 2064 | status = 0; |
| 2065 | goto fw_version_out; |
| 2066 | } |
| 2067 | |
| 2068 | /* get the offset to the Firmware Module block */ |
| 2069 | hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); |
| 2070 | |
| 2071 | if ((fw_offset == 0) || (fw_offset == 0xFFFF)) |
| 2072 | goto fw_version_out; |
| 2073 | |
| 2074 | /* get the offset to the Pass Through Patch Configuration block */ |
| 2075 | hw->eeprom.ops.read(hw, (fw_offset + |
| 2076 | IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), |
| 2077 | &fw_ptp_cfg_offset); |
| 2078 | |
| 2079 | if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) |
| 2080 | goto fw_version_out; |
| 2081 | |
| 2082 | /* get the firmware version */ |
| 2083 | hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + |
| 2084 | IXGBE_FW_PATCH_VERSION_4), |
| 2085 | &fw_version); |
| 2086 | |
| 2087 | if (fw_version > 0x5) |
| 2088 | status = 0; |
| 2089 | |
| 2090 | fw_version_out: |
| 2091 | return status; |
| 2092 | } |
| 2093 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2094 | static struct ixgbe_mac_operations mac_ops_82599 = { |
| 2095 | .init_hw = &ixgbe_init_hw_generic, |
| 2096 | .reset_hw = &ixgbe_reset_hw_82599, |
| 2097 | .start_hw = &ixgbe_start_hw_82599, |
| 2098 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
| 2099 | .get_media_type = &ixgbe_get_media_type_82599, |
| 2100 | .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599, |
| 2101 | .enable_rx_dma = &ixgbe_enable_rx_dma_82599, |
| 2102 | .get_mac_addr = &ixgbe_get_mac_addr_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2103 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 2104 | .get_device_caps = &ixgbe_get_device_caps_82599, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame^] | 2105 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2106 | .stop_adapter = &ixgbe_stop_adapter_generic, |
| 2107 | .get_bus_info = &ixgbe_get_bus_info_generic, |
| 2108 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, |
| 2109 | .read_analog_reg8 = &ixgbe_read_analog_reg8_82599, |
| 2110 | .write_analog_reg8 = &ixgbe_write_analog_reg8_82599, |
| 2111 | .setup_link = &ixgbe_setup_mac_link_82599, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2112 | .check_link = &ixgbe_check_mac_link_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2113 | .get_link_capabilities = &ixgbe_get_link_capabilities_82599, |
| 2114 | .led_on = &ixgbe_led_on_generic, |
| 2115 | .led_off = &ixgbe_led_off_generic, |
PJ Waskiewicz | 87c1201 | 2009-04-08 13:20:31 +0000 | [diff] [blame] | 2116 | .blink_led_start = &ixgbe_blink_led_start_generic, |
| 2117 | .blink_led_stop = &ixgbe_blink_led_stop_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2118 | .set_rar = &ixgbe_set_rar_generic, |
| 2119 | .clear_rar = &ixgbe_clear_rar_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2120 | .set_vmdq = &ixgbe_set_vmdq_generic, |
| 2121 | .clear_vmdq = &ixgbe_clear_vmdq_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2122 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, |
| 2123 | .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic, |
| 2124 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
| 2125 | .enable_mc = &ixgbe_enable_mc_generic, |
| 2126 | .disable_mc = &ixgbe_disable_mc_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2127 | .clear_vfta = &ixgbe_clear_vfta_generic, |
| 2128 | .set_vfta = &ixgbe_set_vfta_generic, |
| 2129 | .fc_enable = &ixgbe_fc_enable_generic, |
| 2130 | .init_uta_tables = &ixgbe_init_uta_tables_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2131 | .setup_sfp = &ixgbe_setup_sfp_modules_82599, |
| 2132 | }; |
| 2133 | |
| 2134 | static struct ixgbe_eeprom_operations eeprom_ops_82599 = { |
| 2135 | .init_params = &ixgbe_init_eeprom_params_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2136 | .read = &ixgbe_read_eerd_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2137 | .write = &ixgbe_write_eeprom_generic, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame^] | 2138 | .calc_checksum = &ixgbe_calc_eeprom_checksum_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2139 | .validate_checksum = &ixgbe_validate_eeprom_checksum_generic, |
| 2140 | .update_checksum = &ixgbe_update_eeprom_checksum_generic, |
| 2141 | }; |
| 2142 | |
| 2143 | static struct ixgbe_phy_operations phy_ops_82599 = { |
| 2144 | .identify = &ixgbe_identify_phy_82599, |
| 2145 | .identify_sfp = &ixgbe_identify_sfp_module_generic, |
Mallikarjuna R Chilakala | 21ce849 | 2010-05-13 17:33:41 +0000 | [diff] [blame] | 2146 | .init = &ixgbe_init_phy_ops_82599, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2147 | .reset = &ixgbe_reset_phy_generic, |
| 2148 | .read_reg = &ixgbe_read_phy_reg_generic, |
| 2149 | .write_reg = &ixgbe_write_phy_reg_generic, |
| 2150 | .setup_link = &ixgbe_setup_phy_link_generic, |
| 2151 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, |
| 2152 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, |
| 2153 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, |
| 2154 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, |
| 2155 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 2156 | .check_overtemp = &ixgbe_tn_check_overtemp, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2157 | }; |
| 2158 | |
| 2159 | struct ixgbe_info ixgbe_82599_info = { |
| 2160 | .mac = ixgbe_mac_82599EB, |
| 2161 | .get_invariants = &ixgbe_get_invariants_82599, |
| 2162 | .mac_ops = &mac_ops_82599, |
| 2163 | .eeprom_ops = &eeprom_ops_82599, |
| 2164 | .phy_ops = &phy_ops_82599, |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame^] | 2165 | .mbx_ops = &mbx_ops_generic, |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 2166 | }; |