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Will Deacon45ae7cf2013-06-24 18:31:25 +01001/*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
Will Deacon45ae7cf2013-06-24 18:31:25 +010026 * - Context fault reporting
27 */
28
29#define pr_fmt(fmt) "arm-smmu: " fmt
30
31#include <linux/delay.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
34#include <linux/interrupt.h>
35#include <linux/io.h>
36#include <linux/iommu.h>
Mitchel Humpherys859a7322014-10-29 21:13:40 +000037#include <linux/iopoll.h>
Will Deacon45ae7cf2013-06-24 18:31:25 +010038#include <linux/module.h>
39#include <linux/of.h>
Will Deacona9a1b0b2014-05-01 18:05:08 +010040#include <linux/pci.h>
Will Deacon45ae7cf2013-06-24 18:31:25 +010041#include <linux/platform_device.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44
45#include <linux/amba/bus.h>
46
Will Deacon518f7132014-11-14 17:17:54 +000047#include "io-pgtable.h"
Will Deacon45ae7cf2013-06-24 18:31:25 +010048
49/* Maximum number of stream IDs assigned to a single device */
Andreas Herrmann636e97b2014-01-30 18:18:08 +000050#define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
Will Deacon45ae7cf2013-06-24 18:31:25 +010051
52/* Maximum number of context banks per SMMU */
53#define ARM_SMMU_MAX_CBS 128
54
55/* Maximum number of mapping groups per SMMU */
56#define ARM_SMMU_MAX_SMRS 128
57
Will Deacon45ae7cf2013-06-24 18:31:25 +010058/* SMMU global address space */
59#define ARM_SMMU_GR0(smmu) ((smmu)->base)
Will Deaconc757e852014-07-30 11:33:25 +010060#define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
Will Deacon45ae7cf2013-06-24 18:31:25 +010061
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +000062/*
63 * SMMU global address space with conditional offset to access secure
64 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
65 * nsGFSYNR0: 0x450)
66 */
67#define ARM_SMMU_GR0_NS(smmu) \
68 ((smmu)->base + \
69 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
70 ? 0x400 : 0))
71
Will Deacon45ae7cf2013-06-24 18:31:25 +010072/* Configuration registers */
73#define ARM_SMMU_GR0_sCR0 0x0
74#define sCR0_CLIENTPD (1 << 0)
75#define sCR0_GFRE (1 << 1)
76#define sCR0_GFIE (1 << 2)
77#define sCR0_GCFGFRE (1 << 4)
78#define sCR0_GCFGFIE (1 << 5)
79#define sCR0_USFCFG (1 << 10)
80#define sCR0_VMIDPNE (1 << 11)
81#define sCR0_PTM (1 << 12)
82#define sCR0_FB (1 << 13)
83#define sCR0_BSU_SHIFT 14
84#define sCR0_BSU_MASK 0x3
85
86/* Identification registers */
87#define ARM_SMMU_GR0_ID0 0x20
88#define ARM_SMMU_GR0_ID1 0x24
89#define ARM_SMMU_GR0_ID2 0x28
90#define ARM_SMMU_GR0_ID3 0x2c
91#define ARM_SMMU_GR0_ID4 0x30
92#define ARM_SMMU_GR0_ID5 0x34
93#define ARM_SMMU_GR0_ID6 0x38
94#define ARM_SMMU_GR0_ID7 0x3c
95#define ARM_SMMU_GR0_sGFSR 0x48
96#define ARM_SMMU_GR0_sGFSYNR0 0x50
97#define ARM_SMMU_GR0_sGFSYNR1 0x54
98#define ARM_SMMU_GR0_sGFSYNR2 0x58
Will Deacon45ae7cf2013-06-24 18:31:25 +010099
100#define ID0_S1TS (1 << 30)
101#define ID0_S2TS (1 << 29)
102#define ID0_NTS (1 << 28)
103#define ID0_SMS (1 << 27)
Mitchel Humpherys859a7322014-10-29 21:13:40 +0000104#define ID0_ATOSNS (1 << 26)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100105#define ID0_CTTW (1 << 14)
106#define ID0_NUMIRPT_SHIFT 16
107#define ID0_NUMIRPT_MASK 0xff
Olav Haugan3c8766d2014-08-22 17:12:32 -0700108#define ID0_NUMSIDB_SHIFT 9
109#define ID0_NUMSIDB_MASK 0xf
Will Deacon45ae7cf2013-06-24 18:31:25 +0100110#define ID0_NUMSMRG_SHIFT 0
111#define ID0_NUMSMRG_MASK 0xff
112
113#define ID1_PAGESIZE (1 << 31)
114#define ID1_NUMPAGENDXB_SHIFT 28
115#define ID1_NUMPAGENDXB_MASK 7
116#define ID1_NUMS2CB_SHIFT 16
117#define ID1_NUMS2CB_MASK 0xff
118#define ID1_NUMCB_SHIFT 0
119#define ID1_NUMCB_MASK 0xff
120
121#define ID2_OAS_SHIFT 4
122#define ID2_OAS_MASK 0xf
123#define ID2_IAS_SHIFT 0
124#define ID2_IAS_MASK 0xf
125#define ID2_UBS_SHIFT 8
126#define ID2_UBS_MASK 0xf
127#define ID2_PTFS_4K (1 << 12)
128#define ID2_PTFS_16K (1 << 13)
129#define ID2_PTFS_64K (1 << 14)
130
Will Deacon45ae7cf2013-06-24 18:31:25 +0100131/* Global TLB invalidation */
Will Deacon45ae7cf2013-06-24 18:31:25 +0100132#define ARM_SMMU_GR0_TLBIVMID 0x64
133#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
134#define ARM_SMMU_GR0_TLBIALLH 0x6c
135#define ARM_SMMU_GR0_sTLBGSYNC 0x70
136#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
137#define sTLBGSTATUS_GSACTIVE (1 << 0)
138#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
139
140/* Stream mapping registers */
141#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
142#define SMR_VALID (1 << 31)
143#define SMR_MASK_SHIFT 16
144#define SMR_MASK_MASK 0x7fff
145#define SMR_ID_SHIFT 0
146#define SMR_ID_MASK 0x7fff
147
148#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
149#define S2CR_CBNDX_SHIFT 0
150#define S2CR_CBNDX_MASK 0xff
151#define S2CR_TYPE_SHIFT 16
152#define S2CR_TYPE_MASK 0x3
153#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
154#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
155#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
156
157/* Context bank attribute registers */
158#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
159#define CBAR_VMID_SHIFT 0
160#define CBAR_VMID_MASK 0xff
Will Deacon57ca90f2014-02-06 14:59:05 +0000161#define CBAR_S1_BPSHCFG_SHIFT 8
162#define CBAR_S1_BPSHCFG_MASK 3
163#define CBAR_S1_BPSHCFG_NSH 3
Will Deacon45ae7cf2013-06-24 18:31:25 +0100164#define CBAR_S1_MEMATTR_SHIFT 12
165#define CBAR_S1_MEMATTR_MASK 0xf
166#define CBAR_S1_MEMATTR_WB 0xf
167#define CBAR_TYPE_SHIFT 16
168#define CBAR_TYPE_MASK 0x3
169#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
170#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
171#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
172#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
173#define CBAR_IRPTNDX_SHIFT 24
174#define CBAR_IRPTNDX_MASK 0xff
175
176#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
177#define CBA2R_RW64_32BIT (0 << 0)
178#define CBA2R_RW64_64BIT (1 << 0)
179
180/* Translation context bank */
181#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
Will Deaconc757e852014-07-30 11:33:25 +0100182#define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
Will Deacon45ae7cf2013-06-24 18:31:25 +0100183
184#define ARM_SMMU_CB_SCTLR 0x0
185#define ARM_SMMU_CB_RESUME 0x8
186#define ARM_SMMU_CB_TTBCR2 0x10
187#define ARM_SMMU_CB_TTBR0_LO 0x20
188#define ARM_SMMU_CB_TTBR0_HI 0x24
Will Deacon518f7132014-11-14 17:17:54 +0000189#define ARM_SMMU_CB_TTBR1_LO 0x28
190#define ARM_SMMU_CB_TTBR1_HI 0x2c
Will Deacon45ae7cf2013-06-24 18:31:25 +0100191#define ARM_SMMU_CB_TTBCR 0x30
192#define ARM_SMMU_CB_S1_MAIR0 0x38
Will Deacon518f7132014-11-14 17:17:54 +0000193#define ARM_SMMU_CB_S1_MAIR1 0x3c
Mitchel Humpherys859a7322014-10-29 21:13:40 +0000194#define ARM_SMMU_CB_PAR_LO 0x50
195#define ARM_SMMU_CB_PAR_HI 0x54
Will Deacon45ae7cf2013-06-24 18:31:25 +0100196#define ARM_SMMU_CB_FSR 0x58
197#define ARM_SMMU_CB_FAR_LO 0x60
198#define ARM_SMMU_CB_FAR_HI 0x64
199#define ARM_SMMU_CB_FSYNR0 0x68
Will Deacon518f7132014-11-14 17:17:54 +0000200#define ARM_SMMU_CB_S1_TLBIVA 0x600
Will Deacon1463fe42013-07-31 19:21:27 +0100201#define ARM_SMMU_CB_S1_TLBIASID 0x610
Will Deacon518f7132014-11-14 17:17:54 +0000202#define ARM_SMMU_CB_S1_TLBIVAL 0x620
203#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
204#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
Mitchel Humpherys859a7322014-10-29 21:13:40 +0000205#define ARM_SMMU_CB_ATS1PR_LO 0x800
206#define ARM_SMMU_CB_ATS1PR_HI 0x804
207#define ARM_SMMU_CB_ATSR 0x8f0
Will Deacon45ae7cf2013-06-24 18:31:25 +0100208
209#define SCTLR_S1_ASIDPNE (1 << 12)
210#define SCTLR_CFCFG (1 << 7)
211#define SCTLR_CFIE (1 << 6)
212#define SCTLR_CFRE (1 << 5)
213#define SCTLR_E (1 << 4)
214#define SCTLR_AFE (1 << 2)
215#define SCTLR_TRE (1 << 1)
216#define SCTLR_M (1 << 0)
217#define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
218
Mitchel Humpherys859a7322014-10-29 21:13:40 +0000219#define CB_PAR_F (1 << 0)
220
221#define ATSR_ACTIVE (1 << 0)
222
Will Deacon45ae7cf2013-06-24 18:31:25 +0100223#define RESUME_RETRY (0 << 0)
224#define RESUME_TERMINATE (1 << 0)
225
Will Deacon45ae7cf2013-06-24 18:31:25 +0100226#define TTBCR2_SEP_SHIFT 15
227#define TTBCR2_SEP_MASK 0x7
228
Will Deacon45ae7cf2013-06-24 18:31:25 +0100229#define TTBCR2_ADDR_32 0
230#define TTBCR2_ADDR_36 1
231#define TTBCR2_ADDR_40 2
232#define TTBCR2_ADDR_42 3
233#define TTBCR2_ADDR_44 4
234#define TTBCR2_ADDR_48 5
235
Will Deacon518f7132014-11-14 17:17:54 +0000236#define TTBRn_HI_ASID_SHIFT 16
Will Deacon45ae7cf2013-06-24 18:31:25 +0100237
238#define FSR_MULTI (1 << 31)
239#define FSR_SS (1 << 30)
240#define FSR_UUT (1 << 8)
241#define FSR_ASF (1 << 7)
242#define FSR_TLBLKF (1 << 6)
243#define FSR_TLBMCF (1 << 5)
244#define FSR_EF (1 << 4)
245#define FSR_PF (1 << 3)
246#define FSR_AFF (1 << 2)
247#define FSR_TF (1 << 1)
248
Mitchel Humpherys29073202014-07-08 09:52:18 -0700249#define FSR_IGN (FSR_AFF | FSR_ASF | \
250 FSR_TLBMCF | FSR_TLBLKF)
251#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
Will Deaconadaba322013-07-31 19:21:26 +0100252 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100253
254#define FSYNR0_WNR (1 << 4)
255
Will Deacon4cf740b2014-07-14 19:47:39 +0100256static int force_stage;
257module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR);
258MODULE_PARM_DESC(force_stage,
259 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
260
Robin Murphy09360402014-08-28 17:51:59 +0100261enum arm_smmu_arch_version {
262 ARM_SMMU_V1 = 1,
263 ARM_SMMU_V2,
264};
265
Will Deacon45ae7cf2013-06-24 18:31:25 +0100266struct arm_smmu_smr {
267 u8 idx;
268 u16 mask;
269 u16 id;
270};
271
Will Deacona9a1b0b2014-05-01 18:05:08 +0100272struct arm_smmu_master_cfg {
Will Deacon45ae7cf2013-06-24 18:31:25 +0100273 int num_streamids;
274 u16 streamids[MAX_MASTER_STREAMIDS];
Will Deacon45ae7cf2013-06-24 18:31:25 +0100275 struct arm_smmu_smr *smrs;
276};
277
Will Deacona9a1b0b2014-05-01 18:05:08 +0100278struct arm_smmu_master {
279 struct device_node *of_node;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100280 struct rb_node node;
281 struct arm_smmu_master_cfg cfg;
282};
283
Will Deacon45ae7cf2013-06-24 18:31:25 +0100284struct arm_smmu_device {
285 struct device *dev;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100286
287 void __iomem *base;
288 unsigned long size;
Will Deaconc757e852014-07-30 11:33:25 +0100289 unsigned long pgshift;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100290
291#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
292#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
293#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
294#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
295#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
Mitchel Humpherys859a7322014-10-29 21:13:40 +0000296#define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100297 u32 features;
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000298
299#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
300 u32 options;
Robin Murphy09360402014-08-28 17:51:59 +0100301 enum arm_smmu_arch_version version;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100302
303 u32 num_context_banks;
304 u32 num_s2_context_banks;
305 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
306 atomic_t irptndx;
307
308 u32 num_mapping_groups;
309 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
310
Will Deacon518f7132014-11-14 17:17:54 +0000311 unsigned long va_size;
312 unsigned long ipa_size;
313 unsigned long pa_size;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100314
315 u32 num_global_irqs;
316 u32 num_context_irqs;
317 unsigned int *irqs;
318
Will Deacon45ae7cf2013-06-24 18:31:25 +0100319 struct list_head list;
320 struct rb_root masters;
321};
322
323struct arm_smmu_cfg {
Will Deacon45ae7cf2013-06-24 18:31:25 +0100324 u8 cbndx;
325 u8 irptndx;
326 u32 cbar;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100327};
Dan Carpenterfaea13b72013-08-21 09:33:30 +0100328#define INVALID_IRPTNDX 0xff
Will Deacon45ae7cf2013-06-24 18:31:25 +0100329
Will Deaconecfadb62013-07-31 19:21:28 +0100330#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
331#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
332
Will Deaconc752ce42014-06-25 22:46:31 +0100333enum arm_smmu_domain_stage {
334 ARM_SMMU_DOMAIN_S1 = 0,
335 ARM_SMMU_DOMAIN_S2,
336 ARM_SMMU_DOMAIN_NESTED,
337};
338
Will Deacon45ae7cf2013-06-24 18:31:25 +0100339struct arm_smmu_domain {
Will Deacon44680ee2014-06-25 11:29:12 +0100340 struct arm_smmu_device *smmu;
Will Deacon518f7132014-11-14 17:17:54 +0000341 struct io_pgtable_ops *pgtbl_ops;
342 spinlock_t pgtbl_lock;
Will Deacon44680ee2014-06-25 11:29:12 +0100343 struct arm_smmu_cfg cfg;
Will Deaconc752ce42014-06-25 22:46:31 +0100344 enum arm_smmu_domain_stage stage;
Will Deacon518f7132014-11-14 17:17:54 +0000345 struct mutex init_mutex; /* Protects smmu pointer */
Will Deacon45ae7cf2013-06-24 18:31:25 +0100346};
347
Will Deacon518f7132014-11-14 17:17:54 +0000348static struct iommu_ops arm_smmu_ops;
349
Will Deacon45ae7cf2013-06-24 18:31:25 +0100350static DEFINE_SPINLOCK(arm_smmu_devices_lock);
351static LIST_HEAD(arm_smmu_devices);
352
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000353struct arm_smmu_option_prop {
354 u32 opt;
355 const char *prop;
356};
357
Mitchel Humpherys29073202014-07-08 09:52:18 -0700358static struct arm_smmu_option_prop arm_smmu_options[] = {
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000359 { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
360 { 0, NULL},
361};
362
363static void parse_driver_options(struct arm_smmu_device *smmu)
364{
365 int i = 0;
Mitchel Humpherys29073202014-07-08 09:52:18 -0700366
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000367 do {
368 if (of_property_read_bool(smmu->dev->of_node,
369 arm_smmu_options[i].prop)) {
370 smmu->options |= arm_smmu_options[i].opt;
371 dev_notice(smmu->dev, "option %s\n",
372 arm_smmu_options[i].prop);
373 }
374 } while (arm_smmu_options[++i].opt);
375}
376
Will Deacon8f68f8e2014-07-15 11:27:08 +0100377static struct device_node *dev_get_dev_node(struct device *dev)
Will Deacona9a1b0b2014-05-01 18:05:08 +0100378{
379 if (dev_is_pci(dev)) {
380 struct pci_bus *bus = to_pci_dev(dev)->bus;
Mitchel Humpherys29073202014-07-08 09:52:18 -0700381
Will Deacona9a1b0b2014-05-01 18:05:08 +0100382 while (!pci_is_root_bus(bus))
383 bus = bus->parent;
Will Deacon8f68f8e2014-07-15 11:27:08 +0100384 return bus->bridge->parent->of_node;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100385 }
386
Will Deacon8f68f8e2014-07-15 11:27:08 +0100387 return dev->of_node;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100388}
389
Will Deacon45ae7cf2013-06-24 18:31:25 +0100390static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
391 struct device_node *dev_node)
392{
393 struct rb_node *node = smmu->masters.rb_node;
394
395 while (node) {
396 struct arm_smmu_master *master;
Mitchel Humpherys29073202014-07-08 09:52:18 -0700397
Will Deacon45ae7cf2013-06-24 18:31:25 +0100398 master = container_of(node, struct arm_smmu_master, node);
399
400 if (dev_node < master->of_node)
401 node = node->rb_left;
402 else if (dev_node > master->of_node)
403 node = node->rb_right;
404 else
405 return master;
406 }
407
408 return NULL;
409}
410
Will Deacona9a1b0b2014-05-01 18:05:08 +0100411static struct arm_smmu_master_cfg *
Will Deacon8f68f8e2014-07-15 11:27:08 +0100412find_smmu_master_cfg(struct device *dev)
Will Deacona9a1b0b2014-05-01 18:05:08 +0100413{
Will Deacon8f68f8e2014-07-15 11:27:08 +0100414 struct arm_smmu_master_cfg *cfg = NULL;
415 struct iommu_group *group = iommu_group_get(dev);
Will Deacona9a1b0b2014-05-01 18:05:08 +0100416
Will Deacon8f68f8e2014-07-15 11:27:08 +0100417 if (group) {
418 cfg = iommu_group_get_iommudata(group);
419 iommu_group_put(group);
420 }
Will Deacona9a1b0b2014-05-01 18:05:08 +0100421
Will Deacon8f68f8e2014-07-15 11:27:08 +0100422 return cfg;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100423}
424
Will Deacon45ae7cf2013-06-24 18:31:25 +0100425static int insert_smmu_master(struct arm_smmu_device *smmu,
426 struct arm_smmu_master *master)
427{
428 struct rb_node **new, *parent;
429
430 new = &smmu->masters.rb_node;
431 parent = NULL;
432 while (*new) {
Mitchel Humpherys29073202014-07-08 09:52:18 -0700433 struct arm_smmu_master *this
434 = container_of(*new, struct arm_smmu_master, node);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100435
436 parent = *new;
437 if (master->of_node < this->of_node)
438 new = &((*new)->rb_left);
439 else if (master->of_node > this->of_node)
440 new = &((*new)->rb_right);
441 else
442 return -EEXIST;
443 }
444
445 rb_link_node(&master->node, parent, new);
446 rb_insert_color(&master->node, &smmu->masters);
447 return 0;
448}
449
450static int register_smmu_master(struct arm_smmu_device *smmu,
451 struct device *dev,
452 struct of_phandle_args *masterspec)
453{
454 int i;
455 struct arm_smmu_master *master;
456
457 master = find_smmu_master(smmu, masterspec->np);
458 if (master) {
459 dev_err(dev,
460 "rejecting multiple registrations for master device %s\n",
461 masterspec->np->name);
462 return -EBUSY;
463 }
464
465 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
466 dev_err(dev,
467 "reached maximum number (%d) of stream IDs for master device %s\n",
468 MAX_MASTER_STREAMIDS, masterspec->np->name);
469 return -ENOSPC;
470 }
471
472 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
473 if (!master)
474 return -ENOMEM;
475
Will Deacona9a1b0b2014-05-01 18:05:08 +0100476 master->of_node = masterspec->np;
477 master->cfg.num_streamids = masterspec->args_count;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100478
Olav Haugan3c8766d2014-08-22 17:12:32 -0700479 for (i = 0; i < master->cfg.num_streamids; ++i) {
480 u16 streamid = masterspec->args[i];
Will Deacon45ae7cf2013-06-24 18:31:25 +0100481
Olav Haugan3c8766d2014-08-22 17:12:32 -0700482 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
483 (streamid >= smmu->num_mapping_groups)) {
484 dev_err(dev,
485 "stream ID for master device %s greater than maximum allowed (%d)\n",
486 masterspec->np->name, smmu->num_mapping_groups);
487 return -ERANGE;
488 }
489 master->cfg.streamids[i] = streamid;
490 }
Will Deacon45ae7cf2013-06-24 18:31:25 +0100491 return insert_smmu_master(smmu, master);
492}
493
Will Deacon44680ee2014-06-25 11:29:12 +0100494static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100495{
Will Deacon44680ee2014-06-25 11:29:12 +0100496 struct arm_smmu_device *smmu;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100497 struct arm_smmu_master *master = NULL;
Will Deacon8f68f8e2014-07-15 11:27:08 +0100498 struct device_node *dev_node = dev_get_dev_node(dev);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100499
500 spin_lock(&arm_smmu_devices_lock);
Will Deacon44680ee2014-06-25 11:29:12 +0100501 list_for_each_entry(smmu, &arm_smmu_devices, list) {
Will Deacona9a1b0b2014-05-01 18:05:08 +0100502 master = find_smmu_master(smmu, dev_node);
503 if (master)
504 break;
505 }
Will Deacon45ae7cf2013-06-24 18:31:25 +0100506 spin_unlock(&arm_smmu_devices_lock);
Will Deacon44680ee2014-06-25 11:29:12 +0100507
Will Deacona9a1b0b2014-05-01 18:05:08 +0100508 return master ? smmu : NULL;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100509}
510
511static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
512{
513 int idx;
514
515 do {
516 idx = find_next_zero_bit(map, end, start);
517 if (idx == end)
518 return -ENOSPC;
519 } while (test_and_set_bit(idx, map));
520
521 return idx;
522}
523
524static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
525{
526 clear_bit(idx, map);
527}
528
529/* Wait for any pending TLB invalidations to complete */
Will Deacon518f7132014-11-14 17:17:54 +0000530static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100531{
532 int count = 0;
533 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
534
535 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
536 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
537 & sTLBGSTATUS_GSACTIVE) {
538 cpu_relax();
539 if (++count == TLB_LOOP_TIMEOUT) {
540 dev_err_ratelimited(smmu->dev,
541 "TLB sync timed out -- SMMU may be deadlocked\n");
542 return;
543 }
544 udelay(1);
545 }
546}
547
Will Deacon518f7132014-11-14 17:17:54 +0000548static void arm_smmu_tlb_sync(void *cookie)
Will Deacon1463fe42013-07-31 19:21:27 +0100549{
Will Deacon518f7132014-11-14 17:17:54 +0000550 struct arm_smmu_domain *smmu_domain = cookie;
551 __arm_smmu_tlb_sync(smmu_domain->smmu);
552}
553
554static void arm_smmu_tlb_inv_context(void *cookie)
555{
556 struct arm_smmu_domain *smmu_domain = cookie;
Will Deacon44680ee2014-06-25 11:29:12 +0100557 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
558 struct arm_smmu_device *smmu = smmu_domain->smmu;
Will Deacon1463fe42013-07-31 19:21:27 +0100559 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
Will Deacon518f7132014-11-14 17:17:54 +0000560 void __iomem *base;
Will Deacon1463fe42013-07-31 19:21:27 +0100561
562 if (stage1) {
563 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
Will Deaconecfadb62013-07-31 19:21:28 +0100564 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
565 base + ARM_SMMU_CB_S1_TLBIASID);
Will Deacon1463fe42013-07-31 19:21:27 +0100566 } else {
567 base = ARM_SMMU_GR0(smmu);
Will Deaconecfadb62013-07-31 19:21:28 +0100568 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
569 base + ARM_SMMU_GR0_TLBIVMID);
Will Deacon1463fe42013-07-31 19:21:27 +0100570 }
571
Will Deacon518f7132014-11-14 17:17:54 +0000572 __arm_smmu_tlb_sync(smmu);
Will Deacon1463fe42013-07-31 19:21:27 +0100573}
574
Will Deacon518f7132014-11-14 17:17:54 +0000575static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
576 bool leaf, void *cookie)
577{
578 struct arm_smmu_domain *smmu_domain = cookie;
579 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
580 struct arm_smmu_device *smmu = smmu_domain->smmu;
581 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
582 void __iomem *reg;
583
584 if (stage1) {
585 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
586 reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
587
588 if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
589 iova &= ~12UL;
590 iova |= ARM_SMMU_CB_ASID(cfg);
591 writel_relaxed(iova, reg);
592#ifdef CONFIG_64BIT
593 } else {
594 iova >>= 12;
595 iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
596 writeq_relaxed(iova, reg);
597#endif
598 }
599#ifdef CONFIG_64BIT
600 } else if (smmu->version == ARM_SMMU_V2) {
601 reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
602 reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
603 ARM_SMMU_CB_S2_TLBIIPAS2;
604 writeq_relaxed(iova >> 12, reg);
605#endif
606 } else {
607 reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
608 writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);
609 }
610}
611
612static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
613{
614 struct arm_smmu_domain *smmu_domain = cookie;
615 struct arm_smmu_device *smmu = smmu_domain->smmu;
616 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
617
618
619 /* Ensure new page tables are visible to the hardware walker */
620 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
621 dsb(ishst);
622 } else {
623 /*
624 * If the SMMU can't walk tables in the CPU caches, treat them
625 * like non-coherent DMA since we need to flush the new entries
626 * all the way out to memory. There's no possibility of
627 * recursion here as the SMMU table walker will not be wired
628 * through another SMMU.
629 */
630 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
631 DMA_TO_DEVICE);
632 }
633}
634
635static struct iommu_gather_ops arm_smmu_gather_ops = {
636 .tlb_flush_all = arm_smmu_tlb_inv_context,
637 .tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
638 .tlb_sync = arm_smmu_tlb_sync,
639 .flush_pgtable = arm_smmu_flush_pgtable,
640};
641
Will Deacon45ae7cf2013-06-24 18:31:25 +0100642static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
643{
644 int flags, ret;
645 u32 fsr, far, fsynr, resume;
646 unsigned long iova;
647 struct iommu_domain *domain = dev;
648 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon44680ee2014-06-25 11:29:12 +0100649 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
650 struct arm_smmu_device *smmu = smmu_domain->smmu;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100651 void __iomem *cb_base;
652
Will Deacon44680ee2014-06-25 11:29:12 +0100653 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100654 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
655
656 if (!(fsr & FSR_FAULT))
657 return IRQ_NONE;
658
659 if (fsr & FSR_IGN)
660 dev_err_ratelimited(smmu->dev,
Hans Wennborg70c9a7d2014-08-06 05:42:01 +0100661 "Unexpected context fault (fsr 0x%x)\n",
Will Deacon45ae7cf2013-06-24 18:31:25 +0100662 fsr);
663
664 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
665 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
666
667 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
668 iova = far;
669#ifdef CONFIG_64BIT
670 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
671 iova |= ((unsigned long)far << 32);
672#endif
673
674 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
675 ret = IRQ_HANDLED;
676 resume = RESUME_RETRY;
677 } else {
Andreas Herrmann2ef0f032013-10-01 13:39:08 +0100678 dev_err_ratelimited(smmu->dev,
679 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
Will Deacon44680ee2014-06-25 11:29:12 +0100680 iova, fsynr, cfg->cbndx);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100681 ret = IRQ_NONE;
682 resume = RESUME_TERMINATE;
683 }
684
685 /* Clear the faulting FSR */
686 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
687
688 /* Retry or terminate any stalled transactions */
689 if (fsr & FSR_SS)
690 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
691
692 return ret;
693}
694
695static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
696{
697 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
698 struct arm_smmu_device *smmu = dev;
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000699 void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100700
701 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
702 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
703 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
704 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
705
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +0000706 if (!gfsr)
707 return IRQ_NONE;
708
Will Deacon45ae7cf2013-06-24 18:31:25 +0100709 dev_err_ratelimited(smmu->dev,
710 "Unexpected global fault, this could be serious\n");
711 dev_err_ratelimited(smmu->dev,
712 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
713 gfsr, gfsynr0, gfsynr1, gfsynr2);
714
715 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
Will Deaconadaba322013-07-31 19:21:26 +0100716 return IRQ_HANDLED;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100717}
718
Will Deacon518f7132014-11-14 17:17:54 +0000719static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
720 struct io_pgtable_cfg *pgtbl_cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100721{
722 u32 reg;
723 bool stage1;
Will Deacon44680ee2014-06-25 11:29:12 +0100724 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
725 struct arm_smmu_device *smmu = smmu_domain->smmu;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100726 void __iomem *cb_base, *gr0_base, *gr1_base;
727
728 gr0_base = ARM_SMMU_GR0(smmu);
729 gr1_base = ARM_SMMU_GR1(smmu);
Will Deacon44680ee2014-06-25 11:29:12 +0100730 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
731 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100732
733 /* CBAR */
Will Deacon44680ee2014-06-25 11:29:12 +0100734 reg = cfg->cbar;
Robin Murphy09360402014-08-28 17:51:59 +0100735 if (smmu->version == ARM_SMMU_V1)
Mitchel Humpherys29073202014-07-08 09:52:18 -0700736 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100737
Will Deacon57ca90f2014-02-06 14:59:05 +0000738 /*
739 * Use the weakest shareability/memory types, so they are
740 * overridden by the ttbcr/pte.
741 */
742 if (stage1) {
743 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
744 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
745 } else {
Will Deacon44680ee2014-06-25 11:29:12 +0100746 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;
Will Deacon57ca90f2014-02-06 14:59:05 +0000747 }
Will Deacon44680ee2014-06-25 11:29:12 +0100748 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
Will Deacon45ae7cf2013-06-24 18:31:25 +0100749
Robin Murphy09360402014-08-28 17:51:59 +0100750 if (smmu->version > ARM_SMMU_V1) {
Will Deacon45ae7cf2013-06-24 18:31:25 +0100751 /* CBA2R */
752#ifdef CONFIG_64BIT
753 reg = CBA2R_RW64_64BIT;
754#else
755 reg = CBA2R_RW64_32BIT;
756#endif
Will Deacon518f7132014-11-14 17:17:54 +0000757 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
Will Deacon45ae7cf2013-06-24 18:31:25 +0100758 }
759
Will Deacon518f7132014-11-14 17:17:54 +0000760 /* TTBRs */
761 if (stage1) {
762 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];
763 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
764 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32;
Will Deacon44680ee2014-06-25 11:29:12 +0100765 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
Will Deacon518f7132014-11-14 17:17:54 +0000766 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100767
Will Deacon518f7132014-11-14 17:17:54 +0000768 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
769 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO);
770 reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32;
771 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT;
772 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI);
773 } else {
774 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
775 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
776 reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32;
777 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
778 }
Will Deacon45ae7cf2013-06-24 18:31:25 +0100779
Will Deacon518f7132014-11-14 17:17:54 +0000780 /* TTBCR */
781 if (stage1) {
782 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
783 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
784 if (smmu->version > ARM_SMMU_V1) {
785 reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
786 switch (smmu->va_size) {
Will Deacon45ae7cf2013-06-24 18:31:25 +0100787 case 32:
Will Deacon518f7132014-11-14 17:17:54 +0000788 reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100789 break;
790 case 36:
Will Deacon518f7132014-11-14 17:17:54 +0000791 reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100792 break;
793 case 40:
Will Deacon518f7132014-11-14 17:17:54 +0000794 reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100795 break;
796 case 42:
Will Deacon518f7132014-11-14 17:17:54 +0000797 reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100798 break;
799 case 44:
Will Deacon518f7132014-11-14 17:17:54 +0000800 reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100801 break;
802 case 48:
Will Deacon518f7132014-11-14 17:17:54 +0000803 reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100804 break;
805 }
Will Deacon518f7132014-11-14 17:17:54 +0000806 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100807 }
808 } else {
Will Deacon518f7132014-11-14 17:17:54 +0000809 reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
810 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100811 }
812
Will Deacon518f7132014-11-14 17:17:54 +0000813 /* MAIRs (stage-1 only) */
Will Deacon45ae7cf2013-06-24 18:31:25 +0100814 if (stage1) {
Will Deacon518f7132014-11-14 17:17:54 +0000815 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
Will Deacon45ae7cf2013-06-24 18:31:25 +0100816 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
Will Deacon518f7132014-11-14 17:17:54 +0000817 reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
818 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100819 }
820
Will Deacon45ae7cf2013-06-24 18:31:25 +0100821 /* SCTLR */
822 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
823 if (stage1)
824 reg |= SCTLR_S1_ASIDPNE;
825#ifdef __BIG_ENDIAN
826 reg |= SCTLR_E;
827#endif
Will Deacon25724842013-08-21 13:49:53 +0100828 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100829}
830
831static int arm_smmu_init_domain_context(struct iommu_domain *domain,
Will Deacon44680ee2014-06-25 11:29:12 +0100832 struct arm_smmu_device *smmu)
Will Deacon45ae7cf2013-06-24 18:31:25 +0100833{
Mitchel Humpherysa18037b2014-07-30 18:58:13 +0100834 int irq, start, ret = 0;
Will Deacon518f7132014-11-14 17:17:54 +0000835 unsigned long ias, oas;
836 struct io_pgtable_ops *pgtbl_ops;
837 struct io_pgtable_cfg pgtbl_cfg;
838 enum io_pgtable_fmt fmt;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100839 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon44680ee2014-06-25 11:29:12 +0100840 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100841
Will Deacon518f7132014-11-14 17:17:54 +0000842 mutex_lock(&smmu_domain->init_mutex);
Mitchel Humpherysa18037b2014-07-30 18:58:13 +0100843 if (smmu_domain->smmu)
844 goto out_unlock;
845
Will Deaconc752ce42014-06-25 22:46:31 +0100846 /*
847 * Mapping the requested stage onto what we support is surprisingly
848 * complicated, mainly because the spec allows S1+S2 SMMUs without
849 * support for nested translation. That means we end up with the
850 * following table:
851 *
852 * Requested Supported Actual
853 * S1 N S1
854 * S1 S1+S2 S1
855 * S1 S2 S2
856 * S1 S1 S1
857 * N N N
858 * N S1+S2 S2
859 * N S2 S2
860 * N S1 S1
861 *
862 * Note that you can't actually request stage-2 mappings.
863 */
864 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
865 smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
866 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
867 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
868
869 switch (smmu_domain->stage) {
870 case ARM_SMMU_DOMAIN_S1:
871 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
872 start = smmu->num_s2_context_banks;
Will Deacon518f7132014-11-14 17:17:54 +0000873 ias = smmu->va_size;
874 oas = smmu->ipa_size;
875 if (IS_ENABLED(CONFIG_64BIT))
876 fmt = ARM_64_LPAE_S1;
877 else
878 fmt = ARM_32_LPAE_S1;
Will Deaconc752ce42014-06-25 22:46:31 +0100879 break;
880 case ARM_SMMU_DOMAIN_NESTED:
Will Deacon45ae7cf2013-06-24 18:31:25 +0100881 /*
882 * We will likely want to change this if/when KVM gets
883 * involved.
884 */
Will Deaconc752ce42014-06-25 22:46:31 +0100885 case ARM_SMMU_DOMAIN_S2:
Will Deacon9c5c92e2014-06-25 12:12:41 +0100886 cfg->cbar = CBAR_TYPE_S2_TRANS;
887 start = 0;
Will Deacon518f7132014-11-14 17:17:54 +0000888 ias = smmu->ipa_size;
889 oas = smmu->pa_size;
890 if (IS_ENABLED(CONFIG_64BIT))
891 fmt = ARM_64_LPAE_S2;
892 else
893 fmt = ARM_32_LPAE_S2;
Will Deaconc752ce42014-06-25 22:46:31 +0100894 break;
895 default:
896 ret = -EINVAL;
897 goto out_unlock;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100898 }
899
900 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
901 smmu->num_context_banks);
902 if (IS_ERR_VALUE(ret))
Mitchel Humpherysa18037b2014-07-30 18:58:13 +0100903 goto out_unlock;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100904
Will Deacon44680ee2014-06-25 11:29:12 +0100905 cfg->cbndx = ret;
Robin Murphy09360402014-08-28 17:51:59 +0100906 if (smmu->version == ARM_SMMU_V1) {
Will Deacon44680ee2014-06-25 11:29:12 +0100907 cfg->irptndx = atomic_inc_return(&smmu->irptndx);
908 cfg->irptndx %= smmu->num_context_irqs;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100909 } else {
Will Deacon44680ee2014-06-25 11:29:12 +0100910 cfg->irptndx = cfg->cbndx;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100911 }
912
Will Deacon518f7132014-11-14 17:17:54 +0000913 pgtbl_cfg = (struct io_pgtable_cfg) {
914 .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap,
915 .ias = ias,
916 .oas = oas,
917 .tlb = &arm_smmu_gather_ops,
918 };
Mitchel Humpherysa18037b2014-07-30 18:58:13 +0100919
Will Deacon518f7132014-11-14 17:17:54 +0000920 smmu_domain->smmu = smmu;
921 pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
922 if (!pgtbl_ops) {
923 ret = -ENOMEM;
924 goto out_clear_smmu;
925 }
926
927 /* Update our support page sizes to reflect the page table format */
928 arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
929
930 /* Initialise the context bank with our page table cfg */
931 arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);
932
933 /*
934 * Request context fault interrupt. Do this last to avoid the
935 * handler seeing a half-initialised domain state.
936 */
Will Deacon44680ee2014-06-25 11:29:12 +0100937 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
Will Deacon45ae7cf2013-06-24 18:31:25 +0100938 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
939 "arm-smmu-context-fault", domain);
940 if (IS_ERR_VALUE(ret)) {
941 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
Will Deacon44680ee2014-06-25 11:29:12 +0100942 cfg->irptndx, irq);
943 cfg->irptndx = INVALID_IRPTNDX;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100944 }
945
Will Deacon518f7132014-11-14 17:17:54 +0000946 mutex_unlock(&smmu_domain->init_mutex);
947
948 /* Publish page table ops for map/unmap */
949 smmu_domain->pgtbl_ops = pgtbl_ops;
Will Deacona9a1b0b2014-05-01 18:05:08 +0100950 return 0;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100951
Will Deacon518f7132014-11-14 17:17:54 +0000952out_clear_smmu:
953 smmu_domain->smmu = NULL;
Mitchel Humpherysa18037b2014-07-30 18:58:13 +0100954out_unlock:
Will Deacon518f7132014-11-14 17:17:54 +0000955 mutex_unlock(&smmu_domain->init_mutex);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100956 return ret;
957}
958
959static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
960{
961 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon44680ee2014-06-25 11:29:12 +0100962 struct arm_smmu_device *smmu = smmu_domain->smmu;
963 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
Will Deacon1463fe42013-07-31 19:21:27 +0100964 void __iomem *cb_base;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100965 int irq;
966
967 if (!smmu)
968 return;
969
Will Deacon518f7132014-11-14 17:17:54 +0000970 /*
971 * Disable the context bank and free the page tables before freeing
972 * it.
973 */
Will Deacon44680ee2014-06-25 11:29:12 +0100974 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
Will Deacon1463fe42013-07-31 19:21:27 +0100975 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
Will Deacon1463fe42013-07-31 19:21:27 +0100976
Will Deacon44680ee2014-06-25 11:29:12 +0100977 if (cfg->irptndx != INVALID_IRPTNDX) {
978 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
Will Deacon45ae7cf2013-06-24 18:31:25 +0100979 free_irq(irq, domain);
980 }
981
Will Deacon518f7132014-11-14 17:17:54 +0000982 if (smmu_domain->pgtbl_ops)
983 free_io_pgtable_ops(smmu_domain->pgtbl_ops);
984
Will Deacon44680ee2014-06-25 11:29:12 +0100985 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
Will Deacon45ae7cf2013-06-24 18:31:25 +0100986}
987
988static int arm_smmu_domain_init(struct iommu_domain *domain)
989{
990 struct arm_smmu_domain *smmu_domain;
Will Deacon45ae7cf2013-06-24 18:31:25 +0100991
992 /*
993 * Allocate the domain and initialise some of its data structures.
994 * We can't really do anything meaningful until we've added a
995 * master.
996 */
997 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
998 if (!smmu_domain)
999 return -ENOMEM;
1000
Will Deacon518f7132014-11-14 17:17:54 +00001001 mutex_init(&smmu_domain->init_mutex);
1002 spin_lock_init(&smmu_domain->pgtbl_lock);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001003 domain->priv = smmu_domain;
1004 return 0;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001005}
1006
1007static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1008{
1009 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon1463fe42013-07-31 19:21:27 +01001010
1011 /*
1012 * Free the domain resources. We assume that all devices have
1013 * already been detached.
1014 */
Will Deacon45ae7cf2013-06-24 18:31:25 +01001015 arm_smmu_destroy_domain_context(domain);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001016 kfree(smmu_domain);
1017}
1018
1019static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
Will Deacona9a1b0b2014-05-01 18:05:08 +01001020 struct arm_smmu_master_cfg *cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001021{
1022 int i;
1023 struct arm_smmu_smr *smrs;
1024 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1025
1026 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1027 return 0;
1028
Will Deacona9a1b0b2014-05-01 18:05:08 +01001029 if (cfg->smrs)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001030 return -EEXIST;
1031
Mitchel Humpherys29073202014-07-08 09:52:18 -07001032 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001033 if (!smrs) {
Will Deacona9a1b0b2014-05-01 18:05:08 +01001034 dev_err(smmu->dev, "failed to allocate %d SMRs\n",
1035 cfg->num_streamids);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001036 return -ENOMEM;
1037 }
1038
Will Deacon44680ee2014-06-25 11:29:12 +01001039 /* Allocate the SMRs on the SMMU */
Will Deacona9a1b0b2014-05-01 18:05:08 +01001040 for (i = 0; i < cfg->num_streamids; ++i) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001041 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1042 smmu->num_mapping_groups);
1043 if (IS_ERR_VALUE(idx)) {
1044 dev_err(smmu->dev, "failed to allocate free SMR\n");
1045 goto err_free_smrs;
1046 }
1047
1048 smrs[i] = (struct arm_smmu_smr) {
1049 .idx = idx,
1050 .mask = 0, /* We don't currently share SMRs */
Will Deacona9a1b0b2014-05-01 18:05:08 +01001051 .id = cfg->streamids[i],
Will Deacon45ae7cf2013-06-24 18:31:25 +01001052 };
1053 }
1054
1055 /* It worked! Now, poke the actual hardware */
Will Deacona9a1b0b2014-05-01 18:05:08 +01001056 for (i = 0; i < cfg->num_streamids; ++i) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001057 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1058 smrs[i].mask << SMR_MASK_SHIFT;
1059 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1060 }
1061
Will Deacona9a1b0b2014-05-01 18:05:08 +01001062 cfg->smrs = smrs;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001063 return 0;
1064
1065err_free_smrs:
1066 while (--i >= 0)
1067 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1068 kfree(smrs);
1069 return -ENOSPC;
1070}
1071
1072static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
Will Deacona9a1b0b2014-05-01 18:05:08 +01001073 struct arm_smmu_master_cfg *cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001074{
1075 int i;
1076 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
Will Deacona9a1b0b2014-05-01 18:05:08 +01001077 struct arm_smmu_smr *smrs = cfg->smrs;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001078
Will Deacon43b412b2014-07-15 11:22:24 +01001079 if (!smrs)
1080 return;
1081
Will Deacon45ae7cf2013-06-24 18:31:25 +01001082 /* Invalidate the SMRs before freeing back to the allocator */
Will Deacona9a1b0b2014-05-01 18:05:08 +01001083 for (i = 0; i < cfg->num_streamids; ++i) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001084 u8 idx = smrs[i].idx;
Mitchel Humpherys29073202014-07-08 09:52:18 -07001085
Will Deacon45ae7cf2013-06-24 18:31:25 +01001086 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1087 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1088 }
1089
Will Deacona9a1b0b2014-05-01 18:05:08 +01001090 cfg->smrs = NULL;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001091 kfree(smrs);
1092}
1093
Will Deacon45ae7cf2013-06-24 18:31:25 +01001094static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
Will Deacona9a1b0b2014-05-01 18:05:08 +01001095 struct arm_smmu_master_cfg *cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001096{
1097 int i, ret;
Will Deacon44680ee2014-06-25 11:29:12 +01001098 struct arm_smmu_device *smmu = smmu_domain->smmu;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001099 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1100
Will Deacon8f68f8e2014-07-15 11:27:08 +01001101 /* Devices in an IOMMU group may already be configured */
Will Deacona9a1b0b2014-05-01 18:05:08 +01001102 ret = arm_smmu_master_configure_smrs(smmu, cfg);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001103 if (ret)
Will Deacon8f68f8e2014-07-15 11:27:08 +01001104 return ret == -EEXIST ? 0 : ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001105
Will Deacona9a1b0b2014-05-01 18:05:08 +01001106 for (i = 0; i < cfg->num_streamids; ++i) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001107 u32 idx, s2cr;
Mitchel Humpherys29073202014-07-08 09:52:18 -07001108
Will Deacona9a1b0b2014-05-01 18:05:08 +01001109 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
Kefeng Wang6069d232014-04-18 10:20:48 +08001110 s2cr = S2CR_TYPE_TRANS |
Will Deacon44680ee2014-06-25 11:29:12 +01001111 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001112 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1113 }
1114
1115 return 0;
1116}
1117
1118static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
Will Deacona9a1b0b2014-05-01 18:05:08 +01001119 struct arm_smmu_master_cfg *cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001120{
Will Deacon43b412b2014-07-15 11:22:24 +01001121 int i;
Will Deacon44680ee2014-06-25 11:29:12 +01001122 struct arm_smmu_device *smmu = smmu_domain->smmu;
Will Deacon43b412b2014-07-15 11:22:24 +01001123 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001124
Will Deacon8f68f8e2014-07-15 11:27:08 +01001125 /* An IOMMU group is torn down by the first device to be removed */
1126 if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
1127 return;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001128
1129 /*
1130 * We *must* clear the S2CR first, because freeing the SMR means
1131 * that it can be re-allocated immediately.
1132 */
Will Deacon43b412b2014-07-15 11:22:24 +01001133 for (i = 0; i < cfg->num_streamids; ++i) {
1134 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1135
1136 writel_relaxed(S2CR_TYPE_BYPASS,
1137 gr0_base + ARM_SMMU_GR0_S2CR(idx));
1138 }
1139
Will Deacona9a1b0b2014-05-01 18:05:08 +01001140 arm_smmu_master_free_smrs(smmu, cfg);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001141}
1142
1143static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1144{
Mitchel Humpherysa18037b2014-07-30 18:58:13 +01001145 int ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001146 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon518f7132014-11-14 17:17:54 +00001147 struct arm_smmu_device *smmu;
Will Deacona9a1b0b2014-05-01 18:05:08 +01001148 struct arm_smmu_master_cfg *cfg;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001149
Will Deacon8f68f8e2014-07-15 11:27:08 +01001150 smmu = find_smmu_for_device(dev);
Will Deacon44680ee2014-06-25 11:29:12 +01001151 if (!smmu) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001152 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1153 return -ENXIO;
1154 }
1155
Will Deacon844e35b2014-07-17 11:23:51 +01001156 if (dev->archdata.iommu) {
1157 dev_err(dev, "already attached to IOMMU domain\n");
1158 return -EEXIST;
1159 }
1160
Will Deacon518f7132014-11-14 17:17:54 +00001161 /* Ensure that the domain is finalised */
1162 ret = arm_smmu_init_domain_context(domain, smmu);
1163 if (IS_ERR_VALUE(ret))
1164 return ret;
1165
Will Deacon45ae7cf2013-06-24 18:31:25 +01001166 /*
Will Deacon44680ee2014-06-25 11:29:12 +01001167 * Sanity check the domain. We don't support domains across
1168 * different SMMUs.
Will Deacon45ae7cf2013-06-24 18:31:25 +01001169 */
Will Deacon518f7132014-11-14 17:17:54 +00001170 if (smmu_domain->smmu != smmu) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001171 dev_err(dev,
1172 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
Mitchel Humpherysa18037b2014-07-30 18:58:13 +01001173 dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
1174 return -EINVAL;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001175 }
Will Deacon45ae7cf2013-06-24 18:31:25 +01001176
1177 /* Looks ok, so add the device to the domain */
Will Deacon8f68f8e2014-07-15 11:27:08 +01001178 cfg = find_smmu_master_cfg(dev);
Will Deacona9a1b0b2014-05-01 18:05:08 +01001179 if (!cfg)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001180 return -ENODEV;
1181
Will Deacon844e35b2014-07-17 11:23:51 +01001182 ret = arm_smmu_domain_add_master(smmu_domain, cfg);
1183 if (!ret)
1184 dev->archdata.iommu = domain;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001185 return ret;
1186}
1187
1188static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1189{
1190 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacona9a1b0b2014-05-01 18:05:08 +01001191 struct arm_smmu_master_cfg *cfg;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001192
Will Deacon8f68f8e2014-07-15 11:27:08 +01001193 cfg = find_smmu_master_cfg(dev);
Will Deacon844e35b2014-07-17 11:23:51 +01001194 if (!cfg)
1195 return;
1196
1197 dev->archdata.iommu = NULL;
1198 arm_smmu_domain_remove_master(smmu_domain, cfg);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001199}
1200
Will Deacon45ae7cf2013-06-24 18:31:25 +01001201static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
Will Deaconb410aed2014-02-20 16:31:06 +00001202 phys_addr_t paddr, size_t size, int prot)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001203{
Will Deacon518f7132014-11-14 17:17:54 +00001204 int ret;
1205 unsigned long flags;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001206 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon518f7132014-11-14 17:17:54 +00001207 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001208
Will Deacon518f7132014-11-14 17:17:54 +00001209 if (!ops)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001210 return -ENODEV;
1211
Will Deacon518f7132014-11-14 17:17:54 +00001212 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1213 ret = ops->map(ops, iova, paddr, size, prot);
1214 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1215 return ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001216}
1217
1218static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1219 size_t size)
1220{
Will Deacon518f7132014-11-14 17:17:54 +00001221 size_t ret;
1222 unsigned long flags;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001223 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon518f7132014-11-14 17:17:54 +00001224 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001225
Will Deacon518f7132014-11-14 17:17:54 +00001226 if (!ops)
1227 return 0;
1228
1229 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1230 ret = ops->unmap(ops, iova, size);
1231 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1232 return ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001233}
1234
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001235static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
1236 dma_addr_t iova)
1237{
1238 struct arm_smmu_domain *smmu_domain = domain->priv;
1239 struct arm_smmu_device *smmu = smmu_domain->smmu;
1240 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1241 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1242 struct device *dev = smmu->dev;
1243 void __iomem *cb_base;
1244 u32 tmp;
1245 u64 phys;
1246
1247 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1248
1249 if (smmu->version == 1) {
1250 u32 reg = iova & ~0xfff;
1251 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
1252 } else {
1253 u32 reg = iova & ~0xfff;
1254 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO);
Arnd Bergmanna4188be2015-01-30 22:55:55 +01001255 reg = ((u64)iova & ~0xfff) >> 32;
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001256 writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI);
1257 }
1258
1259 if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
1260 !(tmp & ATSR_ACTIVE), 5, 50)) {
1261 dev_err(dev,
1262 "iova to phys timed out on 0x%pad. Falling back to software table walk.\n",
1263 &iova);
1264 return ops->iova_to_phys(ops, iova);
1265 }
1266
1267 phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO);
1268 phys |= ((u64)readl_relaxed(cb_base + ARM_SMMU_CB_PAR_HI)) << 32;
1269
1270 if (phys & CB_PAR_F) {
1271 dev_err(dev, "translation fault!\n");
1272 dev_err(dev, "PAR = 0x%llx\n", phys);
1273 return 0;
1274 }
1275
1276 return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
1277}
1278
Will Deacon45ae7cf2013-06-24 18:31:25 +01001279static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001280 dma_addr_t iova)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001281{
Will Deacon518f7132014-11-14 17:17:54 +00001282 phys_addr_t ret;
1283 unsigned long flags;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001284 struct arm_smmu_domain *smmu_domain = domain->priv;
Will Deacon518f7132014-11-14 17:17:54 +00001285 struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001286
Will Deacon518f7132014-11-14 17:17:54 +00001287 if (!ops)
Will Deacona44a9792013-11-07 18:47:50 +00001288 return 0;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001289
Will Deacon518f7132014-11-14 17:17:54 +00001290 spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001291 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS)
1292 ret = arm_smmu_iova_to_phys_hard(domain, iova);
1293 else
1294 ret = ops->iova_to_phys(ops, iova);
Will Deacon518f7132014-11-14 17:17:54 +00001295 spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001296
Will Deacon518f7132014-11-14 17:17:54 +00001297 return ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001298}
1299
Joerg Roedel1fd0c772014-09-05 10:49:34 +02001300static bool arm_smmu_capable(enum iommu_cap cap)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001301{
Will Deacond0948942014-06-24 17:30:10 +01001302 switch (cap) {
1303 case IOMMU_CAP_CACHE_COHERENCY:
Joerg Roedel1fd0c772014-09-05 10:49:34 +02001304 /*
1305 * Return true here as the SMMU can always send out coherent
1306 * requests.
1307 */
1308 return true;
Will Deacond0948942014-06-24 17:30:10 +01001309 case IOMMU_CAP_INTR_REMAP:
Joerg Roedel1fd0c772014-09-05 10:49:34 +02001310 return true; /* MSIs are just memory writes */
Antonios Motakis0029a8d2014-10-13 14:06:18 +01001311 case IOMMU_CAP_NOEXEC:
1312 return true;
Will Deacond0948942014-06-24 17:30:10 +01001313 default:
Joerg Roedel1fd0c772014-09-05 10:49:34 +02001314 return false;
Will Deacond0948942014-06-24 17:30:10 +01001315 }
Will Deacon45ae7cf2013-06-24 18:31:25 +01001316}
Will Deacon45ae7cf2013-06-24 18:31:25 +01001317
Will Deacona9a1b0b2014-05-01 18:05:08 +01001318static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
1319{
1320 *((u16 *)data) = alias;
1321 return 0; /* Continue walking */
Will Deacon45ae7cf2013-06-24 18:31:25 +01001322}
1323
Will Deacon8f68f8e2014-07-15 11:27:08 +01001324static void __arm_smmu_release_pci_iommudata(void *data)
1325{
1326 kfree(data);
1327}
1328
Will Deacon45ae7cf2013-06-24 18:31:25 +01001329static int arm_smmu_add_device(struct device *dev)
1330{
Will Deacona9a1b0b2014-05-01 18:05:08 +01001331 struct arm_smmu_device *smmu;
Will Deacon8f68f8e2014-07-15 11:27:08 +01001332 struct arm_smmu_master_cfg *cfg;
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001333 struct iommu_group *group;
Will Deacon8f68f8e2014-07-15 11:27:08 +01001334 void (*releasefn)(void *) = NULL;
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001335 int ret;
1336
Will Deacon44680ee2014-06-25 11:29:12 +01001337 smmu = find_smmu_for_device(dev);
Will Deacona9a1b0b2014-05-01 18:05:08 +01001338 if (!smmu)
Will Deacon45ae7cf2013-06-24 18:31:25 +01001339 return -ENODEV;
1340
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001341 group = iommu_group_alloc();
1342 if (IS_ERR(group)) {
1343 dev_err(dev, "Failed to allocate IOMMU group\n");
1344 return PTR_ERR(group);
1345 }
1346
Will Deacona9a1b0b2014-05-01 18:05:08 +01001347 if (dev_is_pci(dev)) {
Will Deacona9a1b0b2014-05-01 18:05:08 +01001348 struct pci_dev *pdev = to_pci_dev(dev);
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001349
Will Deacona9a1b0b2014-05-01 18:05:08 +01001350 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1351 if (!cfg) {
1352 ret = -ENOMEM;
1353 goto out_put_group;
1354 }
1355
1356 cfg->num_streamids = 1;
1357 /*
1358 * Assume Stream ID == Requester ID for now.
1359 * We need a way to describe the ID mappings in FDT.
1360 */
1361 pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid,
1362 &cfg->streamids[0]);
Will Deacon8f68f8e2014-07-15 11:27:08 +01001363 releasefn = __arm_smmu_release_pci_iommudata;
Will Deacona9a1b0b2014-05-01 18:05:08 +01001364 } else {
Will Deacon8f68f8e2014-07-15 11:27:08 +01001365 struct arm_smmu_master *master;
1366
1367 master = find_smmu_master(smmu, dev->of_node);
1368 if (!master) {
1369 ret = -ENODEV;
1370 goto out_put_group;
1371 }
1372
1373 cfg = &master->cfg;
Will Deacona9a1b0b2014-05-01 18:05:08 +01001374 }
1375
Will Deacon8f68f8e2014-07-15 11:27:08 +01001376 iommu_group_set_iommudata(group, cfg, releasefn);
Will Deacona9a1b0b2014-05-01 18:05:08 +01001377 ret = iommu_group_add_device(group, dev);
1378
1379out_put_group:
1380 iommu_group_put(group);
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001381 return ret;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001382}
1383
1384static void arm_smmu_remove_device(struct device *dev)
1385{
Antonios Motakis5fc63a72013-10-18 16:08:29 +01001386 iommu_group_remove_device(dev);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001387}
1388
Will Deaconc752ce42014-06-25 22:46:31 +01001389static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
1390 enum iommu_attr attr, void *data)
1391{
1392 struct arm_smmu_domain *smmu_domain = domain->priv;
1393
1394 switch (attr) {
1395 case DOMAIN_ATTR_NESTING:
1396 *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
1397 return 0;
1398 default:
1399 return -ENODEV;
1400 }
1401}
1402
1403static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
1404 enum iommu_attr attr, void *data)
1405{
Will Deacon518f7132014-11-14 17:17:54 +00001406 int ret = 0;
Will Deaconc752ce42014-06-25 22:46:31 +01001407 struct arm_smmu_domain *smmu_domain = domain->priv;
1408
Will Deacon518f7132014-11-14 17:17:54 +00001409 mutex_lock(&smmu_domain->init_mutex);
1410
Will Deaconc752ce42014-06-25 22:46:31 +01001411 switch (attr) {
1412 case DOMAIN_ATTR_NESTING:
Will Deacon518f7132014-11-14 17:17:54 +00001413 if (smmu_domain->smmu) {
1414 ret = -EPERM;
1415 goto out_unlock;
1416 }
1417
Will Deaconc752ce42014-06-25 22:46:31 +01001418 if (*(int *)data)
1419 smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
1420 else
1421 smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
1422
Will Deacon518f7132014-11-14 17:17:54 +00001423 break;
Will Deaconc752ce42014-06-25 22:46:31 +01001424 default:
Will Deacon518f7132014-11-14 17:17:54 +00001425 ret = -ENODEV;
Will Deaconc752ce42014-06-25 22:46:31 +01001426 }
Will Deacon518f7132014-11-14 17:17:54 +00001427
1428out_unlock:
1429 mutex_unlock(&smmu_domain->init_mutex);
1430 return ret;
Will Deaconc752ce42014-06-25 22:46:31 +01001431}
1432
Will Deacon518f7132014-11-14 17:17:54 +00001433static struct iommu_ops arm_smmu_ops = {
Will Deaconc752ce42014-06-25 22:46:31 +01001434 .capable = arm_smmu_capable,
1435 .domain_init = arm_smmu_domain_init,
1436 .domain_destroy = arm_smmu_domain_destroy,
1437 .attach_dev = arm_smmu_attach_dev,
1438 .detach_dev = arm_smmu_detach_dev,
1439 .map = arm_smmu_map,
1440 .unmap = arm_smmu_unmap,
Joerg Roedel76771c92014-12-02 13:07:13 +01001441 .map_sg = default_iommu_map_sg,
Will Deaconc752ce42014-06-25 22:46:31 +01001442 .iova_to_phys = arm_smmu_iova_to_phys,
1443 .add_device = arm_smmu_add_device,
1444 .remove_device = arm_smmu_remove_device,
1445 .domain_get_attr = arm_smmu_domain_get_attr,
1446 .domain_set_attr = arm_smmu_domain_set_attr,
Will Deacon518f7132014-11-14 17:17:54 +00001447 .pgsize_bitmap = -1UL, /* Restricted during device attach */
Will Deacon45ae7cf2013-06-24 18:31:25 +01001448};
1449
1450static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1451{
1452 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001453 void __iomem *cb_base;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001454 int i = 0;
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001455 u32 reg;
1456
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +00001457 /* clear global FSR */
1458 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1459 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001460
1461 /* Mark all SMRn as invalid and all S2CRn as bypass */
1462 for (i = 0; i < smmu->num_mapping_groups; ++i) {
Olav Haugan3c8766d2014-08-22 17:12:32 -07001463 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
Mitchel Humpherys29073202014-07-08 09:52:18 -07001464 writel_relaxed(S2CR_TYPE_BYPASS,
1465 gr0_base + ARM_SMMU_GR0_S2CR(i));
Will Deacon45ae7cf2013-06-24 18:31:25 +01001466 }
1467
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001468 /* Make sure all context banks are disabled and clear CB_FSR */
1469 for (i = 0; i < smmu->num_context_banks; ++i) {
1470 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1471 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1472 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1473 }
Will Deacon1463fe42013-07-31 19:21:27 +01001474
Will Deacon45ae7cf2013-06-24 18:31:25 +01001475 /* Invalidate the TLB, just in case */
Will Deacon45ae7cf2013-06-24 18:31:25 +01001476 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1477 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1478
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +00001479 reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001480
Will Deacon45ae7cf2013-06-24 18:31:25 +01001481 /* Enable fault reporting */
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001482 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001483
1484 /* Disable TLB broadcasting. */
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001485 reg |= (sCR0_VMIDPNE | sCR0_PTM);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001486
1487 /* Enable client access, but bypass when no mapping is found */
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001488 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001489
1490 /* Disable forced broadcasting */
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001491 reg &= ~sCR0_FB;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001492
1493 /* Don't upgrade barriers */
Andreas Herrmann659db6f2013-10-01 13:39:09 +01001494 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001495
1496 /* Push the button */
Will Deacon518f7132014-11-14 17:17:54 +00001497 __arm_smmu_tlb_sync(smmu);
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +00001498 writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001499}
1500
1501static int arm_smmu_id_size_to_bits(int size)
1502{
1503 switch (size) {
1504 case 0:
1505 return 32;
1506 case 1:
1507 return 36;
1508 case 2:
1509 return 40;
1510 case 3:
1511 return 42;
1512 case 4:
1513 return 44;
1514 case 5:
1515 default:
1516 return 48;
1517 }
1518}
1519
1520static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1521{
1522 unsigned long size;
1523 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1524 u32 id;
1525
1526 dev_notice(smmu->dev, "probing hardware configuration...\n");
Will Deacon45ae7cf2013-06-24 18:31:25 +01001527 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1528
1529 /* ID0 */
1530 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
Will Deacon4cf740b2014-07-14 19:47:39 +01001531
1532 /* Restrict available stages based on module parameter */
1533 if (force_stage == 1)
1534 id &= ~(ID0_S2TS | ID0_NTS);
1535 else if (force_stage == 2)
1536 id &= ~(ID0_S1TS | ID0_NTS);
1537
Will Deacon45ae7cf2013-06-24 18:31:25 +01001538 if (id & ID0_S1TS) {
1539 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1540 dev_notice(smmu->dev, "\tstage 1 translation\n");
1541 }
1542
1543 if (id & ID0_S2TS) {
1544 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1545 dev_notice(smmu->dev, "\tstage 2 translation\n");
1546 }
1547
1548 if (id & ID0_NTS) {
1549 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1550 dev_notice(smmu->dev, "\tnested translation\n");
1551 }
1552
1553 if (!(smmu->features &
Will Deacon4cf740b2014-07-14 19:47:39 +01001554 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001555 dev_err(smmu->dev, "\tno translation support!\n");
1556 return -ENODEV;
1557 }
1558
Mitchel Humpherys859a7322014-10-29 21:13:40 +00001559 if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {
1560 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
1561 dev_notice(smmu->dev, "\taddress translation ops\n");
1562 }
1563
Will Deacon45ae7cf2013-06-24 18:31:25 +01001564 if (id & ID0_CTTW) {
1565 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1566 dev_notice(smmu->dev, "\tcoherent table walk\n");
1567 }
1568
1569 if (id & ID0_SMS) {
1570 u32 smr, sid, mask;
1571
1572 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1573 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1574 ID0_NUMSMRG_MASK;
1575 if (smmu->num_mapping_groups == 0) {
1576 dev_err(smmu->dev,
1577 "stream-matching supported, but no SMRs present!\n");
1578 return -ENODEV;
1579 }
1580
1581 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1582 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1583 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1584 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1585
1586 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1587 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1588 if ((mask & sid) != sid) {
1589 dev_err(smmu->dev,
1590 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1591 mask, sid);
1592 return -ENODEV;
1593 }
1594
1595 dev_notice(smmu->dev,
1596 "\tstream matching with %u register groups, mask 0x%x",
1597 smmu->num_mapping_groups, mask);
Olav Haugan3c8766d2014-08-22 17:12:32 -07001598 } else {
1599 smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
1600 ID0_NUMSIDB_MASK;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001601 }
1602
1603 /* ID1 */
1604 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
Will Deaconc757e852014-07-30 11:33:25 +01001605 smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001606
Andreas Herrmannc55af7f2013-10-01 13:39:06 +01001607 /* Check for size mismatch of SMMU address space from mapped region */
Will Deacon518f7132014-11-14 17:17:54 +00001608 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
Will Deaconc757e852014-07-30 11:33:25 +01001609 size *= 2 << smmu->pgshift;
Andreas Herrmannc55af7f2013-10-01 13:39:06 +01001610 if (smmu->size != size)
Mitchel Humpherys29073202014-07-08 09:52:18 -07001611 dev_warn(smmu->dev,
1612 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1613 size, smmu->size);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001614
Will Deacon518f7132014-11-14 17:17:54 +00001615 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001616 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1617 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1618 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1619 return -ENODEV;
1620 }
1621 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1622 smmu->num_context_banks, smmu->num_s2_context_banks);
1623
1624 /* ID2 */
1625 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1626 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
Will Deacon518f7132014-11-14 17:17:54 +00001627 smmu->ipa_size = size;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001628
Will Deacon518f7132014-11-14 17:17:54 +00001629 /* The output mask is also applied for bypass */
Will Deacon45ae7cf2013-06-24 18:31:25 +01001630 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
Will Deacon518f7132014-11-14 17:17:54 +00001631 smmu->pa_size = size;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001632
Robin Murphy09360402014-08-28 17:51:59 +01001633 if (smmu->version == ARM_SMMU_V1) {
Will Deacon518f7132014-11-14 17:17:54 +00001634 smmu->va_size = smmu->ipa_size;
1635 size = SZ_4K | SZ_2M | SZ_1G;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001636 } else {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001637 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
Will Deacon518f7132014-11-14 17:17:54 +00001638 smmu->va_size = arm_smmu_id_size_to_bits(size);
1639#ifndef CONFIG_64BIT
1640 smmu->va_size = min(32UL, smmu->va_size);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001641#endif
Will Deacon518f7132014-11-14 17:17:54 +00001642 size = 0;
1643 if (id & ID2_PTFS_4K)
1644 size |= SZ_4K | SZ_2M | SZ_1G;
1645 if (id & ID2_PTFS_16K)
1646 size |= SZ_16K | SZ_32M;
1647 if (id & ID2_PTFS_64K)
1648 size |= SZ_64K | SZ_512M;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001649 }
1650
Will Deacon518f7132014-11-14 17:17:54 +00001651 arm_smmu_ops.pgsize_bitmap &= size;
1652 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size);
1653
Will Deacon28d60072014-09-01 16:24:48 +01001654 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
1655 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
Will Deacon518f7132014-11-14 17:17:54 +00001656 smmu->va_size, smmu->ipa_size);
Will Deacon28d60072014-09-01 16:24:48 +01001657
1658 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
1659 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
Will Deacon518f7132014-11-14 17:17:54 +00001660 smmu->ipa_size, smmu->pa_size);
Will Deacon28d60072014-09-01 16:24:48 +01001661
Will Deacon45ae7cf2013-06-24 18:31:25 +01001662 return 0;
1663}
1664
Joerg Roedel09b52692014-10-02 12:24:45 +02001665static const struct of_device_id arm_smmu_of_match[] = {
Robin Murphy09360402014-08-28 17:51:59 +01001666 { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 },
1667 { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 },
1668 { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
Robin Murphyd3aba042014-08-28 17:52:00 +01001669 { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
Robin Murphy09360402014-08-28 17:51:59 +01001670 { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
1671 { },
1672};
1673MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1674
Will Deacon45ae7cf2013-06-24 18:31:25 +01001675static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1676{
Robin Murphy09360402014-08-28 17:51:59 +01001677 const struct of_device_id *of_id;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001678 struct resource *res;
1679 struct arm_smmu_device *smmu;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001680 struct device *dev = &pdev->dev;
1681 struct rb_node *node;
1682 struct of_phandle_args masterspec;
1683 int num_irqs, i, err;
1684
1685 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1686 if (!smmu) {
1687 dev_err(dev, "failed to allocate arm_smmu_device\n");
1688 return -ENOMEM;
1689 }
1690 smmu->dev = dev;
1691
Robin Murphy09360402014-08-28 17:51:59 +01001692 of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1693 smmu->version = (enum arm_smmu_arch_version)of_id->data;
1694
Will Deacon45ae7cf2013-06-24 18:31:25 +01001695 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Julia Lawall8a7f4312013-08-19 12:20:37 +01001696 smmu->base = devm_ioremap_resource(dev, res);
1697 if (IS_ERR(smmu->base))
1698 return PTR_ERR(smmu->base);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001699 smmu->size = resource_size(res);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001700
1701 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1702 &smmu->num_global_irqs)) {
1703 dev_err(dev, "missing #global-interrupts property\n");
1704 return -ENODEV;
1705 }
1706
1707 num_irqs = 0;
1708 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1709 num_irqs++;
1710 if (num_irqs > smmu->num_global_irqs)
1711 smmu->num_context_irqs++;
1712 }
1713
Andreas Herrmann44a08de2013-10-01 13:39:07 +01001714 if (!smmu->num_context_irqs) {
1715 dev_err(dev, "found %d interrupts but expected at least %d\n",
1716 num_irqs, smmu->num_global_irqs + 1);
1717 return -ENODEV;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001718 }
Will Deacon45ae7cf2013-06-24 18:31:25 +01001719
1720 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1721 GFP_KERNEL);
1722 if (!smmu->irqs) {
1723 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1724 return -ENOMEM;
1725 }
1726
1727 for (i = 0; i < num_irqs; ++i) {
1728 int irq = platform_get_irq(pdev, i);
Mitchel Humpherys29073202014-07-08 09:52:18 -07001729
Will Deacon45ae7cf2013-06-24 18:31:25 +01001730 if (irq < 0) {
1731 dev_err(dev, "failed to get irq index %d\n", i);
1732 return -ENODEV;
1733 }
1734 smmu->irqs[i] = irq;
1735 }
1736
Olav Haugan3c8766d2014-08-22 17:12:32 -07001737 err = arm_smmu_device_cfg_probe(smmu);
1738 if (err)
1739 return err;
1740
Will Deacon45ae7cf2013-06-24 18:31:25 +01001741 i = 0;
1742 smmu->masters = RB_ROOT;
1743 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1744 "#stream-id-cells", i,
1745 &masterspec)) {
1746 err = register_smmu_master(smmu, dev, &masterspec);
1747 if (err) {
1748 dev_err(dev, "failed to add master %s\n",
1749 masterspec.np->name);
1750 goto out_put_masters;
1751 }
1752
1753 i++;
1754 }
1755 dev_notice(dev, "registered %d master devices\n", i);
1756
Andreas Herrmann3a5df8f2014-01-30 18:18:04 +00001757 parse_driver_options(smmu);
1758
Robin Murphy09360402014-08-28 17:51:59 +01001759 if (smmu->version > ARM_SMMU_V1 &&
Will Deacon45ae7cf2013-06-24 18:31:25 +01001760 smmu->num_context_banks != smmu->num_context_irqs) {
1761 dev_err(dev,
1762 "found only %d context interrupt(s) but %d required\n",
1763 smmu->num_context_irqs, smmu->num_context_banks);
Wei Yongjun89a23cd2013-11-15 09:42:30 +00001764 err = -ENODEV;
Will Deacon44680ee2014-06-25 11:29:12 +01001765 goto out_put_masters;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001766 }
1767
Will Deacon45ae7cf2013-06-24 18:31:25 +01001768 for (i = 0; i < smmu->num_global_irqs; ++i) {
1769 err = request_irq(smmu->irqs[i],
1770 arm_smmu_global_fault,
1771 IRQF_SHARED,
1772 "arm-smmu global fault",
1773 smmu);
1774 if (err) {
1775 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1776 i, smmu->irqs[i]);
1777 goto out_free_irqs;
1778 }
1779 }
1780
1781 INIT_LIST_HEAD(&smmu->list);
1782 spin_lock(&arm_smmu_devices_lock);
1783 list_add(&smmu->list, &arm_smmu_devices);
1784 spin_unlock(&arm_smmu_devices_lock);
Will Deaconfd90cec2013-08-21 13:56:34 +01001785
1786 arm_smmu_device_reset(smmu);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001787 return 0;
1788
1789out_free_irqs:
1790 while (i--)
1791 free_irq(smmu->irqs[i], smmu);
1792
Will Deacon45ae7cf2013-06-24 18:31:25 +01001793out_put_masters:
1794 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
Mitchel Humpherys29073202014-07-08 09:52:18 -07001795 struct arm_smmu_master *master
1796 = container_of(node, struct arm_smmu_master, node);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001797 of_node_put(master->of_node);
1798 }
1799
1800 return err;
1801}
1802
1803static int arm_smmu_device_remove(struct platform_device *pdev)
1804{
1805 int i;
1806 struct device *dev = &pdev->dev;
1807 struct arm_smmu_device *curr, *smmu = NULL;
1808 struct rb_node *node;
1809
1810 spin_lock(&arm_smmu_devices_lock);
1811 list_for_each_entry(curr, &arm_smmu_devices, list) {
1812 if (curr->dev == dev) {
1813 smmu = curr;
1814 list_del(&smmu->list);
1815 break;
1816 }
1817 }
1818 spin_unlock(&arm_smmu_devices_lock);
1819
1820 if (!smmu)
1821 return -ENODEV;
1822
Will Deacon45ae7cf2013-06-24 18:31:25 +01001823 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
Mitchel Humpherys29073202014-07-08 09:52:18 -07001824 struct arm_smmu_master *master
1825 = container_of(node, struct arm_smmu_master, node);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001826 of_node_put(master->of_node);
1827 }
1828
Will Deaconecfadb62013-07-31 19:21:28 +01001829 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
Will Deacon45ae7cf2013-06-24 18:31:25 +01001830 dev_err(dev, "removing device with active domains!\n");
1831
1832 for (i = 0; i < smmu->num_global_irqs; ++i)
1833 free_irq(smmu->irqs[i], smmu);
1834
1835 /* Turn the thing off */
Mitchel Humpherys29073202014-07-08 09:52:18 -07001836 writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001837 return 0;
1838}
1839
Will Deacon45ae7cf2013-06-24 18:31:25 +01001840static struct platform_driver arm_smmu_driver = {
1841 .driver = {
Will Deacon45ae7cf2013-06-24 18:31:25 +01001842 .name = "arm-smmu",
1843 .of_match_table = of_match_ptr(arm_smmu_of_match),
1844 },
1845 .probe = arm_smmu_device_dt_probe,
1846 .remove = arm_smmu_device_remove,
1847};
1848
1849static int __init arm_smmu_init(void)
1850{
Thierry Reding0e7d37a2014-11-07 15:26:18 +00001851 struct device_node *np;
Will Deacon45ae7cf2013-06-24 18:31:25 +01001852 int ret;
1853
Thierry Reding0e7d37a2014-11-07 15:26:18 +00001854 /*
1855 * Play nice with systems that don't have an ARM SMMU by checking that
1856 * an ARM SMMU exists in the system before proceeding with the driver
1857 * and IOMMU bus operation registration.
1858 */
1859 np = of_find_matching_node(NULL, arm_smmu_of_match);
1860 if (!np)
1861 return 0;
1862
1863 of_node_put(np);
1864
Will Deacon45ae7cf2013-06-24 18:31:25 +01001865 ret = platform_driver_register(&arm_smmu_driver);
1866 if (ret)
1867 return ret;
1868
1869 /* Oh, for a proper bus abstraction */
Dan Carpenter6614ee72013-08-21 09:34:20 +01001870 if (!iommu_present(&platform_bus_type))
Will Deacon45ae7cf2013-06-24 18:31:25 +01001871 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1872
Will Deacond123cf82014-02-04 22:17:53 +00001873#ifdef CONFIG_ARM_AMBA
Dan Carpenter6614ee72013-08-21 09:34:20 +01001874 if (!iommu_present(&amba_bustype))
Will Deacon45ae7cf2013-06-24 18:31:25 +01001875 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
Will Deacond123cf82014-02-04 22:17:53 +00001876#endif
Will Deacon45ae7cf2013-06-24 18:31:25 +01001877
Will Deacona9a1b0b2014-05-01 18:05:08 +01001878#ifdef CONFIG_PCI
1879 if (!iommu_present(&pci_bus_type))
1880 bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
1881#endif
1882
Will Deacon45ae7cf2013-06-24 18:31:25 +01001883 return 0;
1884}
1885
1886static void __exit arm_smmu_exit(void)
1887{
1888 return platform_driver_unregister(&arm_smmu_driver);
1889}
1890
Andreas Herrmannb1950b22013-10-01 13:39:05 +01001891subsys_initcall(arm_smmu_init);
Will Deacon45ae7cf2013-06-24 18:31:25 +01001892module_exit(arm_smmu_exit);
1893
1894MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1895MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1896MODULE_LICENSE("GPL v2");