Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Broadcom BCM63xx SPI controller support |
| 3 | * |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 4 | * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 5 | * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version 2 |
| 10 | * of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <linux/kernel.h> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 19 | #include <linux/clk.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/spi/spi.h> |
| 26 | #include <linux/completion.h> |
| 27 | #include <linux/err.h> |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 28 | #include <linux/pm_runtime.h> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 29 | |
| 30 | #include <bcm63xx_dev_spi.h> |
| 31 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 32 | #define BCM63XX_SPI_MAX_PREPEND 15 |
| 33 | |
Jonas Gorski | 6505999 | 2015-09-10 16:11:40 +0200 | [diff] [blame] | 34 | #define BCM63XX_SPI_MAX_CS 8 |
Jonas Gorski | a45fcea | 2015-09-10 16:11:41 +0200 | [diff] [blame^] | 35 | #define BCM63XX_SPI_BUS_NUM 0 |
Jonas Gorski | 6505999 | 2015-09-10 16:11:40 +0200 | [diff] [blame] | 36 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 37 | struct bcm63xx_spi { |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 38 | struct completion done; |
| 39 | |
| 40 | void __iomem *regs; |
| 41 | int irq; |
| 42 | |
| 43 | /* Platform data */ |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 44 | unsigned fifo_size; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 45 | unsigned int msg_type_shift; |
| 46 | unsigned int msg_ctl_width; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 47 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 48 | /* data iomem */ |
| 49 | u8 __iomem *tx_io; |
| 50 | const u8 __iomem *rx_io; |
| 51 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 52 | struct clk *clk; |
| 53 | struct platform_device *pdev; |
| 54 | }; |
| 55 | |
| 56 | static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, |
| 57 | unsigned int offset) |
| 58 | { |
| 59 | return bcm_readb(bs->regs + bcm63xx_spireg(offset)); |
| 60 | } |
| 61 | |
| 62 | static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, |
| 63 | unsigned int offset) |
| 64 | { |
| 65 | return bcm_readw(bs->regs + bcm63xx_spireg(offset)); |
| 66 | } |
| 67 | |
| 68 | static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, |
| 69 | u8 value, unsigned int offset) |
| 70 | { |
| 71 | bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); |
| 72 | } |
| 73 | |
| 74 | static inline void bcm_spi_writew(struct bcm63xx_spi *bs, |
| 75 | u16 value, unsigned int offset) |
| 76 | { |
| 77 | bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); |
| 78 | } |
| 79 | |
| 80 | static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { |
| 81 | { 20000000, SPI_CLK_20MHZ }, |
| 82 | { 12500000, SPI_CLK_12_50MHZ }, |
| 83 | { 6250000, SPI_CLK_6_250MHZ }, |
| 84 | { 3125000, SPI_CLK_3_125MHZ }, |
| 85 | { 1563000, SPI_CLK_1_563MHZ }, |
| 86 | { 781000, SPI_CLK_0_781MHZ }, |
| 87 | { 391000, SPI_CLK_0_391MHZ } |
| 88 | }; |
| 89 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 90 | static void bcm63xx_spi_setup_transfer(struct spi_device *spi, |
| 91 | struct spi_transfer *t) |
| 92 | { |
| 93 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 94 | u8 clk_cfg, reg; |
| 95 | int i; |
| 96 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 97 | /* Find the closest clock configuration */ |
| 98 | for (i = 0; i < SPI_CLK_MASK; i++) { |
Jonas Gorski | 68792e2 | 2013-03-12 00:13:46 +0100 | [diff] [blame] | 99 | if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 100 | clk_cfg = bcm63xx_spi_freq_table[i][1]; |
| 101 | break; |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | /* No matching configuration found, default to lowest */ |
| 106 | if (i == SPI_CLK_MASK) |
| 107 | clk_cfg = SPI_CLK_0_391MHZ; |
| 108 | |
| 109 | /* clear existing clock configuration bits of the register */ |
| 110 | reg = bcm_spi_readb(bs, SPI_CLK_CFG); |
| 111 | reg &= ~SPI_CLK_MASK; |
| 112 | reg |= clk_cfg; |
| 113 | |
| 114 | bcm_spi_writeb(bs, reg, SPI_CLK_CFG); |
| 115 | dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", |
Jonas Gorski | 68792e2 | 2013-03-12 00:13:46 +0100 | [diff] [blame] | 116 | clk_cfg, t->speed_hz); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | /* the spi->mode bits understood by this driver: */ |
| 120 | #define MODEBITS (SPI_CPOL | SPI_CPHA) |
| 121 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 122 | static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
| 123 | unsigned int num_transfers) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 124 | { |
| 125 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
| 126 | u16 msg_ctl; |
| 127 | u16 cmd; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 128 | unsigned int i, timeout = 0, prepend_len = 0, len = 0; |
| 129 | struct spi_transfer *t = first; |
| 130 | bool do_rx = false; |
| 131 | bool do_tx = false; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 132 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 133 | /* Disable the CMD_DONE interrupt */ |
| 134 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
| 135 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 136 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
| 137 | t->tx_buf, t->rx_buf, t->len); |
| 138 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 139 | if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
| 140 | prepend_len = t->len; |
| 141 | |
| 142 | /* prepare the buffer */ |
| 143 | for (i = 0; i < num_transfers; i++) { |
| 144 | if (t->tx_buf) { |
| 145 | do_tx = true; |
| 146 | memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); |
| 147 | |
| 148 | /* don't prepend more than one tx */ |
| 149 | if (t != first) |
| 150 | prepend_len = 0; |
| 151 | } |
| 152 | |
| 153 | if (t->rx_buf) { |
| 154 | do_rx = true; |
| 155 | /* prepend is half-duplex write only */ |
| 156 | if (t == first) |
| 157 | prepend_len = 0; |
| 158 | } |
| 159 | |
| 160 | len += t->len; |
| 161 | |
| 162 | t = list_entry(t->transfer_list.next, struct spi_transfer, |
| 163 | transfer_list); |
| 164 | } |
| 165 | |
Axel Lin | aa0fe82 | 2014-02-09 11:06:04 +0800 | [diff] [blame] | 166 | reinit_completion(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 167 | |
| 168 | /* Fill in the Message control register */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 169 | msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 170 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 171 | if (do_rx && do_tx && prepend_len == 0) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 172 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 173 | else if (do_rx) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 174 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 175 | else if (do_tx) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 176 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 177 | |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 178 | switch (bs->msg_ctl_width) { |
| 179 | case 8: |
| 180 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); |
| 181 | break; |
| 182 | case 16: |
| 183 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); |
| 184 | break; |
| 185 | } |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 186 | |
| 187 | /* Issue the transfer */ |
| 188 | cmd = SPI_CMD_START_IMMEDIATE; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 189 | cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 190 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
| 191 | bcm_spi_writew(bs, cmd, SPI_CMD); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 192 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 193 | /* Enable the CMD_DONE interrupt */ |
| 194 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 195 | |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 196 | timeout = wait_for_completion_timeout(&bs->done, HZ); |
| 197 | if (!timeout) |
| 198 | return -ETIMEDOUT; |
| 199 | |
Jonas Gorski | 20e9e78 | 2013-12-17 21:42:08 +0100 | [diff] [blame] | 200 | if (!do_rx) |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 201 | return 0; |
| 202 | |
| 203 | len = 0; |
| 204 | t = first; |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 205 | /* Read out all the data */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 206 | for (i = 0; i < num_transfers; i++) { |
| 207 | if (t->rx_buf) |
| 208 | memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); |
| 209 | |
| 210 | if (t != first || prepend_len == 0) |
| 211 | len += t->len; |
| 212 | |
| 213 | t = list_entry(t->transfer_list.next, struct spi_transfer, |
| 214 | transfer_list); |
| 215 | } |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 216 | |
| 217 | return 0; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 218 | } |
| 219 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 220 | static int bcm63xx_spi_transfer_one(struct spi_master *master, |
| 221 | struct spi_message *m) |
| 222 | { |
| 223 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 224 | struct spi_transfer *t, *first = NULL; |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 225 | struct spi_device *spi = m->spi; |
| 226 | int status = 0; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 227 | unsigned int n_transfers = 0, total_len = 0; |
| 228 | bool can_use_prepend = false; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 229 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 230 | /* |
| 231 | * This SPI controller does not support keeping CS active after a |
| 232 | * transfer. |
| 233 | * Work around this by merging as many transfers we can into one big |
| 234 | * full-duplex transfers. |
| 235 | */ |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 236 | list_for_each_entry(t, &m->transfers, transfer_list) { |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 237 | if (!first) |
| 238 | first = t; |
| 239 | |
| 240 | n_transfers++; |
| 241 | total_len += t->len; |
| 242 | |
| 243 | if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && |
| 244 | first->len <= BCM63XX_SPI_MAX_PREPEND) |
| 245 | can_use_prepend = true; |
| 246 | else if (can_use_prepend && t->tx_buf) |
| 247 | can_use_prepend = false; |
| 248 | |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 249 | /* we can only transfer one fifo worth of data */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 250 | if ((can_use_prepend && |
| 251 | total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || |
| 252 | (!can_use_prepend && total_len > bs->fifo_size)) { |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 253 | dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 254 | total_len, bs->fifo_size); |
| 255 | status = -EINVAL; |
| 256 | goto exit; |
| 257 | } |
| 258 | |
| 259 | /* all combined transfers have to have the same speed */ |
| 260 | if (t->speed_hz != first->speed_hz) { |
| 261 | dev_err(&spi->dev, "unable to change speed between transfers\n"); |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 262 | status = -EINVAL; |
| 263 | goto exit; |
| 264 | } |
| 265 | |
| 266 | /* CS will be deasserted directly after transfer */ |
| 267 | if (t->delay_usecs) { |
| 268 | dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); |
| 269 | status = -EINVAL; |
| 270 | goto exit; |
| 271 | } |
| 272 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 273 | if (t->cs_change || |
| 274 | list_is_last(&t->transfer_list, &m->transfers)) { |
| 275 | /* configure adapter for a new transfer */ |
| 276 | bcm63xx_spi_setup_transfer(spi, first); |
| 277 | |
| 278 | /* send the data */ |
| 279 | status = bcm63xx_txrx_bufs(spi, first, n_transfers); |
| 280 | if (status) |
| 281 | goto exit; |
| 282 | |
| 283 | m->actual_length += total_len; |
| 284 | |
| 285 | first = NULL; |
| 286 | n_transfers = 0; |
| 287 | total_len = 0; |
| 288 | can_use_prepend = false; |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 289 | } |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 290 | } |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 291 | exit: |
| 292 | m->status = status; |
| 293 | spi_finalize_current_message(master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 294 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 295 | return 0; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | /* This driver supports single master mode only. Hence |
| 299 | * CMD_DONE is the only interrupt we care about |
| 300 | */ |
| 301 | static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) |
| 302 | { |
| 303 | struct spi_master *master = (struct spi_master *)dev_id; |
| 304 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 305 | u8 intr; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 306 | |
| 307 | /* Read interupts and clear them immediately */ |
| 308 | intr = bcm_spi_readb(bs, SPI_INT_STATUS); |
| 309 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
| 310 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
| 311 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 312 | /* A transfer completed */ |
| 313 | if (intr & SPI_INTR_CMD_DONE) |
| 314 | complete(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 315 | |
| 316 | return IRQ_HANDLED; |
| 317 | } |
| 318 | |
| 319 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 320 | static int bcm63xx_spi_probe(struct platform_device *pdev) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 321 | { |
| 322 | struct resource *r; |
| 323 | struct device *dev = &pdev->dev; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 324 | struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 325 | int irq; |
| 326 | struct spi_master *master; |
| 327 | struct clk *clk; |
| 328 | struct bcm63xx_spi *bs; |
| 329 | int ret; |
| 330 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 331 | irq = platform_get_irq(pdev, 0); |
| 332 | if (irq < 0) { |
| 333 | dev_err(dev, "no irq\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 334 | return -ENXIO; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 335 | } |
| 336 | |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 337 | clk = devm_clk_get(dev, "spi"); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 338 | if (IS_ERR(clk)) { |
| 339 | dev_err(dev, "no clock for device\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 340 | return PTR_ERR(clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | master = spi_alloc_master(dev, sizeof(*bs)); |
| 344 | if (!master) { |
| 345 | dev_err(dev, "out of memory\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 346 | return -ENOMEM; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | bs = spi_master_get_devdata(master); |
Axel Lin | aa0fe82 | 2014-02-09 11:06:04 +0800 | [diff] [blame] | 350 | init_completion(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 351 | |
| 352 | platform_set_drvdata(pdev, master); |
| 353 | bs->pdev = pdev; |
| 354 | |
Julia Lawall | de0fa83 | 2013-08-14 11:11:09 +0200 | [diff] [blame] | 355 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jonas Gorski | b66c773 | 2013-03-12 00:13:47 +0100 | [diff] [blame] | 356 | bs->regs = devm_ioremap_resource(&pdev->dev, r); |
| 357 | if (IS_ERR(bs->regs)) { |
| 358 | ret = PTR_ERR(bs->regs); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 359 | goto out_err; |
| 360 | } |
| 361 | |
| 362 | bs->irq = irq; |
| 363 | bs->clk = clk; |
| 364 | bs->fifo_size = pdata->fifo_size; |
| 365 | |
| 366 | ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, |
| 367 | pdev->name, master); |
| 368 | if (ret) { |
| 369 | dev_err(dev, "unable to request irq\n"); |
| 370 | goto out_err; |
| 371 | } |
| 372 | |
Jonas Gorski | a45fcea | 2015-09-10 16:11:41 +0200 | [diff] [blame^] | 373 | master->bus_num = BCM63XX_SPI_BUS_NUM; |
Jonas Gorski | 6505999 | 2015-09-10 16:11:40 +0200 | [diff] [blame] | 374 | master->num_chipselect = BCM63XX_SPI_MAX_CS; |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 375 | master->transfer_one_message = bcm63xx_spi_transfer_one; |
Florian Fainelli | 88a3a25 | 2012-04-20 15:37:35 +0200 | [diff] [blame] | 376 | master->mode_bits = MODEBITS; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 377 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
Mark Brown | 5355d96 | 2013-07-28 15:34:06 +0100 | [diff] [blame] | 378 | master->auto_runtime_pm = true; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 379 | bs->msg_type_shift = pdata->msg_type_shift; |
| 380 | bs->msg_ctl_width = pdata->msg_ctl_width; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 381 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); |
| 382 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 383 | |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 384 | switch (bs->msg_ctl_width) { |
| 385 | case 8: |
| 386 | case 16: |
| 387 | break; |
| 388 | default: |
| 389 | dev_err(dev, "unsupported MSG_CTL width: %d\n", |
| 390 | bs->msg_ctl_width); |
Jonas Gorski | b435ff2 | 2013-03-12 00:13:37 +0100 | [diff] [blame] | 391 | goto out_err; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 392 | } |
| 393 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 394 | /* Initialize hardware */ |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 395 | ret = clk_prepare_enable(bs->clk); |
| 396 | if (ret) |
| 397 | goto out_err; |
| 398 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 399 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
| 400 | |
| 401 | /* register and we are done */ |
Jingoo Han | bca7693 | 2013-09-24 13:24:57 +0900 | [diff] [blame] | 402 | ret = devm_spi_register_master(dev, master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 403 | if (ret) { |
| 404 | dev_err(dev, "spi register failed\n"); |
| 405 | goto out_clk_disable; |
| 406 | } |
| 407 | |
Florian Fainelli | 61d1596 | 2012-10-03 11:56:53 +0200 | [diff] [blame] | 408 | dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", |
| 409 | r->start, irq, bs->fifo_size); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 410 | |
| 411 | return 0; |
| 412 | |
| 413 | out_clk_disable: |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 414 | clk_disable_unprepare(clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 415 | out_err: |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 416 | spi_master_put(master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 417 | return ret; |
| 418 | } |
| 419 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 420 | static int bcm63xx_spi_remove(struct platform_device *pdev) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 421 | { |
Wei Yongjun | 9637b86 | 2013-11-15 15:50:59 +0800 | [diff] [blame] | 422 | struct spi_master *master = platform_get_drvdata(pdev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 423 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 424 | |
| 425 | /* reset spi block */ |
| 426 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 427 | |
| 428 | /* HW shutdown */ |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 429 | clk_disable_unprepare(bs->clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 430 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 431 | return 0; |
| 432 | } |
| 433 | |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 434 | #ifdef CONFIG_PM_SLEEP |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 435 | static int bcm63xx_spi_suspend(struct device *dev) |
| 436 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 437 | struct spi_master *master = dev_get_drvdata(dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 438 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 439 | |
Florian Fainelli | 9651995 | 2012-10-03 11:56:54 +0200 | [diff] [blame] | 440 | spi_master_suspend(master); |
| 441 | |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 442 | clk_disable_unprepare(bs->clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 443 | |
| 444 | return 0; |
| 445 | } |
| 446 | |
| 447 | static int bcm63xx_spi_resume(struct device *dev) |
| 448 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 449 | struct spi_master *master = dev_get_drvdata(dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 450 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 451 | int ret; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 452 | |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 453 | ret = clk_prepare_enable(bs->clk); |
| 454 | if (ret) |
| 455 | return ret; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 456 | |
Florian Fainelli | 9651995 | 2012-10-03 11:56:54 +0200 | [diff] [blame] | 457 | spi_master_resume(master); |
| 458 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 459 | return 0; |
| 460 | } |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 461 | #endif |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 462 | |
| 463 | static const struct dev_pm_ops bcm63xx_spi_pm_ops = { |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 464 | SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 465 | }; |
| 466 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 467 | static struct platform_driver bcm63xx_spi_driver = { |
| 468 | .driver = { |
| 469 | .name = "bcm63xx-spi", |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 470 | .pm = &bcm63xx_spi_pm_ops, |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 471 | }, |
| 472 | .probe = bcm63xx_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 473 | .remove = bcm63xx_spi_remove, |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 474 | }; |
| 475 | |
| 476 | module_platform_driver(bcm63xx_spi_driver); |
| 477 | |
| 478 | MODULE_ALIAS("platform:bcm63xx_spi"); |
| 479 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); |
| 480 | MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); |
| 481 | MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); |
| 482 | MODULE_LICENSE("GPL"); |