Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 1 | /include/ "skeleton.dtsi" |
| 2 | |
| 3 | / { |
| 4 | compatible = "marvell,dove"; |
| 5 | model = "Marvell Armada 88AP510 SoC"; |
| 6 | |
Sebastian Hesselbarth | 9139acd | 2012-11-19 10:39:55 +0100 | [diff] [blame] | 7 | aliases { |
| 8 | gpio0 = &gpio0; |
| 9 | gpio1 = &gpio1; |
| 10 | gpio2 = &gpio2; |
| 11 | }; |
| 12 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 13 | cpus { |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <0>; |
| 16 | |
| 17 | cpu0: cpu@0 { |
| 18 | compatible = "marvell,pj4a", "marvell,sheeva-v7"; |
| 19 | device_type = "cpu"; |
| 20 | next-level-cache = <&l2>; |
| 21 | reg = <0>; |
| 22 | }; |
| 23 | }; |
| 24 | |
| 25 | l2: l2-cache { |
| 26 | compatible = "marvell,tauros2-cache"; |
| 27 | marvell,tauros2-cache-features = <0>; |
| 28 | }; |
| 29 | |
Sebastian Hesselbarth | 138ee96 | 2012-09-25 02:02:16 +0200 | [diff] [blame] | 30 | soc@f1000000 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 31 | compatible = "simple-bus"; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 32 | #address-cells = <1>; |
| 33 | #size-cells = <1>; |
Sebastian Hesselbarth | 138ee96 | 2012-09-25 02:02:16 +0200 | [diff] [blame] | 34 | interrupt-parent = <&intc>; |
| 35 | |
| 36 | ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ |
| 37 | 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ |
| 38 | 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ |
| 39 | 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ |
| 40 | 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ |
| 41 | 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ |
| 42 | 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ |
| 43 | 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 44 | |
Sebastian Hesselbarth | 953b710 | 2013-07-02 13:03:37 +0200 | [diff] [blame] | 45 | timer: timer@20300 { |
| 46 | compatible = "marvell,orion-timer"; |
| 47 | reg = <0x20300 0x20>; |
| 48 | interrupt-parent = <&bridge_intc>; |
| 49 | interrupts = <1>, <2>; |
| 50 | clocks = <&core_clk 0>; |
| 51 | }; |
| 52 | |
| 53 | intc: main-interrupt-ctrl@20200 { |
Sebastian Hesselbarth | 138ee96 | 2012-09-25 02:02:16 +0200 | [diff] [blame] | 54 | compatible = "marvell,orion-intc"; |
| 55 | interrupt-controller; |
| 56 | #interrupt-cells = <1>; |
Sebastian Hesselbarth | 953b710 | 2013-07-02 13:03:37 +0200 | [diff] [blame] | 57 | reg = <0x20200 0x10>, <0x20210 0x10>; |
| 58 | }; |
| 59 | |
| 60 | bridge_intc: bridge-interrupt-ctrl@20110 { |
| 61 | compatible = "marvell,orion-bridge-intc"; |
| 62 | interrupt-controller; |
| 63 | #interrupt-cells = <1>; |
| 64 | reg = <0x20110 0x8>; |
| 65 | interrupts = <0>; |
| 66 | marvell,#interrupts = <5>; |
Sebastian Hesselbarth | 138ee96 | 2012-09-25 02:02:16 +0200 | [diff] [blame] | 67 | }; |
| 68 | |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 69 | core_clk: core-clocks@d0214 { |
| 70 | compatible = "marvell,dove-core-clock"; |
| 71 | reg = <0xd0214 0x4>; |
| 72 | #clock-cells = <1>; |
| 73 | }; |
| 74 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 75 | gate_clk: clock-gating-ctrl@d0038 { |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 76 | compatible = "marvell,dove-gating-clock"; |
| 77 | reg = <0xd0038 0x4>; |
| 78 | clocks = <&core_clk 0>; |
| 79 | #clock-cells = <1>; |
| 80 | }; |
| 81 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 82 | thermal: thermal-diode@d001c { |
Andrew Lunn | c3117ed | 2013-02-06 07:35:27 +0100 | [diff] [blame] | 83 | compatible = "marvell,dove-thermal"; |
| 84 | reg = <0xd001c 0x0c>, <0xd005c 0x08>; |
| 85 | }; |
| 86 | |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 87 | uart0: serial@12000 { |
| 88 | compatible = "ns16550a"; |
| 89 | reg = <0x12000 0x100>; |
| 90 | reg-shift = <2>; |
| 91 | interrupts = <7>; |
Sebastian Hesselbarth | 8be7a96 | 2013-01-29 21:59:46 +0100 | [diff] [blame] | 92 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 93 | status = "disabled"; |
| 94 | }; |
| 95 | |
| 96 | uart1: serial@12100 { |
| 97 | compatible = "ns16550a"; |
| 98 | reg = <0x12100 0x100>; |
| 99 | reg-shift = <2>; |
| 100 | interrupts = <8>; |
Sebastian Hesselbarth | 8be7a96 | 2013-01-29 21:59:46 +0100 | [diff] [blame] | 101 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 102 | pinctrl-0 = <&pmx_uart1>; |
| 103 | pinctrl-names = "default"; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 104 | status = "disabled"; |
| 105 | }; |
| 106 | |
| 107 | uart2: serial@12200 { |
| 108 | compatible = "ns16550a"; |
| 109 | reg = <0x12000 0x100>; |
| 110 | reg-shift = <2>; |
| 111 | interrupts = <9>; |
Sebastian Hesselbarth | 8be7a96 | 2013-01-29 21:59:46 +0100 | [diff] [blame] | 112 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 113 | status = "disabled"; |
| 114 | }; |
| 115 | |
| 116 | uart3: serial@12300 { |
| 117 | compatible = "ns16550a"; |
| 118 | reg = <0x12100 0x100>; |
| 119 | reg-shift = <2>; |
| 120 | interrupts = <10>; |
Sebastian Hesselbarth | 8be7a96 | 2013-01-29 21:59:46 +0100 | [diff] [blame] | 121 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 122 | status = "disabled"; |
| 123 | }; |
| 124 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 125 | gpio0: gpio-ctrl@d0400 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 126 | compatible = "marvell,orion-gpio"; |
| 127 | #gpio-cells = <2>; |
| 128 | gpio-controller; |
| 129 | reg = <0xd0400 0x20>; |
Sebastian Hesselbarth | 9139acd | 2012-11-19 10:39:55 +0100 | [diff] [blame] | 130 | ngpios = <32>; |
| 131 | interrupt-controller; |
Jean-Francois Moine | fd2704e | 2013-01-23 09:38:16 +0100 | [diff] [blame] | 132 | #interrupt-cells = <2>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 133 | interrupts = <12>, <13>, <14>, <60>; |
| 134 | }; |
| 135 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 136 | gpio1: gpio-ctrl@d0420 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 137 | compatible = "marvell,orion-gpio"; |
| 138 | #gpio-cells = <2>; |
| 139 | gpio-controller; |
| 140 | reg = <0xd0420 0x20>; |
Sebastian Hesselbarth | 9139acd | 2012-11-19 10:39:55 +0100 | [diff] [blame] | 141 | ngpios = <32>; |
| 142 | interrupt-controller; |
Jean-Francois Moine | fd2704e | 2013-01-23 09:38:16 +0100 | [diff] [blame] | 143 | #interrupt-cells = <2>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 144 | interrupts = <61>; |
| 145 | }; |
| 146 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 147 | gpio2: gpio-ctrl@e8400 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 148 | compatible = "marvell,orion-gpio"; |
| 149 | #gpio-cells = <2>; |
| 150 | gpio-controller; |
| 151 | reg = <0xe8400 0x0c>; |
Sebastian Hesselbarth | 9139acd | 2012-11-19 10:39:55 +0100 | [diff] [blame] | 152 | ngpios = <8>; |
| 153 | }; |
| 154 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 155 | pinctrl: pin-ctrl@d0200 { |
Sebastian Hesselbarth | 9139acd | 2012-11-19 10:39:55 +0100 | [diff] [blame] | 156 | compatible = "marvell,dove-pinctrl"; |
| 157 | reg = <0xd0200 0x10>; |
Sebastian Hesselbarth | db7d77e | 2012-11-26 20:16:38 +0100 | [diff] [blame] | 158 | clocks = <&gate_clk 22>; |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 159 | |
| 160 | pmx_gpio_0: pmx-gpio-0 { |
| 161 | marvell,pins = "mpp0"; |
| 162 | marvell,function = "gpio"; |
| 163 | }; |
| 164 | |
| 165 | pmx_gpio_1: pmx-gpio-1 { |
| 166 | marvell,pins = "mpp1"; |
| 167 | marvell,function = "gpio"; |
| 168 | }; |
| 169 | |
| 170 | pmx_gpio_2: pmx-gpio-2 { |
| 171 | marvell,pins = "mpp2"; |
| 172 | marvell,function = "gpio"; |
| 173 | }; |
| 174 | |
| 175 | pmx_gpio_3: pmx-gpio-3 { |
| 176 | marvell,pins = "mpp3"; |
| 177 | marvell,function = "gpio"; |
| 178 | }; |
| 179 | |
| 180 | pmx_gpio_4: pmx-gpio-4 { |
| 181 | marvell,pins = "mpp4"; |
| 182 | marvell,function = "gpio"; |
| 183 | }; |
| 184 | |
| 185 | pmx_gpio_5: pmx-gpio-5 { |
| 186 | marvell,pins = "mpp5"; |
| 187 | marvell,function = "gpio"; |
| 188 | }; |
| 189 | |
| 190 | pmx_gpio_6: pmx-gpio-6 { |
| 191 | marvell,pins = "mpp6"; |
| 192 | marvell,function = "gpio"; |
| 193 | }; |
| 194 | |
| 195 | pmx_gpio_7: pmx-gpio-7 { |
| 196 | marvell,pins = "mpp7"; |
| 197 | marvell,function = "gpio"; |
| 198 | }; |
| 199 | |
| 200 | pmx_gpio_8: pmx-gpio-8 { |
| 201 | marvell,pins = "mpp8"; |
| 202 | marvell,function = "gpio"; |
| 203 | }; |
| 204 | |
| 205 | pmx_gpio_9: pmx-gpio-9 { |
| 206 | marvell,pins = "mpp9"; |
| 207 | marvell,function = "gpio"; |
| 208 | }; |
| 209 | |
| 210 | pmx_gpio_10: pmx-gpio-10 { |
| 211 | marvell,pins = "mpp10"; |
| 212 | marvell,function = "gpio"; |
| 213 | }; |
| 214 | |
| 215 | pmx_gpio_11: pmx-gpio-11 { |
| 216 | marvell,pins = "mpp11"; |
| 217 | marvell,function = "gpio"; |
| 218 | }; |
| 219 | |
| 220 | pmx_gpio_12: pmx-gpio-12 { |
| 221 | marvell,pins = "mpp12"; |
| 222 | marvell,function = "gpio"; |
| 223 | }; |
| 224 | |
| 225 | pmx_gpio_13: pmx-gpio-13 { |
| 226 | marvell,pins = "mpp13"; |
| 227 | marvell,function = "gpio"; |
| 228 | }; |
| 229 | |
| 230 | pmx_gpio_14: pmx-gpio-14 { |
| 231 | marvell,pins = "mpp14"; |
| 232 | marvell,function = "gpio"; |
| 233 | }; |
| 234 | |
| 235 | pmx_gpio_15: pmx-gpio-15 { |
| 236 | marvell,pins = "mpp15"; |
| 237 | marvell,function = "gpio"; |
| 238 | }; |
| 239 | |
| 240 | pmx_gpio_16: pmx-gpio-16 { |
| 241 | marvell,pins = "mpp16"; |
| 242 | marvell,function = "gpio"; |
| 243 | }; |
| 244 | |
| 245 | pmx_gpio_17: pmx-gpio-17 { |
| 246 | marvell,pins = "mpp17"; |
| 247 | marvell,function = "gpio"; |
| 248 | }; |
| 249 | |
| 250 | pmx_gpio_18: pmx-gpio-18 { |
| 251 | marvell,pins = "mpp18"; |
| 252 | marvell,function = "gpio"; |
| 253 | }; |
| 254 | |
| 255 | pmx_gpio_19: pmx-gpio-19 { |
| 256 | marvell,pins = "mpp19"; |
| 257 | marvell,function = "gpio"; |
| 258 | }; |
| 259 | |
| 260 | pmx_gpio_20: pmx-gpio-20 { |
| 261 | marvell,pins = "mpp20"; |
| 262 | marvell,function = "gpio"; |
| 263 | }; |
| 264 | |
| 265 | pmx_gpio_21: pmx-gpio-21 { |
| 266 | marvell,pins = "mpp21"; |
| 267 | marvell,function = "gpio"; |
| 268 | }; |
| 269 | |
| 270 | pmx_camera: pmx-camera { |
| 271 | marvell,pins = "mpp_camera"; |
| 272 | marvell,function = "camera"; |
| 273 | }; |
| 274 | |
| 275 | pmx_camera_gpio: pmx-camera-gpio { |
| 276 | marvell,pins = "mpp_camera"; |
| 277 | marvell,function = "gpio"; |
| 278 | }; |
| 279 | |
| 280 | pmx_sdio0: pmx-sdio0 { |
| 281 | marvell,pins = "mpp_sdio0"; |
| 282 | marvell,function = "sdio0"; |
| 283 | }; |
| 284 | |
| 285 | pmx_sdio0_gpio: pmx-sdio0-gpio { |
| 286 | marvell,pins = "mpp_sdio0"; |
| 287 | marvell,function = "gpio"; |
| 288 | }; |
| 289 | |
| 290 | pmx_sdio1: pmx-sdio1 { |
| 291 | marvell,pins = "mpp_sdio1"; |
| 292 | marvell,function = "sdio1"; |
| 293 | }; |
| 294 | |
| 295 | pmx_sdio1_gpio: pmx-sdio1-gpio { |
| 296 | marvell,pins = "mpp_sdio1"; |
| 297 | marvell,function = "gpio"; |
| 298 | }; |
| 299 | |
| 300 | pmx_audio1_gpio: pmx-audio1-gpio { |
| 301 | marvell,pins = "mpp_audio1"; |
| 302 | marvell,function = "gpio"; |
| 303 | }; |
| 304 | |
| 305 | pmx_spi0: pmx-spi0 { |
| 306 | marvell,pins = "mpp_spi0"; |
| 307 | marvell,function = "spi0"; |
| 308 | }; |
| 309 | |
| 310 | pmx_spi0_gpio: pmx-spi0-gpio { |
| 311 | marvell,pins = "mpp_spi0"; |
| 312 | marvell,function = "gpio"; |
| 313 | }; |
| 314 | |
| 315 | pmx_uart1: pmx-uart1 { |
| 316 | marvell,pins = "mpp_uart1"; |
| 317 | marvell,function = "uart1"; |
| 318 | }; |
| 319 | |
| 320 | pmx_uart1_gpio: pmx-uart1-gpio { |
| 321 | marvell,pins = "mpp_uart1"; |
| 322 | marvell,function = "gpio"; |
| 323 | }; |
| 324 | |
| 325 | pmx_nand: pmx-nand { |
| 326 | marvell,pins = "mpp_nand"; |
| 327 | marvell,function = "nand"; |
| 328 | }; |
| 329 | |
| 330 | pmx_nand_gpo: pmx-nand-gpo { |
| 331 | marvell,pins = "mpp_nand"; |
| 332 | marvell,function = "gpo"; |
| 333 | }; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 334 | }; |
| 335 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 336 | spi0: spi-ctrl@10600 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 337 | compatible = "marvell,orion-spi"; |
| 338 | #address-cells = <1>; |
| 339 | #size-cells = <0>; |
| 340 | cell-index = <0>; |
| 341 | interrupts = <6>; |
| 342 | reg = <0x10600 0x28>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 343 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 344 | pinctrl-0 = <&pmx_spi0>; |
| 345 | pinctrl-names = "default"; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 346 | status = "disabled"; |
| 347 | }; |
| 348 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 349 | spi1: spi-ctrl@14600 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 350 | compatible = "marvell,orion-spi"; |
| 351 | #address-cells = <1>; |
| 352 | #size-cells = <0>; |
| 353 | cell-index = <1>; |
| 354 | interrupts = <5>; |
| 355 | reg = <0x14600 0x28>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 356 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 357 | status = "disabled"; |
| 358 | }; |
| 359 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 360 | i2c0: i2c-ctrl@11000 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 361 | compatible = "marvell,mv64xxx-i2c"; |
| 362 | reg = <0x11000 0x20>; |
| 363 | #address-cells = <1>; |
| 364 | #size-cells = <0>; |
| 365 | interrupts = <11>; |
| 366 | clock-frequency = <400000>; |
| 367 | timeout-ms = <1000>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 368 | clocks = <&core_clk 0>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 369 | status = "disabled"; |
| 370 | }; |
| 371 | |
Sebastian Hesselbarth | a1abcd7 | 2013-01-28 16:54:08 +0100 | [diff] [blame] | 372 | ehci0: usb-host@50000 { |
| 373 | compatible = "marvell,orion-ehci"; |
| 374 | reg = <0x50000 0x1000>; |
| 375 | interrupts = <24>; |
| 376 | clocks = <&gate_clk 0>; |
| 377 | status = "okay"; |
| 378 | }; |
| 379 | |
| 380 | ehci1: usb-host@51000 { |
| 381 | compatible = "marvell,orion-ehci"; |
| 382 | reg = <0x51000 0x1000>; |
| 383 | interrupts = <25>; |
| 384 | clocks = <&gate_clk 1>; |
| 385 | status = "okay"; |
| 386 | }; |
| 387 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 388 | sdio0: sdio-host@92000 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 389 | compatible = "marvell,dove-sdhci"; |
| 390 | reg = <0x92000 0x100>; |
| 391 | interrupts = <35>, <37>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 392 | clocks = <&gate_clk 8>; |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 393 | pinctrl-0 = <&pmx_sdio0>; |
| 394 | pinctrl-names = "default"; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 395 | status = "disabled"; |
| 396 | }; |
| 397 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 398 | sdio1: sdio-host@90000 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 399 | compatible = "marvell,dove-sdhci"; |
| 400 | reg = <0x90000 0x100>; |
| 401 | interrupts = <36>, <38>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 402 | clocks = <&gate_clk 9>; |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 403 | pinctrl-0 = <&pmx_sdio1>; |
| 404 | pinctrl-names = "default"; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 405 | status = "disabled"; |
| 406 | }; |
| 407 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 408 | sata0: sata-host@a0000 { |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 409 | compatible = "marvell,orion-sata"; |
| 410 | reg = <0xa0000 0x2400>; |
| 411 | interrupts = <62>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 412 | clocks = <&gate_clk 3>; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 413 | nr-ports = <1>; |
| 414 | status = "disabled"; |
| 415 | }; |
Sebastian Hesselbarth | a458926 | 2012-09-25 02:02:18 +0200 | [diff] [blame] | 416 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 417 | rtc: real-time-clock@d8500 { |
Jean-Francois Moine | 85c0c13 | 2013-03-08 12:13:17 +0100 | [diff] [blame] | 418 | compatible = "marvell,orion-rtc"; |
| 419 | reg = <0xd8500 0x20>; |
| 420 | }; |
| 421 | |
Sebastian Hesselbarth | 2d29983 | 2013-07-29 14:29:03 +0200 | [diff] [blame] | 422 | crypto: crypto-engine@30000 { |
Sebastian Hesselbarth | a458926 | 2012-09-25 02:02:18 +0200 | [diff] [blame] | 423 | compatible = "marvell,orion-crypto"; |
| 424 | reg = <0x30000 0x10000>, |
| 425 | <0xc8000000 0x800>; |
| 426 | reg-names = "regs", "sram"; |
| 427 | interrupts = <31>; |
Sebastian Hesselbarth | 5b03df9 | 2012-11-17 15:22:27 +0100 | [diff] [blame] | 428 | clocks = <&gate_clk 15>; |
Sebastian Hesselbarth | a458926 | 2012-09-25 02:02:18 +0200 | [diff] [blame] | 429 | status = "okay"; |
| 430 | }; |
Sebastian Hesselbarth | 49f175b | 2012-11-19 09:37:24 +0100 | [diff] [blame] | 431 | |
| 432 | xor0: dma-engine@60800 { |
| 433 | compatible = "marvell,orion-xor"; |
| 434 | reg = <0x60800 0x100 |
| 435 | 0x60a00 0x100>; |
| 436 | clocks = <&gate_clk 23>; |
| 437 | status = "okay"; |
| 438 | |
| 439 | channel0 { |
| 440 | interrupts = <39>; |
| 441 | dmacap,memcpy; |
| 442 | dmacap,xor; |
| 443 | }; |
| 444 | |
| 445 | channel1 { |
| 446 | interrupts = <40>; |
| 447 | dmacap,memset; |
| 448 | dmacap,memcpy; |
| 449 | dmacap,xor; |
| 450 | }; |
| 451 | }; |
| 452 | |
| 453 | xor1: dma-engine@60900 { |
| 454 | compatible = "marvell,orion-xor"; |
| 455 | reg = <0x60900 0x100 |
| 456 | 0x60b00 0x100>; |
| 457 | clocks = <&gate_clk 24>; |
| 458 | status = "okay"; |
| 459 | |
| 460 | channel0 { |
| 461 | interrupts = <42>; |
| 462 | dmacap,memcpy; |
| 463 | dmacap,xor; |
| 464 | }; |
| 465 | |
| 466 | channel1 { |
| 467 | interrupts = <43>; |
| 468 | dmacap,memset; |
| 469 | dmacap,memcpy; |
| 470 | dmacap,xor; |
| 471 | }; |
| 472 | }; |
Sebastian Hesselbarth | 4c3f6b8 | 2013-07-02 13:00:18 +0200 | [diff] [blame] | 473 | |
| 474 | mdio: mdio-bus@72004 { |
| 475 | compatible = "marvell,orion-mdio"; |
| 476 | #address-cells = <1>; |
| 477 | #size-cells = <0>; |
| 478 | reg = <0x72004 0x84>; |
| 479 | interrupts = <30>; |
| 480 | clocks = <&gate_clk 2>; |
| 481 | status = "disabled"; |
| 482 | |
| 483 | ethphy: ethernet-phy { |
| 484 | device-type = "ethernet-phy"; |
| 485 | /* set phy address in board file */ |
| 486 | }; |
| 487 | }; |
| 488 | |
| 489 | eth: ethernet-controller@72000 { |
| 490 | compatible = "marvell,orion-eth"; |
| 491 | #address-cells = <1>; |
| 492 | #size-cells = <0>; |
| 493 | reg = <0x72000 0x4000>; |
| 494 | clocks = <&gate_clk 2>; |
| 495 | marvell,tx-checksum-limit = <1600>; |
| 496 | status = "disabled"; |
| 497 | |
| 498 | ethernet-port@0 { |
| 499 | device_type = "network"; |
| 500 | compatible = "marvell,orion-eth-port"; |
| 501 | reg = <0>; |
| 502 | interrupts = <29>; |
| 503 | /* overwrite MAC address in bootloader */ |
| 504 | local-mac-address = [00 00 00 00 00 00]; |
| 505 | phy-handle = <ðphy>; |
| 506 | }; |
| 507 | }; |
Sebastian Hesselbarth | 80a8b54 | 2012-08-15 19:07:34 +0200 | [diff] [blame] | 508 | }; |
| 509 | }; |