Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 1 | /* |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/workqueue.h> |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 23 | #include <linux/interrupt.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/dma-mapping.h> |
| 27 | #include <linux/platform_device.h> |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 28 | #include <linux/pm_runtime.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 29 | #include <linux/spi/spi.h> |
| 30 | |
| 31 | #include <mach/dma.h> |
Jassi Brar | e6b873c | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 32 | #include <plat/s3c64xx-spi.h> |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 33 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 34 | #define MAX_SPI_PORTS 3 |
| 35 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 36 | /* Registers and bit-fields */ |
| 37 | |
| 38 | #define S3C64XX_SPI_CH_CFG 0x00 |
| 39 | #define S3C64XX_SPI_CLK_CFG 0x04 |
| 40 | #define S3C64XX_SPI_MODE_CFG 0x08 |
| 41 | #define S3C64XX_SPI_SLAVE_SEL 0x0C |
| 42 | #define S3C64XX_SPI_INT_EN 0x10 |
| 43 | #define S3C64XX_SPI_STATUS 0x14 |
| 44 | #define S3C64XX_SPI_TX_DATA 0x18 |
| 45 | #define S3C64XX_SPI_RX_DATA 0x1C |
| 46 | #define S3C64XX_SPI_PACKET_CNT 0x20 |
| 47 | #define S3C64XX_SPI_PENDING_CLR 0x24 |
| 48 | #define S3C64XX_SPI_SWAP_CFG 0x28 |
| 49 | #define S3C64XX_SPI_FB_CLK 0x2C |
| 50 | |
| 51 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ |
| 52 | #define S3C64XX_SPI_CH_SW_RST (1<<5) |
| 53 | #define S3C64XX_SPI_CH_SLAVE (1<<4) |
| 54 | #define S3C64XX_SPI_CPOL_L (1<<3) |
| 55 | #define S3C64XX_SPI_CPHA_B (1<<2) |
| 56 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) |
| 57 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) |
| 58 | |
| 59 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) |
| 60 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 |
| 61 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) |
| 62 | #define S3C64XX_SPI_PSR_MASK 0xff |
| 63 | |
| 64 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) |
| 65 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) |
| 66 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) |
| 67 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) |
| 68 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) |
| 69 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) |
| 70 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) |
| 71 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) |
| 72 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) |
| 73 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) |
| 74 | #define S3C64XX_SPI_MODE_4BURST (1<<0) |
| 75 | |
| 76 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) |
| 77 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) |
| 78 | |
| 79 | #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) |
| 80 | |
| 81 | #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ |
| 82 | (c)->regs + S3C64XX_SPI_SLAVE_SEL) |
| 83 | |
| 84 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
| 85 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) |
| 86 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) |
| 87 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) |
| 88 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) |
| 89 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) |
| 90 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) |
| 91 | |
| 92 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) |
| 93 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) |
| 94 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) |
| 95 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) |
| 96 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) |
| 97 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) |
| 98 | |
| 99 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) |
| 100 | |
| 101 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) |
| 102 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) |
| 103 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) |
| 104 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) |
| 105 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) |
| 106 | |
| 107 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) |
| 108 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) |
| 109 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) |
| 110 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) |
| 111 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) |
| 112 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) |
| 113 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) |
| 114 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) |
| 115 | |
| 116 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) |
| 117 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 118 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
| 119 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ |
| 120 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) |
| 121 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) |
| 122 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ |
| 123 | FIFO_LVL_MASK(i)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 124 | |
| 125 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff |
| 126 | #define S3C64XX_SPI_TRAILCNT_OFF 19 |
| 127 | |
| 128 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT |
| 129 | |
| 130 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) |
| 131 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 132 | #define RXBUSY (1<<2) |
| 133 | #define TXBUSY (1<<3) |
| 134 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 135 | struct s3c64xx_spi_dma_data { |
| 136 | unsigned ch; |
| 137 | enum dma_data_direction direction; |
| 138 | enum dma_ch dmach; |
| 139 | }; |
| 140 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 141 | /** |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 142 | * struct s3c64xx_spi_info - SPI Controller hardware info |
| 143 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. |
| 144 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. |
| 145 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. |
| 146 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. |
| 147 | * @clk_from_cmu: True, if the controller does not include a clock mux and |
| 148 | * prescaler unit. |
| 149 | * |
| 150 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but |
| 151 | * differ in some aspects such as the size of the fifo and spi bus clock |
| 152 | * setup. Such differences are specified to the driver using this structure |
| 153 | * which is provided as driver data to the driver. |
| 154 | */ |
| 155 | struct s3c64xx_spi_port_config { |
| 156 | int fifo_lvl_mask[MAX_SPI_PORTS]; |
| 157 | int rx_lvl_offset; |
| 158 | int tx_st_done; |
| 159 | bool high_speed; |
| 160 | bool clk_from_cmu; |
| 161 | }; |
| 162 | |
| 163 | /** |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 164 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. |
| 165 | * @clk: Pointer to the spi clock. |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 166 | * @src_clk: Pointer to the clock used to generate SPI signals. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 167 | * @master: Pointer to the SPI Protocol master. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 168 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
| 169 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 170 | * @queue: To log SPI xfer requests. |
| 171 | * @lock: Controller specific lock. |
| 172 | * @state: Set of FLAGS to indicate status. |
| 173 | * @rx_dmach: Controller's DMA channel for Rx. |
| 174 | * @tx_dmach: Controller's DMA channel for Tx. |
| 175 | * @sfr_start: BUS address of SPI controller regs. |
| 176 | * @regs: Pointer to ioremap'ed controller registers. |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 177 | * @irq: interrupt |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 178 | * @xfer_completion: To indicate completion of xfer task. |
| 179 | * @cur_mode: Stores the active configuration of the controller. |
| 180 | * @cur_bpw: Stores the active bits per word settings. |
| 181 | * @cur_speed: Stores the active xfer clock speed. |
| 182 | */ |
| 183 | struct s3c64xx_spi_driver_data { |
| 184 | void __iomem *regs; |
| 185 | struct clk *clk; |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 186 | struct clk *src_clk; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 187 | struct platform_device *pdev; |
| 188 | struct spi_master *master; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 189 | struct s3c64xx_spi_info *cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 190 | struct spi_device *tgl_spi; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 191 | struct list_head queue; |
| 192 | spinlock_t lock; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 193 | unsigned long sfr_start; |
| 194 | struct completion xfer_completion; |
| 195 | unsigned state; |
| 196 | unsigned cur_mode, cur_bpw; |
| 197 | unsigned cur_speed; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 198 | struct s3c64xx_spi_dma_data rx_dma; |
| 199 | struct s3c64xx_spi_dma_data tx_dma; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 200 | struct samsung_dma_ops *ops; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 201 | struct s3c64xx_spi_port_config *port_conf; |
| 202 | unsigned int port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 203 | }; |
| 204 | |
| 205 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { |
| 206 | .name = "samsung-spi-dma", |
| 207 | }; |
| 208 | |
| 209 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
| 210 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 211 | void __iomem *regs = sdd->regs; |
| 212 | unsigned long loops; |
| 213 | u32 val; |
| 214 | |
| 215 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 216 | |
| 217 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 218 | val |= S3C64XX_SPI_CH_SW_RST; |
| 219 | val &= ~S3C64XX_SPI_CH_HS_EN; |
| 220 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 221 | |
| 222 | /* Flush TxFIFO*/ |
| 223 | loops = msecs_to_loops(1); |
| 224 | do { |
| 225 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 226 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 227 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 228 | if (loops == 0) |
| 229 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); |
| 230 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 231 | /* Flush RxFIFO*/ |
| 232 | loops = msecs_to_loops(1); |
| 233 | do { |
| 234 | val = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 235 | if (RX_FIFO_LVL(val, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 236 | readl(regs + S3C64XX_SPI_RX_DATA); |
| 237 | else |
| 238 | break; |
| 239 | } while (loops--); |
| 240 | |
Mark Brown | be7852a | 2010-08-23 17:40:56 +0100 | [diff] [blame] | 241 | if (loops == 0) |
| 242 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); |
| 243 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 244 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 245 | val &= ~S3C64XX_SPI_CH_SW_RST; |
| 246 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 247 | |
| 248 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 249 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 250 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 251 | |
| 252 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 253 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); |
| 254 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 255 | } |
| 256 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 257 | static void s3c64xx_spi_dmacb(void *data) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 258 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 259 | struct s3c64xx_spi_driver_data *sdd; |
| 260 | struct s3c64xx_spi_dma_data *dma = data; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 261 | unsigned long flags; |
| 262 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 263 | if (dma->direction == DMA_DEV_TO_MEM) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 264 | sdd = container_of(data, |
| 265 | struct s3c64xx_spi_driver_data, rx_dma); |
| 266 | else |
| 267 | sdd = container_of(data, |
| 268 | struct s3c64xx_spi_driver_data, tx_dma); |
| 269 | |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 270 | spin_lock_irqsave(&sdd->lock, flags); |
| 271 | |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 272 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 273 | sdd->state &= ~RXBUSY; |
| 274 | if (!(sdd->state & TXBUSY)) |
| 275 | complete(&sdd->xfer_completion); |
| 276 | } else { |
| 277 | sdd->state &= ~TXBUSY; |
| 278 | if (!(sdd->state & RXBUSY)) |
| 279 | complete(&sdd->xfer_completion); |
| 280 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 281 | |
| 282 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 283 | } |
| 284 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 285 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
| 286 | unsigned len, dma_addr_t buf) |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 287 | { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 288 | struct s3c64xx_spi_driver_data *sdd; |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 289 | struct samsung_dma_prep info; |
| 290 | struct samsung_dma_config config; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 291 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 292 | if (dma->direction == DMA_DEV_TO_MEM) { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 293 | sdd = container_of((void *)dma, |
| 294 | struct s3c64xx_spi_driver_data, rx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 295 | config.direction = sdd->rx_dma.direction; |
| 296 | config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; |
| 297 | config.width = sdd->cur_bpw / 8; |
| 298 | sdd->ops->config(sdd->rx_dma.ch, &config); |
| 299 | } else { |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 300 | sdd = container_of((void *)dma, |
| 301 | struct s3c64xx_spi_driver_data, tx_dma); |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 302 | config.direction = sdd->tx_dma.direction; |
| 303 | config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; |
| 304 | config.width = sdd->cur_bpw / 8; |
| 305 | sdd->ops->config(sdd->tx_dma.ch, &config); |
| 306 | } |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 307 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 308 | info.cap = DMA_SLAVE; |
| 309 | info.len = len; |
| 310 | info.fp = s3c64xx_spi_dmacb; |
| 311 | info.fp_param = dma; |
| 312 | info.direction = dma->direction; |
| 313 | info.buf = buf; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 314 | |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 315 | sdd->ops->prepare(dma->ch, &info); |
| 316 | sdd->ops->trigger(dma->ch); |
| 317 | } |
| 318 | |
| 319 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) |
| 320 | { |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 321 | struct samsung_dma_req req; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 322 | |
| 323 | sdd->ops = samsung_dma_get_ops(); |
| 324 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 325 | req.cap = DMA_SLAVE; |
| 326 | req.client = &s3c64xx_spi_dma_client; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 327 | |
Boojin Kim | 4969c32 | 2012-06-19 13:27:03 +0900 | [diff] [blame] | 328 | sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req); |
| 329 | sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 330 | |
| 331 | return 1; |
Boojin Kim | 39d3e80 | 2011-09-02 09:44:41 +0900 | [diff] [blame] | 332 | } |
| 333 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 334 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
| 335 | struct spi_device *spi, |
| 336 | struct spi_transfer *xfer, int dma_mode) |
| 337 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 338 | void __iomem *regs = sdd->regs; |
| 339 | u32 modecfg, chcfg; |
| 340 | |
| 341 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 342 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); |
| 343 | |
| 344 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); |
| 345 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; |
| 346 | |
| 347 | if (dma_mode) { |
| 348 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; |
| 349 | } else { |
| 350 | /* Always shift in data in FIFO, even if xfer is Tx only, |
| 351 | * this helps setting PCKT_CNT value for generating clocks |
| 352 | * as exactly needed. |
| 353 | */ |
| 354 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 355 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 356 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 357 | regs + S3C64XX_SPI_PACKET_CNT); |
| 358 | } |
| 359 | |
| 360 | if (xfer->tx_buf != NULL) { |
| 361 | sdd->state |= TXBUSY; |
| 362 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; |
| 363 | if (dma_mode) { |
| 364 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 365 | prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 366 | } else { |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 367 | switch (sdd->cur_bpw) { |
| 368 | case 32: |
| 369 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, |
| 370 | xfer->tx_buf, xfer->len / 4); |
| 371 | break; |
| 372 | case 16: |
| 373 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, |
| 374 | xfer->tx_buf, xfer->len / 2); |
| 375 | break; |
| 376 | default: |
| 377 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, |
| 378 | xfer->tx_buf, xfer->len); |
| 379 | break; |
| 380 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 381 | } |
| 382 | } |
| 383 | |
| 384 | if (xfer->rx_buf != NULL) { |
| 385 | sdd->state |= RXBUSY; |
| 386 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 387 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 388 | && !(sdd->cur_mode & SPI_CPHA)) |
| 389 | chcfg |= S3C64XX_SPI_CH_HS_EN; |
| 390 | |
| 391 | if (dma_mode) { |
| 392 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; |
| 393 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; |
| 394 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) |
| 395 | | S3C64XX_SPI_PACKET_CNT_EN, |
| 396 | regs + S3C64XX_SPI_PACKET_CNT); |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 397 | prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 398 | } |
| 399 | } |
| 400 | |
| 401 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); |
| 402 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); |
| 403 | } |
| 404 | |
| 405 | static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 406 | struct spi_device *spi) |
| 407 | { |
| 408 | struct s3c64xx_spi_csinfo *cs; |
| 409 | |
| 410 | if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ |
| 411 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ |
| 412 | /* Deselect the last toggled device */ |
| 413 | cs = sdd->tgl_spi->controller_data; |
Jassi Brar | fa0fcde | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 414 | cs->set_level(cs->line, |
| 415 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 416 | } |
| 417 | sdd->tgl_spi = NULL; |
| 418 | } |
| 419 | |
| 420 | cs = spi->controller_data; |
Jassi Brar | fa0fcde | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 421 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, |
| 425 | struct spi_transfer *xfer, int dma_mode) |
| 426 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 427 | void __iomem *regs = sdd->regs; |
| 428 | unsigned long val; |
| 429 | int ms; |
| 430 | |
| 431 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
| 432 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; |
Mark Brown | 9d8f86b | 2010-09-07 16:37:52 +0100 | [diff] [blame] | 433 | ms += 10; /* some tolerance */ |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 434 | |
| 435 | if (dma_mode) { |
| 436 | val = msecs_to_jiffies(ms) + 10; |
| 437 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); |
| 438 | } else { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 439 | u32 status; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 440 | val = msecs_to_loops(ms); |
| 441 | do { |
Jassi Brar | c3f139b | 2010-09-03 10:36:46 +0900 | [diff] [blame] | 442 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 443 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | if (!val) |
| 447 | return -EIO; |
| 448 | |
| 449 | if (dma_mode) { |
| 450 | u32 status; |
| 451 | |
| 452 | /* |
| 453 | * DmaTx returns after simply writing data in the FIFO, |
| 454 | * w/o waiting for real transmission on the bus to finish. |
| 455 | * DmaRx returns only after Dma read data from FIFO which |
| 456 | * needs bus transmission to finish, so we don't worry if |
| 457 | * Xfer involved Rx(with or without Tx). |
| 458 | */ |
| 459 | if (xfer->rx_buf == NULL) { |
| 460 | val = msecs_to_loops(10); |
| 461 | status = readl(regs + S3C64XX_SPI_STATUS); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 462 | while ((TX_FIFO_LVL(status, sdd) |
| 463 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 464 | && --val) { |
| 465 | cpu_relax(); |
| 466 | status = readl(regs + S3C64XX_SPI_STATUS); |
| 467 | } |
| 468 | |
| 469 | if (!val) |
| 470 | return -EIO; |
| 471 | } |
| 472 | } else { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 473 | /* If it was only Tx */ |
| 474 | if (xfer->rx_buf == NULL) { |
| 475 | sdd->state &= ~TXBUSY; |
| 476 | return 0; |
| 477 | } |
| 478 | |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 479 | switch (sdd->cur_bpw) { |
| 480 | case 32: |
| 481 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, |
| 482 | xfer->rx_buf, xfer->len / 4); |
| 483 | break; |
| 484 | case 16: |
| 485 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, |
| 486 | xfer->rx_buf, xfer->len / 2); |
| 487 | break; |
| 488 | default: |
| 489 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, |
| 490 | xfer->rx_buf, xfer->len); |
| 491 | break; |
| 492 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 493 | sdd->state &= ~RXBUSY; |
| 494 | } |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, |
| 500 | struct spi_device *spi) |
| 501 | { |
| 502 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 503 | |
| 504 | if (sdd->tgl_spi == spi) |
| 505 | sdd->tgl_spi = NULL; |
| 506 | |
Jassi Brar | fa0fcde | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 507 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
| 511 | { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 512 | void __iomem *regs = sdd->regs; |
| 513 | u32 val; |
| 514 | |
| 515 | /* Disable Clock */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 516 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 517 | clk_disable(sdd->src_clk); |
| 518 | } else { |
| 519 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 520 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; |
| 521 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 522 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 523 | |
| 524 | /* Set Polarity and Phase */ |
| 525 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
| 526 | val &= ~(S3C64XX_SPI_CH_SLAVE | |
| 527 | S3C64XX_SPI_CPOL_L | |
| 528 | S3C64XX_SPI_CPHA_B); |
| 529 | |
| 530 | if (sdd->cur_mode & SPI_CPOL) |
| 531 | val |= S3C64XX_SPI_CPOL_L; |
| 532 | |
| 533 | if (sdd->cur_mode & SPI_CPHA) |
| 534 | val |= S3C64XX_SPI_CPHA_B; |
| 535 | |
| 536 | writel(val, regs + S3C64XX_SPI_CH_CFG); |
| 537 | |
| 538 | /* Set Channel & DMA Mode */ |
| 539 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 540 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK |
| 541 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); |
| 542 | |
| 543 | switch (sdd->cur_bpw) { |
| 544 | case 32: |
| 545 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 546 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 547 | break; |
| 548 | case 16: |
| 549 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 550 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 551 | break; |
| 552 | default: |
| 553 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 554 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 555 | break; |
| 556 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 557 | |
| 558 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 559 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 560 | if (sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 561 | /* Configure Clock */ |
| 562 | /* There is half-multiplier before the SPI */ |
| 563 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
| 564 | /* Enable Clock */ |
| 565 | clk_enable(sdd->src_clk); |
| 566 | } else { |
| 567 | /* Configure Clock */ |
| 568 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 569 | val &= ~S3C64XX_SPI_PSR_MASK; |
| 570 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) |
| 571 | & S3C64XX_SPI_PSR_MASK); |
| 572 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 573 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 574 | /* Enable Clock */ |
| 575 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
| 576 | val |= S3C64XX_SPI_ENCLK_ENABLE; |
| 577 | writel(val, regs + S3C64XX_SPI_CLK_CFG); |
| 578 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 579 | } |
| 580 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 581 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
| 582 | |
| 583 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 584 | struct spi_message *msg) |
| 585 | { |
| 586 | struct device *dev = &sdd->pdev->dev; |
| 587 | struct spi_transfer *xfer; |
| 588 | |
| 589 | if (msg->is_dma_mapped) |
| 590 | return 0; |
| 591 | |
| 592 | /* First mark all xfer unmapped */ |
| 593 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 594 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 595 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 596 | } |
| 597 | |
| 598 | /* Map until end or first fail */ |
| 599 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 600 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 601 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 602 | continue; |
| 603 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 604 | if (xfer->tx_buf != NULL) { |
Jassi Brar | 251ee47 | 2010-09-03 10:36:26 +0900 | [diff] [blame] | 605 | xfer->tx_dma = dma_map_single(dev, |
| 606 | (void *)xfer->tx_buf, xfer->len, |
| 607 | DMA_TO_DEVICE); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 608 | if (dma_mapping_error(dev, xfer->tx_dma)) { |
| 609 | dev_err(dev, "dma_map_single Tx failed\n"); |
| 610 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 611 | return -ENOMEM; |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | if (xfer->rx_buf != NULL) { |
| 616 | xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, |
| 617 | xfer->len, DMA_FROM_DEVICE); |
| 618 | if (dma_mapping_error(dev, xfer->rx_dma)) { |
| 619 | dev_err(dev, "dma_map_single Rx failed\n"); |
| 620 | dma_unmap_single(dev, xfer->tx_dma, |
| 621 | xfer->len, DMA_TO_DEVICE); |
| 622 | xfer->tx_dma = XFER_DMAADDR_INVALID; |
| 623 | xfer->rx_dma = XFER_DMAADDR_INVALID; |
| 624 | return -ENOMEM; |
| 625 | } |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | return 0; |
| 630 | } |
| 631 | |
| 632 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, |
| 633 | struct spi_message *msg) |
| 634 | { |
| 635 | struct device *dev = &sdd->pdev->dev; |
| 636 | struct spi_transfer *xfer; |
| 637 | |
| 638 | if (msg->is_dma_mapped) |
| 639 | return; |
| 640 | |
| 641 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 642 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 643 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | e02ddd4 | 2010-09-29 17:31:31 +0900 | [diff] [blame] | 644 | continue; |
| 645 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 646 | if (xfer->rx_buf != NULL |
| 647 | && xfer->rx_dma != XFER_DMAADDR_INVALID) |
| 648 | dma_unmap_single(dev, xfer->rx_dma, |
| 649 | xfer->len, DMA_FROM_DEVICE); |
| 650 | |
| 651 | if (xfer->tx_buf != NULL |
| 652 | && xfer->tx_dma != XFER_DMAADDR_INVALID) |
| 653 | dma_unmap_single(dev, xfer->tx_dma, |
| 654 | xfer->len, DMA_TO_DEVICE); |
| 655 | } |
| 656 | } |
| 657 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 658 | static int s3c64xx_spi_transfer_one_message(struct spi_master *master, |
| 659 | struct spi_message *msg) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 660 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 661 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 662 | struct spi_device *spi = msg->spi; |
| 663 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 664 | struct spi_transfer *xfer; |
| 665 | int status = 0, cs_toggle = 0; |
| 666 | u32 speed; |
| 667 | u8 bpw; |
| 668 | |
| 669 | /* If Master's(controller) state differs from that needed by Slave */ |
| 670 | if (sdd->cur_speed != spi->max_speed_hz |
| 671 | || sdd->cur_mode != spi->mode |
| 672 | || sdd->cur_bpw != spi->bits_per_word) { |
| 673 | sdd->cur_bpw = spi->bits_per_word; |
| 674 | sdd->cur_speed = spi->max_speed_hz; |
| 675 | sdd->cur_mode = spi->mode; |
| 676 | s3c64xx_spi_config(sdd); |
| 677 | } |
| 678 | |
| 679 | /* Map all the transfers if needed */ |
| 680 | if (s3c64xx_spi_map_mssg(sdd, msg)) { |
| 681 | dev_err(&spi->dev, |
| 682 | "Xfer: Unable to map message buffers!\n"); |
| 683 | status = -ENOMEM; |
| 684 | goto out; |
| 685 | } |
| 686 | |
| 687 | /* Configure feedback delay */ |
| 688 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); |
| 689 | |
| 690 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
| 691 | |
| 692 | unsigned long flags; |
| 693 | int use_dma; |
| 694 | |
| 695 | INIT_COMPLETION(sdd->xfer_completion); |
| 696 | |
| 697 | /* Only BPW and Speed may change across transfers */ |
| 698 | bpw = xfer->bits_per_word ? : spi->bits_per_word; |
| 699 | speed = xfer->speed_hz ? : spi->max_speed_hz; |
| 700 | |
Jassi Brar | 0c92ecf | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 701 | if (xfer->len % (bpw / 8)) { |
| 702 | dev_err(&spi->dev, |
| 703 | "Xfer length(%u) not a multiple of word size(%u)\n", |
| 704 | xfer->len, bpw / 8); |
| 705 | status = -EIO; |
| 706 | goto out; |
| 707 | } |
| 708 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 709 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
| 710 | sdd->cur_bpw = bpw; |
| 711 | sdd->cur_speed = speed; |
| 712 | s3c64xx_spi_config(sdd); |
| 713 | } |
| 714 | |
| 715 | /* Polling method for xfers not bigger than FIFO capacity */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 716 | if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 717 | use_dma = 0; |
| 718 | else |
| 719 | use_dma = 1; |
| 720 | |
| 721 | spin_lock_irqsave(&sdd->lock, flags); |
| 722 | |
| 723 | /* Pending only which is to be done */ |
| 724 | sdd->state &= ~RXBUSY; |
| 725 | sdd->state &= ~TXBUSY; |
| 726 | |
| 727 | enable_datapath(sdd, spi, xfer, use_dma); |
| 728 | |
| 729 | /* Slave Select */ |
| 730 | enable_cs(sdd, spi); |
| 731 | |
| 732 | /* Start the signals */ |
| 733 | S3C64XX_SPI_ACT(sdd); |
| 734 | |
| 735 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 736 | |
| 737 | status = wait_for_xfer(sdd, xfer, use_dma); |
| 738 | |
| 739 | /* Quiese the signals */ |
| 740 | S3C64XX_SPI_DEACT(sdd); |
| 741 | |
| 742 | if (status) { |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 743 | dev_err(&spi->dev, "I/O Error: " |
| 744 | "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 745 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
| 746 | (sdd->state & RXBUSY) ? 'f' : 'p', |
| 747 | (sdd->state & TXBUSY) ? 'f' : 'p', |
| 748 | xfer->len); |
| 749 | |
| 750 | if (use_dma) { |
| 751 | if (xfer->tx_buf != NULL |
| 752 | && (sdd->state & TXBUSY)) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 753 | sdd->ops->stop(sdd->tx_dma.ch); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 754 | if (xfer->rx_buf != NULL |
| 755 | && (sdd->state & RXBUSY)) |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 756 | sdd->ops->stop(sdd->rx_dma.ch); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 757 | } |
| 758 | |
| 759 | goto out; |
| 760 | } |
| 761 | |
| 762 | if (xfer->delay_usecs) |
| 763 | udelay(xfer->delay_usecs); |
| 764 | |
| 765 | if (xfer->cs_change) { |
| 766 | /* Hint that the next mssg is gonna be |
| 767 | for the same device */ |
| 768 | if (list_is_last(&xfer->transfer_list, |
| 769 | &msg->transfers)) |
| 770 | cs_toggle = 1; |
| 771 | else |
| 772 | disable_cs(sdd, spi); |
| 773 | } |
| 774 | |
| 775 | msg->actual_length += xfer->len; |
| 776 | |
| 777 | flush_fifo(sdd); |
| 778 | } |
| 779 | |
| 780 | out: |
| 781 | if (!cs_toggle || status) |
| 782 | disable_cs(sdd, spi); |
| 783 | else |
| 784 | sdd->tgl_spi = spi; |
| 785 | |
| 786 | s3c64xx_spi_unmap_mssg(sdd, msg); |
| 787 | |
| 788 | msg->status = status; |
| 789 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 790 | spi_finalize_current_message(master); |
| 791 | |
| 792 | return 0; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 793 | } |
| 794 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 795 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 796 | { |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 797 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 798 | |
| 799 | /* Acquire DMA channels */ |
| 800 | while (!acquire_dma(sdd)) |
| 801 | msleep(10); |
| 802 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 803 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 804 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 805 | return 0; |
| 806 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 807 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 808 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) |
| 809 | { |
| 810 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 811 | |
| 812 | /* Free DMA channels */ |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 813 | sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client); |
| 814 | sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client); |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 815 | |
| 816 | pm_runtime_put(&sdd->pdev->dev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 817 | |
| 818 | return 0; |
| 819 | } |
| 820 | |
| 821 | /* |
| 822 | * Here we only check the validity of requested configuration |
| 823 | * and save the configuration in a local data-structure. |
| 824 | * The controller is actually configured only just before we |
| 825 | * get a message to transfer. |
| 826 | */ |
| 827 | static int s3c64xx_spi_setup(struct spi_device *spi) |
| 828 | { |
| 829 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; |
| 830 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 831 | struct s3c64xx_spi_info *sci; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 832 | struct spi_message *msg; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 833 | unsigned long flags; |
| 834 | int err = 0; |
| 835 | |
| 836 | if (cs == NULL || cs->set_level == NULL) { |
| 837 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
| 838 | return -ENODEV; |
| 839 | } |
| 840 | |
| 841 | sdd = spi_master_get_devdata(spi->master); |
| 842 | sci = sdd->cntrlr_info; |
| 843 | |
| 844 | spin_lock_irqsave(&sdd->lock, flags); |
| 845 | |
| 846 | list_for_each_entry(msg, &sdd->queue, queue) { |
| 847 | /* Is some mssg is already queued for this device */ |
| 848 | if (msg->spi == spi) { |
| 849 | dev_err(&spi->dev, |
| 850 | "setup: attempt while mssg in queue!\n"); |
| 851 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 852 | return -EBUSY; |
| 853 | } |
| 854 | } |
| 855 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 856 | spin_unlock_irqrestore(&sdd->lock, flags); |
| 857 | |
| 858 | if (spi->bits_per_word != 8 |
| 859 | && spi->bits_per_word != 16 |
| 860 | && spi->bits_per_word != 32) { |
| 861 | dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", |
| 862 | spi->bits_per_word); |
| 863 | err = -EINVAL; |
| 864 | goto setup_exit; |
| 865 | } |
| 866 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 867 | pm_runtime_get_sync(&sdd->pdev->dev); |
| 868 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 869 | /* Check if we can provide the requested rate */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 870 | if (!sdd->port_conf->clk_from_cmu) { |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 871 | u32 psr, speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 872 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 873 | /* Max possible */ |
| 874 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 875 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 876 | if (spi->max_speed_hz > speed) |
| 877 | spi->max_speed_hz = speed; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 878 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 879 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; |
| 880 | psr &= S3C64XX_SPI_PSR_MASK; |
| 881 | if (psr == S3C64XX_SPI_PSR_MASK) |
| 882 | psr--; |
| 883 | |
| 884 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 885 | if (spi->max_speed_hz < speed) { |
| 886 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { |
| 887 | psr++; |
| 888 | } else { |
| 889 | err = -EINVAL; |
| 890 | goto setup_exit; |
| 891 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 892 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 893 | |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 894 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
| 895 | if (spi->max_speed_hz >= speed) |
| 896 | spi->max_speed_hz = speed; |
| 897 | else |
| 898 | err = -EINVAL; |
| 899 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 900 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 901 | pm_runtime_put(&sdd->pdev->dev); |
| 902 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 903 | setup_exit: |
| 904 | |
| 905 | /* setup() returns with device de-selected */ |
| 906 | disable_cs(sdd, spi); |
| 907 | |
| 908 | return err; |
| 909 | } |
| 910 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 911 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
| 912 | { |
| 913 | struct s3c64xx_spi_driver_data *sdd = data; |
| 914 | struct spi_master *spi = sdd->master; |
| 915 | unsigned int val; |
| 916 | |
| 917 | val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 918 | |
| 919 | val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR | |
| 920 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | |
| 921 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | |
| 922 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; |
| 923 | |
| 924 | writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR); |
| 925 | |
| 926 | if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR) |
| 927 | dev_err(&spi->dev, "RX overrun\n"); |
| 928 | if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR) |
| 929 | dev_err(&spi->dev, "RX underrun\n"); |
| 930 | if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR) |
| 931 | dev_err(&spi->dev, "TX overrun\n"); |
| 932 | if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR) |
| 933 | dev_err(&spi->dev, "TX underrun\n"); |
| 934 | |
| 935 | return IRQ_HANDLED; |
| 936 | } |
| 937 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 938 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
| 939 | { |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 940 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 941 | void __iomem *regs = sdd->regs; |
| 942 | unsigned int val; |
| 943 | |
| 944 | sdd->cur_speed = 0; |
| 945 | |
| 946 | S3C64XX_SPI_DEACT(sdd); |
| 947 | |
| 948 | /* Disable Interrupts - we use Polling if not DMA mode */ |
| 949 | writel(0, regs + S3C64XX_SPI_INT_EN); |
| 950 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 951 | if (!sdd->port_conf->clk_from_cmu) |
Jassi Brar | b42a81c | 2010-09-29 17:31:33 +0900 | [diff] [blame] | 952 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 953 | regs + S3C64XX_SPI_CLK_CFG); |
| 954 | writel(0, regs + S3C64XX_SPI_MODE_CFG); |
| 955 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); |
| 956 | |
| 957 | /* Clear any irq pending bits */ |
| 958 | writel(readl(regs + S3C64XX_SPI_PENDING_CLR), |
| 959 | regs + S3C64XX_SPI_PENDING_CLR); |
| 960 | |
| 961 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); |
| 962 | |
| 963 | val = readl(regs + S3C64XX_SPI_MODE_CFG); |
| 964 | val &= ~S3C64XX_SPI_MODE_4BURST; |
| 965 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 966 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); |
| 967 | writel(val, regs + S3C64XX_SPI_MODE_CFG); |
| 968 | |
| 969 | flush_fifo(sdd); |
| 970 | } |
| 971 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 972 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
| 973 | struct platform_device *pdev) |
| 974 | { |
| 975 | return (struct s3c64xx_spi_port_config *) |
| 976 | platform_get_device_id(pdev)->driver_data; |
| 977 | } |
| 978 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 979 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) |
| 980 | { |
| 981 | struct resource *mem_res, *dmatx_res, *dmarx_res; |
| 982 | struct s3c64xx_spi_driver_data *sdd; |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 983 | struct s3c64xx_spi_info *sci; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 984 | struct spi_master *master; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 985 | int ret, irq; |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 986 | char clk_name[16]; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 987 | |
| 988 | if (pdev->id < 0) { |
| 989 | dev_err(&pdev->dev, |
| 990 | "Invalid platform device id-%d\n", pdev->id); |
| 991 | return -ENODEV; |
| 992 | } |
| 993 | |
| 994 | if (pdev->dev.platform_data == NULL) { |
| 995 | dev_err(&pdev->dev, "platform_data missing!\n"); |
| 996 | return -ENODEV; |
| 997 | } |
| 998 | |
Mark Brown | cc0fc0b | 2010-09-01 08:55:22 -0600 | [diff] [blame] | 999 | sci = pdev->dev.platform_data; |
Mark Brown | cc0fc0b | 2010-09-01 08:55:22 -0600 | [diff] [blame] | 1000 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1001 | /* Check for availability of necessary resource */ |
| 1002 | |
| 1003 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 1004 | if (dmatx_res == NULL) { |
| 1005 | dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); |
| 1006 | return -ENXIO; |
| 1007 | } |
| 1008 | |
| 1009 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 1010 | if (dmarx_res == NULL) { |
| 1011 | dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); |
| 1012 | return -ENXIO; |
| 1013 | } |
| 1014 | |
| 1015 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1016 | if (mem_res == NULL) { |
| 1017 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); |
| 1018 | return -ENXIO; |
| 1019 | } |
| 1020 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1021 | irq = platform_get_irq(pdev, 0); |
| 1022 | if (irq < 0) { |
| 1023 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); |
| 1024 | return irq; |
| 1025 | } |
| 1026 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1027 | master = spi_alloc_master(&pdev->dev, |
| 1028 | sizeof(struct s3c64xx_spi_driver_data)); |
| 1029 | if (master == NULL) { |
| 1030 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); |
| 1031 | return -ENOMEM; |
| 1032 | } |
| 1033 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1034 | platform_set_drvdata(pdev, master); |
| 1035 | |
| 1036 | sdd = spi_master_get_devdata(master); |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1037 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1038 | sdd->master = master; |
| 1039 | sdd->cntrlr_info = sci; |
| 1040 | sdd->pdev = pdev; |
| 1041 | sdd->sfr_start = mem_res->start; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1042 | sdd->tx_dma.dmach = dmatx_res->start; |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 1043 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1044 | sdd->rx_dma.dmach = dmarx_res->start; |
Kyoungil Kim | 054ebcc | 2012-03-10 09:48:46 +0900 | [diff] [blame] | 1045 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1046 | sdd->port_id = pdev->id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1047 | |
| 1048 | sdd->cur_bpw = 8; |
| 1049 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1050 | master->bus_num = sdd->port_id; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1051 | master->setup = s3c64xx_spi_setup; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1052 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
| 1053 | master->transfer_one_message = s3c64xx_spi_transfer_one_message; |
| 1054 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1055 | master->num_chipselect = sci->num_cs; |
| 1056 | master->dma_alignment = 8; |
| 1057 | /* the spi->mode bits understood by this driver: */ |
| 1058 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1059 | |
| 1060 | if (request_mem_region(mem_res->start, |
| 1061 | resource_size(mem_res), pdev->name) == NULL) { |
| 1062 | dev_err(&pdev->dev, "Req mem region failed\n"); |
| 1063 | ret = -ENXIO; |
| 1064 | goto err0; |
| 1065 | } |
| 1066 | |
| 1067 | sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); |
| 1068 | if (sdd->regs == NULL) { |
| 1069 | dev_err(&pdev->dev, "Unable to remap IO\n"); |
| 1070 | ret = -ENXIO; |
| 1071 | goto err1; |
| 1072 | } |
| 1073 | |
| 1074 | if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { |
| 1075 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
| 1076 | ret = -EBUSY; |
| 1077 | goto err2; |
| 1078 | } |
| 1079 | |
| 1080 | /* Setup clocks */ |
| 1081 | sdd->clk = clk_get(&pdev->dev, "spi"); |
| 1082 | if (IS_ERR(sdd->clk)) { |
| 1083 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); |
| 1084 | ret = PTR_ERR(sdd->clk); |
| 1085 | goto err3; |
| 1086 | } |
| 1087 | |
| 1088 | if (clk_enable(sdd->clk)) { |
| 1089 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
| 1090 | ret = -EBUSY; |
| 1091 | goto err4; |
| 1092 | } |
| 1093 | |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1094 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
| 1095 | sdd->src_clk = clk_get(&pdev->dev, clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1096 | if (IS_ERR(sdd->src_clk)) { |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1097 | dev_err(&pdev->dev, |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1098 | "Unable to acquire clock '%s'\n", clk_name); |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1099 | ret = PTR_ERR(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1100 | goto err5; |
| 1101 | } |
| 1102 | |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1103 | if (clk_enable(sdd->src_clk)) { |
Padmavathi Venna | a24d850 | 2011-11-02 20:04:19 +0900 | [diff] [blame] | 1104 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1105 | ret = -EBUSY; |
| 1106 | goto err6; |
| 1107 | } |
| 1108 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1109 | /* Setup Deufult Mode */ |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1110 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1111 | |
| 1112 | spin_lock_init(&sdd->lock); |
| 1113 | init_completion(&sdd->xfer_completion); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1114 | INIT_LIST_HEAD(&sdd->queue); |
| 1115 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1116 | ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd); |
| 1117 | if (ret != 0) { |
| 1118 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", |
| 1119 | irq, ret); |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1120 | goto err7; |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1121 | } |
| 1122 | |
| 1123 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | |
| 1124 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, |
| 1125 | sdd->regs + S3C64XX_SPI_INT_EN); |
| 1126 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1127 | if (spi_register_master(master)) { |
| 1128 | dev_err(&pdev->dev, "cannot register SPI master\n"); |
| 1129 | ret = -EBUSY; |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1130 | goto err8; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1131 | } |
| 1132 | |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 1133 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " |
| 1134 | "with %d Slaves attached\n", |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1135 | sdd->port_id, master->num_chipselect); |
Joe Perches | 8a349d4 | 2010-02-02 07:22:13 +0000 | [diff] [blame] | 1136 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1137 | mem_res->end, mem_res->start, |
Boojin Kim | 82ab8cd | 2011-09-02 09:44:42 +0900 | [diff] [blame] | 1138 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1139 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1140 | pm_runtime_enable(&pdev->dev); |
| 1141 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1142 | return 0; |
| 1143 | |
| 1144 | err8: |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1145 | free_irq(irq, sdd); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1146 | err7: |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1147 | clk_disable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1148 | err6: |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1149 | clk_put(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1150 | err5: |
| 1151 | clk_disable(sdd->clk); |
| 1152 | err4: |
| 1153 | clk_put(sdd->clk); |
| 1154 | err3: |
| 1155 | err2: |
| 1156 | iounmap((void *) sdd->regs); |
| 1157 | err1: |
| 1158 | release_mem_region(mem_res->start, resource_size(mem_res)); |
| 1159 | err0: |
| 1160 | platform_set_drvdata(pdev, NULL); |
| 1161 | spi_master_put(master); |
| 1162 | |
| 1163 | return ret; |
| 1164 | } |
| 1165 | |
| 1166 | static int s3c64xx_spi_remove(struct platform_device *pdev) |
| 1167 | { |
| 1168 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); |
| 1169 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1170 | struct resource *mem_res; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1171 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1172 | pm_runtime_disable(&pdev->dev); |
| 1173 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1174 | spi_unregister_master(master); |
| 1175 | |
Mark Brown | c257312 | 2011-11-10 10:57:32 +0000 | [diff] [blame] | 1176 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
| 1177 | |
| 1178 | free_irq(platform_get_irq(pdev, 0), sdd); |
| 1179 | |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1180 | clk_disable(sdd->src_clk); |
| 1181 | clk_put(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1182 | |
| 1183 | clk_disable(sdd->clk); |
| 1184 | clk_put(sdd->clk); |
| 1185 | |
| 1186 | iounmap((void *) sdd->regs); |
| 1187 | |
| 1188 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jassi Brar | ef6c680 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1189 | if (mem_res != NULL) |
| 1190 | release_mem_region(mem_res->start, resource_size(mem_res)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1191 | |
| 1192 | platform_set_drvdata(pdev, NULL); |
| 1193 | spi_master_put(master); |
| 1194 | |
| 1195 | return 0; |
| 1196 | } |
| 1197 | |
| 1198 | #ifdef CONFIG_PM |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1199 | static int s3c64xx_spi_suspend(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1200 | { |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1201 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1202 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1203 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1204 | spi_master_suspend(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1205 | |
| 1206 | /* Disable the clock */ |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1207 | clk_disable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1208 | clk_disable(sdd->clk); |
| 1209 | |
| 1210 | sdd->cur_speed = 0; /* Output Clock is stopped */ |
| 1211 | |
| 1212 | return 0; |
| 1213 | } |
| 1214 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1215 | static int s3c64xx_spi_resume(struct device *dev) |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1216 | { |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1217 | struct platform_device *pdev = to_platform_device(dev); |
| 1218 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1219 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
Jassi Brar | ad7de72 | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1220 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1221 | |
| 1222 | sci->cfg_gpio(pdev); |
| 1223 | |
| 1224 | /* Enable the clock */ |
Jassi Brar | b0d5d6e | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 1225 | clk_enable(sdd->src_clk); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1226 | clk_enable(sdd->clk); |
| 1227 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1228 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1229 | |
Mark Brown | ad2a99a | 2012-02-15 14:48:32 -0800 | [diff] [blame] | 1230 | spi_master_resume(master); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1231 | |
| 1232 | return 0; |
| 1233 | } |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1234 | #endif /* CONFIG_PM */ |
| 1235 | |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1236 | #ifdef CONFIG_PM_RUNTIME |
| 1237 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
| 1238 | { |
| 1239 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
| 1240 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1241 | |
| 1242 | clk_disable(sdd->clk); |
| 1243 | clk_disable(sdd->src_clk); |
| 1244 | |
| 1245 | return 0; |
| 1246 | } |
| 1247 | |
| 1248 | static int s3c64xx_spi_runtime_resume(struct device *dev) |
| 1249 | { |
| 1250 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
| 1251 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
| 1252 | |
| 1253 | clk_enable(sdd->src_clk); |
| 1254 | clk_enable(sdd->clk); |
| 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | #endif /* CONFIG_PM_RUNTIME */ |
| 1259 | |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1260 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
| 1261 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) |
Mark Brown | b97b662 | 2011-12-04 00:58:06 +0000 | [diff] [blame] | 1262 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
| 1263 | s3c64xx_spi_runtime_resume, NULL) |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1264 | }; |
| 1265 | |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1266 | struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
| 1267 | .fifo_lvl_mask = { 0x7f }, |
| 1268 | .rx_lvl_offset = 13, |
| 1269 | .tx_st_done = 21, |
| 1270 | .high_speed = true, |
| 1271 | }; |
| 1272 | |
| 1273 | struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
| 1274 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1275 | .rx_lvl_offset = 13, |
| 1276 | .tx_st_done = 21, |
| 1277 | }; |
| 1278 | |
| 1279 | struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { |
| 1280 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1281 | .rx_lvl_offset = 15, |
| 1282 | .tx_st_done = 25, |
| 1283 | }; |
| 1284 | |
| 1285 | struct s3c64xx_spi_port_config s5pc100_spi_port_config = { |
| 1286 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
| 1287 | .rx_lvl_offset = 13, |
| 1288 | .tx_st_done = 21, |
| 1289 | .high_speed = true, |
| 1290 | }; |
| 1291 | |
| 1292 | struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
| 1293 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
| 1294 | .rx_lvl_offset = 15, |
| 1295 | .tx_st_done = 25, |
| 1296 | .high_speed = true, |
| 1297 | }; |
| 1298 | |
| 1299 | struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
| 1300 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
| 1301 | .rx_lvl_offset = 15, |
| 1302 | .tx_st_done = 25, |
| 1303 | .high_speed = true, |
| 1304 | .clk_from_cmu = true, |
| 1305 | }; |
| 1306 | |
| 1307 | static struct platform_device_id s3c64xx_spi_driver_ids[] = { |
| 1308 | { |
| 1309 | .name = "s3c2443-spi", |
| 1310 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, |
| 1311 | }, { |
| 1312 | .name = "s3c6410-spi", |
| 1313 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, |
| 1314 | }, { |
| 1315 | .name = "s5p64x0-spi", |
| 1316 | .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, |
| 1317 | }, { |
| 1318 | .name = "s5pc100-spi", |
| 1319 | .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, |
| 1320 | }, { |
| 1321 | .name = "s5pv210-spi", |
| 1322 | .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, |
| 1323 | }, { |
| 1324 | .name = "exynos4210-spi", |
| 1325 | .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, |
| 1326 | }, |
| 1327 | { }, |
| 1328 | }; |
| 1329 | |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1330 | static struct platform_driver s3c64xx_spi_driver = { |
| 1331 | .driver = { |
| 1332 | .name = "s3c64xx-spi", |
| 1333 | .owner = THIS_MODULE, |
Mark Brown | e25d0bf | 2011-12-04 00:36:18 +0000 | [diff] [blame] | 1334 | .pm = &s3c64xx_spi_pm, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1335 | }, |
| 1336 | .remove = s3c64xx_spi_remove, |
Thomas Abraham | a5238e3 | 2012-07-13 07:15:14 +0900 | [diff] [blame^] | 1337 | .id_table = s3c64xx_spi_driver_ids, |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1338 | }; |
| 1339 | MODULE_ALIAS("platform:s3c64xx-spi"); |
| 1340 | |
| 1341 | static int __init s3c64xx_spi_init(void) |
| 1342 | { |
| 1343 | return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); |
| 1344 | } |
Mark Brown | d2a787f | 2010-09-07 11:29:17 +0100 | [diff] [blame] | 1345 | subsys_initcall(s3c64xx_spi_init); |
Jassi Brar | 230d42d | 2009-11-30 07:39:42 +0000 | [diff] [blame] | 1346 | |
| 1347 | static void __exit s3c64xx_spi_exit(void) |
| 1348 | { |
| 1349 | platform_driver_unregister(&s3c64xx_spi_driver); |
| 1350 | } |
| 1351 | module_exit(s3c64xx_spi_exit); |
| 1352 | |
| 1353 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); |
| 1354 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); |
| 1355 | MODULE_LICENSE("GPL"); |