Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/mm.h> |
| 14 | #include <linux/delay.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> |
| 17 | |
| 18 | #include <asm/clkdev.h> |
Dinh Nguyen | 17807f9 | 2010-04-13 14:05:08 -0500 | [diff] [blame] | 19 | #include <asm/div64.h> |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 20 | |
| 21 | #include <mach/hardware.h> |
| 22 | #include <mach/common.h> |
| 23 | #include <mach/clock.h> |
| 24 | |
| 25 | #include "crm_regs.h" |
| 26 | |
| 27 | /* External clock values passed-in by the board code */ |
| 28 | static unsigned long external_high_reference, external_low_reference; |
| 29 | static unsigned long oscillator_reference, ckih2_reference; |
| 30 | |
| 31 | static struct clk osc_clk; |
| 32 | static struct clk pll1_main_clk; |
| 33 | static struct clk pll1_sw_clk; |
| 34 | static struct clk pll2_sw_clk; |
| 35 | static struct clk pll3_sw_clk; |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 36 | static struct clk mx53_pll4_sw_clk; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 37 | static struct clk lp_apm_clk; |
| 38 | static struct clk periph_apm_clk; |
| 39 | static struct clk ahb_clk; |
| 40 | static struct clk ipg_clk; |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 41 | static struct clk usboh3_clk; |
Sascha Hauer | b848169 | 2010-12-06 09:13:21 +0100 | [diff] [blame] | 42 | static struct clk emi_fast_clk; |
| 43 | static struct clk ipu_clk; |
| 44 | static struct clk mipi_hsc1_clk; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 45 | |
| 46 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
| 47 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 48 | /* calculate best pre and post dividers to get the required divider */ |
| 49 | static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post, |
| 50 | u32 max_pre, u32 max_post) |
| 51 | { |
| 52 | if (div >= max_pre * max_post) { |
| 53 | *pre = max_pre; |
| 54 | *post = max_post; |
| 55 | } else if (div >= max_pre) { |
| 56 | u32 min_pre, temp_pre, old_err, err; |
| 57 | min_pre = DIV_ROUND_UP(div, max_post); |
| 58 | old_err = max_pre; |
| 59 | for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) { |
| 60 | err = div % temp_pre; |
| 61 | if (err == 0) { |
| 62 | *pre = temp_pre; |
| 63 | break; |
| 64 | } |
| 65 | err = temp_pre - err; |
| 66 | if (err < old_err) { |
| 67 | old_err = err; |
| 68 | *pre = temp_pre; |
| 69 | } |
| 70 | } |
| 71 | *post = DIV_ROUND_UP(div, *pre); |
| 72 | } else { |
| 73 | *pre = div; |
| 74 | *post = 1; |
| 75 | } |
| 76 | } |
| 77 | |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 78 | static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) |
| 79 | { |
| 80 | u32 reg = __raw_readl(clk->enable_reg); |
| 81 | |
| 82 | reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); |
| 83 | reg |= mode << clk->enable_shift; |
| 84 | |
| 85 | __raw_writel(reg, clk->enable_reg); |
| 86 | } |
| 87 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 88 | static int _clk_ccgr_enable(struct clk *clk) |
| 89 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 90 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | static void _clk_ccgr_disable(struct clk *clk) |
| 95 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 96 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); |
| 97 | } |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 98 | |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 99 | static int _clk_ccgr_enable_inrun(struct clk *clk) |
| 100 | { |
| 101 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); |
| 102 | return 0; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static void _clk_ccgr_disable_inwait(struct clk *clk) |
| 106 | { |
Uwe Kleine-König | 7990147 | 2010-09-10 16:58:42 +0200 | [diff] [blame] | 107 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | /* |
| 111 | * For the 4-to-1 muxed input clock |
| 112 | */ |
| 113 | static inline u32 _get_mux(struct clk *parent, struct clk *m0, |
| 114 | struct clk *m1, struct clk *m2, struct clk *m3) |
| 115 | { |
| 116 | if (parent == m0) |
| 117 | return 0; |
| 118 | else if (parent == m1) |
| 119 | return 1; |
| 120 | else if (parent == m2) |
| 121 | return 2; |
| 122 | else if (parent == m3) |
| 123 | return 3; |
| 124 | else |
| 125 | BUG(); |
| 126 | |
| 127 | return -EINVAL; |
| 128 | } |
| 129 | |
Yong Shen | 644b1d5 | 2011-01-04 14:22:55 +0800 | [diff] [blame] | 130 | static inline void __iomem *_mx51_get_pll_base(struct clk *pll) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 131 | { |
| 132 | if (pll == &pll1_main_clk) |
| 133 | return MX51_DPLL1_BASE; |
| 134 | else if (pll == &pll2_sw_clk) |
| 135 | return MX51_DPLL2_BASE; |
| 136 | else if (pll == &pll3_sw_clk) |
| 137 | return MX51_DPLL3_BASE; |
Yong Shen | 644b1d5 | 2011-01-04 14:22:55 +0800 | [diff] [blame] | 138 | else |
| 139 | BUG(); |
| 140 | |
| 141 | return NULL; |
| 142 | } |
| 143 | |
| 144 | static inline void __iomem *_mx53_get_pll_base(struct clk *pll) |
| 145 | { |
| 146 | if (pll == &pll1_main_clk) |
| 147 | return MX53_DPLL1_BASE; |
| 148 | else if (pll == &pll2_sw_clk) |
| 149 | return MX53_DPLL2_BASE; |
| 150 | else if (pll == &pll3_sw_clk) |
| 151 | return MX53_DPLL3_BASE; |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 152 | else if (pll == &mx53_pll4_sw_clk) |
| 153 | return MX53_DPLL4_BASE; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 154 | else |
| 155 | BUG(); |
| 156 | |
| 157 | return NULL; |
| 158 | } |
| 159 | |
Yong Shen | 644b1d5 | 2011-01-04 14:22:55 +0800 | [diff] [blame] | 160 | static inline void __iomem *_get_pll_base(struct clk *pll) |
| 161 | { |
| 162 | if (cpu_is_mx51()) |
| 163 | return _mx51_get_pll_base(pll); |
| 164 | else |
| 165 | return _mx53_get_pll_base(pll); |
| 166 | } |
| 167 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 168 | static unsigned long clk_pll_get_rate(struct clk *clk) |
| 169 | { |
| 170 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; |
| 171 | unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; |
| 172 | void __iomem *pllbase; |
| 173 | s64 temp; |
| 174 | unsigned long parent_rate; |
| 175 | |
| 176 | parent_rate = clk_get_rate(clk->parent); |
| 177 | |
| 178 | pllbase = _get_pll_base(clk); |
| 179 | |
| 180 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 181 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 182 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; |
| 183 | |
| 184 | if (pll_hfsm == 0) { |
| 185 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); |
| 186 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); |
| 187 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); |
| 188 | } else { |
| 189 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); |
| 190 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); |
| 191 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); |
| 192 | } |
| 193 | pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; |
| 194 | mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; |
| 195 | mfi = (mfi <= 5) ? 5 : mfi; |
| 196 | mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; |
| 197 | mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; |
| 198 | /* Sign extend to 32-bits */ |
| 199 | if (mfn >= 0x04000000) { |
| 200 | mfn |= 0xFC000000; |
| 201 | mfn_abs = -mfn; |
| 202 | } |
| 203 | |
| 204 | ref_clk = 2 * parent_rate; |
| 205 | if (dbl != 0) |
| 206 | ref_clk *= 2; |
| 207 | |
| 208 | ref_clk /= (pdf + 1); |
| 209 | temp = (u64) ref_clk * mfn_abs; |
| 210 | do_div(temp, mfd + 1); |
| 211 | if (mfn < 0) |
| 212 | temp = -temp; |
| 213 | temp = (ref_clk * mfi) + temp; |
| 214 | |
| 215 | return temp; |
| 216 | } |
| 217 | |
| 218 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) |
| 219 | { |
| 220 | u32 reg; |
| 221 | void __iomem *pllbase; |
| 222 | |
| 223 | long mfi, pdf, mfn, mfd = 999999; |
| 224 | s64 temp64; |
| 225 | unsigned long quad_parent_rate; |
| 226 | unsigned long pll_hfsm, dp_ctl; |
| 227 | unsigned long parent_rate; |
| 228 | |
| 229 | parent_rate = clk_get_rate(clk->parent); |
| 230 | |
| 231 | pllbase = _get_pll_base(clk); |
| 232 | |
| 233 | quad_parent_rate = 4 * parent_rate; |
| 234 | pdf = mfi = -1; |
| 235 | while (++pdf < 16 && mfi < 5) |
| 236 | mfi = rate * (pdf+1) / quad_parent_rate; |
| 237 | if (mfi > 15) |
| 238 | return -EINVAL; |
| 239 | pdf--; |
| 240 | |
| 241 | temp64 = rate * (pdf+1) - quad_parent_rate * mfi; |
| 242 | do_div(temp64, quad_parent_rate/1000000); |
| 243 | mfn = (long)temp64; |
| 244 | |
| 245 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 246 | /* use dpdck0_2 */ |
| 247 | __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); |
| 248 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; |
| 249 | if (pll_hfsm == 0) { |
| 250 | reg = mfi << 4 | pdf; |
| 251 | __raw_writel(reg, pllbase + MXC_PLL_DP_OP); |
| 252 | __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); |
| 253 | __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); |
| 254 | } else { |
| 255 | reg = mfi << 4 | pdf; |
| 256 | __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); |
| 257 | __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); |
| 258 | __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); |
| 259 | } |
| 260 | |
| 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | static int _clk_pll_enable(struct clk *clk) |
| 265 | { |
| 266 | u32 reg; |
| 267 | void __iomem *pllbase; |
| 268 | int i = 0; |
| 269 | |
| 270 | pllbase = _get_pll_base(clk); |
| 271 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; |
| 272 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 273 | |
| 274 | /* Wait for lock */ |
| 275 | do { |
| 276 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
| 277 | if (reg & MXC_PLL_DP_CTL_LRF) |
| 278 | break; |
| 279 | |
| 280 | udelay(1); |
| 281 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 282 | |
| 283 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 284 | pr_err("MX5: pll locking failed\n"); |
| 285 | return -EINVAL; |
| 286 | } |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | static void _clk_pll_disable(struct clk *clk) |
| 292 | { |
| 293 | u32 reg; |
| 294 | void __iomem *pllbase; |
| 295 | |
| 296 | pllbase = _get_pll_base(clk); |
| 297 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; |
| 298 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
| 299 | } |
| 300 | |
| 301 | static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) |
| 302 | { |
| 303 | u32 reg, step; |
| 304 | |
| 305 | reg = __raw_readl(MXC_CCM_CCSR); |
| 306 | |
| 307 | /* When switching from pll_main_clk to a bypass clock, first select a |
| 308 | * multiplexed clock in 'step_sel', then shift the glitchless mux |
| 309 | * 'pll1_sw_clk_sel'. |
| 310 | * |
| 311 | * When switching back, do it in reverse order |
| 312 | */ |
| 313 | if (parent == &pll1_main_clk) { |
| 314 | /* Switch to pll1_main_clk */ |
| 315 | reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 316 | __raw_writel(reg, MXC_CCM_CCSR); |
| 317 | /* step_clk mux switched to lp_apm, to save power. */ |
| 318 | reg = __raw_readl(MXC_CCM_CCSR); |
| 319 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 320 | reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << |
| 321 | MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 322 | } else { |
| 323 | if (parent == &lp_apm_clk) { |
| 324 | step = MXC_CCM_CCSR_STEP_SEL_LP_APM; |
| 325 | } else if (parent == &pll2_sw_clk) { |
| 326 | step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; |
| 327 | } else if (parent == &pll3_sw_clk) { |
| 328 | step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; |
| 329 | } else |
| 330 | return -EINVAL; |
| 331 | |
| 332 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; |
| 333 | reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); |
| 334 | |
| 335 | __raw_writel(reg, MXC_CCM_CCSR); |
| 336 | /* Switch to step_clk */ |
| 337 | reg = __raw_readl(MXC_CCM_CCSR); |
| 338 | reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; |
| 339 | } |
| 340 | __raw_writel(reg, MXC_CCM_CCSR); |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | static unsigned long clk_pll1_sw_get_rate(struct clk *clk) |
| 345 | { |
| 346 | u32 reg, div; |
| 347 | unsigned long parent_rate; |
| 348 | |
| 349 | parent_rate = clk_get_rate(clk->parent); |
| 350 | |
| 351 | reg = __raw_readl(MXC_CCM_CCSR); |
| 352 | |
| 353 | if (clk->parent == &pll2_sw_clk) { |
| 354 | div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> |
| 355 | MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; |
| 356 | } else if (clk->parent == &pll3_sw_clk) { |
| 357 | div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> |
| 358 | MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; |
| 359 | } else |
| 360 | div = 1; |
| 361 | return parent_rate / div; |
| 362 | } |
| 363 | |
| 364 | static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) |
| 365 | { |
| 366 | u32 reg; |
| 367 | |
| 368 | reg = __raw_readl(MXC_CCM_CCSR); |
| 369 | |
| 370 | if (parent == &pll2_sw_clk) |
| 371 | reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 372 | else |
| 373 | reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; |
| 374 | |
| 375 | __raw_writel(reg, MXC_CCM_CCSR); |
| 376 | return 0; |
| 377 | } |
| 378 | |
| 379 | static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) |
| 380 | { |
| 381 | u32 reg; |
| 382 | |
| 383 | if (parent == &osc_clk) |
| 384 | reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; |
| 385 | else |
| 386 | return -EINVAL; |
| 387 | |
| 388 | __raw_writel(reg, MXC_CCM_CCSR); |
| 389 | |
| 390 | return 0; |
| 391 | } |
| 392 | |
Yong Shen | 64f102b | 2010-10-21 21:18:59 +0800 | [diff] [blame] | 393 | static unsigned long clk_cpu_get_rate(struct clk *clk) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 394 | { |
| 395 | u32 cacrr, div; |
| 396 | unsigned long parent_rate; |
| 397 | |
| 398 | parent_rate = clk_get_rate(clk->parent); |
| 399 | cacrr = __raw_readl(MXC_CCM_CACRR); |
| 400 | div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; |
| 401 | |
| 402 | return parent_rate / div; |
| 403 | } |
| 404 | |
Yong Shen | 64f102b | 2010-10-21 21:18:59 +0800 | [diff] [blame] | 405 | static int clk_cpu_set_rate(struct clk *clk, unsigned long rate) |
| 406 | { |
| 407 | u32 reg, cpu_podf; |
| 408 | unsigned long parent_rate; |
| 409 | |
| 410 | parent_rate = clk_get_rate(clk->parent); |
| 411 | cpu_podf = parent_rate / rate - 1; |
| 412 | /* use post divider to change freq */ |
| 413 | reg = __raw_readl(MXC_CCM_CACRR); |
| 414 | reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK; |
| 415 | reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET; |
| 416 | __raw_writel(reg, MXC_CCM_CACRR); |
| 417 | |
| 418 | return 0; |
| 419 | } |
| 420 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 421 | static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) |
| 422 | { |
| 423 | u32 reg, mux; |
| 424 | int i = 0; |
| 425 | |
| 426 | mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); |
| 427 | |
| 428 | reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; |
| 429 | reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; |
| 430 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 431 | |
| 432 | /* Wait for lock */ |
| 433 | do { |
| 434 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 435 | if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) |
| 436 | break; |
| 437 | |
| 438 | udelay(1); |
| 439 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 440 | |
| 441 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 442 | pr_err("MX5: Set parent for periph_apm clock failed\n"); |
| 443 | return -EINVAL; |
| 444 | } |
| 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) |
| 450 | { |
| 451 | u32 reg; |
| 452 | |
| 453 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 454 | |
| 455 | if (parent == &pll2_sw_clk) |
| 456 | reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 457 | else if (parent == &periph_apm_clk) |
| 458 | reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; |
| 459 | else |
| 460 | return -EINVAL; |
| 461 | |
| 462 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 463 | |
| 464 | return 0; |
| 465 | } |
| 466 | |
| 467 | static struct clk main_bus_clk = { |
| 468 | .parent = &pll2_sw_clk, |
| 469 | .set_parent = _clk_main_bus_set_parent, |
| 470 | }; |
| 471 | |
| 472 | static unsigned long clk_ahb_get_rate(struct clk *clk) |
| 473 | { |
| 474 | u32 reg, div; |
| 475 | unsigned long parent_rate; |
| 476 | |
| 477 | parent_rate = clk_get_rate(clk->parent); |
| 478 | |
| 479 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 480 | div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> |
| 481 | MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; |
| 482 | return parent_rate / div; |
| 483 | } |
| 484 | |
| 485 | |
| 486 | static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) |
| 487 | { |
| 488 | u32 reg, div; |
| 489 | unsigned long parent_rate; |
| 490 | int i = 0; |
| 491 | |
| 492 | parent_rate = clk_get_rate(clk->parent); |
| 493 | |
| 494 | div = parent_rate / rate; |
| 495 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) |
| 496 | return -EINVAL; |
| 497 | |
| 498 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 499 | reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; |
| 500 | reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; |
| 501 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 502 | |
| 503 | /* Wait for lock */ |
| 504 | do { |
| 505 | reg = __raw_readl(MXC_CCM_CDHIPR); |
| 506 | if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) |
| 507 | break; |
| 508 | |
| 509 | udelay(1); |
| 510 | } while (++i < MAX_DPLL_WAIT_TRIES); |
| 511 | |
| 512 | if (i == MAX_DPLL_WAIT_TRIES) { |
| 513 | pr_err("MX5: clk_ahb_set_rate failed\n"); |
| 514 | return -EINVAL; |
| 515 | } |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
| 520 | static unsigned long _clk_ahb_round_rate(struct clk *clk, |
| 521 | unsigned long rate) |
| 522 | { |
| 523 | u32 div; |
| 524 | unsigned long parent_rate; |
| 525 | |
| 526 | parent_rate = clk_get_rate(clk->parent); |
| 527 | |
| 528 | div = parent_rate / rate; |
| 529 | if (div > 8) |
| 530 | div = 8; |
| 531 | else if (div == 0) |
| 532 | div++; |
| 533 | return parent_rate / div; |
| 534 | } |
| 535 | |
| 536 | |
| 537 | static int _clk_max_enable(struct clk *clk) |
| 538 | { |
| 539 | u32 reg; |
| 540 | |
| 541 | _clk_ccgr_enable(clk); |
| 542 | |
| 543 | /* Handshake with MAX when LPM is entered. */ |
| 544 | reg = __raw_readl(MXC_CCM_CLPCR); |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 545 | if (cpu_is_mx51()) |
| 546 | reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 547 | else if (cpu_is_mx53()) |
| 548 | reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 549 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 550 | |
| 551 | return 0; |
| 552 | } |
| 553 | |
| 554 | static void _clk_max_disable(struct clk *clk) |
| 555 | { |
| 556 | u32 reg; |
| 557 | |
| 558 | _clk_ccgr_disable_inwait(clk); |
| 559 | |
| 560 | /* No Handshake with MAX when LPM is entered as its disabled. */ |
| 561 | reg = __raw_readl(MXC_CCM_CLPCR); |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 562 | if (cpu_is_mx51()) |
| 563 | reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
| 564 | else if (cpu_is_mx53()) |
| 565 | reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS; |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 566 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 567 | } |
| 568 | |
| 569 | static unsigned long clk_ipg_get_rate(struct clk *clk) |
| 570 | { |
| 571 | u32 reg, div; |
| 572 | unsigned long parent_rate; |
| 573 | |
| 574 | parent_rate = clk_get_rate(clk->parent); |
| 575 | |
| 576 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 577 | div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> |
| 578 | MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; |
| 579 | |
| 580 | return parent_rate / div; |
| 581 | } |
| 582 | |
| 583 | static unsigned long clk_ipg_per_get_rate(struct clk *clk) |
| 584 | { |
| 585 | u32 reg, prediv1, prediv2, podf; |
| 586 | unsigned long parent_rate; |
| 587 | |
| 588 | parent_rate = clk_get_rate(clk->parent); |
| 589 | |
| 590 | if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { |
| 591 | /* the main_bus_clk is the one before the DVFS engine */ |
| 592 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 593 | prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> |
| 594 | MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; |
| 595 | prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> |
| 596 | MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; |
| 597 | podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> |
| 598 | MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; |
| 599 | return parent_rate / (prediv1 * prediv2 * podf); |
| 600 | } else if (clk->parent == &ipg_clk) |
| 601 | return parent_rate; |
| 602 | else |
| 603 | BUG(); |
| 604 | } |
| 605 | |
| 606 | static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) |
| 607 | { |
| 608 | u32 reg; |
| 609 | |
| 610 | reg = __raw_readl(MXC_CCM_CBCMR); |
| 611 | |
| 612 | reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 613 | reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 614 | |
| 615 | if (parent == &ipg_clk) |
| 616 | reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; |
| 617 | else if (parent == &lp_apm_clk) |
| 618 | reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; |
| 619 | else if (parent != &main_bus_clk) |
| 620 | return -EINVAL; |
| 621 | |
| 622 | __raw_writel(reg, MXC_CCM_CBCMR); |
| 623 | |
| 624 | return 0; |
| 625 | } |
| 626 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 627 | #define clk_nfc_set_parent NULL |
| 628 | |
| 629 | static unsigned long clk_nfc_get_rate(struct clk *clk) |
| 630 | { |
| 631 | unsigned long rate; |
| 632 | u32 reg, div; |
| 633 | |
| 634 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 635 | div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >> |
| 636 | MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1; |
| 637 | rate = clk_get_rate(clk->parent) / div; |
| 638 | WARN_ON(rate == 0); |
| 639 | return rate; |
| 640 | } |
| 641 | |
| 642 | static unsigned long clk_nfc_round_rate(struct clk *clk, |
| 643 | unsigned long rate) |
| 644 | { |
| 645 | u32 div; |
| 646 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| 647 | |
| 648 | if (!rate) |
| 649 | return -EINVAL; |
| 650 | |
| 651 | div = parent_rate / rate; |
| 652 | |
| 653 | if (parent_rate % rate) |
| 654 | div++; |
| 655 | |
| 656 | if (div > 8) |
| 657 | return -EINVAL; |
| 658 | |
| 659 | return parent_rate / div; |
| 660 | |
| 661 | } |
| 662 | |
| 663 | static int clk_nfc_set_rate(struct clk *clk, unsigned long rate) |
| 664 | { |
| 665 | u32 reg, div; |
| 666 | |
| 667 | div = clk_get_rate(clk->parent) / rate; |
| 668 | if (div == 0) |
| 669 | div++; |
| 670 | if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8)) |
| 671 | return -EINVAL; |
| 672 | |
| 673 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 674 | reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; |
| 675 | reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; |
| 676 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 677 | |
| 678 | while (__raw_readl(MXC_CCM_CDHIPR) & |
| 679 | MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){ |
| 680 | } |
| 681 | |
| 682 | return 0; |
| 683 | } |
| 684 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 685 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
| 686 | { |
| 687 | return external_high_reference; |
| 688 | } |
| 689 | |
| 690 | static unsigned long get_low_reference_clock_rate(struct clk *clk) |
| 691 | { |
| 692 | return external_low_reference; |
| 693 | } |
| 694 | |
| 695 | static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) |
| 696 | { |
| 697 | return oscillator_reference; |
| 698 | } |
| 699 | |
| 700 | static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) |
| 701 | { |
| 702 | return ckih2_reference; |
| 703 | } |
| 704 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 705 | static unsigned long clk_emi_slow_get_rate(struct clk *clk) |
| 706 | { |
| 707 | u32 reg, div; |
| 708 | |
| 709 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 710 | div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> |
| 711 | MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; |
| 712 | |
| 713 | return clk_get_rate(clk->parent) / div; |
| 714 | } |
| 715 | |
Sascha Hauer | b848169 | 2010-12-06 09:13:21 +0100 | [diff] [blame] | 716 | static unsigned long _clk_ddr_hf_get_rate(struct clk *clk) |
| 717 | { |
| 718 | unsigned long rate; |
| 719 | u32 reg, div; |
| 720 | |
| 721 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 722 | div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >> |
| 723 | MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1; |
| 724 | rate = clk_get_rate(clk->parent) / div; |
| 725 | |
| 726 | return rate; |
| 727 | } |
| 728 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 729 | /* External high frequency clock */ |
| 730 | static struct clk ckih_clk = { |
| 731 | .get_rate = get_high_reference_clock_rate, |
| 732 | }; |
| 733 | |
| 734 | static struct clk ckih2_clk = { |
| 735 | .get_rate = get_ckih2_reference_clock_rate, |
| 736 | }; |
| 737 | |
| 738 | static struct clk osc_clk = { |
| 739 | .get_rate = get_oscillator_reference_clock_rate, |
| 740 | }; |
| 741 | |
| 742 | /* External low frequency (32kHz) clock */ |
| 743 | static struct clk ckil_clk = { |
| 744 | .get_rate = get_low_reference_clock_rate, |
| 745 | }; |
| 746 | |
| 747 | static struct clk pll1_main_clk = { |
| 748 | .parent = &osc_clk, |
| 749 | .get_rate = clk_pll_get_rate, |
| 750 | .enable = _clk_pll_enable, |
| 751 | .disable = _clk_pll_disable, |
| 752 | }; |
| 753 | |
| 754 | /* Clock tree block diagram (WIP): |
| 755 | * CCM: Clock Controller Module |
| 756 | * |
| 757 | * PLL output -> | |
| 758 | * | CCM Switcher -> CCM_CLK_ROOT_GEN -> |
| 759 | * PLL bypass -> | |
| 760 | * |
| 761 | */ |
| 762 | |
| 763 | /* PLL1 SW supplies to ARM core */ |
| 764 | static struct clk pll1_sw_clk = { |
| 765 | .parent = &pll1_main_clk, |
| 766 | .set_parent = _clk_pll1_sw_set_parent, |
| 767 | .get_rate = clk_pll1_sw_get_rate, |
| 768 | }; |
| 769 | |
| 770 | /* PLL2 SW supplies to AXI/AHB/IP buses */ |
| 771 | static struct clk pll2_sw_clk = { |
| 772 | .parent = &osc_clk, |
| 773 | .get_rate = clk_pll_get_rate, |
| 774 | .set_rate = _clk_pll_set_rate, |
| 775 | .set_parent = _clk_pll2_sw_set_parent, |
| 776 | .enable = _clk_pll_enable, |
| 777 | .disable = _clk_pll_disable, |
| 778 | }; |
| 779 | |
| 780 | /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ |
| 781 | static struct clk pll3_sw_clk = { |
| 782 | .parent = &osc_clk, |
| 783 | .set_rate = _clk_pll_set_rate, |
| 784 | .get_rate = clk_pll_get_rate, |
| 785 | .enable = _clk_pll_enable, |
| 786 | .disable = _clk_pll_disable, |
| 787 | }; |
| 788 | |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 789 | /* PLL4 SW supplies to LVDS Display Bridge(LDB) */ |
| 790 | static struct clk mx53_pll4_sw_clk = { |
| 791 | .parent = &osc_clk, |
| 792 | .set_rate = _clk_pll_set_rate, |
| 793 | .enable = _clk_pll_enable, |
| 794 | .disable = _clk_pll_disable, |
| 795 | }; |
| 796 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 797 | /* Low-power Audio Playback Mode clock */ |
| 798 | static struct clk lp_apm_clk = { |
| 799 | .parent = &osc_clk, |
| 800 | .set_parent = _clk_lp_apm_set_parent, |
| 801 | }; |
| 802 | |
| 803 | static struct clk periph_apm_clk = { |
| 804 | .parent = &pll1_sw_clk, |
| 805 | .set_parent = _clk_periph_apm_set_parent, |
| 806 | }; |
| 807 | |
| 808 | static struct clk cpu_clk = { |
| 809 | .parent = &pll1_sw_clk, |
Yong Shen | 64f102b | 2010-10-21 21:18:59 +0800 | [diff] [blame] | 810 | .get_rate = clk_cpu_get_rate, |
| 811 | .set_rate = clk_cpu_set_rate, |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 812 | }; |
| 813 | |
| 814 | static struct clk ahb_clk = { |
| 815 | .parent = &main_bus_clk, |
| 816 | .get_rate = clk_ahb_get_rate, |
| 817 | .set_rate = _clk_ahb_set_rate, |
| 818 | .round_rate = _clk_ahb_round_rate, |
| 819 | }; |
| 820 | |
Dinh Nguyen | 9ab4650 | 2010-11-15 11:30:01 -0600 | [diff] [blame] | 821 | static struct clk iim_clk = { |
| 822 | .parent = &ipg_clk, |
| 823 | .enable_reg = MXC_CCM_CCGR0, |
| 824 | .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, |
| 825 | }; |
| 826 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 827 | /* Main IP interface clock for access to registers */ |
| 828 | static struct clk ipg_clk = { |
| 829 | .parent = &ahb_clk, |
| 830 | .get_rate = clk_ipg_get_rate, |
| 831 | }; |
| 832 | |
| 833 | static struct clk ipg_perclk = { |
| 834 | .parent = &lp_apm_clk, |
| 835 | .get_rate = clk_ipg_per_get_rate, |
| 836 | .set_parent = _clk_ipg_per_set_parent, |
| 837 | }; |
| 838 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 839 | static struct clk ahb_max_clk = { |
| 840 | .parent = &ahb_clk, |
| 841 | .enable_reg = MXC_CCM_CCGR0, |
| 842 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, |
| 843 | .enable = _clk_max_enable, |
| 844 | .disable = _clk_max_disable, |
| 845 | }; |
| 846 | |
| 847 | static struct clk aips_tz1_clk = { |
| 848 | .parent = &ahb_clk, |
| 849 | .secondary = &ahb_max_clk, |
| 850 | .enable_reg = MXC_CCM_CCGR0, |
| 851 | .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, |
| 852 | .enable = _clk_ccgr_enable, |
| 853 | .disable = _clk_ccgr_disable_inwait, |
| 854 | }; |
| 855 | |
| 856 | static struct clk aips_tz2_clk = { |
| 857 | .parent = &ahb_clk, |
| 858 | .secondary = &ahb_max_clk, |
| 859 | .enable_reg = MXC_CCM_CCGR0, |
| 860 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, |
| 861 | .enable = _clk_ccgr_enable, |
| 862 | .disable = _clk_ccgr_disable_inwait, |
| 863 | }; |
| 864 | |
| 865 | static struct clk gpt_32k_clk = { |
| 866 | .id = 0, |
| 867 | .parent = &ckil_clk, |
| 868 | }; |
| 869 | |
Jason Wang | a7ebd93 | 2010-07-14 21:24:53 +0800 | [diff] [blame] | 870 | static struct clk kpp_clk = { |
| 871 | .id = 0, |
| 872 | }; |
| 873 | |
Fabio Estevam | 7f77f91 | 2010-12-06 16:38:33 -0200 | [diff] [blame] | 874 | static struct clk dummy_clk = { |
| 875 | .id = 0, |
| 876 | }; |
| 877 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 878 | static struct clk emi_slow_clk = { |
| 879 | .parent = &pll2_sw_clk, |
| 880 | .enable_reg = MXC_CCM_CCGR5, |
| 881 | .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, |
| 882 | .enable = _clk_ccgr_enable, |
| 883 | .disable = _clk_ccgr_disable_inwait, |
| 884 | .get_rate = clk_emi_slow_get_rate, |
| 885 | }; |
| 886 | |
Sascha Hauer | b848169 | 2010-12-06 09:13:21 +0100 | [diff] [blame] | 887 | static int clk_ipu_enable(struct clk *clk) |
| 888 | { |
| 889 | u32 reg; |
| 890 | |
| 891 | _clk_ccgr_enable(clk); |
| 892 | |
| 893 | /* Enable handshake with IPU when certain clock rates are changed */ |
| 894 | reg = __raw_readl(MXC_CCM_CCDR); |
| 895 | reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; |
| 896 | __raw_writel(reg, MXC_CCM_CCDR); |
| 897 | |
| 898 | /* Enable handshake with IPU when LPM is entered */ |
| 899 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 900 | reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; |
| 901 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 902 | |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | static void clk_ipu_disable(struct clk *clk) |
| 907 | { |
| 908 | u32 reg; |
| 909 | |
| 910 | _clk_ccgr_disable(clk); |
| 911 | |
| 912 | /* Disable handshake with IPU whe dividers are changed */ |
| 913 | reg = __raw_readl(MXC_CCM_CCDR); |
| 914 | reg |= MXC_CCM_CCDR_IPU_HS_MASK; |
| 915 | __raw_writel(reg, MXC_CCM_CCDR); |
| 916 | |
| 917 | /* Disable handshake with IPU when LPM is entered */ |
| 918 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 919 | reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; |
| 920 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 921 | } |
| 922 | |
| 923 | static struct clk ahbmux1_clk = { |
| 924 | .parent = &ahb_clk, |
| 925 | .secondary = &ahb_max_clk, |
| 926 | .enable_reg = MXC_CCM_CCGR0, |
| 927 | .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, |
| 928 | .enable = _clk_ccgr_enable, |
| 929 | .disable = _clk_ccgr_disable_inwait, |
| 930 | }; |
| 931 | |
| 932 | static struct clk ipu_sec_clk = { |
| 933 | .parent = &emi_fast_clk, |
| 934 | .secondary = &ahbmux1_clk, |
| 935 | }; |
| 936 | |
| 937 | static struct clk ddr_hf_clk = { |
| 938 | .parent = &pll1_sw_clk, |
| 939 | .get_rate = _clk_ddr_hf_get_rate, |
| 940 | }; |
| 941 | |
| 942 | static struct clk ddr_clk = { |
| 943 | .parent = &ddr_hf_clk, |
| 944 | }; |
| 945 | |
| 946 | /* clock definitions for MIPI HSC unit which has been removed |
| 947 | * from documentation, but not from hardware |
| 948 | */ |
| 949 | static int _clk_hsc_enable(struct clk *clk) |
| 950 | { |
| 951 | u32 reg; |
| 952 | |
| 953 | _clk_ccgr_enable(clk); |
| 954 | /* Handshake with IPU when certain clock rates are changed. */ |
| 955 | reg = __raw_readl(MXC_CCM_CCDR); |
| 956 | reg &= ~MXC_CCM_CCDR_HSC_HS_MASK; |
| 957 | __raw_writel(reg, MXC_CCM_CCDR); |
| 958 | |
| 959 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 960 | reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; |
| 961 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 962 | |
| 963 | return 0; |
| 964 | } |
| 965 | |
| 966 | static void _clk_hsc_disable(struct clk *clk) |
| 967 | { |
| 968 | u32 reg; |
| 969 | |
| 970 | _clk_ccgr_disable(clk); |
| 971 | /* No handshake with HSC as its not enabled. */ |
| 972 | reg = __raw_readl(MXC_CCM_CCDR); |
| 973 | reg |= MXC_CCM_CCDR_HSC_HS_MASK; |
| 974 | __raw_writel(reg, MXC_CCM_CCDR); |
| 975 | |
| 976 | reg = __raw_readl(MXC_CCM_CLPCR); |
| 977 | reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS; |
| 978 | __raw_writel(reg, MXC_CCM_CLPCR); |
| 979 | } |
| 980 | |
| 981 | static struct clk mipi_hsp_clk = { |
| 982 | .parent = &ipu_clk, |
| 983 | .enable_reg = MXC_CCM_CCGR4, |
| 984 | .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, |
| 985 | .enable = _clk_hsc_enable, |
| 986 | .disable = _clk_hsc_disable, |
| 987 | .secondary = &mipi_hsc1_clk, |
| 988 | }; |
| 989 | |
Eric Bénard | 7e5a747 | 2010-10-12 12:26:32 +0200 | [diff] [blame] | 990 | #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 991 | static struct clk name = { \ |
| 992 | .id = i, \ |
| 993 | .enable_reg = er, \ |
| 994 | .enable_shift = es, \ |
| 995 | .get_rate = pfx##_get_rate, \ |
| 996 | .set_rate = pfx##_set_rate, \ |
| 997 | .round_rate = pfx##_round_rate, \ |
| 998 | .set_parent = pfx##_set_parent, \ |
| 999 | .enable = _clk_ccgr_enable, \ |
| 1000 | .disable = _clk_ccgr_disable, \ |
| 1001 | .parent = p, \ |
| 1002 | .secondary = s, \ |
| 1003 | } |
| 1004 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1005 | #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \ |
| 1006 | static struct clk name = { \ |
| 1007 | .id = i, \ |
| 1008 | .enable_reg = er, \ |
| 1009 | .enable_shift = es, \ |
| 1010 | .get_rate = pfx##_get_rate, \ |
| 1011 | .set_rate = pfx##_set_rate, \ |
| 1012 | .set_parent = pfx##_set_parent, \ |
| 1013 | .enable = _clk_max_enable, \ |
| 1014 | .disable = _clk_max_disable, \ |
| 1015 | .parent = p, \ |
| 1016 | .secondary = s, \ |
| 1017 | } |
| 1018 | |
Eric Bénard | 0076232 | 2010-10-11 21:55:24 +0200 | [diff] [blame] | 1019 | #define CLK_GET_RATE(name, nr, bitsname) \ |
| 1020 | static unsigned long clk_##name##_get_rate(struct clk *clk) \ |
| 1021 | { \ |
| 1022 | u32 reg, pred, podf; \ |
| 1023 | \ |
| 1024 | reg = __raw_readl(MXC_CCM_CSCDR##nr); \ |
| 1025 | pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \ |
| 1026 | >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \ |
| 1027 | podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \ |
| 1028 | >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \ |
| 1029 | \ |
| 1030 | return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \ |
| 1031 | (pred + 1) * (podf + 1)); \ |
| 1032 | } |
| 1033 | |
| 1034 | #define CLK_SET_PARENT(name, nr, bitsname) \ |
| 1035 | static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \ |
| 1036 | { \ |
| 1037 | u32 reg, mux; \ |
| 1038 | \ |
| 1039 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \ |
| 1040 | &pll3_sw_clk, &lp_apm_clk); \ |
| 1041 | reg = __raw_readl(MXC_CCM_CSCMR##nr) & \ |
| 1042 | ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \ |
| 1043 | reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \ |
| 1044 | __raw_writel(reg, MXC_CCM_CSCMR##nr); \ |
| 1045 | \ |
| 1046 | return 0; \ |
| 1047 | } |
| 1048 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1049 | #define CLK_SET_RATE(name, nr, bitsname) \ |
| 1050 | static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \ |
| 1051 | { \ |
| 1052 | u32 reg, div, parent_rate; \ |
| 1053 | u32 pre = 0, post = 0; \ |
| 1054 | \ |
| 1055 | parent_rate = clk_get_rate(clk->parent); \ |
| 1056 | div = parent_rate / rate; \ |
| 1057 | \ |
| 1058 | if ((parent_rate / div) != rate) \ |
| 1059 | return -EINVAL; \ |
| 1060 | \ |
| 1061 | __calc_pre_post_dividers(div, &pre, &post, \ |
| 1062 | (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \ |
| 1063 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \ |
| 1064 | (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \ |
| 1065 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\ |
| 1066 | \ |
| 1067 | /* Set sdhc1 clock divider */ \ |
| 1068 | reg = __raw_readl(MXC_CCM_CSCDR##nr) & \ |
| 1069 | ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \ |
| 1070 | | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \ |
| 1071 | reg |= (post - 1) << \ |
| 1072 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \ |
| 1073 | reg |= (pre - 1) << \ |
| 1074 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \ |
| 1075 | __raw_writel(reg, MXC_CCM_CSCDR##nr); \ |
| 1076 | \ |
| 1077 | return 0; \ |
| 1078 | } |
| 1079 | |
Eric Bénard | 0076232 | 2010-10-11 21:55:24 +0200 | [diff] [blame] | 1080 | /* UART */ |
| 1081 | CLK_GET_RATE(uart, 1, UART) |
| 1082 | CLK_SET_PARENT(uart, 1, UART) |
| 1083 | |
| 1084 | static struct clk uart_root_clk = { |
| 1085 | .parent = &pll2_sw_clk, |
| 1086 | .get_rate = clk_uart_get_rate, |
| 1087 | .set_parent = clk_uart_set_parent, |
| 1088 | }; |
| 1089 | |
| 1090 | /* USBOH3 */ |
| 1091 | CLK_GET_RATE(usboh3, 1, USBOH3) |
| 1092 | CLK_SET_PARENT(usboh3, 1, USBOH3) |
| 1093 | |
| 1094 | static struct clk usboh3_clk = { |
| 1095 | .parent = &pll2_sw_clk, |
| 1096 | .get_rate = clk_usboh3_get_rate, |
| 1097 | .set_parent = clk_usboh3_set_parent, |
Arnaud Patard (Rtp) | 711669e | 2010-12-20 16:48:58 +0100 | [diff] [blame] | 1098 | .enable = _clk_ccgr_enable, |
| 1099 | .disable = _clk_ccgr_disable, |
| 1100 | .enable_reg = MXC_CCM_CCGR2, |
| 1101 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, |
| 1102 | }; |
| 1103 | |
| 1104 | static struct clk usb_ahb_clk = { |
| 1105 | .parent = &ipg_clk, |
| 1106 | .enable = _clk_ccgr_enable, |
| 1107 | .disable = _clk_ccgr_disable, |
| 1108 | .enable_reg = MXC_CCM_CCGR2, |
| 1109 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, |
| 1110 | }; |
| 1111 | |
| 1112 | static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent) |
| 1113 | { |
| 1114 | u32 reg; |
| 1115 | |
| 1116 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL; |
| 1117 | |
| 1118 | if (parent == &pll3_sw_clk) |
| 1119 | reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET; |
| 1120 | |
| 1121 | __raw_writel(reg, MXC_CCM_CSCMR1); |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
| 1126 | static struct clk usb_phy1_clk = { |
| 1127 | .parent = &pll3_sw_clk, |
| 1128 | .set_parent = clk_usb_phy1_set_parent, |
| 1129 | .enable = _clk_ccgr_enable, |
| 1130 | .enable_reg = MXC_CCM_CCGR2, |
| 1131 | .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, |
| 1132 | .disable = _clk_ccgr_disable, |
Eric Bénard | 0076232 | 2010-10-11 21:55:24 +0200 | [diff] [blame] | 1133 | }; |
| 1134 | |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 1135 | /* eCSPI */ |
Eric Bénard | 0076232 | 2010-10-11 21:55:24 +0200 | [diff] [blame] | 1136 | CLK_GET_RATE(ecspi, 2, CSPI) |
| 1137 | CLK_SET_PARENT(ecspi, 1, CSPI) |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 1138 | |
| 1139 | static struct clk ecspi_main_clk = { |
| 1140 | .parent = &pll3_sw_clk, |
| 1141 | .get_rate = clk_ecspi_get_rate, |
| 1142 | .set_parent = clk_ecspi_set_parent, |
| 1143 | }; |
| 1144 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1145 | /* eSDHC */ |
| 1146 | CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1) |
| 1147 | CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) |
| 1148 | CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) |
| 1149 | |
| 1150 | CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) |
| 1151 | CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) |
| 1152 | CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) |
| 1153 | |
Uwe Kleine-König | 74d99f3 | 2010-09-10 17:01:26 +0200 | [diff] [blame] | 1154 | #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ |
| 1155 | static struct clk name = { \ |
| 1156 | .id = i, \ |
| 1157 | .enable_reg = er, \ |
| 1158 | .enable_shift = es, \ |
| 1159 | .get_rate = gr, \ |
| 1160 | .set_rate = sr, \ |
| 1161 | .enable = e, \ |
| 1162 | .disable = d, \ |
| 1163 | .parent = p, \ |
| 1164 | .secondary = s, \ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1165 | } |
| 1166 | |
Uwe Kleine-König | 74d99f3 | 2010-09-10 17:01:26 +0200 | [diff] [blame] | 1167 | #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ |
| 1168 | DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1169 | |
| 1170 | /* Shared peripheral bus arbiter */ |
| 1171 | DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, |
| 1172 | NULL, NULL, &ipg_clk, NULL); |
| 1173 | |
| 1174 | /* UART */ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1175 | DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, |
| 1176 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 1177 | DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, |
| 1178 | NULL, NULL, &ipg_clk, &aips_tz1_clk); |
| 1179 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, |
| 1180 | NULL, NULL, &ipg_clk, &spba_clk); |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 1181 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, |
| 1182 | NULL, NULL, &uart_root_clk, &uart1_ipg_clk); |
| 1183 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, |
| 1184 | NULL, NULL, &uart_root_clk, &uart2_ipg_clk); |
| 1185 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, |
| 1186 | NULL, NULL, &uart_root_clk, &uart3_ipg_clk); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1187 | |
| 1188 | /* GPT */ |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1189 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, |
| 1190 | NULL, NULL, &ipg_clk, NULL); |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 1191 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, |
| 1192 | NULL, NULL, &ipg_clk, &gpt_ipg_clk); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1193 | |
Dinh Nguyen | 71c2e51 | 2010-05-27 10:45:04 -0500 | [diff] [blame] | 1194 | /* I2C */ |
| 1195 | DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, |
| 1196 | NULL, NULL, &ipg_clk, NULL); |
| 1197 | DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, |
| 1198 | NULL, NULL, &ipg_clk, NULL); |
| 1199 | DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, |
| 1200 | NULL, NULL, &ipg_clk, NULL); |
| 1201 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1202 | /* FEC */ |
| 1203 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, |
| 1204 | NULL, NULL, &ipg_clk, NULL); |
| 1205 | |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 1206 | /* NFC */ |
Eric Bénard | 7e5a747 | 2010-10-12 12:26:32 +0200 | [diff] [blame] | 1207 | DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 1208 | clk_nfc, &emi_slow_clk, NULL); |
| 1209 | |
Sascha Hauer | b861866 | 2010-08-20 16:43:54 +0200 | [diff] [blame] | 1210 | /* SSI */ |
| 1211 | DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET, |
| 1212 | NULL, NULL, &ipg_clk, NULL); |
| 1213 | DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET, |
| 1214 | NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk); |
| 1215 | DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, |
| 1216 | NULL, NULL, &ipg_clk, NULL); |
| 1217 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, |
| 1218 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); |
Peter Horton | f259722 | 2010-12-03 17:07:28 +0000 | [diff] [blame] | 1219 | DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, |
| 1220 | NULL, NULL, &ipg_clk, NULL); |
| 1221 | DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, |
| 1222 | NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); |
Sascha Hauer | b861866 | 2010-08-20 16:43:54 +0200 | [diff] [blame] | 1223 | |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 1224 | /* eCSPI */ |
| 1225 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
| 1226 | NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, |
| 1227 | &ipg_clk, &spba_clk); |
| 1228 | DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET, |
| 1229 | NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk); |
| 1230 | DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET, |
| 1231 | NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, |
| 1232 | &ipg_clk, &aips_tz2_clk); |
| 1233 | DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET, |
| 1234 | NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk); |
| 1235 | |
| 1236 | /* CSPI */ |
| 1237 | DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
| 1238 | NULL, NULL, &ipg_clk, &aips_tz2_clk); |
| 1239 | DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET, |
| 1240 | NULL, NULL, &ipg_clk, &cspi_ipg_clk); |
| 1241 | |
Uwe Kleine-König | 8a8d206 | 2010-10-08 16:00:11 +0200 | [diff] [blame] | 1242 | /* SDMA */ |
| 1243 | DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET, |
| 1244 | NULL, NULL, &ahb_clk, NULL); |
| 1245 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1246 | /* eSDHC */ |
| 1247 | DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET, |
| 1248 | NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); |
| 1249 | DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET, |
| 1250 | clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); |
| 1251 | DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, |
| 1252 | NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); |
| 1253 | DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, |
| 1254 | clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); |
| 1255 | |
Sascha Hauer | b848169 | 2010-12-06 09:13:21 +0100 | [diff] [blame] | 1256 | DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); |
| 1257 | DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); |
| 1258 | DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); |
| 1259 | |
| 1260 | /* IPU */ |
| 1261 | DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET, |
| 1262 | NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk); |
| 1263 | |
| 1264 | DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET, |
| 1265 | NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait, |
| 1266 | &ddr_clk, NULL); |
| 1267 | |
| 1268 | DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET, |
| 1269 | NULL, NULL, &pll3_sw_clk, NULL); |
| 1270 | DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET, |
| 1271 | NULL, NULL, &pll3_sw_clk, NULL); |
| 1272 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1273 | #define _REGISTER_CLOCK(d, n, c) \ |
| 1274 | { \ |
| 1275 | .dev_id = d, \ |
| 1276 | .con_id = n, \ |
| 1277 | .clk = &c, \ |
| 1278 | }, |
| 1279 | |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1280 | static struct clk_lookup mx51_lookups[] = { |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1281 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 1282 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 1283 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 1284 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 1285 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
Dinh Nguyen | 71c2e51 | 2010-05-27 10:45:04 -0500 | [diff] [blame] | 1286 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 1287 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| 1288 | _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) |
Dinh Nguyen | c53bdf1 | 2010-04-30 15:48:24 -0500 | [diff] [blame] | 1289 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) |
Arnaud Patard (Rtp) | 711669e | 2010-12-20 16:48:58 +0100 | [diff] [blame] | 1290 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk) |
| 1291 | _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk) |
Dinh Nguyen | c53bdf1 | 2010-04-30 15:48:24 -0500 | [diff] [blame] | 1292 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) |
Arnaud Patard (Rtp) | 711669e | 2010-12-20 16:48:58 +0100 | [diff] [blame] | 1293 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk) |
| 1294 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk) |
| 1295 | _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) |
Dinh Nguyen | 2ba5a2c | 2010-05-10 13:45:59 -0500 | [diff] [blame] | 1296 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) |
| 1297 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) |
Fabio Estevam | a5fcfef | 2010-12-01 11:11:47 -0200 | [diff] [blame^] | 1298 | _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) |
Sascha Hauer | 2b82e64 | 2010-08-03 11:59:07 +0200 | [diff] [blame] | 1299 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) |
Sascha Hauer | b861866 | 2010-08-20 16:43:54 +0200 | [diff] [blame] | 1300 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 1301 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
Peter Horton | f259722 | 2010-12-03 17:07:28 +0000 | [diff] [blame] | 1302 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) |
Uwe Kleine-König | 8a8d206 | 2010-10-08 16:00:11 +0200 | [diff] [blame] | 1303 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) |
Sascha Hauer | 8f6e900 | 2010-08-25 11:56:26 +0200 | [diff] [blame] | 1304 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) |
| 1305 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) |
| 1306 | _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk) |
Jason Wang | 8d83db8 | 2010-09-02 15:52:00 +0800 | [diff] [blame] | 1307 | _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) |
| 1308 | _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) |
| 1309 | _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1310 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
| 1311 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) |
Yong Shen | 64f102b | 2010-10-21 21:18:59 +0800 | [diff] [blame] | 1312 | _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) |
Dinh Nguyen | 9ab4650 | 2010-11-15 11:30:01 -0600 | [diff] [blame] | 1313 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) |
Fabio Estevam | 2c1f467 | 2010-12-07 14:16:04 -0200 | [diff] [blame] | 1314 | _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) |
| 1315 | _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk) |
Sascha Hauer | b848169 | 2010-12-06 09:13:21 +0100 | [diff] [blame] | 1316 | _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk) |
| 1317 | _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) |
| 1318 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) |
| 1319 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1320 | }; |
| 1321 | |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1322 | static struct clk_lookup mx53_lookups[] = { |
| 1323 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 1324 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 1325 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 1326 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 1327 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
Dinh Nguyen | 9ab4650 | 2010-11-15 11:30:01 -0600 | [diff] [blame] | 1328 | _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) |
Yong Shen | 0d7671e | 2011-01-07 12:25:33 +0800 | [diff] [blame] | 1329 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 1330 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
Yong Shen | 410d3458 | 2011-01-07 12:25:34 +0800 | [diff] [blame] | 1331 | _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) |
| 1332 | _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) |
Yong Shen | b0a6ba5 | 2011-01-10 20:08:53 +0800 | [diff] [blame] | 1333 | _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) |
| 1334 | _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) |
| 1335 | _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1336 | }; |
| 1337 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1338 | static void clk_tree_init(void) |
| 1339 | { |
| 1340 | u32 reg; |
| 1341 | |
| 1342 | ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); |
| 1343 | |
| 1344 | /* |
| 1345 | * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at |
| 1346 | * 8MHz, its derived from lp_apm. |
| 1347 | * |
| 1348 | * FIXME: Verify if true for all boards |
| 1349 | */ |
| 1350 | reg = __raw_readl(MXC_CCM_CBCDR); |
| 1351 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; |
| 1352 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; |
| 1353 | reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; |
| 1354 | reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); |
| 1355 | __raw_writel(reg, MXC_CCM_CBCDR); |
| 1356 | } |
| 1357 | |
| 1358 | int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, |
| 1359 | unsigned long ckih1, unsigned long ckih2) |
| 1360 | { |
| 1361 | int i; |
| 1362 | |
| 1363 | external_low_reference = ckil; |
| 1364 | external_high_reference = ckih1; |
| 1365 | ckih2_reference = ckih2; |
| 1366 | oscillator_reference = osc; |
| 1367 | |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1368 | for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++) |
| 1369 | clkdev_add(&mx51_lookups[i]); |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1370 | |
| 1371 | clk_tree_init(); |
| 1372 | |
| 1373 | clk_enable(&cpu_clk); |
| 1374 | clk_enable(&main_bus_clk); |
| 1375 | |
Dinh Nguyen | 9ab4650 | 2010-11-15 11:30:01 -0600 | [diff] [blame] | 1376 | clk_enable(&iim_clk); |
| 1377 | mx51_revision(); |
| 1378 | clk_disable(&iim_clk); |
| 1379 | |
Arnaud Patard (Rtp) | 711669e | 2010-12-20 16:48:58 +0100 | [diff] [blame] | 1380 | /* move usb_phy_clk to 24MHz */ |
| 1381 | clk_set_parent(&usb_phy1_clk, &osc_clk); |
| 1382 | |
Dinh Nguyen | c79504e | 2010-05-10 13:45:58 -0500 | [diff] [blame] | 1383 | /* set the usboh3_clk parent to pll2_sw_clk */ |
| 1384 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); |
| 1385 | |
Eric Bénard | 6a001b8 | 2010-10-11 17:59:47 +0200 | [diff] [blame] | 1386 | /* Set SDHC parents to be PLL2 */ |
| 1387 | clk_set_parent(&esdhc1_clk, &pll2_sw_clk); |
| 1388 | clk_set_parent(&esdhc2_clk, &pll2_sw_clk); |
| 1389 | |
| 1390 | /* set SDHC root clock as 166.25MHZ*/ |
| 1391 | clk_set_rate(&esdhc1_clk, 166250000); |
| 1392 | clk_set_rate(&esdhc2_clk, 166250000); |
| 1393 | |
Amit Kucheria | a329b48 | 2010-02-04 12:21:53 -0800 | [diff] [blame] | 1394 | /* System timer */ |
| 1395 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
| 1396 | MX51_MXC_INT_GPT); |
| 1397 | return 0; |
| 1398 | } |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1399 | |
| 1400 | int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, |
| 1401 | unsigned long ckih1, unsigned long ckih2) |
| 1402 | { |
| 1403 | int i; |
| 1404 | |
| 1405 | external_low_reference = ckil; |
| 1406 | external_high_reference = ckih1; |
| 1407 | ckih2_reference = ckih2; |
| 1408 | oscillator_reference = osc; |
| 1409 | |
| 1410 | for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++) |
| 1411 | clkdev_add(&mx53_lookups[i]); |
| 1412 | |
| 1413 | clk_tree_init(); |
| 1414 | |
Yong Shen | 2cad26a | 2011-01-10 20:08:54 +0800 | [diff] [blame] | 1415 | clk_set_parent(&uart_root_clk, &pll3_sw_clk); |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1416 | clk_enable(&cpu_clk); |
| 1417 | clk_enable(&main_bus_clk); |
| 1418 | |
Dinh Nguyen | 9ab4650 | 2010-11-15 11:30:01 -0600 | [diff] [blame] | 1419 | clk_enable(&iim_clk); |
| 1420 | mx53_revision(); |
| 1421 | clk_disable(&iim_clk); |
| 1422 | |
Dinh Nguyen | c0abefd | 2010-11-15 11:29:59 -0600 | [diff] [blame] | 1423 | /* System timer */ |
| 1424 | mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), |
| 1425 | MX53_INT_GPT); |
| 1426 | return 0; |
| 1427 | } |