Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 20 | #include <linux/kthread.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 21 | #include "msm_drv.h" |
Rob Clark | edcd60c | 2016-03-16 12:56:12 -0400 | [diff] [blame] | 22 | #include "msm_debugfs.h" |
Rob Clark | fde5de6 | 2016-03-15 15:35:08 -0400 | [diff] [blame] | 23 | #include "msm_fence.h" |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 24 | #include "msm_gpu.h" |
Rob Clark | dd2da6e | 2013-11-30 16:12:10 -0500 | [diff] [blame] | 25 | #include "msm_kms.h" |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 26 | #include "sde_wb.h" |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 27 | |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 28 | /* |
| 29 | * MSM driver version: |
| 30 | * - 1.0.0 - initial interface |
| 31 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers |
Rob Clark | 7a3bcc0 | 2016-09-16 18:37:44 -0400 | [diff] [blame] | 32 | * - 1.2.0 - adds explicit fence support for submit ioctl |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 33 | */ |
| 34 | #define MSM_VERSION_MAJOR 1 |
Rob Clark | 7a3bcc0 | 2016-09-16 18:37:44 -0400 | [diff] [blame] | 35 | #define MSM_VERSION_MINOR 2 |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 36 | #define MSM_VERSION_PATCHLEVEL 0 |
| 37 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 38 | #define TEARDOWN_DEADLOCK_RETRY_MAX 5 |
| 39 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 40 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
| 41 | { |
| 42 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 43 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 44 | if (priv->fbdev) |
| 45 | drm_fb_helper_hotplug_event(priv->fbdev); |
| 46 | } |
| 47 | |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 48 | int msm_atomic_check(struct drm_device *dev, |
| 49 | struct drm_atomic_state *state) |
| 50 | { |
| 51 | if (msm_is_suspend_blocked(dev)) { |
| 52 | DRM_DEBUG("rejecting commit during suspend\n"); |
| 53 | return -EBUSY; |
| 54 | } |
| 55 | return drm_atomic_helper_check(dev, state); |
| 56 | } |
| 57 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 58 | static const struct drm_mode_config_funcs mode_config_funcs = { |
| 59 | .fb_create = msm_framebuffer_create, |
| 60 | .output_poll_changed = msm_fb_output_poll_changed, |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 61 | .atomic_check = msm_atomic_check, |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 62 | .atomic_commit = msm_atomic_commit, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 63 | }; |
| 64 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 65 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 66 | { |
| 67 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 68 | int idx = priv->num_mmus++; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 69 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 70 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 71 | return -EINVAL; |
| 72 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 73 | priv->mmus[idx] = mmu; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 74 | |
| 75 | return idx; |
| 76 | } |
| 77 | |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 78 | void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
| 79 | { |
| 80 | struct msm_drm_private *priv = dev->dev_private; |
| 81 | int idx; |
| 82 | |
| 83 | if (priv->num_mmus <= 0) { |
| 84 | dev_err(dev->dev, "invalid num mmus %d\n", priv->num_mmus); |
| 85 | return; |
| 86 | } |
| 87 | |
| 88 | idx = priv->num_mmus - 1; |
| 89 | |
| 90 | /* only support reverse-order deallocation */ |
| 91 | if (priv->mmus[idx] != mmu) { |
| 92 | dev_err(dev->dev, "unexpected mmu at idx %d\n", idx); |
| 93 | return; |
| 94 | } |
| 95 | |
| 96 | --priv->num_mmus; |
| 97 | priv->mmus[idx] = 0; |
| 98 | } |
| 99 | |
| 100 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 101 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
| 102 | static bool reglog = false; |
| 103 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); |
| 104 | module_param(reglog, bool, 0600); |
| 105 | #else |
| 106 | #define reglog 0 |
| 107 | #endif |
| 108 | |
Archit Taneja | a9ee34b | 2015-07-13 12:12:07 +0530 | [diff] [blame] | 109 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Rob Clark | e90dfec | 2015-01-30 17:05:41 -0500 | [diff] [blame] | 110 | static bool fbdev = true; |
| 111 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); |
| 112 | module_param(fbdev, bool, 0600); |
| 113 | #endif |
| 114 | |
Rob Clark | 3a10ba8 | 2014-09-08 14:24:57 -0400 | [diff] [blame] | 115 | static char *vram = "16m"; |
Rob Clark | 4313c74 | 2016-02-03 14:02:04 -0500 | [diff] [blame] | 116 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 117 | module_param(vram, charp, 0); |
| 118 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 119 | /* |
| 120 | * Util/helpers: |
| 121 | */ |
| 122 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 123 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 124 | const char *dbgname) |
| 125 | { |
| 126 | struct resource *res; |
| 127 | unsigned long size; |
| 128 | void __iomem *ptr; |
| 129 | |
| 130 | if (name) |
| 131 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); |
| 132 | else |
| 133 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 134 | |
| 135 | if (!res) { |
| 136 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); |
| 137 | return ERR_PTR(-EINVAL); |
| 138 | } |
| 139 | |
| 140 | size = resource_size(res); |
| 141 | |
| 142 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); |
| 143 | if (!ptr) { |
| 144 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); |
| 145 | return ERR_PTR(-ENOMEM); |
| 146 | } |
| 147 | |
| 148 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 149 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 150 | |
| 151 | return ptr; |
| 152 | } |
| 153 | |
Lloyd Atkinson | 1a0c917 | 2016-10-04 10:01:24 -0400 | [diff] [blame] | 154 | void msm_iounmap(struct platform_device *pdev, void __iomem *addr) |
| 155 | { |
| 156 | devm_iounmap(&pdev->dev, addr); |
| 157 | } |
| 158 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 159 | void msm_writel(u32 data, void __iomem *addr) |
| 160 | { |
| 161 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 162 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 163 | writel(data, addr); |
| 164 | } |
| 165 | |
| 166 | u32 msm_readl(const void __iomem *addr) |
| 167 | { |
| 168 | u32 val = readl(addr); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 169 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 170 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 171 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 172 | return val; |
| 173 | } |
| 174 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 175 | struct vblank_event { |
| 176 | struct list_head node; |
| 177 | int crtc_id; |
| 178 | bool enable; |
| 179 | }; |
| 180 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 181 | static void vblank_ctrl_worker(struct kthread_work *work) |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 182 | { |
| 183 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, |
| 184 | struct msm_vblank_ctrl, work); |
| 185 | struct msm_drm_private *priv = container_of(vbl_ctrl, |
| 186 | struct msm_drm_private, vblank_ctrl); |
| 187 | struct msm_kms *kms = priv->kms; |
| 188 | struct vblank_event *vbl_ev, *tmp; |
| 189 | unsigned long flags; |
| 190 | |
| 191 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 192 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { |
| 193 | list_del(&vbl_ev->node); |
| 194 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 195 | |
| 196 | if (vbl_ev->enable) |
| 197 | kms->funcs->enable_vblank(kms, |
| 198 | priv->crtcs[vbl_ev->crtc_id]); |
| 199 | else |
| 200 | kms->funcs->disable_vblank(kms, |
| 201 | priv->crtcs[vbl_ev->crtc_id]); |
| 202 | |
| 203 | kfree(vbl_ev); |
| 204 | |
| 205 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 206 | } |
| 207 | |
| 208 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 209 | } |
| 210 | |
| 211 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, |
| 212 | int crtc_id, bool enable) |
| 213 | { |
| 214 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
| 215 | struct vblank_event *vbl_ev; |
| 216 | unsigned long flags; |
| 217 | |
| 218 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); |
| 219 | if (!vbl_ev) |
| 220 | return -ENOMEM; |
| 221 | |
| 222 | vbl_ev->crtc_id = crtc_id; |
| 223 | vbl_ev->enable = enable; |
| 224 | |
| 225 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 226 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); |
| 227 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 228 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 229 | kthread_queue_work(&priv->disp_thread[crtc_id].worker, &vbl_ctrl->work); |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 234 | static int msm_drm_uninit(struct device *dev) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 235 | { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 236 | struct platform_device *pdev = to_platform_device(dev); |
| 237 | struct drm_device *ddev = platform_get_drvdata(pdev); |
| 238 | struct msm_drm_private *priv = ddev->dev_private; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 239 | struct msm_kms *kms = priv->kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 240 | struct msm_gpu *gpu = priv->gpu; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 241 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
| 242 | struct vblank_event *vbl_ev, *tmp; |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 243 | int i; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 244 | |
| 245 | /* We must cancel and cleanup any pending vblank enable/disable |
| 246 | * work before drm_irq_uninstall() to avoid work re-enabling an |
| 247 | * irq after uninstall has disabled it. |
| 248 | */ |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 249 | kthread_flush_work(&vbl_ctrl->work); |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 250 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { |
| 251 | list_del(&vbl_ev->node); |
| 252 | kfree(vbl_ev); |
| 253 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 254 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 255 | /* clean up display commit worker threads */ |
| 256 | for (i = 0; i < priv->num_crtcs; i++) { |
| 257 | if (priv->disp_thread[i].thread) { |
| 258 | kthread_flush_worker(&priv->disp_thread[i].worker); |
| 259 | kthread_stop(priv->disp_thread[i].thread); |
| 260 | priv->disp_thread[i].thread = NULL; |
| 261 | } |
| 262 | } |
| 263 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 264 | msm_gem_shrinker_cleanup(ddev); |
| 265 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 266 | drm_kms_helper_poll_fini(ddev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 267 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 268 | drm_mode_config_cleanup(ddev); |
| 269 | drm_vblank_cleanup(ddev); |
| 270 | |
Lloyd Atkinson | ab3dd30 | 2017-02-13 10:44:55 -0800 | [diff] [blame] | 271 | if (priv->registered) { |
| 272 | drm_dev_unregister(ddev); |
| 273 | priv->registered = false; |
| 274 | } |
Archit Taneja | 8208ed9 | 2016-05-02 11:05:53 +0530 | [diff] [blame] | 275 | |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 276 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 277 | if (fbdev && priv->fbdev) |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 278 | msm_fbdev_free(ddev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 279 | #endif |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 280 | drm_mode_config_cleanup(ddev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 281 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 282 | pm_runtime_get_sync(dev); |
| 283 | drm_irq_uninstall(ddev); |
| 284 | pm_runtime_put_sync(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 285 | |
| 286 | flush_workqueue(priv->wq); |
| 287 | destroy_workqueue(priv->wq); |
| 288 | |
Archit Taneja | 1697608 | 2016-11-03 17:36:18 +0530 | [diff] [blame] | 289 | if (kms && kms->funcs) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 290 | kms->funcs->destroy(kms); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 291 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 292 | if (gpu) { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 293 | mutex_lock(&ddev->struct_mutex); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 294 | gpu->funcs->pm_suspend(gpu); |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 295 | mutex_unlock(&ddev->struct_mutex); |
Rob Clark | 774449e | 2015-05-15 09:19:36 -0400 | [diff] [blame] | 296 | gpu->funcs->destroy(gpu); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 297 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 298 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 299 | if (priv->vram.paddr) { |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 300 | unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 301 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 302 | drm_mm_takedown(&priv->vram.mm); |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 303 | dma_free_attrs(dev, priv->vram.size, NULL, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 304 | priv->vram.paddr, attrs); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 305 | } |
| 306 | |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 307 | sde_dbg_destroy(); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 308 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 309 | sde_power_client_destroy(&priv->phandle, priv->pclient); |
| 310 | sde_power_resource_deinit(pdev, &priv->phandle); |
| 311 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 312 | component_unbind_all(dev, ddev); |
| 313 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 314 | sde_power_resource_deinit(pdev, &priv->phandle); |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 315 | |
Archit Taneja | 0a6030d | 2016-05-08 21:36:28 +0530 | [diff] [blame] | 316 | msm_mdss_destroy(ddev); |
| 317 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 318 | ddev->dev_private = NULL; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 319 | kfree(priv); |
| 320 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 321 | drm_dev_unref(ddev); |
| 322 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 323 | return 0; |
| 324 | } |
| 325 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 326 | #define KMS_MDP4 4 |
| 327 | #define KMS_MDP5 5 |
| 328 | #define KMS_SDE 3 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 329 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 330 | static int get_mdp_ver(struct platform_device *pdev) |
| 331 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 332 | #ifdef CONFIG_OF |
| 333 | static const struct of_device_id match_types[] = { { |
| 334 | .compatible = "qcom,mdss_mdp", |
| 335 | .data = (void *)KMS_MDP5, |
| 336 | }, |
| 337 | { |
| 338 | .compatible = "qcom,sde-kms", |
| 339 | .data = (void *)KMS_SDE, |
| 340 | /* end node */ |
| 341 | } }; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 342 | struct device *dev = &pdev->dev; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 343 | const struct of_device_id *match; |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 344 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 345 | match = of_match_node(match_types, dev->of_node); |
| 346 | if (match) |
| 347 | return (int)(unsigned long)match->data; |
| 348 | #endif |
| 349 | return KMS_MDP4; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 350 | } |
| 351 | |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 352 | static int msm_init_vram(struct drm_device *dev) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 353 | { |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 354 | struct msm_drm_private *priv = dev->dev_private; |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 355 | struct device_node *node; |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 356 | unsigned long size = 0; |
| 357 | int ret = 0; |
| 358 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 359 | /* In the device-tree world, we could have a 'memory-region' |
| 360 | * phandle, which gives us a link to our "vram". Allocating |
| 361 | * is all nicely abstracted behind the dma api, but we need |
| 362 | * to know the entire size to allocate it all in one go. There |
| 363 | * are two cases: |
| 364 | * 1) device with no IOMMU, in which case we need exclusive |
| 365 | * access to a VRAM carveout big enough for all gpu |
| 366 | * buffers |
| 367 | * 2) device with IOMMU, but where the bootloader puts up |
| 368 | * a splash screen. In this case, the VRAM carveout |
| 369 | * need only be large enough for fbdev fb. But we need |
| 370 | * exclusive access to the buffer to avoid the kernel |
| 371 | * using those pages for other purposes (which appears |
| 372 | * as corruption on screen before we have a chance to |
| 373 | * load and do initial modeset) |
| 374 | */ |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 375 | |
| 376 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); |
| 377 | if (node) { |
| 378 | struct resource r; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 379 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 380 | ret = of_address_to_resource(node, 0, &r); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 381 | |
Peter Chen | 2ca41c17 | 2016-07-04 16:49:50 +0800 | [diff] [blame] | 382 | of_node_put(node); |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 383 | if (ret) |
| 384 | return ret; |
| 385 | size = r.end - r.start; |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 386 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 387 | |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 388 | /* if we have no IOMMU, then we need to use carveout allocator. |
| 389 | * Grab the entire CMA chunk carved out in early startup in |
| 390 | * mach-msm: |
| 391 | */ |
| 392 | } else if (!iommu_present(&platform_bus_type)) { |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 393 | DRM_INFO("using %s VRAM carveout\n", vram); |
| 394 | size = memparse(vram, NULL); |
| 395 | } |
| 396 | |
| 397 | if (size) { |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 398 | unsigned long attrs = 0; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 399 | void *p; |
| 400 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 401 | priv->vram.size = size; |
| 402 | |
| 403 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); |
| 404 | |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 405 | attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
| 406 | attrs |= DMA_ATTR_WRITE_COMBINE; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 407 | |
| 408 | /* note that for no-kernel-mapping, the vaddr returned |
| 409 | * is bogus, but non-null if allocation succeeded: |
| 410 | */ |
| 411 | p = dma_alloc_attrs(dev->dev, size, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 412 | &priv->vram.paddr, GFP_KERNEL, attrs); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 413 | if (!p) { |
| 414 | dev_err(dev->dev, "failed to allocate VRAM\n"); |
| 415 | priv->vram.paddr = 0; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 416 | return -ENOMEM; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 417 | } |
| 418 | |
| 419 | dev_info(dev->dev, "VRAM: %08x->%08x\n", |
| 420 | (uint32_t)priv->vram.paddr, |
| 421 | (uint32_t)(priv->vram.paddr + size)); |
| 422 | } |
| 423 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 424 | return ret; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 425 | } |
| 426 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 427 | #ifdef CONFIG_OF |
| 428 | static int msm_component_bind_all(struct device *dev, |
| 429 | struct drm_device *drm_dev) |
| 430 | { |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 431 | int ret; |
| 432 | |
| 433 | ret = component_bind_all(dev, drm_dev); |
| 434 | if (ret) |
| 435 | DRM_ERROR("component_bind_all failed: %d\n", ret); |
| 436 | |
| 437 | return ret; |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 438 | } |
| 439 | #else |
| 440 | static int msm_component_bind_all(struct device *dev, |
| 441 | struct drm_device *drm_dev) |
| 442 | { |
| 443 | return 0; |
| 444 | } |
| 445 | #endif |
| 446 | |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 447 | static int msm_power_enable_wrapper(void *handle, void *client, bool enable) |
| 448 | { |
| 449 | return sde_power_resource_enable(handle, client, enable); |
| 450 | } |
| 451 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 452 | static int msm_drm_init(struct device *dev, struct drm_driver *drv) |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 453 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 454 | struct platform_device *pdev = to_platform_device(dev); |
| 455 | struct drm_device *ddev; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 456 | struct msm_drm_private *priv; |
| 457 | struct msm_kms *kms; |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 458 | struct sde_dbg_power_ctrl dbg_power_ctrl = { 0 }; |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 459 | int ret, i; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 460 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 461 | ddev = drm_dev_alloc(drv, dev); |
| 462 | if (!ddev) { |
| 463 | dev_err(dev, "failed to allocate drm_device\n"); |
| 464 | return -ENOMEM; |
| 465 | } |
| 466 | |
| 467 | drm_mode_config_init(ddev); |
| 468 | platform_set_drvdata(pdev, ddev); |
| 469 | ddev->platformdev = pdev; |
| 470 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 471 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 472 | if (!priv) { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 473 | ret = -ENOMEM; |
| 474 | goto priv_alloc_fail; |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 475 | } |
| 476 | |
| 477 | ddev->dev_private = priv; |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 478 | priv->dev = ddev; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 479 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 480 | ret = msm_mdss_init(ddev); |
| 481 | if (ret) |
| 482 | goto mdss_init_fail; |
| 483 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 484 | priv->wq = alloc_ordered_workqueue("msm_drm", 0); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 485 | init_waitqueue_head(&priv->pending_crtcs_event); |
| 486 | |
| 487 | INIT_LIST_HEAD(&priv->client_event_list); |
| 488 | INIT_LIST_HEAD(&priv->inactive_list); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 489 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 490 | kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 491 | spin_lock_init(&priv->vblank_ctrl.lock); |
| 492 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 493 | ret = sde_power_resource_init(pdev, &priv->phandle); |
| 494 | if (ret) { |
| 495 | pr_err("sde power resource init failed\n"); |
| 496 | goto fail; |
| 497 | } |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 498 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 499 | priv->pclient = sde_power_client_create(&priv->phandle, "sde"); |
| 500 | if (IS_ERR_OR_NULL(priv->pclient)) { |
| 501 | pr_err("sde power client create failed\n"); |
| 502 | ret = -EINVAL; |
| 503 | goto fail; |
| 504 | } |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 505 | |
| 506 | /* Bind all our sub-components: */ |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 507 | ret = msm_component_bind_all(dev, ddev); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 508 | if (ret) |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 509 | return ret; |
| 510 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 511 | ret = msm_init_vram(ddev); |
Rob Clark | 13f1556 | 2015-05-07 15:20:13 -0400 | [diff] [blame] | 512 | if (ret) |
| 513 | goto fail; |
| 514 | |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 515 | dbg_power_ctrl.handle = &priv->phandle; |
| 516 | dbg_power_ctrl.client = priv->pclient; |
| 517 | dbg_power_ctrl.enable_fn = msm_power_enable_wrapper; |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 518 | ret = sde_dbg_init(&pdev->dev, &dbg_power_ctrl); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 519 | if (ret) { |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 520 | dev_err(dev, "failed to init sde dbg: %d\n", ret); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 521 | goto fail; |
| 522 | } |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 523 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 524 | switch (get_mdp_ver(pdev)) { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 525 | case KMS_MDP4: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 526 | kms = mdp4_kms_init(ddev); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 527 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 528 | case KMS_MDP5: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 529 | kms = mdp5_kms_init(ddev); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 530 | break; |
| 531 | case KMS_SDE: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 532 | kms = sde_kms_init(ddev); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 533 | break; |
| 534 | default: |
| 535 | kms = ERR_PTR(-ENODEV); |
| 536 | break; |
| 537 | } |
| 538 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 539 | if (IS_ERR(kms)) { |
| 540 | /* |
| 541 | * NOTE: once we have GPU support, having no kms should not |
| 542 | * be considered fatal.. ideally we would still support gpu |
| 543 | * and (for example) use dmabuf/prime to share buffers with |
| 544 | * imx drm driver on iMX5 |
| 545 | */ |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 546 | priv->kms = NULL; |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 547 | dev_err(dev, "failed to load kms\n"); |
Thomas Meyer | e4826a9 | 2013-09-16 23:19:54 +0200 | [diff] [blame] | 548 | ret = PTR_ERR(kms); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 549 | goto fail; |
| 550 | } |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 551 | priv->kms = kms; |
| 552 | pm_runtime_enable(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 553 | |
Alan Kwong | 2994628 | 2017-02-01 21:55:56 -0800 | [diff] [blame] | 554 | if (kms) { |
| 555 | ret = kms->funcs->hw_init(kms); |
| 556 | if (ret) { |
| 557 | dev_err(dev, "kms hw init failed: %d\n", ret); |
| 558 | goto fail; |
| 559 | } |
| 560 | } |
| 561 | ddev->mode_config.funcs = &mode_config_funcs; |
| 562 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 563 | for (i = 0; i < priv->num_crtcs; i++) { |
| 564 | priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id; |
| 565 | kthread_init_worker(&priv->disp_thread[i].worker); |
| 566 | priv->disp_thread[i].dev = ddev; |
| 567 | priv->disp_thread[i].thread = |
| 568 | kthread_run(kthread_worker_fn, |
| 569 | &priv->disp_thread[i].worker, |
| 570 | "crtc_commit:%d", |
| 571 | priv->disp_thread[i].crtc_id); |
| 572 | |
| 573 | if (IS_ERR(priv->disp_thread[i].thread)) { |
| 574 | dev_err(dev, "failed to create kthread\n"); |
| 575 | priv->disp_thread[i].thread = NULL; |
| 576 | /* clean up previously created threads if any */ |
| 577 | for (i -= 1; i >= 0; i--) { |
| 578 | kthread_stop(priv->disp_thread[i].thread); |
| 579 | priv->disp_thread[i].thread = NULL; |
| 580 | } |
| 581 | goto fail; |
| 582 | } |
| 583 | } |
| 584 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 585 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 586 | if (ret < 0) { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 587 | dev_err(dev, "failed to initialize vblank\n"); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 588 | goto fail; |
| 589 | } |
| 590 | |
Archit Taneja | a2b3a55 | 2016-05-18 15:06:03 +0530 | [diff] [blame] | 591 | if (kms) { |
| 592 | pm_runtime_get_sync(dev); |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 593 | ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); |
Archit Taneja | a2b3a55 | 2016-05-18 15:06:03 +0530 | [diff] [blame] | 594 | pm_runtime_put_sync(dev); |
| 595 | if (ret < 0) { |
| 596 | dev_err(dev, "failed to install IRQ handler\n"); |
| 597 | goto fail; |
| 598 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 599 | } |
| 600 | |
Lloyd Atkinson | ab3dd30 | 2017-02-13 10:44:55 -0800 | [diff] [blame] | 601 | ret = drm_dev_register(ddev, 0); |
| 602 | if (ret) |
| 603 | goto fail; |
| 604 | priv->registered = true; |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 605 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 606 | drm_mode_config_reset(ddev); |
| 607 | |
| 608 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 609 | if (fbdev) |
| 610 | priv->fbdev = msm_fbdev_init(ddev); |
| 611 | #endif |
| 612 | |
| 613 | ret = msm_debugfs_late_init(ddev); |
| 614 | if (ret) |
| 615 | goto fail; |
| 616 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 617 | ret = sde_dbg_debugfs_register(ddev->primary->debugfs_root); |
| 618 | if (ret) { |
| 619 | dev_err(dev, "failed to reg sde dbg debugfs: %d\n", ret); |
| 620 | goto fail; |
| 621 | } |
| 622 | |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 623 | /* perform subdriver post initialization */ |
| 624 | if (kms && kms->funcs && kms->funcs->postinit) { |
| 625 | ret = kms->funcs->postinit(kms); |
| 626 | if (ret) { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 627 | pr_err("kms post init failed: %d\n", ret); |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 628 | goto fail; |
| 629 | } |
| 630 | } |
| 631 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 632 | drm_kms_helper_poll_init(ddev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 633 | |
| 634 | return 0; |
| 635 | |
| 636 | fail: |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 637 | msm_drm_uninit(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 638 | return ret; |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 639 | mdss_init_fail: |
| 640 | kfree(priv); |
| 641 | priv_alloc_fail: |
| 642 | drm_dev_unref(ddev); |
| 643 | return ret; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 644 | } |
| 645 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 646 | /* |
| 647 | * DRM operations: |
| 648 | */ |
| 649 | |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 650 | #ifdef CONFIG_QCOM_KGSL |
| 651 | static void load_gpu(struct drm_device *dev) |
| 652 | { |
| 653 | } |
| 654 | #else |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 655 | static void load_gpu(struct drm_device *dev) |
| 656 | { |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 657 | static DEFINE_MUTEX(init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 658 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 659 | |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 660 | mutex_lock(&init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 661 | |
Rob Clark | e2550b7 | 2014-09-05 13:30:27 -0400 | [diff] [blame] | 662 | if (!priv->gpu) |
| 663 | priv->gpu = adreno_load_gpu(dev); |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 664 | |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 665 | mutex_unlock(&init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 666 | } |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 667 | #endif |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 668 | |
| 669 | static int msm_open(struct drm_device *dev, struct drm_file *file) |
| 670 | { |
| 671 | struct msm_file_private *ctx; |
| 672 | |
| 673 | /* For now, load gpu on open.. to avoid the requirement of having |
| 674 | * firmware in the initrd. |
| 675 | */ |
| 676 | load_gpu(dev); |
| 677 | |
| 678 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
| 679 | if (!ctx) |
| 680 | return -ENOMEM; |
| 681 | |
| 682 | file->driver_priv = ctx; |
| 683 | |
Clarence Ip | 0e19a5d | 2016-08-10 16:36:50 -0400 | [diff] [blame] | 684 | if (dev && dev->dev_private) { |
| 685 | struct msm_drm_private *priv = dev->dev_private; |
| 686 | struct msm_kms *kms; |
| 687 | |
| 688 | kms = priv->kms; |
| 689 | if (kms && kms->funcs && kms->funcs->postopen) |
| 690 | kms->funcs->postopen(kms, file); |
| 691 | } |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 692 | return 0; |
| 693 | } |
| 694 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 695 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
| 696 | { |
| 697 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 698 | struct msm_kms *kms = priv->kms; |
| 699 | |
| 700 | if (kms && kms->funcs && kms->funcs->preclose) |
| 701 | kms->funcs->preclose(kms, file); |
| 702 | } |
| 703 | |
| 704 | static void msm_postclose(struct drm_device *dev, struct drm_file *file) |
| 705 | { |
| 706 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 707 | struct msm_file_private *ctx = file->driver_priv; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 708 | struct msm_kms *kms = priv->kms; |
| 709 | |
| 710 | if (kms && kms->funcs && kms->funcs->postclose) |
| 711 | kms->funcs->postclose(kms, file); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 712 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 713 | mutex_lock(&dev->struct_mutex); |
| 714 | if (ctx == priv->lastctx) |
| 715 | priv->lastctx = NULL; |
| 716 | mutex_unlock(&dev->struct_mutex); |
| 717 | |
| 718 | kfree(ctx); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 719 | } |
| 720 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 721 | static int msm_disable_all_modes_commit( |
| 722 | struct drm_device *dev, |
| 723 | struct drm_atomic_state *state) |
| 724 | { |
| 725 | struct drm_plane *plane; |
| 726 | struct drm_crtc *crtc; |
| 727 | unsigned int plane_mask; |
| 728 | int ret; |
| 729 | |
| 730 | plane_mask = 0; |
| 731 | drm_for_each_plane(plane, dev) { |
| 732 | struct drm_plane_state *plane_state; |
| 733 | |
| 734 | plane_state = drm_atomic_get_plane_state(state, plane); |
| 735 | if (IS_ERR(plane_state)) { |
| 736 | ret = PTR_ERR(plane_state); |
| 737 | goto fail; |
| 738 | } |
| 739 | |
Alan Kwong | 76c9d18 | 2016-12-14 14:39:17 -0800 | [diff] [blame] | 740 | plane_state->rotation = 0; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 741 | |
| 742 | plane->old_fb = plane->fb; |
| 743 | plane_mask |= 1 << drm_plane_index(plane); |
| 744 | |
| 745 | /* disable non-primary: */ |
| 746 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
| 747 | continue; |
| 748 | |
| 749 | DRM_DEBUG("disabling plane %d\n", plane->base.id); |
| 750 | |
| 751 | ret = __drm_atomic_helper_disable_plane(plane, plane_state); |
| 752 | if (ret != 0) |
| 753 | DRM_ERROR("error %d disabling plane %d\n", ret, |
| 754 | plane->base.id); |
| 755 | } |
| 756 | |
| 757 | drm_for_each_crtc(crtc, dev) { |
| 758 | struct drm_mode_set mode_set; |
| 759 | |
| 760 | memset(&mode_set, 0, sizeof(struct drm_mode_set)); |
| 761 | mode_set.crtc = crtc; |
| 762 | |
| 763 | DRM_DEBUG("disabling crtc %d\n", crtc->base.id); |
| 764 | |
| 765 | ret = __drm_atomic_helper_set_config(&mode_set, state); |
| 766 | if (ret != 0) |
| 767 | DRM_ERROR("error %d disabling crtc %d\n", ret, |
| 768 | crtc->base.id); |
| 769 | } |
| 770 | |
| 771 | DRM_DEBUG("committing disables\n"); |
| 772 | ret = drm_atomic_commit(state); |
| 773 | |
| 774 | fail: |
| 775 | drm_atomic_clean_old_fb(dev, plane_mask, ret); |
| 776 | DRM_DEBUG("disables result %d\n", ret); |
| 777 | return ret; |
| 778 | } |
| 779 | |
| 780 | /** |
| 781 | * msm_clear_all_modes - disables all planes and crtcs via an atomic commit |
| 782 | * based on restore_fbdev_mode_atomic in drm_fb_helper.c |
| 783 | * @dev: device pointer |
| 784 | * @Return: 0 on success, otherwise -error |
| 785 | */ |
| 786 | static int msm_disable_all_modes(struct drm_device *dev) |
| 787 | { |
| 788 | struct drm_atomic_state *state; |
| 789 | int ret, i; |
| 790 | |
| 791 | state = drm_atomic_state_alloc(dev); |
| 792 | if (!state) |
| 793 | return -ENOMEM; |
| 794 | |
| 795 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
| 796 | |
| 797 | for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) { |
| 798 | ret = msm_disable_all_modes_commit(dev, state); |
| 799 | if (ret != -EDEADLK) |
| 800 | break; |
| 801 | drm_atomic_state_clear(state); |
| 802 | drm_atomic_legacy_backoff(state); |
| 803 | } |
| 804 | |
| 805 | /* on successful atomic commit state ownership transfers to framework */ |
| 806 | if (ret != 0) |
| 807 | drm_atomic_state_free(state); |
| 808 | |
| 809 | return ret; |
| 810 | } |
| 811 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 812 | static void msm_lastclose(struct drm_device *dev) |
| 813 | { |
| 814 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 815 | struct msm_kms *kms = priv->kms; |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 816 | int i; |
| 817 | |
| 818 | /* |
| 819 | * clean up vblank disable immediately as this is the last close. |
| 820 | */ |
| 821 | for (i = 0; i < dev->num_crtcs; i++) { |
| 822 | struct drm_vblank_crtc *vblank = &dev->vblank[i]; |
| 823 | struct timer_list *disable_timer = &vblank->disable_timer; |
| 824 | |
| 825 | if (del_timer_sync(disable_timer)) |
| 826 | disable_timer->function(disable_timer->data); |
| 827 | } |
| 828 | |
| 829 | /* wait for pending vblank requests to be executed by worker thread */ |
| 830 | flush_workqueue(priv->wq); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 831 | |
| 832 | if (priv->fbdev) { |
Rob Clark | 5ea1f75 | 2014-05-30 12:29:48 -0400 | [diff] [blame] | 833 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 834 | } else { |
| 835 | drm_modeset_lock_all(dev); |
| 836 | msm_disable_all_modes(dev); |
| 837 | drm_modeset_unlock_all(dev); |
| 838 | if (kms && kms->funcs && kms->funcs->lastclose) |
| 839 | kms->funcs->lastclose(kms); |
| 840 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 841 | } |
| 842 | |
Daniel Vetter | e9f0d76 | 2013-12-11 11:34:42 +0100 | [diff] [blame] | 843 | static irqreturn_t msm_irq(int irq, void *arg) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 844 | { |
| 845 | struct drm_device *dev = arg; |
| 846 | struct msm_drm_private *priv = dev->dev_private; |
| 847 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 848 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 849 | BUG_ON(!kms); |
| 850 | return kms->funcs->irq(kms); |
| 851 | } |
| 852 | |
| 853 | static void msm_irq_preinstall(struct drm_device *dev) |
| 854 | { |
| 855 | struct msm_drm_private *priv = dev->dev_private; |
| 856 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 857 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 858 | BUG_ON(!kms); |
| 859 | kms->funcs->irq_preinstall(kms); |
| 860 | } |
| 861 | |
| 862 | static int msm_irq_postinstall(struct drm_device *dev) |
| 863 | { |
| 864 | struct msm_drm_private *priv = dev->dev_private; |
| 865 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 866 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 867 | BUG_ON(!kms); |
| 868 | return kms->funcs->irq_postinstall(kms); |
| 869 | } |
| 870 | |
| 871 | static void msm_irq_uninstall(struct drm_device *dev) |
| 872 | { |
| 873 | struct msm_drm_private *priv = dev->dev_private; |
| 874 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 875 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 876 | BUG_ON(!kms); |
| 877 | kms->funcs->irq_uninstall(kms); |
| 878 | } |
| 879 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 880 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 881 | { |
| 882 | struct msm_drm_private *priv = dev->dev_private; |
| 883 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 884 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 885 | if (!kms) |
| 886 | return -ENXIO; |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 887 | DBG("dev=%p, crtc=%u", dev, pipe); |
| 888 | return vblank_ctrl_queue_work(priv, pipe, true); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 889 | } |
| 890 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 891 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 892 | { |
| 893 | struct msm_drm_private *priv = dev->dev_private; |
| 894 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 895 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 896 | if (!kms) |
| 897 | return; |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 898 | DBG("dev=%p, crtc=%u", dev, pipe); |
| 899 | vblank_ctrl_queue_work(priv, pipe, false); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 900 | } |
| 901 | |
| 902 | /* |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 903 | * DRM ioctls: |
| 904 | */ |
| 905 | |
| 906 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, |
| 907 | struct drm_file *file) |
| 908 | { |
| 909 | struct msm_drm_private *priv = dev->dev_private; |
| 910 | struct drm_msm_param *args = data; |
| 911 | struct msm_gpu *gpu; |
| 912 | |
| 913 | /* for now, we just have 3d pipe.. eventually this would need to |
| 914 | * be more clever to dispatch to appropriate gpu module: |
| 915 | */ |
| 916 | if (args->pipe != MSM_PIPE_3D0) |
| 917 | return -EINVAL; |
| 918 | |
| 919 | gpu = priv->gpu; |
| 920 | |
| 921 | if (!gpu) |
| 922 | return -ENXIO; |
| 923 | |
| 924 | return gpu->funcs->get_param(gpu, args->param, &args->value); |
| 925 | } |
| 926 | |
| 927 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, |
| 928 | struct drm_file *file) |
| 929 | { |
| 930 | struct drm_msm_gem_new *args = data; |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 931 | |
| 932 | if (args->flags & ~MSM_BO_FLAGS) { |
| 933 | DRM_ERROR("invalid flags: %08x\n", args->flags); |
| 934 | return -EINVAL; |
| 935 | } |
| 936 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 937 | return msm_gem_new_handle(dev, file, args->size, |
| 938 | args->flags, &args->handle); |
| 939 | } |
| 940 | |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 941 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
| 942 | { |
| 943 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); |
| 944 | } |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 945 | |
| 946 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, |
| 947 | struct drm_file *file) |
| 948 | { |
| 949 | struct drm_msm_gem_cpu_prep *args = data; |
| 950 | struct drm_gem_object *obj; |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 951 | ktime_t timeout = to_ktime(args->timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 952 | int ret; |
| 953 | |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 954 | if (args->op & ~MSM_PREP_FLAGS) { |
| 955 | DRM_ERROR("invalid op: %08x\n", args->op); |
| 956 | return -EINVAL; |
| 957 | } |
| 958 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 959 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 960 | if (!obj) |
| 961 | return -ENOENT; |
| 962 | |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 963 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 964 | |
| 965 | drm_gem_object_unreference_unlocked(obj); |
| 966 | |
| 967 | return ret; |
| 968 | } |
| 969 | |
| 970 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, |
| 971 | struct drm_file *file) |
| 972 | { |
| 973 | struct drm_msm_gem_cpu_fini *args = data; |
| 974 | struct drm_gem_object *obj; |
| 975 | int ret; |
| 976 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 977 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 978 | if (!obj) |
| 979 | return -ENOENT; |
| 980 | |
| 981 | ret = msm_gem_cpu_fini(obj); |
| 982 | |
| 983 | drm_gem_object_unreference_unlocked(obj); |
| 984 | |
| 985 | return ret; |
| 986 | } |
| 987 | |
| 988 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, |
| 989 | struct drm_file *file) |
| 990 | { |
| 991 | struct drm_msm_gem_info *args = data; |
| 992 | struct drm_gem_object *obj; |
| 993 | int ret = 0; |
| 994 | |
| 995 | if (args->pad) |
| 996 | return -EINVAL; |
| 997 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 998 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 999 | if (!obj) |
| 1000 | return -ENOENT; |
| 1001 | |
| 1002 | args->offset = msm_gem_mmap_offset(obj); |
| 1003 | |
| 1004 | drm_gem_object_unreference_unlocked(obj); |
| 1005 | |
| 1006 | return ret; |
| 1007 | } |
| 1008 | |
| 1009 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, |
| 1010 | struct drm_file *file) |
| 1011 | { |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 1012 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1013 | struct drm_msm_wait_fence *args = data; |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 1014 | ktime_t timeout = to_ktime(args->timeout); |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 1015 | |
| 1016 | if (args->pad) { |
| 1017 | DRM_ERROR("invalid pad: %08x\n", args->pad); |
| 1018 | return -EINVAL; |
| 1019 | } |
| 1020 | |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 1021 | if (!priv->gpu) |
| 1022 | return 0; |
| 1023 | |
| 1024 | return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1025 | } |
| 1026 | |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 1027 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
| 1028 | struct drm_file *file) |
| 1029 | { |
| 1030 | struct drm_msm_gem_madvise *args = data; |
| 1031 | struct drm_gem_object *obj; |
| 1032 | int ret; |
| 1033 | |
| 1034 | switch (args->madv) { |
| 1035 | case MSM_MADV_DONTNEED: |
| 1036 | case MSM_MADV_WILLNEED: |
| 1037 | break; |
| 1038 | default: |
| 1039 | return -EINVAL; |
| 1040 | } |
| 1041 | |
| 1042 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1043 | if (ret) |
| 1044 | return ret; |
| 1045 | |
| 1046 | obj = drm_gem_object_lookup(file, args->handle); |
| 1047 | if (!obj) { |
| 1048 | ret = -ENOENT; |
| 1049 | goto unlock; |
| 1050 | } |
| 1051 | |
| 1052 | ret = msm_gem_madvise(obj, args->madv); |
| 1053 | if (ret >= 0) { |
| 1054 | args->retained = ret; |
| 1055 | ret = 0; |
| 1056 | } |
| 1057 | |
| 1058 | drm_gem_object_unreference(obj); |
| 1059 | |
| 1060 | unlock: |
| 1061 | mutex_unlock(&dev->struct_mutex); |
| 1062 | return ret; |
| 1063 | } |
| 1064 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1065 | static const struct drm_ioctl_desc msm_ioctls[] = { |
Daniel Vetter | f8c4714 | 2015-09-08 13:56:30 +0200 | [diff] [blame] | 1066 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1067 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1068 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1069 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1070 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1071 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1072 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 1073 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW), |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 1074 | DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH), |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1075 | }; |
| 1076 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1077 | static const struct vm_operations_struct vm_ops = { |
| 1078 | .fault = msm_gem_fault, |
| 1079 | .open = drm_gem_vm_open, |
| 1080 | .close = drm_gem_vm_close, |
| 1081 | }; |
| 1082 | |
| 1083 | static const struct file_operations fops = { |
| 1084 | .owner = THIS_MODULE, |
| 1085 | .open = drm_open, |
| 1086 | .release = drm_release, |
| 1087 | .unlocked_ioctl = drm_ioctl, |
| 1088 | #ifdef CONFIG_COMPAT |
| 1089 | .compat_ioctl = drm_compat_ioctl, |
| 1090 | #endif |
| 1091 | .poll = drm_poll, |
| 1092 | .read = drm_read, |
| 1093 | .llseek = no_llseek, |
| 1094 | .mmap = msm_gem_mmap, |
| 1095 | }; |
| 1096 | |
| 1097 | static struct drm_driver msm_driver = { |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1098 | .driver_features = DRIVER_HAVE_IRQ | |
| 1099 | DRIVER_GEM | |
| 1100 | DRIVER_PRIME | |
Rob Clark | b4b15c8 | 2013-09-28 12:01:25 -0400 | [diff] [blame] | 1101 | DRIVER_RENDER | |
Rob Clark | a5436e1 | 2015-06-04 10:12:22 -0400 | [diff] [blame] | 1102 | DRIVER_ATOMIC | |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1103 | DRIVER_MODESET, |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1104 | .open = msm_open, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1105 | .preclose = msm_preclose, |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 1106 | .postclose = msm_postclose, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1107 | .lastclose = msm_lastclose, |
| 1108 | .irq_handler = msm_irq, |
| 1109 | .irq_preinstall = msm_irq_preinstall, |
| 1110 | .irq_postinstall = msm_irq_postinstall, |
| 1111 | .irq_uninstall = msm_irq_uninstall, |
Ville Syrjälä | b44f840 | 2015-09-30 16:46:48 +0300 | [diff] [blame] | 1112 | .get_vblank_counter = drm_vblank_no_hw_counter, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1113 | .enable_vblank = msm_enable_vblank, |
| 1114 | .disable_vblank = msm_disable_vblank, |
| 1115 | .gem_free_object = msm_gem_free_object, |
| 1116 | .gem_vm_ops = &vm_ops, |
| 1117 | .dumb_create = msm_gem_dumb_create, |
| 1118 | .dumb_map_offset = msm_gem_dumb_map_offset, |
Rob Clark | 30600a909 | 2013-09-28 10:13:04 -0400 | [diff] [blame] | 1119 | .dumb_destroy = drm_gem_dumb_destroy, |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1120 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1121 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1122 | .gem_prime_export = drm_gem_prime_export, |
| 1123 | .gem_prime_import = drm_gem_prime_import, |
| 1124 | .gem_prime_pin = msm_gem_prime_pin, |
| 1125 | .gem_prime_unpin = msm_gem_prime_unpin, |
| 1126 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, |
| 1127 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, |
| 1128 | .gem_prime_vmap = msm_gem_prime_vmap, |
| 1129 | .gem_prime_vunmap = msm_gem_prime_vunmap, |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 1130 | .gem_prime_mmap = msm_gem_prime_mmap, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1131 | #ifdef CONFIG_DEBUG_FS |
| 1132 | .debugfs_init = msm_debugfs_init, |
| 1133 | .debugfs_cleanup = msm_debugfs_cleanup, |
| 1134 | #endif |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1135 | .ioctls = msm_ioctls, |
| 1136 | .num_ioctls = DRM_MSM_NUM_IOCTLS, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1137 | .fops = &fops, |
Stephane Viau | aa6ed8b | 2016-07-19 12:59:42 -0400 | [diff] [blame] | 1138 | .name = "msm_drm", |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1139 | .desc = "MSM Snapdragon DRM", |
| 1140 | .date = "20130625", |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 1141 | .major = MSM_VERSION_MAJOR, |
| 1142 | .minor = MSM_VERSION_MINOR, |
| 1143 | .patchlevel = MSM_VERSION_PATCHLEVEL, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1144 | }; |
| 1145 | |
| 1146 | #ifdef CONFIG_PM_SLEEP |
| 1147 | static int msm_pm_suspend(struct device *dev) |
| 1148 | { |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1149 | struct drm_device *ddev; |
| 1150 | struct drm_modeset_acquire_ctx ctx; |
| 1151 | struct drm_connector *conn; |
| 1152 | struct drm_atomic_state *state; |
| 1153 | struct drm_crtc_state *crtc_state; |
| 1154 | struct msm_drm_private *priv; |
| 1155 | int ret = 0; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1156 | |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1157 | if (!dev) |
| 1158 | return -EINVAL; |
| 1159 | |
| 1160 | ddev = dev_get_drvdata(dev); |
| 1161 | if (!ddev || !ddev->dev_private) |
| 1162 | return -EINVAL; |
| 1163 | |
| 1164 | priv = ddev->dev_private; |
| 1165 | SDE_EVT32(0); |
| 1166 | |
| 1167 | /* acquire modeset lock(s) */ |
| 1168 | drm_modeset_acquire_init(&ctx, 0); |
| 1169 | |
| 1170 | retry: |
| 1171 | ret = drm_modeset_lock_all_ctx(ddev, &ctx); |
| 1172 | if (ret) |
| 1173 | goto unlock; |
| 1174 | |
| 1175 | /* save current state for resume */ |
| 1176 | if (priv->suspend_state) |
| 1177 | drm_atomic_state_free(priv->suspend_state); |
| 1178 | priv->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx); |
| 1179 | if (IS_ERR_OR_NULL(priv->suspend_state)) { |
| 1180 | DRM_ERROR("failed to back up suspend state\n"); |
| 1181 | priv->suspend_state = NULL; |
| 1182 | goto unlock; |
| 1183 | } |
| 1184 | |
| 1185 | /* create atomic state to disable all CRTCs */ |
| 1186 | state = drm_atomic_state_alloc(ddev); |
| 1187 | if (IS_ERR_OR_NULL(state)) { |
| 1188 | DRM_ERROR("failed to allocate crtc disable state\n"); |
| 1189 | goto unlock; |
| 1190 | } |
| 1191 | |
| 1192 | state->acquire_ctx = &ctx; |
| 1193 | drm_for_each_connector(conn, ddev) { |
| 1194 | |
| 1195 | if (!conn->state || !conn->state->crtc || |
| 1196 | conn->dpms != DRM_MODE_DPMS_ON) |
| 1197 | continue; |
| 1198 | |
| 1199 | /* force CRTC to be inactive */ |
| 1200 | crtc_state = drm_atomic_get_crtc_state(state, |
| 1201 | conn->state->crtc); |
| 1202 | if (IS_ERR_OR_NULL(crtc_state)) { |
| 1203 | DRM_ERROR("failed to get crtc %d state\n", |
| 1204 | conn->state->crtc->base.id); |
| 1205 | drm_atomic_state_free(state); |
| 1206 | goto unlock; |
| 1207 | } |
| 1208 | crtc_state->active = false; |
| 1209 | } |
| 1210 | |
| 1211 | /* commit the "disable all" state */ |
| 1212 | ret = drm_atomic_commit(state); |
| 1213 | if (ret < 0) { |
| 1214 | DRM_ERROR("failed to disable crtcs, %d\n", ret); |
| 1215 | drm_atomic_state_free(state); |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 1216 | } else { |
| 1217 | priv->suspend_block = true; |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1218 | } |
| 1219 | |
| 1220 | unlock: |
| 1221 | if (ret == -EDEADLK) { |
| 1222 | drm_modeset_backoff(&ctx); |
| 1223 | goto retry; |
| 1224 | } |
| 1225 | drm_modeset_drop_locks(&ctx); |
| 1226 | drm_modeset_acquire_fini(&ctx); |
| 1227 | |
| 1228 | /* disable hot-plug polling */ |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1229 | drm_kms_helper_poll_disable(ddev); |
| 1230 | |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
| 1234 | static int msm_pm_resume(struct device *dev) |
| 1235 | { |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1236 | struct drm_device *ddev; |
| 1237 | struct msm_drm_private *priv; |
| 1238 | int ret; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1239 | |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1240 | if (!dev) |
| 1241 | return -EINVAL; |
| 1242 | |
| 1243 | ddev = dev_get_drvdata(dev); |
| 1244 | if (!ddev || !ddev->dev_private) |
| 1245 | return -EINVAL; |
| 1246 | |
| 1247 | priv = ddev->dev_private; |
| 1248 | |
| 1249 | SDE_EVT32(priv->suspend_state != NULL); |
| 1250 | |
| 1251 | drm_mode_config_reset(ddev); |
| 1252 | |
| 1253 | drm_modeset_lock_all(ddev); |
| 1254 | |
Clarence Ip | a65cba5 | 2017-03-17 15:18:29 -0400 | [diff] [blame^] | 1255 | priv->suspend_block = false; |
| 1256 | |
Clarence Ip | e5f1f4c | 2016-11-19 18:02:23 -0500 | [diff] [blame] | 1257 | if (priv->suspend_state) { |
| 1258 | priv->suspend_state->acquire_ctx = |
| 1259 | ddev->mode_config.acquire_ctx; |
| 1260 | ret = drm_atomic_commit(priv->suspend_state); |
| 1261 | if (ret < 0) { |
| 1262 | DRM_ERROR("failed to restore state, %d\n", ret); |
| 1263 | drm_atomic_state_free(priv->suspend_state); |
| 1264 | } |
| 1265 | priv->suspend_state = NULL; |
| 1266 | } |
| 1267 | drm_modeset_unlock_all(ddev); |
| 1268 | |
| 1269 | /* enable hot-plug polling */ |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1270 | drm_kms_helper_poll_enable(ddev); |
| 1271 | |
| 1272 | return 0; |
| 1273 | } |
| 1274 | #endif |
| 1275 | |
| 1276 | static const struct dev_pm_ops msm_pm_ops = { |
| 1277 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) |
| 1278 | }; |
| 1279 | |
| 1280 | /* |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 1281 | * Componentized driver support: |
| 1282 | */ |
| 1283 | |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 1284 | /* |
| 1285 | * NOTE: duplication of the same code as exynos or imx (or probably any other). |
| 1286 | * so probably some room for some helpers |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 1287 | */ |
| 1288 | static int compare_of(struct device *dev, void *data) |
| 1289 | { |
| 1290 | return dev->of_node == data; |
| 1291 | } |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 1292 | |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1293 | /* |
| 1294 | * Identify what components need to be added by parsing what remote-endpoints |
| 1295 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there |
| 1296 | * is no external component that we need to add since LVDS is within MDP4 |
| 1297 | * itself. |
| 1298 | */ |
| 1299 | static int add_components_mdp(struct device *mdp_dev, |
| 1300 | struct component_match **matchptr) |
| 1301 | { |
| 1302 | struct device_node *np = mdp_dev->of_node; |
| 1303 | struct device_node *ep_node; |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1304 | struct device *master_dev; |
| 1305 | |
| 1306 | /* |
| 1307 | * on MDP4 based platforms, the MDP platform device is the component |
| 1308 | * master that adds other display interface components to itself. |
| 1309 | * |
| 1310 | * on MDP5 based platforms, the MDSS platform device is the component |
| 1311 | * master that adds MDP5 and other display interface components to |
| 1312 | * itself. |
| 1313 | */ |
| 1314 | if (of_device_is_compatible(np, "qcom,mdp4")) |
| 1315 | master_dev = mdp_dev; |
| 1316 | else |
| 1317 | master_dev = mdp_dev->parent; |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1318 | |
| 1319 | for_each_endpoint_of_node(np, ep_node) { |
| 1320 | struct device_node *intf; |
| 1321 | struct of_endpoint ep; |
| 1322 | int ret; |
| 1323 | |
| 1324 | ret = of_graph_parse_endpoint(ep_node, &ep); |
| 1325 | if (ret) { |
| 1326 | dev_err(mdp_dev, "unable to parse port endpoint\n"); |
| 1327 | of_node_put(ep_node); |
| 1328 | return ret; |
| 1329 | } |
| 1330 | |
| 1331 | /* |
| 1332 | * The LCDC/LVDS port on MDP4 is a speacial case where the |
| 1333 | * remote-endpoint isn't a component that we need to add |
| 1334 | */ |
| 1335 | if (of_device_is_compatible(np, "qcom,mdp4") && |
| 1336 | ep.port == 0) { |
| 1337 | of_node_put(ep_node); |
| 1338 | continue; |
| 1339 | } |
| 1340 | |
| 1341 | /* |
| 1342 | * It's okay if some of the ports don't have a remote endpoint |
| 1343 | * specified. It just means that the port isn't connected to |
| 1344 | * any external interface. |
| 1345 | */ |
| 1346 | intf = of_graph_get_remote_port_parent(ep_node); |
| 1347 | if (!intf) { |
| 1348 | of_node_put(ep_node); |
| 1349 | continue; |
| 1350 | } |
| 1351 | |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1352 | component_match_add(master_dev, matchptr, compare_of, intf); |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1353 | |
| 1354 | of_node_put(intf); |
| 1355 | of_node_put(ep_node); |
| 1356 | } |
| 1357 | |
| 1358 | return 0; |
| 1359 | } |
| 1360 | |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1361 | static int compare_name_mdp(struct device *dev, void *data) |
| 1362 | { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1363 | return (strnstr(dev_name(dev), "mdp", strlen("mdp")) != NULL); |
| 1364 | } |
| 1365 | |
| 1366 | static int add_display_components(struct device *dev, |
| 1367 | struct component_match **matchptr) |
| 1368 | { |
| 1369 | struct device *mdp_dev = NULL; |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1370 | int ret; |
| 1371 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1372 | if (of_device_is_compatible(dev->of_node, "qcom,sde-kms")) { |
| 1373 | struct device_node *np = dev->of_node; |
| 1374 | unsigned int i; |
| 1375 | |
| 1376 | for (i = 0; ; i++) { |
| 1377 | struct device_node *node; |
| 1378 | |
| 1379 | node = of_parse_phandle(np, "connectors", i); |
| 1380 | if (!node) |
| 1381 | break; |
| 1382 | |
| 1383 | component_match_add(dev, matchptr, compare_of, node); |
| 1384 | } |
| 1385 | return 0; |
| 1386 | } |
| 1387 | |
| 1388 | /* |
| 1389 | * MDP5 based devices don't have a flat hierarchy. There is a top level |
| 1390 | * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the |
| 1391 | * children devices, find the MDP5 node, and then add the interfaces |
| 1392 | * to our components list. |
| 1393 | */ |
| 1394 | if (of_device_is_compatible(dev->of_node, "qcom,mdss")) { |
| 1395 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); |
| 1396 | if (ret) { |
| 1397 | dev_err(dev, "failed to populate children devices\n"); |
| 1398 | return ret; |
| 1399 | } |
| 1400 | |
| 1401 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); |
| 1402 | if (!mdp_dev) { |
| 1403 | dev_err(dev, "failed to find MDSS MDP node\n"); |
| 1404 | of_platform_depopulate(dev); |
| 1405 | return -ENODEV; |
| 1406 | } |
| 1407 | |
| 1408 | put_device(mdp_dev); |
| 1409 | |
| 1410 | /* add the MDP component itself */ |
| 1411 | component_match_add(dev, matchptr, compare_of, |
| 1412 | mdp_dev->of_node); |
| 1413 | } else { |
| 1414 | /* MDP4 */ |
| 1415 | mdp_dev = dev; |
| 1416 | } |
| 1417 | |
| 1418 | ret = add_components_mdp(mdp_dev, matchptr); |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1419 | if (ret) |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1420 | of_platform_depopulate(dev); |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1421 | |
| 1422 | return ret; |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1423 | } |
| 1424 | |
Archit Taneja | dc3ea26 | 2016-05-19 13:33:52 +0530 | [diff] [blame] | 1425 | /* |
| 1426 | * We don't know what's the best binding to link the gpu with the drm device. |
| 1427 | * Fow now, we just hunt for all the possible gpus that we support, and add them |
| 1428 | * as components. |
| 1429 | */ |
| 1430 | static const struct of_device_id msm_gpu_match[] = { |
| 1431 | { .compatible = "qcom,adreno-3xx" }, |
| 1432 | { .compatible = "qcom,kgsl-3d0" }, |
| 1433 | { }, |
| 1434 | }; |
| 1435 | |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1436 | static int add_gpu_components(struct device *dev, |
| 1437 | struct component_match **matchptr) |
| 1438 | { |
Archit Taneja | dc3ea26 | 2016-05-19 13:33:52 +0530 | [diff] [blame] | 1439 | struct device_node *np; |
| 1440 | |
| 1441 | np = of_find_matching_node(NULL, msm_gpu_match); |
| 1442 | if (!np) |
| 1443 | return 0; |
| 1444 | |
| 1445 | component_match_add(dev, matchptr, compare_of, np); |
| 1446 | |
| 1447 | of_node_put(np); |
| 1448 | |
| 1449 | return 0; |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1450 | } |
| 1451 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1452 | static int msm_drm_bind(struct device *dev) |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1453 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 1454 | return msm_drm_init(dev, &msm_driver); |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1455 | } |
| 1456 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1457 | static void msm_drm_unbind(struct device *dev) |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1458 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 1459 | msm_drm_uninit(dev); |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1460 | } |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1461 | |
| 1462 | static const struct component_master_ops msm_drm_ops = { |
| 1463 | .bind = msm_drm_bind, |
| 1464 | .unbind = msm_drm_unbind, |
| 1465 | }; |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1466 | |
| 1467 | /* |
| 1468 | * Platform driver: |
| 1469 | */ |
| 1470 | |
| 1471 | static int msm_pdev_probe(struct platform_device *pdev) |
| 1472 | { |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 1473 | int ret; |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1474 | struct component_match *match = NULL; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 1475 | |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1476 | ret = add_display_components(&pdev->dev, &match); |
| 1477 | if (ret) |
| 1478 | return ret; |
| 1479 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1480 | ret = add_gpu_components(&pdev->dev, &match); |
| 1481 | if (ret) |
| 1482 | return ret; |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 1483 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1484 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
| 1485 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1486 | } |
| 1487 | |
| 1488 | static int msm_pdev_remove(struct platform_device *pdev) |
| 1489 | { |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 1490 | component_master_del(&pdev->dev, &msm_drm_ops); |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1491 | of_platform_depopulate(&pdev->dev); |
| 1492 | |
| 1493 | msm_drm_unbind(&pdev->dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1494 | return 0; |
| 1495 | } |
| 1496 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1497 | static const struct of_device_id dt_match[] = { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1498 | { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */ |
| 1499 | { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */ |
| 1500 | { .compatible = "qcom,sde-kms", .data = (void *)3 }, /* sde */ |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1501 | {} |
| 1502 | }; |
| 1503 | MODULE_DEVICE_TABLE(of, dt_match); |
| 1504 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1505 | static struct platform_driver msm_platform_driver = { |
| 1506 | .probe = msm_pdev_probe, |
| 1507 | .remove = msm_pdev_remove, |
| 1508 | .driver = { |
Stephane Viau | aa6ed8b | 2016-07-19 12:59:42 -0400 | [diff] [blame] | 1509 | .name = "msm_drm", |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1510 | .of_match_table = dt_match, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1511 | .pm = &msm_pm_ops, |
| 1512 | }, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1513 | }; |
| 1514 | |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 1515 | #ifdef CONFIG_QCOM_KGSL |
| 1516 | void __init adreno_register(void) |
| 1517 | { |
| 1518 | } |
| 1519 | |
| 1520 | void __exit adreno_unregister(void) |
| 1521 | { |
| 1522 | } |
| 1523 | #endif |
| 1524 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1525 | static int __init msm_drm_register(void) |
| 1526 | { |
| 1527 | DBG("init"); |
Hai Li | d5af49c | 2015-03-26 19:25:17 -0400 | [diff] [blame] | 1528 | msm_dsi_register(); |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 1529 | msm_edp_register(); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 1530 | msm_hdmi_register(); |
Rob Clark | bfd28b1 | 2014-09-05 13:06:37 -0400 | [diff] [blame] | 1531 | adreno_register(); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1532 | return platform_driver_register(&msm_platform_driver); |
| 1533 | } |
| 1534 | |
| 1535 | static void __exit msm_drm_unregister(void) |
| 1536 | { |
| 1537 | DBG("fini"); |
| 1538 | platform_driver_unregister(&msm_platform_driver); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 1539 | msm_hdmi_unregister(); |
Rob Clark | bfd28b1 | 2014-09-05 13:06:37 -0400 | [diff] [blame] | 1540 | adreno_unregister(); |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 1541 | msm_edp_unregister(); |
Hai Li | d5af49c | 2015-03-26 19:25:17 -0400 | [diff] [blame] | 1542 | msm_dsi_unregister(); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1543 | } |
| 1544 | |
| 1545 | module_init(msm_drm_register); |
| 1546 | module_exit(msm_drm_unregister); |
| 1547 | |
| 1548 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); |
| 1549 | MODULE_DESCRIPTION("MSM DRM Driver"); |
| 1550 | MODULE_LICENSE("GPL"); |