Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1 | /* |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 2 | * Copyright (C) Ericsson AB 2007-2008 |
| 3 | * Copyright (C) ST-Ericsson SA 2008-2010 |
Per Forlin | 661385f | 2010-10-06 09:05:28 +0000 | [diff] [blame] | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 6 | * License terms: GNU General Public License (GPL) version 2 |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
Alexey Dobriyan | b7f080c | 2011-06-16 11:01:34 +0000 | [diff] [blame] | 9 | #include <linux/dma-mapping.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 10 | #include <linux/kernel.h> |
| 11 | #include <linux/slab.h> |
Paul Gortmaker | f492b21 | 2011-07-31 16:17:36 -0400 | [diff] [blame] | 12 | #include <linux/export.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 13 | #include <linux/dmaengine.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/delay.h> |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 17 | #include <linux/pm.h> |
| 18 | #include <linux/pm_runtime.h> |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 19 | #include <linux/err.h> |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 20 | #include <linux/amba/bus.h> |
Linus Walleij | 15e4b78 | 2012-04-12 18:12:43 +0200 | [diff] [blame] | 21 | #include <linux/regulator/consumer.h> |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 22 | |
| 23 | #include <plat/ste_dma40.h> |
| 24 | |
Russell King - ARM Linux | d2ebfb3 | 2012-03-06 22:34:26 +0000 | [diff] [blame] | 25 | #include "dmaengine.h" |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 26 | #include "ste_dma40_ll.h" |
| 27 | |
| 28 | #define D40_NAME "dma40" |
| 29 | |
| 30 | #define D40_PHY_CHAN -1 |
| 31 | |
| 32 | /* For masking out/in 2 bit channel positions */ |
| 33 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) |
| 34 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) |
| 35 | |
| 36 | /* Maximum iterations taken before giving up suspending a channel */ |
| 37 | #define D40_SUSPEND_MAX_IT 500 |
| 38 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 39 | /* Milliseconds */ |
| 40 | #define DMA40_AUTOSUSPEND_DELAY 100 |
| 41 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 42 | /* Hardware requirement on LCLA alignment */ |
| 43 | #define LCLA_ALIGNMENT 0x40000 |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 44 | |
| 45 | /* Max number of links per event group */ |
| 46 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 |
| 47 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP |
| 48 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 49 | /* Attempts before giving up to trying to get pages that are aligned */ |
| 50 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 |
| 51 | |
| 52 | /* Bit markings for allocation map */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 53 | #define D40_ALLOC_FREE (1 << 31) |
| 54 | #define D40_ALLOC_PHY (1 << 30) |
| 55 | #define D40_ALLOC_LOG_FREE 0 |
| 56 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 57 | /** |
| 58 | * enum 40_command - The different commands and/or statuses. |
| 59 | * |
| 60 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, |
| 61 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. |
| 62 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. |
| 63 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. |
| 64 | */ |
| 65 | enum d40_command { |
| 66 | D40_DMA_STOP = 0, |
| 67 | D40_DMA_RUN = 1, |
| 68 | D40_DMA_SUSPEND_REQ = 2, |
| 69 | D40_DMA_SUSPENDED = 3 |
| 70 | }; |
| 71 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 72 | /* |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 73 | * enum d40_events - The different Event Enables for the event lines. |
| 74 | * |
| 75 | * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan. |
| 76 | * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan. |
| 77 | * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line. |
| 78 | * @D40_ROUND_EVENTLINE: Status check for event line. |
| 79 | */ |
| 80 | |
| 81 | enum d40_events { |
| 82 | D40_DEACTIVATE_EVENTLINE = 0, |
| 83 | D40_ACTIVATE_EVENTLINE = 1, |
| 84 | D40_SUSPEND_REQ_EVENTLINE = 2, |
| 85 | D40_ROUND_EVENTLINE = 3 |
| 86 | }; |
| 87 | |
| 88 | /* |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 89 | * These are the registers that has to be saved and later restored |
| 90 | * when the DMA hw is powered off. |
| 91 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. |
| 92 | */ |
| 93 | static u32 d40_backup_regs[] = { |
| 94 | D40_DREG_LCPA, |
| 95 | D40_DREG_LCLA, |
| 96 | D40_DREG_PRMSE, |
| 97 | D40_DREG_PRMSO, |
| 98 | D40_DREG_PRMOE, |
| 99 | D40_DREG_PRMOO, |
| 100 | }; |
| 101 | |
| 102 | #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) |
| 103 | |
| 104 | /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */ |
| 105 | static u32 d40_backup_regs_v3[] = { |
| 106 | D40_DREG_PSEG1, |
| 107 | D40_DREG_PSEG2, |
| 108 | D40_DREG_PSEG3, |
| 109 | D40_DREG_PSEG4, |
| 110 | D40_DREG_PCEG1, |
| 111 | D40_DREG_PCEG2, |
| 112 | D40_DREG_PCEG3, |
| 113 | D40_DREG_PCEG4, |
| 114 | D40_DREG_RSEG1, |
| 115 | D40_DREG_RSEG2, |
| 116 | D40_DREG_RSEG3, |
| 117 | D40_DREG_RSEG4, |
| 118 | D40_DREG_RCEG1, |
| 119 | D40_DREG_RCEG2, |
| 120 | D40_DREG_RCEG3, |
| 121 | D40_DREG_RCEG4, |
| 122 | }; |
| 123 | |
| 124 | #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3) |
| 125 | |
| 126 | static u32 d40_backup_regs_chan[] = { |
| 127 | D40_CHAN_REG_SSCFG, |
| 128 | D40_CHAN_REG_SSELT, |
| 129 | D40_CHAN_REG_SSPTR, |
| 130 | D40_CHAN_REG_SSLNK, |
| 131 | D40_CHAN_REG_SDCFG, |
| 132 | D40_CHAN_REG_SDELT, |
| 133 | D40_CHAN_REG_SDPTR, |
| 134 | D40_CHAN_REG_SDLNK, |
| 135 | }; |
| 136 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 137 | /** |
| 138 | * struct d40_lli_pool - Structure for keeping LLIs in memory |
| 139 | * |
| 140 | * @base: Pointer to memory area when the pre_alloc_lli's are not large |
| 141 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if |
| 142 | * pre_alloc_lli is used. |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 143 | * @dma_addr: DMA address, if mapped |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 144 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
| 145 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, |
| 146 | * one buffer to one buffer. |
| 147 | */ |
| 148 | struct d40_lli_pool { |
| 149 | void *base; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 150 | int size; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 151 | dma_addr_t dma_addr; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 152 | /* Space for dst and src, plus an extra for padding */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 153 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 154 | }; |
| 155 | |
| 156 | /** |
| 157 | * struct d40_desc - A descriptor is one DMA job. |
| 158 | * |
| 159 | * @lli_phy: LLI settings for physical channel. Both src and dst= |
| 160 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if |
| 161 | * lli_len equals one. |
| 162 | * @lli_log: Same as above but for logical channels. |
| 163 | * @lli_pool: The pool with two entries pre-allocated. |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 164 | * @lli_len: Number of llis of current descriptor. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 165 | * @lli_current: Number of transferred llis. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 166 | * @lcla_alloc: Number of LCLA entries allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 167 | * @txd: DMA engine struct. Used for among other things for communication |
| 168 | * during a transfer. |
| 169 | * @node: List entry. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 170 | * @is_in_client_list: true if the client owns this descriptor. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 171 | * @cyclic: true if this is a cyclic job |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 172 | * |
| 173 | * This descriptor is used for both logical and physical transfers. |
| 174 | */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 175 | struct d40_desc { |
| 176 | /* LLI physical */ |
| 177 | struct d40_phy_lli_bidir lli_phy; |
| 178 | /* LLI logical */ |
| 179 | struct d40_log_lli_bidir lli_log; |
| 180 | |
| 181 | struct d40_lli_pool lli_pool; |
Per Friden | 941b77a | 2010-06-20 21:24:45 +0000 | [diff] [blame] | 182 | int lli_len; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 183 | int lli_current; |
| 184 | int lcla_alloc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 185 | |
| 186 | struct dma_async_tx_descriptor txd; |
| 187 | struct list_head node; |
| 188 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 189 | bool is_in_client_list; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 190 | bool cyclic; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 191 | }; |
| 192 | |
| 193 | /** |
| 194 | * struct d40_lcla_pool - LCLA pool settings and data. |
| 195 | * |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 196 | * @base: The virtual address of LCLA. 18 bit aligned. |
| 197 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. |
| 198 | * This pointer is only there for clean-up on error. |
| 199 | * @pages: The number of pages needed for all physical channels. |
| 200 | * Only used later for clean-up on error |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 201 | * @lock: Lock to protect the content in this struct. |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 202 | * @alloc_map: big map over which LCLA entry is own by which job. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 203 | */ |
| 204 | struct d40_lcla_pool { |
| 205 | void *base; |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 206 | dma_addr_t dma_addr; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 207 | void *base_unaligned; |
| 208 | int pages; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 209 | spinlock_t lock; |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 210 | struct d40_desc **alloc_map; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | /** |
| 214 | * struct d40_phy_res - struct for handling eventlines mapped to physical |
| 215 | * channels. |
| 216 | * |
| 217 | * @lock: A lock protection this entity. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 218 | * @reserved: True if used by secure world or otherwise. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 219 | * @num: The physical channel number of this entity. |
| 220 | * @allocated_src: Bit mapped to show which src event line's are mapped to |
| 221 | * this physical channel. Can also be free or physically allocated. |
| 222 | * @allocated_dst: Same as for src but is dst. |
| 223 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 224 | * event line number. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 225 | */ |
| 226 | struct d40_phy_res { |
| 227 | spinlock_t lock; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 228 | bool reserved; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 229 | int num; |
| 230 | u32 allocated_src; |
| 231 | u32 allocated_dst; |
| 232 | }; |
| 233 | |
| 234 | struct d40_base; |
| 235 | |
| 236 | /** |
| 237 | * struct d40_chan - Struct that describes a channel. |
| 238 | * |
| 239 | * @lock: A spinlock to protect this struct. |
| 240 | * @log_num: The logical number, if any of this channel. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 241 | * @pending_tx: The number of pending transfers. Used between interrupt handler |
| 242 | * and tasklet. |
| 243 | * @busy: Set to true when transfer is ongoing on this channel. |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 244 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
| 245 | * point is NULL, then the channel is not allocated. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 246 | * @chan: DMA engine handle. |
| 247 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a |
| 248 | * transfer and call client callback. |
| 249 | * @client: Cliented owned descriptor list. |
Per Forlin | da063d2 | 2011-08-29 13:33:32 +0200 | [diff] [blame] | 250 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 251 | * @active: Active descriptor. |
| 252 | * @queue: Queued jobs. |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 253 | * @prepare_queue: Prepared jobs. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 254 | * @dma_cfg: The client configuration of this dma channel. |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 255 | * @configured: whether the dma_cfg configuration is valid |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 256 | * @base: Pointer to the device instance struct. |
| 257 | * @src_def_cfg: Default cfg register setting for src. |
| 258 | * @dst_def_cfg: Default cfg register setting for dst. |
| 259 | * @log_def: Default logical channel settings. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 260 | * @lcpa: Pointer to dst and src lcpa settings. |
om prakash | ae752bf | 2011-06-27 11:33:31 +0200 | [diff] [blame] | 261 | * @runtime_addr: runtime configured address. |
| 262 | * @runtime_direction: runtime configured direction. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 263 | * |
| 264 | * This struct can either "be" a logical or a physical channel. |
| 265 | */ |
| 266 | struct d40_chan { |
| 267 | spinlock_t lock; |
| 268 | int log_num; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 269 | int pending_tx; |
| 270 | bool busy; |
| 271 | struct d40_phy_res *phy_chan; |
| 272 | struct dma_chan chan; |
| 273 | struct tasklet_struct tasklet; |
| 274 | struct list_head client; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 275 | struct list_head pending_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 276 | struct list_head active; |
| 277 | struct list_head queue; |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 278 | struct list_head prepare_queue; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 279 | struct stedma40_chan_cfg dma_cfg; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 280 | bool configured; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 281 | struct d40_base *base; |
| 282 | /* Default register configurations */ |
| 283 | u32 src_def_cfg; |
| 284 | u32 dst_def_cfg; |
| 285 | struct d40_def_lcsp log_def; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 286 | struct d40_log_lli_full *lcpa; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 287 | /* Runtime reconfiguration */ |
| 288 | dma_addr_t runtime_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 289 | enum dma_transfer_direction runtime_direction; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | /** |
| 293 | * struct d40_base - The big global struct, one for each probe'd instance. |
| 294 | * |
| 295 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. |
| 296 | * @execmd_lock: Lock for execute command usage since several channels share |
| 297 | * the same physical register. |
| 298 | * @dev: The device structure. |
| 299 | * @virtbase: The virtual base address of the DMA's register. |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 300 | * @rev: silicon revision detected. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 301 | * @clk: Pointer to the DMA clock structure. |
| 302 | * @phy_start: Physical memory start of the DMA registers. |
| 303 | * @phy_size: Size of the DMA register map. |
| 304 | * @irq: The IRQ number. |
| 305 | * @num_phy_chans: The number of physical channels. Read from HW. This |
| 306 | * is the number of available channels for this driver, not counting "Secure |
| 307 | * mode" allocated physical channels. |
| 308 | * @num_log_chans: The number of logical channels. Calculated from |
| 309 | * num_phy_chans. |
| 310 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. |
| 311 | * @dma_slave: dma_device channels that can do only do slave transfers. |
| 312 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 313 | * @phy_chans: Room for all possible physical channels in system. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 314 | * @log_chans: Room for all possible logical channels in system. |
| 315 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points |
| 316 | * to log_chans entries. |
| 317 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points |
| 318 | * to phy_chans entries. |
| 319 | * @plat_data: Pointer to provided platform_data which is the driver |
| 320 | * configuration. |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 321 | * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla. |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 322 | * @phy_res: Vector containing all physical channels. |
| 323 | * @lcla_pool: lcla pool settings and data. |
| 324 | * @lcpa_base: The virtual mapped address of LCPA. |
| 325 | * @phy_lcpa: The physical address of the LCPA. |
| 326 | * @lcpa_size: The size of the LCPA area. |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 327 | * @desc_slab: cache for descriptors. |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 328 | * @reg_val_backup: Here the values of some hardware registers are stored |
| 329 | * before the DMA is powered off. They are restored when the power is back on. |
| 330 | * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and |
| 331 | * later. |
| 332 | * @reg_val_backup_chan: Backup data for standard channel parameter registers. |
| 333 | * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. |
| 334 | * @initialized: true if the dma has been initialized |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 335 | */ |
| 336 | struct d40_base { |
| 337 | spinlock_t interrupt_lock; |
| 338 | spinlock_t execmd_lock; |
| 339 | struct device *dev; |
| 340 | void __iomem *virtbase; |
Linus Walleij | f418559 | 2010-06-22 18:06:42 -0700 | [diff] [blame] | 341 | u8 rev:4; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 342 | struct clk *clk; |
| 343 | phys_addr_t phy_start; |
| 344 | resource_size_t phy_size; |
| 345 | int irq; |
| 346 | int num_phy_chans; |
| 347 | int num_log_chans; |
| 348 | struct dma_device dma_both; |
| 349 | struct dma_device dma_slave; |
| 350 | struct dma_device dma_memcpy; |
| 351 | struct d40_chan *phy_chans; |
| 352 | struct d40_chan *log_chans; |
| 353 | struct d40_chan **lookup_log_chans; |
| 354 | struct d40_chan **lookup_phy_chans; |
| 355 | struct stedma40_platform_data *plat_data; |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 356 | struct regulator *lcpa_regulator; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 357 | /* Physical half channels */ |
| 358 | struct d40_phy_res *phy_res; |
| 359 | struct d40_lcla_pool lcla_pool; |
| 360 | void *lcpa_base; |
| 361 | dma_addr_t phy_lcpa; |
| 362 | resource_size_t lcpa_size; |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 363 | struct kmem_cache *desc_slab; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 364 | u32 reg_val_backup[BACKUP_REGS_SZ]; |
| 365 | u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3]; |
| 366 | u32 *reg_val_backup_chan; |
| 367 | u16 gcc_pwr_off_mask; |
| 368 | bool initialized; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | /** |
| 372 | * struct d40_interrupt_lookup - lookup table for interrupt handler |
| 373 | * |
| 374 | * @src: Interrupt mask register. |
| 375 | * @clr: Interrupt clear register. |
| 376 | * @is_error: true if this is an error interrupt. |
| 377 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to |
| 378 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. |
| 379 | */ |
| 380 | struct d40_interrupt_lookup { |
| 381 | u32 src; |
| 382 | u32 clr; |
| 383 | bool is_error; |
| 384 | int offset; |
| 385 | }; |
| 386 | |
| 387 | /** |
| 388 | * struct d40_reg_val - simple lookup struct |
| 389 | * |
| 390 | * @reg: The register. |
| 391 | * @val: The value that belongs to the register in reg. |
| 392 | */ |
| 393 | struct d40_reg_val { |
| 394 | unsigned int reg; |
| 395 | unsigned int val; |
| 396 | }; |
| 397 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 398 | static struct device *chan2dev(struct d40_chan *d40c) |
| 399 | { |
| 400 | return &d40c->chan.dev->device; |
| 401 | } |
| 402 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 403 | static bool chan_is_physical(struct d40_chan *chan) |
| 404 | { |
| 405 | return chan->log_num == D40_PHY_CHAN; |
| 406 | } |
| 407 | |
| 408 | static bool chan_is_logical(struct d40_chan *chan) |
| 409 | { |
| 410 | return !chan_is_physical(chan); |
| 411 | } |
| 412 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 413 | static void __iomem *chan_base(struct d40_chan *chan) |
| 414 | { |
| 415 | return chan->base->virtbase + D40_DREG_PCBASE + |
| 416 | chan->phy_chan->num * D40_DREG_PCDELTA; |
| 417 | } |
| 418 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 419 | #define d40_err(dev, format, arg...) \ |
| 420 | dev_err(dev, "[%s] " format, __func__, ## arg) |
| 421 | |
| 422 | #define chan_err(d40c, format, arg...) \ |
| 423 | d40_err(chan2dev(d40c), format, ## arg) |
| 424 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 425 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 426 | int lli_len) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 427 | { |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 428 | bool is_log = chan_is_logical(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 429 | u32 align; |
| 430 | void *base; |
| 431 | |
| 432 | if (is_log) |
| 433 | align = sizeof(struct d40_log_lli); |
| 434 | else |
| 435 | align = sizeof(struct d40_phy_lli); |
| 436 | |
| 437 | if (lli_len == 1) { |
| 438 | base = d40d->lli_pool.pre_alloc_lli; |
| 439 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); |
| 440 | d40d->lli_pool.base = NULL; |
| 441 | } else { |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 442 | d40d->lli_pool.size = lli_len * 2 * align; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 443 | |
| 444 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); |
| 445 | d40d->lli_pool.base = base; |
| 446 | |
| 447 | if (d40d->lli_pool.base == NULL) |
| 448 | return -ENOMEM; |
| 449 | } |
| 450 | |
| 451 | if (is_log) { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 452 | d40d->lli_log.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 453 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 454 | |
| 455 | d40d->lli_pool.dma_addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 456 | } else { |
Rabin Vincent | d924aba | 2011-01-25 11:18:16 +0100 | [diff] [blame] | 457 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
Rabin Vincent | 594ece4 | 2011-01-25 11:18:12 +0100 | [diff] [blame] | 458 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 459 | |
| 460 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, |
| 461 | d40d->lli_phy.src, |
| 462 | d40d->lli_pool.size, |
| 463 | DMA_TO_DEVICE); |
| 464 | |
| 465 | if (dma_mapping_error(d40c->base->dev, |
| 466 | d40d->lli_pool.dma_addr)) { |
| 467 | kfree(d40d->lli_pool.base); |
| 468 | d40d->lli_pool.base = NULL; |
| 469 | d40d->lli_pool.dma_addr = 0; |
| 470 | return -ENOMEM; |
| 471 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 472 | } |
| 473 | |
| 474 | return 0; |
| 475 | } |
| 476 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 477 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 478 | { |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 479 | if (d40d->lli_pool.dma_addr) |
| 480 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, |
| 481 | d40d->lli_pool.size, DMA_TO_DEVICE); |
| 482 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 483 | kfree(d40d->lli_pool.base); |
| 484 | d40d->lli_pool.base = NULL; |
| 485 | d40d->lli_pool.size = 0; |
| 486 | d40d->lli_log.src = NULL; |
| 487 | d40d->lli_log.dst = NULL; |
| 488 | d40d->lli_phy.src = NULL; |
| 489 | d40d->lli_phy.dst = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 490 | } |
| 491 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 492 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
| 493 | struct d40_desc *d40d) |
| 494 | { |
| 495 | unsigned long flags; |
| 496 | int i; |
| 497 | int ret = -EINVAL; |
| 498 | int p; |
| 499 | |
| 500 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 501 | |
| 502 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; |
| 503 | |
| 504 | /* |
| 505 | * Allocate both src and dst at the same time, therefore the half |
| 506 | * start on 1 since 0 can't be used since zero is used as end marker. |
| 507 | */ |
| 508 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
| 509 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { |
| 510 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; |
| 511 | d40d->lcla_alloc++; |
| 512 | ret = i; |
| 513 | break; |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 518 | |
| 519 | return ret; |
| 520 | } |
| 521 | |
| 522 | static int d40_lcla_free_all(struct d40_chan *d40c, |
| 523 | struct d40_desc *d40d) |
| 524 | { |
| 525 | unsigned long flags; |
| 526 | int i; |
| 527 | int ret = -EINVAL; |
| 528 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 529 | if (chan_is_physical(d40c)) |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 530 | return 0; |
| 531 | |
| 532 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); |
| 533 | |
| 534 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { |
| 535 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * |
| 536 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { |
| 537 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * |
| 538 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; |
| 539 | d40d->lcla_alloc--; |
| 540 | if (d40d->lcla_alloc == 0) { |
| 541 | ret = 0; |
| 542 | break; |
| 543 | } |
| 544 | } |
| 545 | } |
| 546 | |
| 547 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); |
| 548 | |
| 549 | return ret; |
| 550 | |
| 551 | } |
| 552 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 553 | static void d40_desc_remove(struct d40_desc *d40d) |
| 554 | { |
| 555 | list_del(&d40d->node); |
| 556 | } |
| 557 | |
| 558 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) |
| 559 | { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 560 | struct d40_desc *desc = NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 561 | |
| 562 | if (!list_empty(&d40c->client)) { |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 563 | struct d40_desc *d; |
| 564 | struct d40_desc *_d; |
| 565 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 566 | list_for_each_entry_safe(d, _d, &d40c->client, node) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 567 | if (async_tx_test_ack(&d->txd)) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 568 | d40_desc_remove(d); |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 569 | desc = d; |
| 570 | memset(desc, 0, sizeof(*desc)); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 571 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 572 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 573 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 574 | } |
Rabin Vincent | a2c15fa | 2010-10-06 08:20:37 +0000 | [diff] [blame] | 575 | |
| 576 | if (!desc) |
| 577 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); |
| 578 | |
| 579 | if (desc) |
| 580 | INIT_LIST_HEAD(&desc->node); |
| 581 | |
| 582 | return desc; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 583 | } |
| 584 | |
| 585 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) |
| 586 | { |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 587 | |
Rabin Vincent | b00f938 | 2011-01-25 11:18:15 +0100 | [diff] [blame] | 588 | d40_pool_lli_free(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 589 | d40_lcla_free_all(d40c, d40d); |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 590 | kmem_cache_free(d40c->base->desc_slab, d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 591 | } |
| 592 | |
| 593 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) |
| 594 | { |
| 595 | list_add_tail(&desc->node, &d40c->active); |
| 596 | } |
| 597 | |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 598 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
| 599 | { |
| 600 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; |
| 601 | struct d40_phy_lli *lli_src = desc->lli_phy.src; |
| 602 | void __iomem *base = chan_base(chan); |
| 603 | |
| 604 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); |
| 605 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); |
| 606 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); |
| 607 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); |
| 608 | |
| 609 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); |
| 610 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); |
| 611 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); |
| 612 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); |
| 613 | } |
| 614 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 615 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
| 616 | { |
| 617 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
| 618 | struct d40_log_lli_bidir *lli = &desc->lli_log; |
| 619 | int lli_current = desc->lli_current; |
| 620 | int lli_len = desc->lli_len; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 621 | bool cyclic = desc->cyclic; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 622 | int curr_lcla = -EINVAL; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 623 | int first_lcla = 0; |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 624 | bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 625 | bool linkback; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 626 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 627 | /* |
| 628 | * We may have partially running cyclic transfers, in case we did't get |
| 629 | * enough LCLA entries. |
| 630 | */ |
| 631 | linkback = cyclic && lli_current == 0; |
| 632 | |
| 633 | /* |
| 634 | * For linkback, we need one LCLA even with only one link, because we |
| 635 | * can't link back to the one in LCPA space |
| 636 | */ |
| 637 | if (linkback || (lli_len - lli_current > 1)) { |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 638 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 639 | first_lcla = curr_lcla; |
| 640 | } |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 641 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 642 | /* |
| 643 | * For linkback, we normally load the LCPA in the loop since we need to |
| 644 | * link it to the second LCLA and not the first. However, if we |
| 645 | * couldn't even get a first LCLA, then we have to run in LCPA and |
| 646 | * reload manually. |
| 647 | */ |
| 648 | if (!linkback || curr_lcla == -EINVAL) { |
| 649 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 650 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 651 | if (curr_lcla == -EINVAL) |
| 652 | flags |= LLI_TERM_INT; |
| 653 | |
| 654 | d40_log_lli_lcpa_write(chan->lcpa, |
| 655 | &lli->dst[lli_current], |
| 656 | &lli->src[lli_current], |
| 657 | curr_lcla, |
| 658 | flags); |
| 659 | lli_current++; |
| 660 | } |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 661 | |
| 662 | if (curr_lcla < 0) |
| 663 | goto out; |
| 664 | |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 665 | for (; lli_current < lli_len; lli_current++) { |
| 666 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + |
| 667 | 8 * curr_lcla * 2; |
| 668 | struct d40_log_lli *lcla = pool->base + lcla_offset; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 669 | unsigned int flags = 0; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 670 | int next_lcla; |
| 671 | |
| 672 | if (lli_current + 1 < lli_len) |
| 673 | next_lcla = d40_lcla_alloc_one(chan, desc); |
| 674 | else |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 675 | next_lcla = linkback ? first_lcla : -EINVAL; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 676 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 677 | if (cyclic || next_lcla == -EINVAL) |
| 678 | flags |= LLI_TERM_INT; |
| 679 | |
| 680 | if (linkback && curr_lcla == first_lcla) { |
| 681 | /* First link goes in both LCPA and LCLA */ |
| 682 | d40_log_lli_lcpa_write(chan->lcpa, |
| 683 | &lli->dst[lli_current], |
| 684 | &lli->src[lli_current], |
| 685 | next_lcla, flags); |
| 686 | } |
| 687 | |
| 688 | /* |
| 689 | * One unused LCLA in the cyclic case if the very first |
| 690 | * next_lcla fails... |
| 691 | */ |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 692 | d40_log_lli_lcla_write(lcla, |
| 693 | &lli->dst[lli_current], |
| 694 | &lli->src[lli_current], |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 695 | next_lcla, flags); |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 696 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 697 | /* |
| 698 | * Cache maintenance is not needed if lcla is |
| 699 | * mapped in esram |
| 700 | */ |
| 701 | if (!use_esram_lcla) { |
| 702 | dma_sync_single_range_for_device(chan->base->dev, |
| 703 | pool->dma_addr, lcla_offset, |
| 704 | 2 * sizeof(struct d40_log_lli), |
| 705 | DMA_TO_DEVICE); |
| 706 | } |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 707 | curr_lcla = next_lcla; |
| 708 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 709 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 710 | lli_current++; |
| 711 | break; |
| 712 | } |
| 713 | } |
| 714 | |
Rabin Vincent | 6045f0b | 2011-01-25 11:18:32 +0100 | [diff] [blame] | 715 | out: |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 716 | desc->lli_current = lli_current; |
| 717 | } |
| 718 | |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 719 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
| 720 | { |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 721 | if (chan_is_physical(d40c)) { |
Rabin Vincent | 1c4b092 | 2011-01-25 11:18:24 +0100 | [diff] [blame] | 722 | d40_phy_lli_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 723 | d40d->lli_current = d40d->lli_len; |
Rabin Vincent | e65889c | 2011-01-25 11:18:31 +0100 | [diff] [blame] | 724 | } else |
| 725 | d40_log_lli_to_lcxa(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 726 | } |
| 727 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 728 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
| 729 | { |
| 730 | struct d40_desc *d; |
| 731 | |
| 732 | if (list_empty(&d40c->active)) |
| 733 | return NULL; |
| 734 | |
| 735 | d = list_first_entry(&d40c->active, |
| 736 | struct d40_desc, |
| 737 | node); |
| 738 | return d; |
| 739 | } |
| 740 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 741 | /* remove desc from current queue and add it to the pending_queue */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 742 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
| 743 | { |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 744 | d40_desc_remove(desc); |
| 745 | desc->is_in_client_list = false; |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 746 | list_add_tail(&desc->node, &d40c->pending_queue); |
| 747 | } |
| 748 | |
| 749 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) |
| 750 | { |
| 751 | struct d40_desc *d; |
| 752 | |
| 753 | if (list_empty(&d40c->pending_queue)) |
| 754 | return NULL; |
| 755 | |
| 756 | d = list_first_entry(&d40c->pending_queue, |
| 757 | struct d40_desc, |
| 758 | node); |
| 759 | return d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 760 | } |
| 761 | |
| 762 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) |
| 763 | { |
| 764 | struct d40_desc *d; |
| 765 | |
| 766 | if (list_empty(&d40c->queue)) |
| 767 | return NULL; |
| 768 | |
| 769 | d = list_first_entry(&d40c->queue, |
| 770 | struct d40_desc, |
| 771 | node); |
| 772 | return d; |
| 773 | } |
| 774 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 775 | static int d40_psize_2_burst_size(bool is_log, int psize) |
| 776 | { |
| 777 | if (is_log) { |
| 778 | if (psize == STEDMA40_PSIZE_LOG_1) |
| 779 | return 1; |
| 780 | } else { |
| 781 | if (psize == STEDMA40_PSIZE_PHY_1) |
| 782 | return 1; |
| 783 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 784 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 785 | return 2 << psize; |
| 786 | } |
| 787 | |
| 788 | /* |
| 789 | * The dma only supports transmitting packages up to |
| 790 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of |
| 791 | * dma elements required to send the entire sg list |
| 792 | */ |
| 793 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) |
| 794 | { |
| 795 | int dmalen; |
| 796 | u32 max_w = max(data_width1, data_width2); |
| 797 | u32 min_w = min(data_width1, data_width2); |
| 798 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); |
| 799 | |
| 800 | if (seg_max > STEDMA40_MAX_SEG_SIZE) |
| 801 | seg_max -= (1 << max_w); |
| 802 | |
| 803 | if (!IS_ALIGNED(size, 1 << max_w)) |
| 804 | return -EINVAL; |
| 805 | |
| 806 | if (size <= seg_max) |
| 807 | dmalen = 1; |
| 808 | else { |
| 809 | dmalen = size / seg_max; |
| 810 | if (dmalen * seg_max < size) |
| 811 | dmalen++; |
| 812 | } |
| 813 | return dmalen; |
| 814 | } |
| 815 | |
| 816 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, |
| 817 | u32 data_width1, u32 data_width2) |
| 818 | { |
| 819 | struct scatterlist *sg; |
| 820 | int i; |
| 821 | int len = 0; |
| 822 | int ret; |
| 823 | |
| 824 | for_each_sg(sgl, sg, sg_len, i) { |
| 825 | ret = d40_size_2_dmalen(sg_dma_len(sg), |
| 826 | data_width1, data_width2); |
| 827 | if (ret < 0) |
| 828 | return ret; |
| 829 | len += ret; |
| 830 | } |
| 831 | return len; |
| 832 | } |
| 833 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 834 | |
| 835 | #ifdef CONFIG_PM |
| 836 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, |
| 837 | u32 *regaddr, int num, bool save) |
| 838 | { |
| 839 | int i; |
| 840 | |
| 841 | for (i = 0; i < num; i++) { |
| 842 | void __iomem *addr = baseaddr + regaddr[i]; |
| 843 | |
| 844 | if (save) |
| 845 | backup[i] = readl_relaxed(addr); |
| 846 | else |
| 847 | writel_relaxed(backup[i], addr); |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 852 | { |
| 853 | int i; |
| 854 | |
| 855 | /* Save/Restore channel specific registers */ |
| 856 | for (i = 0; i < base->num_phy_chans; i++) { |
| 857 | void __iomem *addr; |
| 858 | int idx; |
| 859 | |
| 860 | if (base->phy_res[i].reserved) |
| 861 | continue; |
| 862 | |
| 863 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; |
| 864 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); |
| 865 | |
| 866 | dma40_backup(addr, &base->reg_val_backup_chan[idx], |
| 867 | d40_backup_regs_chan, |
| 868 | ARRAY_SIZE(d40_backup_regs_chan), |
| 869 | save); |
| 870 | } |
| 871 | |
| 872 | /* Save/Restore global registers */ |
| 873 | dma40_backup(base->virtbase, base->reg_val_backup, |
| 874 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), |
| 875 | save); |
| 876 | |
| 877 | /* Save/Restore registers only existing on dma40 v3 and later */ |
| 878 | if (base->rev >= 3) |
| 879 | dma40_backup(base->virtbase, base->reg_val_backup_v3, |
| 880 | d40_backup_regs_v3, |
| 881 | ARRAY_SIZE(d40_backup_regs_v3), |
| 882 | save); |
| 883 | } |
| 884 | #else |
| 885 | static void d40_save_restore_registers(struct d40_base *base, bool save) |
| 886 | { |
| 887 | } |
| 888 | #endif |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 889 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 890 | static int __d40_execute_command_phy(struct d40_chan *d40c, |
| 891 | enum d40_command command) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 892 | { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 893 | u32 status; |
| 894 | int i; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 895 | void __iomem *active_reg; |
| 896 | int ret = 0; |
| 897 | unsigned long flags; |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 898 | u32 wmask; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 899 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 900 | if (command == D40_DMA_STOP) { |
| 901 | ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ); |
| 902 | if (ret) |
| 903 | return ret; |
| 904 | } |
| 905 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 906 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); |
| 907 | |
| 908 | if (d40c->phy_chan->num % 2 == 0) |
| 909 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 910 | else |
| 911 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 912 | |
| 913 | if (command == D40_DMA_SUSPEND_REQ) { |
| 914 | status = (readl(active_reg) & |
| 915 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 916 | D40_CHAN_POS(d40c->phy_chan->num); |
| 917 | |
| 918 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 919 | goto done; |
| 920 | } |
| 921 | |
Jonas Aaberg | 1d392a7 | 2010-06-20 21:26:01 +0000 | [diff] [blame] | 922 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
| 923 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), |
| 924 | active_reg); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 925 | |
| 926 | if (command == D40_DMA_SUSPEND_REQ) { |
| 927 | |
| 928 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { |
| 929 | status = (readl(active_reg) & |
| 930 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 931 | D40_CHAN_POS(d40c->phy_chan->num); |
| 932 | |
| 933 | cpu_relax(); |
| 934 | /* |
| 935 | * Reduce the number of bus accesses while |
| 936 | * waiting for the DMA to suspend. |
| 937 | */ |
| 938 | udelay(3); |
| 939 | |
| 940 | if (status == D40_DMA_STOP || |
| 941 | status == D40_DMA_SUSPENDED) |
| 942 | break; |
| 943 | } |
| 944 | |
| 945 | if (i == D40_SUSPEND_MAX_IT) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 946 | chan_err(d40c, |
| 947 | "unable to suspend the chl %d (log: %d) status %x\n", |
| 948 | d40c->phy_chan->num, d40c->log_num, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 949 | status); |
| 950 | dump_stack(); |
| 951 | ret = -EBUSY; |
| 952 | } |
| 953 | |
| 954 | } |
| 955 | done: |
| 956 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); |
| 957 | return ret; |
| 958 | } |
| 959 | |
| 960 | static void d40_term_all(struct d40_chan *d40c) |
| 961 | { |
| 962 | struct d40_desc *d40d; |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 963 | struct d40_desc *_d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 964 | |
| 965 | /* Release active descriptors */ |
| 966 | while ((d40d = d40_first_active_get(d40c))) { |
| 967 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 968 | d40_desc_free(d40c, d40d); |
| 969 | } |
| 970 | |
| 971 | /* Release queued descriptors waiting for transfer */ |
| 972 | while ((d40d = d40_first_queued(d40c))) { |
| 973 | d40_desc_remove(d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 974 | d40_desc_free(d40c, d40d); |
| 975 | } |
| 976 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 977 | /* Release pending descriptors */ |
| 978 | while ((d40d = d40_first_pending(d40c))) { |
| 979 | d40_desc_remove(d40d); |
| 980 | d40_desc_free(d40c, d40d); |
| 981 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 982 | |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 983 | /* Release client owned descriptors */ |
| 984 | if (!list_empty(&d40c->client)) |
| 985 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { |
| 986 | d40_desc_remove(d40d); |
| 987 | d40_desc_free(d40c, d40d); |
| 988 | } |
| 989 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 990 | /* Release descriptors in prepare queue */ |
| 991 | if (!list_empty(&d40c->prepare_queue)) |
| 992 | list_for_each_entry_safe(d40d, _d, |
| 993 | &d40c->prepare_queue, node) { |
| 994 | d40_desc_remove(d40d); |
| 995 | d40_desc_free(d40c, d40d); |
| 996 | } |
Per Forlin | 7404368 | 2011-08-29 13:33:34 +0200 | [diff] [blame] | 997 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 998 | d40c->pending_tx = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 999 | } |
| 1000 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1001 | static void __d40_config_set_event(struct d40_chan *d40c, |
| 1002 | enum d40_events event_type, u32 event, |
| 1003 | int reg) |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1004 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1005 | void __iomem *addr = chan_base(d40c) + reg; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1006 | int tries; |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1007 | u32 status; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1008 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1009 | switch (event_type) { |
| 1010 | |
| 1011 | case D40_DEACTIVATE_EVENTLINE: |
| 1012 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1013 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 1014 | | ~D40_EVENTLINE_MASK(event), addr); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1015 | break; |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1016 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1017 | case D40_SUSPEND_REQ_EVENTLINE: |
| 1018 | status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> |
| 1019 | D40_EVENTLINE_POS(event); |
| 1020 | |
| 1021 | if (status == D40_DEACTIVATE_EVENTLINE || |
| 1022 | status == D40_SUSPEND_REQ_EVENTLINE) |
| 1023 | break; |
| 1024 | |
| 1025 | writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event)) |
| 1026 | | ~D40_EVENTLINE_MASK(event), addr); |
| 1027 | |
| 1028 | for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) { |
| 1029 | |
| 1030 | status = (readl(addr) & D40_EVENTLINE_MASK(event)) >> |
| 1031 | D40_EVENTLINE_POS(event); |
| 1032 | |
| 1033 | cpu_relax(); |
| 1034 | /* |
| 1035 | * Reduce the number of bus accesses while |
| 1036 | * waiting for the DMA to suspend. |
| 1037 | */ |
| 1038 | udelay(3); |
| 1039 | |
| 1040 | if (status == D40_DEACTIVATE_EVENTLINE) |
| 1041 | break; |
| 1042 | } |
| 1043 | |
| 1044 | if (tries == D40_SUSPEND_MAX_IT) { |
| 1045 | chan_err(d40c, |
| 1046 | "unable to stop the event_line chl %d (log: %d)" |
| 1047 | "status %x\n", d40c->phy_chan->num, |
| 1048 | d40c->log_num, status); |
| 1049 | } |
| 1050 | break; |
| 1051 | |
| 1052 | case D40_ACTIVATE_EVENTLINE: |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1053 | /* |
| 1054 | * The hardware sometimes doesn't register the enable when src and dst |
| 1055 | * event lines are active on the same logical channel. Retry to ensure |
| 1056 | * it does. Usually only one retry is sufficient. |
| 1057 | */ |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1058 | tries = 100; |
| 1059 | while (--tries) { |
| 1060 | writel((D40_ACTIVATE_EVENTLINE << |
| 1061 | D40_EVENTLINE_POS(event)) | |
| 1062 | ~D40_EVENTLINE_MASK(event), addr); |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1063 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1064 | if (readl(addr) & D40_EVENTLINE_MASK(event)) |
| 1065 | break; |
| 1066 | } |
| 1067 | |
| 1068 | if (tries != 99) |
| 1069 | dev_dbg(chan2dev(d40c), |
| 1070 | "[%s] workaround enable S%cLNK (%d tries)\n", |
| 1071 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', |
| 1072 | 100 - tries); |
| 1073 | |
| 1074 | WARN_ON(!tries); |
| 1075 | break; |
| 1076 | |
| 1077 | case D40_ROUND_EVENTLINE: |
| 1078 | BUG(); |
| 1079 | break; |
| 1080 | |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1081 | } |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1082 | } |
| 1083 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1084 | static void d40_config_set_event(struct d40_chan *d40c, |
| 1085 | enum d40_events event_type) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1086 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1087 | /* Enable event line connected to device (or memcpy) */ |
| 1088 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
| 1089 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { |
| 1090 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
| 1091 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1092 | __d40_config_set_event(d40c, event_type, event, |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1093 | D40_CHAN_REG_SSLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1094 | } |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1095 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1096 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
| 1097 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
| 1098 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1099 | __d40_config_set_event(d40c, event_type, event, |
Rabin Vincent | 262d291 | 2011-01-25 11:18:05 +0100 | [diff] [blame] | 1100 | D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1101 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1102 | } |
| 1103 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1104 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1105 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1106 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | be8cb7d | 2010-08-09 12:07:44 +0000 | [diff] [blame] | 1107 | u32 val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1108 | |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1109 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
| 1110 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1111 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1112 | return val; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1113 | } |
| 1114 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1115 | static int |
| 1116 | __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command) |
| 1117 | { |
| 1118 | unsigned long flags; |
| 1119 | int ret = 0; |
| 1120 | u32 active_status; |
| 1121 | void __iomem *active_reg; |
| 1122 | |
| 1123 | if (d40c->phy_chan->num % 2 == 0) |
| 1124 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 1125 | else |
| 1126 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 1127 | |
| 1128 | |
| 1129 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
| 1130 | |
| 1131 | switch (command) { |
| 1132 | case D40_DMA_STOP: |
| 1133 | case D40_DMA_SUSPEND_REQ: |
| 1134 | |
| 1135 | active_status = (readl(active_reg) & |
| 1136 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1137 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1138 | |
| 1139 | if (active_status == D40_DMA_RUN) |
| 1140 | d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE); |
| 1141 | else |
| 1142 | d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE); |
| 1143 | |
| 1144 | if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP)) |
| 1145 | ret = __d40_execute_command_phy(d40c, command); |
| 1146 | |
| 1147 | break; |
| 1148 | |
| 1149 | case D40_DMA_RUN: |
| 1150 | |
| 1151 | d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE); |
| 1152 | ret = __d40_execute_command_phy(d40c, command); |
| 1153 | break; |
| 1154 | |
| 1155 | case D40_DMA_SUSPENDED: |
| 1156 | BUG(); |
| 1157 | break; |
| 1158 | } |
| 1159 | |
| 1160 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); |
| 1161 | return ret; |
| 1162 | } |
| 1163 | |
| 1164 | static int d40_channel_execute_command(struct d40_chan *d40c, |
| 1165 | enum d40_command command) |
| 1166 | { |
| 1167 | if (chan_is_logical(d40c)) |
| 1168 | return __d40_execute_command_log(d40c, command); |
| 1169 | else |
| 1170 | return __d40_execute_command_phy(d40c, command); |
| 1171 | } |
| 1172 | |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1173 | static u32 d40_get_prmo(struct d40_chan *d40c) |
| 1174 | { |
| 1175 | static const unsigned int phy_map[] = { |
| 1176 | [STEDMA40_PCHAN_BASIC_MODE] |
| 1177 | = D40_DREG_PRMO_PCHAN_BASIC, |
| 1178 | [STEDMA40_PCHAN_MODULO_MODE] |
| 1179 | = D40_DREG_PRMO_PCHAN_MODULO, |
| 1180 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] |
| 1181 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, |
| 1182 | }; |
| 1183 | static const unsigned int log_map[] = { |
| 1184 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] |
| 1185 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, |
| 1186 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] |
| 1187 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, |
| 1188 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] |
| 1189 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, |
| 1190 | }; |
| 1191 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1192 | if (chan_is_physical(d40c)) |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1193 | return phy_map[d40c->dma_cfg.mode_opt]; |
| 1194 | else |
| 1195 | return log_map[d40c->dma_cfg.mode_opt]; |
| 1196 | } |
| 1197 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1198 | static void d40_config_write(struct d40_chan *d40c) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1199 | { |
| 1200 | u32 addr_base; |
| 1201 | u32 var; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1202 | |
| 1203 | /* Odd addresses are even addresses + 4 */ |
| 1204 | addr_base = (d40c->phy_chan->num % 2) * 4; |
| 1205 | /* Setup channel mode to logical or physical */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1206 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1207 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1208 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); |
| 1209 | |
| 1210 | /* Setup operational mode option register */ |
Rabin Vincent | 20a5b6d | 2010-10-12 13:00:52 +0000 | [diff] [blame] | 1211 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1212 | |
| 1213 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); |
| 1214 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1215 | if (chan_is_logical(d40c)) { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1216 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
| 1217 | & D40_SREG_ELEM_LOG_LIDX_MASK; |
| 1218 | void __iomem *chanbase = chan_base(d40c); |
| 1219 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1220 | /* Set default config for CFG reg */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1221 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
| 1222 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1223 | |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 1224 | /* Set LIDX for lcla */ |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1225 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
| 1226 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); |
Rabin Vincent | e9f3a49 | 2011-12-28 11:27:40 +0530 | [diff] [blame] | 1227 | |
| 1228 | /* Clear LNK which will be used by d40_chan_has_events() */ |
| 1229 | writel(0, chanbase + D40_CHAN_REG_SSLNK); |
| 1230 | writel(0, chanbase + D40_CHAN_REG_SDLNK); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1231 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1232 | } |
| 1233 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1234 | static u32 d40_residue(struct d40_chan *d40c) |
| 1235 | { |
| 1236 | u32 num_elt; |
| 1237 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1238 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1239 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
| 1240 | >> D40_MEM_LCSP2_ECNT_POS; |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1241 | else { |
| 1242 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); |
| 1243 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) |
| 1244 | >> D40_SREG_ELEM_PHY_ECNT_POS; |
| 1245 | } |
| 1246 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1247 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
| 1248 | } |
| 1249 | |
| 1250 | static bool d40_tx_is_linked(struct d40_chan *d40c) |
| 1251 | { |
| 1252 | bool is_link; |
| 1253 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1254 | if (chan_is_logical(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1255 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
| 1256 | else |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1257 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
| 1258 | & D40_SREG_LNK_PHYS_LNK_MASK; |
| 1259 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1260 | return is_link; |
| 1261 | } |
| 1262 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1263 | static int d40_pause(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1264 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1265 | int res = 0; |
| 1266 | unsigned long flags; |
| 1267 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1268 | if (!d40c->busy) |
| 1269 | return 0; |
| 1270 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1271 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1272 | spin_lock_irqsave(&d40c->lock, flags); |
| 1273 | |
| 1274 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1275 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1276 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1277 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1278 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1279 | return res; |
| 1280 | } |
| 1281 | |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 1282 | static int d40_resume(struct d40_chan *d40c) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1283 | { |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1284 | int res = 0; |
| 1285 | unsigned long flags; |
| 1286 | |
Jonas Aaberg | 3ac012a | 2010-08-09 12:09:12 +0000 | [diff] [blame] | 1287 | if (!d40c->busy) |
| 1288 | return 0; |
| 1289 | |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1290 | spin_lock_irqsave(&d40c->lock, flags); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1291 | pm_runtime_get_sync(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1292 | |
| 1293 | /* If bytes left to transfer or linked tx resume job */ |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1294 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1295 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1296 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1297 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1298 | pm_runtime_put_autosuspend(d40c->base->dev); |
Jonas Aaberg | aa182ae | 2010-08-09 12:08:26 +0000 | [diff] [blame] | 1299 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1300 | return res; |
| 1301 | } |
| 1302 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1303 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
| 1304 | { |
| 1305 | struct d40_chan *d40c = container_of(tx->chan, |
| 1306 | struct d40_chan, |
| 1307 | chan); |
| 1308 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); |
| 1309 | unsigned long flags; |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1310 | dma_cookie_t cookie; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1311 | |
| 1312 | spin_lock_irqsave(&d40c->lock, flags); |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1313 | cookie = dma_cookie_assign(tx); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1314 | d40_desc_queue(d40c, d40d); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1315 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1316 | |
Russell King - ARM Linux | 884485e | 2012-03-06 22:34:46 +0000 | [diff] [blame] | 1317 | return cookie; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1318 | } |
| 1319 | |
| 1320 | static int d40_start(struct d40_chan *d40c) |
| 1321 | { |
Jonas Aaberg | 0c32269 | 2010-06-20 21:25:46 +0000 | [diff] [blame] | 1322 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1323 | } |
| 1324 | |
| 1325 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) |
| 1326 | { |
| 1327 | struct d40_desc *d40d; |
| 1328 | int err; |
| 1329 | |
| 1330 | /* Start queued jobs, if any */ |
| 1331 | d40d = d40_first_queued(d40c); |
| 1332 | |
| 1333 | if (d40d != NULL) { |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1334 | if (!d40c->busy) { |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1335 | d40c->busy = true; |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1336 | pm_runtime_get_sync(d40c->base->dev); |
| 1337 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1338 | |
| 1339 | /* Remove from queue */ |
| 1340 | d40_desc_remove(d40d); |
| 1341 | |
| 1342 | /* Add to active queue */ |
| 1343 | d40_desc_submit(d40c, d40d); |
| 1344 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1345 | /* Initiate DMA job */ |
| 1346 | d40_desc_load(d40c, d40d); |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 1347 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1348 | /* Start dma job */ |
| 1349 | err = d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1350 | |
Rabin Vincent | 7d83a85 | 2011-01-25 11:18:06 +0100 | [diff] [blame] | 1351 | if (err) |
| 1352 | return NULL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1353 | } |
| 1354 | |
| 1355 | return d40d; |
| 1356 | } |
| 1357 | |
| 1358 | /* called from interrupt context */ |
| 1359 | static void dma_tc_handle(struct d40_chan *d40c) |
| 1360 | { |
| 1361 | struct d40_desc *d40d; |
| 1362 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1363 | /* Get first active entry from list */ |
| 1364 | d40d = d40_first_active_get(d40c); |
| 1365 | |
| 1366 | if (d40d == NULL) |
| 1367 | return; |
| 1368 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1369 | if (d40d->cyclic) { |
| 1370 | /* |
| 1371 | * If this was a paritially loaded list, we need to reloaded |
| 1372 | * it, and only when the list is completed. We need to check |
| 1373 | * for done because the interrupt will hit for every link, and |
| 1374 | * not just the last one. |
| 1375 | */ |
| 1376 | if (d40d->lli_current < d40d->lli_len |
| 1377 | && !d40_tx_is_linked(d40c) |
| 1378 | && !d40_residue(d40c)) { |
| 1379 | d40_lcla_free_all(d40c, d40d); |
| 1380 | d40_desc_load(d40c, d40d); |
| 1381 | (void) d40_start(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1382 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1383 | if (d40d->lli_current == d40d->lli_len) |
| 1384 | d40d->lli_current = 0; |
| 1385 | } |
| 1386 | } else { |
| 1387 | d40_lcla_free_all(d40c, d40d); |
| 1388 | |
| 1389 | if (d40d->lli_current < d40d->lli_len) { |
| 1390 | d40_desc_load(d40c, d40d); |
| 1391 | /* Start dma job */ |
| 1392 | (void) d40_start(d40c); |
| 1393 | return; |
| 1394 | } |
| 1395 | |
| 1396 | if (d40_queue_start(d40c) == NULL) |
| 1397 | d40c->busy = false; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1398 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1399 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1400 | } |
| 1401 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1402 | d40c->pending_tx++; |
| 1403 | tasklet_schedule(&d40c->tasklet); |
| 1404 | |
| 1405 | } |
| 1406 | |
| 1407 | static void dma_tasklet(unsigned long data) |
| 1408 | { |
| 1409 | struct d40_chan *d40c = (struct d40_chan *) data; |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1410 | struct d40_desc *d40d; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1411 | unsigned long flags; |
| 1412 | dma_async_tx_callback callback; |
| 1413 | void *callback_param; |
| 1414 | |
| 1415 | spin_lock_irqsave(&d40c->lock, flags); |
| 1416 | |
| 1417 | /* Get first active entry from list */ |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1418 | d40d = d40_first_active_get(d40c); |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1419 | if (d40d == NULL) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1420 | goto err; |
| 1421 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1422 | if (!d40d->cyclic) |
Russell King - ARM Linux | f7fbce0 | 2012-03-06 22:35:07 +0000 | [diff] [blame] | 1423 | dma_cookie_complete(&d40d->txd); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1424 | |
| 1425 | /* |
| 1426 | * If terminating a channel pending_tx is set to zero. |
| 1427 | * This prevents any finished active jobs to return to the client. |
| 1428 | */ |
| 1429 | if (d40c->pending_tx == 0) { |
| 1430 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1431 | return; |
| 1432 | } |
| 1433 | |
| 1434 | /* Callback to client */ |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1435 | callback = d40d->txd.callback; |
| 1436 | callback_param = d40d->txd.callback_param; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1437 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1438 | if (!d40d->cyclic) { |
| 1439 | if (async_tx_test_ack(&d40d->txd)) { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1440 | d40_desc_remove(d40d); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 1441 | d40_desc_free(d40c, d40d); |
| 1442 | } else { |
| 1443 | if (!d40d->is_in_client_list) { |
| 1444 | d40_desc_remove(d40d); |
| 1445 | d40_lcla_free_all(d40c, d40d); |
| 1446 | list_add_tail(&d40d->node, &d40c->client); |
| 1447 | d40d->is_in_client_list = true; |
| 1448 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1449 | } |
| 1450 | } |
| 1451 | |
| 1452 | d40c->pending_tx--; |
| 1453 | |
| 1454 | if (d40c->pending_tx) |
| 1455 | tasklet_schedule(&d40c->tasklet); |
| 1456 | |
| 1457 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1458 | |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 1459 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1460 | callback(callback_param); |
| 1461 | |
| 1462 | return; |
| 1463 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1464 | err: |
| 1465 | /* Rescue manouver if receiving double interrupts */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1466 | if (d40c->pending_tx > 0) |
| 1467 | d40c->pending_tx--; |
| 1468 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1469 | } |
| 1470 | |
| 1471 | static irqreturn_t d40_handle_interrupt(int irq, void *data) |
| 1472 | { |
| 1473 | static const struct d40_interrupt_lookup il[] = { |
| 1474 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, |
| 1475 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, |
| 1476 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, |
| 1477 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, |
| 1478 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, |
| 1479 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, |
| 1480 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, |
| 1481 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, |
| 1482 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, |
| 1483 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, |
| 1484 | }; |
| 1485 | |
| 1486 | int i; |
| 1487 | u32 regs[ARRAY_SIZE(il)]; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1488 | u32 idx; |
| 1489 | u32 row; |
| 1490 | long chan = -1; |
| 1491 | struct d40_chan *d40c; |
| 1492 | unsigned long flags; |
| 1493 | struct d40_base *base = data; |
| 1494 | |
| 1495 | spin_lock_irqsave(&base->interrupt_lock, flags); |
| 1496 | |
| 1497 | /* Read interrupt status of both logical and physical channels */ |
| 1498 | for (i = 0; i < ARRAY_SIZE(il); i++) |
| 1499 | regs[i] = readl(base->virtbase + il[i].src); |
| 1500 | |
| 1501 | for (;;) { |
| 1502 | |
| 1503 | chan = find_next_bit((unsigned long *)regs, |
| 1504 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); |
| 1505 | |
| 1506 | /* No more set bits found? */ |
| 1507 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) |
| 1508 | break; |
| 1509 | |
| 1510 | row = chan / BITS_PER_LONG; |
| 1511 | idx = chan & (BITS_PER_LONG - 1); |
| 1512 | |
| 1513 | /* ACK interrupt */ |
Jonas Aaberg | 1b00348 | 2010-08-09 12:07:54 +0000 | [diff] [blame] | 1514 | writel(1 << idx, base->virtbase + il[row].clr); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1515 | |
| 1516 | if (il[row].offset == D40_PHY_CHAN) |
| 1517 | d40c = base->lookup_phy_chans[idx]; |
| 1518 | else |
| 1519 | d40c = base->lookup_log_chans[il[row].offset + idx]; |
| 1520 | spin_lock(&d40c->lock); |
| 1521 | |
| 1522 | if (!il[row].is_error) |
| 1523 | dma_tc_handle(d40c); |
| 1524 | else |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1525 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
| 1526 | chan, il[row].offset, idx); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1527 | |
| 1528 | spin_unlock(&d40c->lock); |
| 1529 | } |
| 1530 | |
| 1531 | spin_unlock_irqrestore(&base->interrupt_lock, flags); |
| 1532 | |
| 1533 | return IRQ_HANDLED; |
| 1534 | } |
| 1535 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1536 | static int d40_validate_conf(struct d40_chan *d40c, |
| 1537 | struct stedma40_chan_cfg *conf) |
| 1538 | { |
| 1539 | int res = 0; |
| 1540 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); |
| 1541 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1542 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1543 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1544 | if (!conf->dir) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1545 | chan_err(d40c, "Invalid direction.\n"); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1546 | res = -EINVAL; |
| 1547 | } |
| 1548 | |
| 1549 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && |
| 1550 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && |
| 1551 | d40c->runtime_addr == 0) { |
| 1552 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1553 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
| 1554 | conf->dst_dev_type); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1555 | res = -EINVAL; |
| 1556 | } |
| 1557 | |
| 1558 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && |
| 1559 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && |
| 1560 | d40c->runtime_addr == 0) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1561 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
| 1562 | conf->src_dev_type); |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1563 | res = -EINVAL; |
| 1564 | } |
| 1565 | |
| 1566 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1567 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1568 | chan_err(d40c, "Invalid dst\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1569 | res = -EINVAL; |
| 1570 | } |
| 1571 | |
Linus Walleij | 0747c7ba | 2010-08-09 12:07:36 +0000 | [diff] [blame] | 1572 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1573 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1574 | chan_err(d40c, "Invalid src\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1575 | res = -EINVAL; |
| 1576 | } |
| 1577 | |
| 1578 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && |
| 1579 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1580 | chan_err(d40c, "No event line\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1581 | res = -EINVAL; |
| 1582 | } |
| 1583 | |
| 1584 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && |
| 1585 | (src_event_group != dst_event_group)) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1586 | chan_err(d40c, "Invalid event group\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1587 | res = -EINVAL; |
| 1588 | } |
| 1589 | |
| 1590 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { |
| 1591 | /* |
| 1592 | * DMAC HW supports it. Will be added to this driver, |
| 1593 | * in case any dma client requires it. |
| 1594 | */ |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1595 | chan_err(d40c, "periph to periph not supported\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1596 | res = -EINVAL; |
| 1597 | } |
| 1598 | |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1599 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
| 1600 | (1 << conf->src_info.data_width) != |
| 1601 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * |
| 1602 | (1 << conf->dst_info.data_width)) { |
| 1603 | /* |
| 1604 | * The DMAC hardware only supports |
| 1605 | * src (burst x width) == dst (burst x width) |
| 1606 | */ |
| 1607 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1608 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
Per Forlin | d49278e | 2010-12-20 18:31:38 +0100 | [diff] [blame] | 1609 | res = -EINVAL; |
| 1610 | } |
| 1611 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1612 | return res; |
| 1613 | } |
| 1614 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1615 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, |
| 1616 | bool is_src, int log_event_line, bool is_log, |
| 1617 | bool *first_user) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1618 | { |
| 1619 | unsigned long flags; |
| 1620 | spin_lock_irqsave(&phy->lock, flags); |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1621 | |
| 1622 | *first_user = ((phy->allocated_src | phy->allocated_dst) |
| 1623 | == D40_ALLOC_FREE); |
| 1624 | |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1625 | if (!is_log) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1626 | /* Physical interrupts are masked per physical full channel */ |
| 1627 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 1628 | phy->allocated_dst == D40_ALLOC_FREE) { |
| 1629 | phy->allocated_dst = D40_ALLOC_PHY; |
| 1630 | phy->allocated_src = D40_ALLOC_PHY; |
| 1631 | goto found; |
| 1632 | } else |
| 1633 | goto not_found; |
| 1634 | } |
| 1635 | |
| 1636 | /* Logical channel */ |
| 1637 | if (is_src) { |
| 1638 | if (phy->allocated_src == D40_ALLOC_PHY) |
| 1639 | goto not_found; |
| 1640 | |
| 1641 | if (phy->allocated_src == D40_ALLOC_FREE) |
| 1642 | phy->allocated_src = D40_ALLOC_LOG_FREE; |
| 1643 | |
| 1644 | if (!(phy->allocated_src & (1 << log_event_line))) { |
| 1645 | phy->allocated_src |= 1 << log_event_line; |
| 1646 | goto found; |
| 1647 | } else |
| 1648 | goto not_found; |
| 1649 | } else { |
| 1650 | if (phy->allocated_dst == D40_ALLOC_PHY) |
| 1651 | goto not_found; |
| 1652 | |
| 1653 | if (phy->allocated_dst == D40_ALLOC_FREE) |
| 1654 | phy->allocated_dst = D40_ALLOC_LOG_FREE; |
| 1655 | |
| 1656 | if (!(phy->allocated_dst & (1 << log_event_line))) { |
| 1657 | phy->allocated_dst |= 1 << log_event_line; |
| 1658 | goto found; |
| 1659 | } else |
| 1660 | goto not_found; |
| 1661 | } |
| 1662 | |
| 1663 | not_found: |
| 1664 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1665 | return false; |
| 1666 | found: |
| 1667 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1668 | return true; |
| 1669 | } |
| 1670 | |
| 1671 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, |
| 1672 | int log_event_line) |
| 1673 | { |
| 1674 | unsigned long flags; |
| 1675 | bool is_free = false; |
| 1676 | |
| 1677 | spin_lock_irqsave(&phy->lock, flags); |
| 1678 | if (!log_event_line) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1679 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1680 | phy->allocated_src = D40_ALLOC_FREE; |
| 1681 | is_free = true; |
| 1682 | goto out; |
| 1683 | } |
| 1684 | |
| 1685 | /* Logical channel */ |
| 1686 | if (is_src) { |
| 1687 | phy->allocated_src &= ~(1 << log_event_line); |
| 1688 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) |
| 1689 | phy->allocated_src = D40_ALLOC_FREE; |
| 1690 | } else { |
| 1691 | phy->allocated_dst &= ~(1 << log_event_line); |
| 1692 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) |
| 1693 | phy->allocated_dst = D40_ALLOC_FREE; |
| 1694 | } |
| 1695 | |
| 1696 | is_free = ((phy->allocated_src | phy->allocated_dst) == |
| 1697 | D40_ALLOC_FREE); |
| 1698 | |
| 1699 | out: |
| 1700 | spin_unlock_irqrestore(&phy->lock, flags); |
| 1701 | |
| 1702 | return is_free; |
| 1703 | } |
| 1704 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1705 | static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1706 | { |
| 1707 | int dev_type; |
| 1708 | int event_group; |
| 1709 | int event_line; |
| 1710 | struct d40_phy_res *phys; |
| 1711 | int i; |
| 1712 | int j; |
| 1713 | int log_num; |
| 1714 | bool is_src; |
Rabin Vincent | 38bdbf0 | 2010-10-12 13:00:51 +0000 | [diff] [blame] | 1715 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1716 | |
| 1717 | phys = d40c->base->phy_res; |
| 1718 | |
| 1719 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
| 1720 | dev_type = d40c->dma_cfg.src_dev_type; |
| 1721 | log_num = 2 * dev_type; |
| 1722 | is_src = true; |
| 1723 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
| 1724 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1725 | /* dst event lines are used for logical memcpy */ |
| 1726 | dev_type = d40c->dma_cfg.dst_dev_type; |
| 1727 | log_num = 2 * dev_type + 1; |
| 1728 | is_src = false; |
| 1729 | } else |
| 1730 | return -EINVAL; |
| 1731 | |
| 1732 | event_group = D40_TYPE_TO_GROUP(dev_type); |
| 1733 | event_line = D40_TYPE_TO_EVENT(dev_type); |
| 1734 | |
| 1735 | if (!is_log) { |
| 1736 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1737 | /* Find physical half channel */ |
| 1738 | for (i = 0; i < d40c->base->num_phy_chans; i++) { |
| 1739 | |
Marcin Mielczarczyk | 4aed79b | 2010-05-18 00:41:21 +0200 | [diff] [blame] | 1740 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1741 | 0, is_log, |
| 1742 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1743 | goto found_phy; |
| 1744 | } |
| 1745 | } else |
| 1746 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1747 | int phy_num = j + event_group * 2; |
| 1748 | for (i = phy_num; i < phy_num + 2; i++) { |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 1749 | if (d40_alloc_mask_set(&phys[i], |
| 1750 | is_src, |
| 1751 | 0, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1752 | is_log, |
| 1753 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1754 | goto found_phy; |
| 1755 | } |
| 1756 | } |
| 1757 | return -EINVAL; |
| 1758 | found_phy: |
| 1759 | d40c->phy_chan = &phys[i]; |
| 1760 | d40c->log_num = D40_PHY_CHAN; |
| 1761 | goto out; |
| 1762 | } |
| 1763 | if (dev_type == -1) |
| 1764 | return -EINVAL; |
| 1765 | |
| 1766 | /* Find logical channel */ |
| 1767 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { |
| 1768 | int phy_num = j + event_group * 2; |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1769 | |
| 1770 | if (d40c->dma_cfg.use_fixed_channel) { |
| 1771 | i = d40c->dma_cfg.phy_channel; |
| 1772 | |
| 1773 | if ((i != phy_num) && (i != phy_num + 1)) { |
| 1774 | dev_err(chan2dev(d40c), |
| 1775 | "invalid fixed phy channel %d\n", i); |
| 1776 | return -EINVAL; |
| 1777 | } |
| 1778 | |
| 1779 | if (d40_alloc_mask_set(&phys[i], is_src, event_line, |
| 1780 | is_log, first_phy_user)) |
| 1781 | goto found_log; |
| 1782 | |
| 1783 | dev_err(chan2dev(d40c), |
| 1784 | "could not allocate fixed phy channel %d\n", i); |
| 1785 | return -EINVAL; |
| 1786 | } |
| 1787 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1788 | /* |
| 1789 | * Spread logical channels across all available physical rather |
| 1790 | * than pack every logical channel at the first available phy |
| 1791 | * channels. |
| 1792 | */ |
| 1793 | if (is_src) { |
| 1794 | for (i = phy_num; i < phy_num + 2; i++) { |
| 1795 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1796 | event_line, is_log, |
| 1797 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1798 | goto found_log; |
| 1799 | } |
| 1800 | } else { |
| 1801 | for (i = phy_num + 1; i >= phy_num; i--) { |
| 1802 | if (d40_alloc_mask_set(&phys[i], is_src, |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 1803 | event_line, is_log, |
| 1804 | first_phy_user)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1805 | goto found_log; |
| 1806 | } |
| 1807 | } |
| 1808 | } |
| 1809 | return -EINVAL; |
| 1810 | |
| 1811 | found_log: |
| 1812 | d40c->phy_chan = &phys[i]; |
| 1813 | d40c->log_num = log_num; |
| 1814 | out: |
| 1815 | |
| 1816 | if (is_log) |
| 1817 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; |
| 1818 | else |
| 1819 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; |
| 1820 | |
| 1821 | return 0; |
| 1822 | |
| 1823 | } |
| 1824 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1825 | static int d40_config_memcpy(struct d40_chan *d40c) |
| 1826 | { |
| 1827 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; |
| 1828 | |
| 1829 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { |
| 1830 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; |
| 1831 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; |
| 1832 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> |
| 1833 | memcpy[d40c->chan.chan_id]; |
| 1834 | |
| 1835 | } else if (dma_has_cap(DMA_MEMCPY, cap) && |
| 1836 | dma_has_cap(DMA_SLAVE, cap)) { |
| 1837 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; |
| 1838 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1839 | chan_err(d40c, "No memcpy\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1840 | return -EINVAL; |
| 1841 | } |
| 1842 | |
| 1843 | return 0; |
| 1844 | } |
| 1845 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1846 | static int d40_free_dma(struct d40_chan *d40c) |
| 1847 | { |
| 1848 | |
| 1849 | int res = 0; |
Jonas Aaberg | d181b3a | 2010-06-20 21:26:38 +0000 | [diff] [blame] | 1850 | u32 event; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1851 | struct d40_phy_res *phy = d40c->phy_chan; |
| 1852 | bool is_src; |
| 1853 | |
| 1854 | /* Terminate all queued and active transfers */ |
| 1855 | d40_term_all(d40c); |
| 1856 | |
| 1857 | if (phy == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1858 | chan_err(d40c, "phy == null\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1859 | return -EINVAL; |
| 1860 | } |
| 1861 | |
| 1862 | if (phy->allocated_src == D40_ALLOC_FREE && |
| 1863 | phy->allocated_dst == D40_ALLOC_FREE) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1864 | chan_err(d40c, "channel already free\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1865 | return -EINVAL; |
| 1866 | } |
| 1867 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1868 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
| 1869 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
| 1870 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1871 | is_src = false; |
| 1872 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
| 1873 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1874 | is_src = true; |
| 1875 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1876 | chan_err(d40c, "Unknown direction\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1877 | return -EINVAL; |
| 1878 | } |
| 1879 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1880 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1881 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); |
| 1882 | if (res) { |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1883 | chan_err(d40c, "stop failed\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1884 | goto out; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1885 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1886 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 1887 | d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0); |
| 1888 | |
| 1889 | if (chan_is_logical(d40c)) |
| 1890 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
| 1891 | else |
| 1892 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
| 1893 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1894 | if (d40c->busy) { |
| 1895 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1896 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 1897 | } |
| 1898 | |
| 1899 | d40c->busy = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1900 | d40c->phy_chan = NULL; |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 1901 | d40c->configured = false; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1902 | out: |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1903 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 1904 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 1905 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 1906 | return res; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1907 | } |
| 1908 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1909 | static bool d40_is_paused(struct d40_chan *d40c) |
| 1910 | { |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1911 | void __iomem *chanbase = chan_base(d40c); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1912 | bool is_paused = false; |
| 1913 | unsigned long flags; |
| 1914 | void __iomem *active_reg; |
| 1915 | u32 status; |
| 1916 | u32 event; |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1917 | |
| 1918 | spin_lock_irqsave(&d40c->lock, flags); |
| 1919 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 1920 | if (chan_is_physical(d40c)) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1921 | if (d40c->phy_chan->num % 2 == 0) |
| 1922 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; |
| 1923 | else |
| 1924 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; |
| 1925 | |
| 1926 | status = (readl(active_reg) & |
| 1927 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> |
| 1928 | D40_CHAN_POS(d40c->phy_chan->num); |
| 1929 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) |
| 1930 | is_paused = true; |
| 1931 | |
| 1932 | goto _exit; |
| 1933 | } |
| 1934 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1935 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1936 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1937 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1938 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1939 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1940 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
Rabin Vincent | 8ca8468 | 2011-01-25 11:18:07 +0100 | [diff] [blame] | 1941 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1942 | } else { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 1943 | chan_err(d40c, "Unknown direction\n"); |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1944 | goto _exit; |
| 1945 | } |
Jonas Aaberg | 9dbfbd35c | 2010-08-09 12:08:41 +0000 | [diff] [blame] | 1946 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1947 | status = (status & D40_EVENTLINE_MASK(event)) >> |
| 1948 | D40_EVENTLINE_POS(event); |
| 1949 | |
| 1950 | if (status != D40_DMA_RUN) |
| 1951 | is_paused = true; |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 1952 | _exit: |
| 1953 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1954 | return is_paused; |
| 1955 | |
| 1956 | } |
| 1957 | |
| 1958 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 1959 | static u32 stedma40_residue(struct dma_chan *chan) |
| 1960 | { |
| 1961 | struct d40_chan *d40c = |
| 1962 | container_of(chan, struct d40_chan, chan); |
| 1963 | u32 bytes_left; |
| 1964 | unsigned long flags; |
| 1965 | |
| 1966 | spin_lock_irqsave(&d40c->lock, flags); |
| 1967 | bytes_left = d40_residue(d40c); |
| 1968 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 1969 | |
| 1970 | return bytes_left; |
| 1971 | } |
| 1972 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1973 | static int |
| 1974 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, |
| 1975 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 1976 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 1977 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1978 | { |
| 1979 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 1980 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 1981 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1982 | int ret; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1983 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1984 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
| 1985 | src_dev_addr, |
| 1986 | desc->lli_log.src, |
| 1987 | chan->log_def.lcsp1, |
| 1988 | src_info->data_width, |
| 1989 | dst_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1990 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1991 | ret = d40_log_sg_to_lli(sg_dst, sg_len, |
| 1992 | dst_dev_addr, |
| 1993 | desc->lli_log.dst, |
| 1994 | chan->log_def.lcsp3, |
| 1995 | dst_info->data_width, |
| 1996 | src_info->data_width); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1997 | |
Rabin Vincent | 5ed04b8 | 2011-01-25 11:18:26 +0100 | [diff] [blame] | 1998 | return ret < 0 ? ret : 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 1999 | } |
| 2000 | |
| 2001 | static int |
| 2002 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, |
| 2003 | struct scatterlist *sg_src, struct scatterlist *sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2004 | unsigned int sg_len, dma_addr_t src_dev_addr, |
| 2005 | dma_addr_t dst_dev_addr) |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2006 | { |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2007 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 2008 | struct stedma40_half_channel_info *src_info = &cfg->src_info; |
| 2009 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2010 | unsigned long flags = 0; |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2011 | int ret; |
| 2012 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2013 | if (desc->cyclic) |
| 2014 | flags |= LLI_CYCLIC | LLI_TERM_INT; |
| 2015 | |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2016 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
| 2017 | desc->lli_phy.src, |
| 2018 | virt_to_phys(desc->lli_phy.src), |
| 2019 | chan->src_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2020 | src_info, dst_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2021 | |
| 2022 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, |
| 2023 | desc->lli_phy.dst, |
| 2024 | virt_to_phys(desc->lli_phy.dst), |
| 2025 | chan->dst_def_cfg, |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2026 | dst_info, src_info, flags); |
Rabin Vincent | 3e3a076 | 2011-01-25 11:18:21 +0100 | [diff] [blame] | 2027 | |
| 2028 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, |
| 2029 | desc->lli_pool.size, DMA_TO_DEVICE); |
| 2030 | |
| 2031 | return ret < 0 ? ret : 0; |
| 2032 | } |
| 2033 | |
| 2034 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2035 | static struct d40_desc * |
| 2036 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, |
| 2037 | unsigned int sg_len, unsigned long dma_flags) |
| 2038 | { |
| 2039 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
| 2040 | struct d40_desc *desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2041 | int ret; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2042 | |
| 2043 | desc = d40_desc_get(chan); |
| 2044 | if (!desc) |
| 2045 | return NULL; |
| 2046 | |
| 2047 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, |
| 2048 | cfg->dst_info.data_width); |
| 2049 | if (desc->lli_len < 0) { |
| 2050 | chan_err(chan, "Unaligned size\n"); |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2051 | goto err; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2052 | } |
| 2053 | |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2054 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
| 2055 | if (ret < 0) { |
| 2056 | chan_err(chan, "Could not allocate lli\n"); |
| 2057 | goto err; |
| 2058 | } |
| 2059 | |
| 2060 | |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2061 | desc->lli_current = 0; |
| 2062 | desc->txd.flags = dma_flags; |
| 2063 | desc->txd.tx_submit = d40_tx_submit; |
| 2064 | |
| 2065 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); |
| 2066 | |
| 2067 | return desc; |
Rabin Vincent | dbd8878 | 2011-01-25 11:18:19 +0100 | [diff] [blame] | 2068 | |
| 2069 | err: |
| 2070 | d40_desc_free(chan, desc); |
| 2071 | return NULL; |
Rabin Vincent | 5f81158 | 2011-01-25 11:18:18 +0100 | [diff] [blame] | 2072 | } |
| 2073 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2074 | static dma_addr_t |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2075 | d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2076 | { |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2077 | struct stedma40_platform_data *plat = chan->base->plat_data; |
| 2078 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
Philippe Langlais | 711b9ce | 2011-05-07 17:09:43 +0200 | [diff] [blame] | 2079 | dma_addr_t addr = 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2080 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2081 | if (chan->runtime_addr) |
| 2082 | return chan->runtime_addr; |
| 2083 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2084 | if (direction == DMA_DEV_TO_MEM) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2085 | addr = plat->dev_rx[cfg->src_dev_type]; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2086 | else if (direction == DMA_MEM_TO_DEV) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2087 | addr = plat->dev_tx[cfg->dst_dev_type]; |
| 2088 | |
| 2089 | return addr; |
| 2090 | } |
| 2091 | |
| 2092 | static struct dma_async_tx_descriptor * |
| 2093 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, |
| 2094 | struct scatterlist *sg_dst, unsigned int sg_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2095 | enum dma_transfer_direction direction, unsigned long dma_flags) |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2096 | { |
| 2097 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2098 | dma_addr_t src_dev_addr = 0; |
| 2099 | dma_addr_t dst_dev_addr = 0; |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2100 | struct d40_desc *desc; |
| 2101 | unsigned long flags; |
| 2102 | int ret; |
| 2103 | |
| 2104 | if (!chan->phy_chan) { |
| 2105 | chan_err(chan, "Cannot prepare unallocated channel\n"); |
| 2106 | return NULL; |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2107 | } |
| 2108 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2109 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2110 | spin_lock_irqsave(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2111 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2112 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
| 2113 | if (desc == NULL) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2114 | goto err; |
| 2115 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2116 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
| 2117 | desc->cyclic = true; |
| 2118 | |
Linus Walleij | 7e426da | 2012-04-12 18:12:52 +0200 | [diff] [blame] | 2119 | if (direction != DMA_TRANS_NONE) { |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2120 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); |
| 2121 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2122 | if (direction == DMA_DEV_TO_MEM) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2123 | src_dev_addr = dev_addr; |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2124 | else if (direction == DMA_MEM_TO_DEV) |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2125 | dst_dev_addr = dev_addr; |
| 2126 | } |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2127 | |
| 2128 | if (chan_is_logical(chan)) |
| 2129 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2130 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2131 | else |
| 2132 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, |
Rabin Vincent | 822c567 | 2011-01-25 11:18:28 +0100 | [diff] [blame] | 2133 | sg_len, src_dev_addr, dst_dev_addr); |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2134 | |
| 2135 | if (ret) { |
| 2136 | chan_err(chan, "Failed to prepare %s sg job: %d\n", |
| 2137 | chan_is_logical(chan) ? "log" : "phy", ret); |
| 2138 | goto err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2139 | } |
| 2140 | |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2141 | /* |
| 2142 | * add descriptor to the prepare queue in order to be able |
| 2143 | * to free them later in terminate_all |
| 2144 | */ |
| 2145 | list_add_tail(&desc->node, &chan->prepare_queue); |
| 2146 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2147 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2148 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2149 | return &desc->txd; |
| 2150 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2151 | err: |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2152 | if (desc) |
| 2153 | d40_desc_free(chan, desc); |
| 2154 | spin_unlock_irqrestore(&chan->lock, flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2155 | return NULL; |
| 2156 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2157 | |
| 2158 | bool stedma40_filter(struct dma_chan *chan, void *data) |
| 2159 | { |
| 2160 | struct stedma40_chan_cfg *info = data; |
| 2161 | struct d40_chan *d40c = |
| 2162 | container_of(chan, struct d40_chan, chan); |
| 2163 | int err; |
| 2164 | |
| 2165 | if (data) { |
| 2166 | err = d40_validate_conf(d40c, info); |
| 2167 | if (!err) |
| 2168 | d40c->dma_cfg = *info; |
| 2169 | } else |
| 2170 | err = d40_config_memcpy(d40c); |
| 2171 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2172 | if (!err) |
| 2173 | d40c->configured = true; |
| 2174 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2175 | return err == 0; |
| 2176 | } |
| 2177 | EXPORT_SYMBOL(stedma40_filter); |
| 2178 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2179 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
| 2180 | { |
| 2181 | bool realtime = d40c->dma_cfg.realtime; |
| 2182 | bool highprio = d40c->dma_cfg.high_priority; |
| 2183 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; |
| 2184 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; |
| 2185 | u32 event = D40_TYPE_TO_EVENT(dev_type); |
| 2186 | u32 group = D40_TYPE_TO_GROUP(dev_type); |
| 2187 | u32 bit = 1 << event; |
| 2188 | |
| 2189 | /* Destination event lines are stored in the upper halfword */ |
| 2190 | if (!src) |
| 2191 | bit <<= 16; |
| 2192 | |
| 2193 | writel(bit, d40c->base->virtbase + prioreg + group * 4); |
| 2194 | writel(bit, d40c->base->virtbase + rtreg + group * 4); |
| 2195 | } |
| 2196 | |
| 2197 | static void d40_set_prio_realtime(struct d40_chan *d40c) |
| 2198 | { |
| 2199 | if (d40c->base->rev < 3) |
| 2200 | return; |
| 2201 | |
| 2202 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || |
| 2203 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
| 2204 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); |
| 2205 | |
| 2206 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || |
| 2207 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) |
| 2208 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); |
| 2209 | } |
| 2210 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2211 | /* DMA ENGINE functions */ |
| 2212 | static int d40_alloc_chan_resources(struct dma_chan *chan) |
| 2213 | { |
| 2214 | int err; |
| 2215 | unsigned long flags; |
| 2216 | struct d40_chan *d40c = |
| 2217 | container_of(chan, struct d40_chan, chan); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2218 | bool is_free_phy; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2219 | spin_lock_irqsave(&d40c->lock, flags); |
| 2220 | |
Russell King - ARM Linux | d3ee98cdc | 2012-03-06 22:35:47 +0000 | [diff] [blame] | 2221 | dma_cookie_init(chan); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2222 | |
Rabin Vincent | ce2ca12 | 2010-10-12 13:00:49 +0000 | [diff] [blame] | 2223 | /* If no dma configuration is set use default configuration (memcpy) */ |
| 2224 | if (!d40c->configured) { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2225 | err = d40_config_memcpy(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2226 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2227 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2228 | goto fail; |
| 2229 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2230 | } |
| 2231 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2232 | err = d40_allocate_channel(d40c, &is_free_phy); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2233 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2234 | chan_err(d40c, "Failed to allocate channel\n"); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2235 | d40c->configured = false; |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2236 | goto fail; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2237 | } |
| 2238 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2239 | pm_runtime_get_sync(d40c->base->dev); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2240 | /* Fill in basic CFG register values */ |
| 2241 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2242 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2243 | |
Rabin Vincent | ac2c0a3 | 2011-01-25 11:18:11 +0100 | [diff] [blame] | 2244 | d40_set_prio_realtime(d40c); |
| 2245 | |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2246 | if (chan_is_logical(d40c)) { |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2247 | d40_log_cfg(&d40c->dma_cfg, |
| 2248 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2249 | |
| 2250 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) |
| 2251 | d40c->lcpa = d40c->base->lcpa_base + |
| 2252 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; |
| 2253 | else |
| 2254 | d40c->lcpa = d40c->base->lcpa_base + |
| 2255 | d40c->dma_cfg.dst_dev_type * |
| 2256 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; |
| 2257 | } |
| 2258 | |
Narayanan G | 5cd326f | 2011-11-30 19:20:42 +0530 | [diff] [blame] | 2259 | dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", |
| 2260 | chan_is_logical(d40c) ? "logical" : "physical", |
| 2261 | d40c->phy_chan->num, |
| 2262 | d40c->dma_cfg.use_fixed_channel ? ", fixed" : ""); |
| 2263 | |
| 2264 | |
Linus Walleij | ef1872e | 2010-06-20 21:24:52 +0000 | [diff] [blame] | 2265 | /* |
| 2266 | * Only write channel configuration to the DMA if the physical |
| 2267 | * resource is free. In case of multiple logical channels |
| 2268 | * on the same physical resource, only the first write is necessary. |
| 2269 | */ |
Jonas Aaberg | b55912c | 2010-08-09 12:08:02 +0000 | [diff] [blame] | 2270 | if (is_free_phy) |
| 2271 | d40_config_write(d40c); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2272 | fail: |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2273 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2274 | pm_runtime_put_autosuspend(d40c->base->dev); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2275 | spin_unlock_irqrestore(&d40c->lock, flags); |
Jonas Aaberg | ff0b12b | 2010-06-20 21:25:15 +0000 | [diff] [blame] | 2276 | return err; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2277 | } |
| 2278 | |
| 2279 | static void d40_free_chan_resources(struct dma_chan *chan) |
| 2280 | { |
| 2281 | struct d40_chan *d40c = |
| 2282 | container_of(chan, struct d40_chan, chan); |
| 2283 | int err; |
| 2284 | unsigned long flags; |
| 2285 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2286 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2287 | chan_err(d40c, "Cannot free unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2288 | return; |
| 2289 | } |
| 2290 | |
| 2291 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2292 | spin_lock_irqsave(&d40c->lock, flags); |
| 2293 | |
| 2294 | err = d40_free_dma(d40c); |
| 2295 | |
| 2296 | if (err) |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2297 | chan_err(d40c, "Failed to free channel\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2298 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2299 | } |
| 2300 | |
| 2301 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, |
| 2302 | dma_addr_t dst, |
| 2303 | dma_addr_t src, |
| 2304 | size_t size, |
Jonas Aaberg | 2a61434 | 2010-06-20 21:25:24 +0000 | [diff] [blame] | 2305 | unsigned long dma_flags) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2306 | { |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2307 | struct scatterlist dst_sg; |
| 2308 | struct scatterlist src_sg; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2309 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2310 | sg_init_table(&dst_sg, 1); |
| 2311 | sg_init_table(&src_sg, 1); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2312 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2313 | sg_dma_address(&dst_sg) = dst; |
| 2314 | sg_dma_address(&src_sg) = src; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2315 | |
Rabin Vincent | 95944c6 | 2011-01-25 11:18:17 +0100 | [diff] [blame] | 2316 | sg_dma_len(&dst_sg) = size; |
| 2317 | sg_dma_len(&src_sg) = size; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2318 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2319 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2320 | } |
| 2321 | |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2322 | static struct dma_async_tx_descriptor * |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2323 | d40_prep_memcpy_sg(struct dma_chan *chan, |
| 2324 | struct scatterlist *dst_sg, unsigned int dst_nents, |
| 2325 | struct scatterlist *src_sg, unsigned int src_nents, |
| 2326 | unsigned long dma_flags) |
Ira Snyder | 0d68866 | 2010-09-30 11:46:47 +0000 | [diff] [blame] | 2327 | { |
| 2328 | if (dst_nents != src_nents) |
| 2329 | return NULL; |
| 2330 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2331 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2332 | } |
| 2333 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2334 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
| 2335 | struct scatterlist *sgl, |
| 2336 | unsigned int sg_len, |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2337 | enum dma_transfer_direction direction, |
Alexandre Bounine | 185ecb5 | 2012-03-08 15:35:13 -0500 | [diff] [blame] | 2338 | unsigned long dma_flags, |
| 2339 | void *context) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2340 | { |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2341 | if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) |
Rabin Vincent | 00ac034 | 2011-01-25 11:18:20 +0100 | [diff] [blame] | 2342 | return NULL; |
| 2343 | |
Rabin Vincent | cade1d3 | 2011-01-25 11:18:23 +0100 | [diff] [blame] | 2344 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2345 | } |
| 2346 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2347 | static struct dma_async_tx_descriptor * |
| 2348 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, |
| 2349 | size_t buf_len, size_t period_len, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 2350 | enum dma_transfer_direction direction, unsigned long flags, |
| 2351 | void *context) |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2352 | { |
| 2353 | unsigned int periods = buf_len / period_len; |
| 2354 | struct dma_async_tx_descriptor *txd; |
| 2355 | struct scatterlist *sg; |
| 2356 | int i; |
| 2357 | |
Robert Marklund | 79ca7ec | 2011-06-27 11:33:24 +0200 | [diff] [blame] | 2358 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2359 | for (i = 0; i < periods; i++) { |
| 2360 | sg_dma_address(&sg[i]) = dma_addr; |
| 2361 | sg_dma_len(&sg[i]) = period_len; |
| 2362 | dma_addr += period_len; |
| 2363 | } |
| 2364 | |
| 2365 | sg[periods].offset = 0; |
Lars-Peter Clausen | fdaf9c4 | 2012-04-25 20:50:52 +0200 | [diff] [blame] | 2366 | sg_dma_len(&sg[periods]) = 0; |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2367 | sg[periods].page_link = |
| 2368 | ((unsigned long)sg | 0x01) & ~0x02; |
| 2369 | |
| 2370 | txd = d40_prep_sg(chan, sg, sg, periods, direction, |
| 2371 | DMA_PREP_INTERRUPT); |
| 2372 | |
| 2373 | kfree(sg); |
| 2374 | |
| 2375 | return txd; |
| 2376 | } |
| 2377 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2378 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
| 2379 | dma_cookie_t cookie, |
| 2380 | struct dma_tx_state *txstate) |
| 2381 | { |
| 2382 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 2383 | enum dma_status ret; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2384 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2385 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2386 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2387 | return -EINVAL; |
| 2388 | } |
| 2389 | |
Russell King - ARM Linux | 96a2af4 | 2012-03-06 22:35:27 +0000 | [diff] [blame] | 2390 | ret = dma_cookie_status(chan, cookie, txstate); |
| 2391 | if (ret != DMA_SUCCESS) |
| 2392 | dma_set_residue(txstate, stedma40_residue(chan)); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2393 | |
Jonas Aaberg | a5ebca4 | 2010-05-18 00:41:09 +0200 | [diff] [blame] | 2394 | if (d40_is_paused(d40c)) |
| 2395 | ret = DMA_PAUSED; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2396 | |
| 2397 | return ret; |
| 2398 | } |
| 2399 | |
| 2400 | static void d40_issue_pending(struct dma_chan *chan) |
| 2401 | { |
| 2402 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2403 | unsigned long flags; |
| 2404 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2405 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2406 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2407 | return; |
| 2408 | } |
| 2409 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2410 | spin_lock_irqsave(&d40c->lock, flags); |
| 2411 | |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2412 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
| 2413 | |
| 2414 | /* Busy means that queued jobs are already being processed */ |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2415 | if (!d40c->busy) |
| 2416 | (void) d40_queue_start(d40c); |
| 2417 | |
| 2418 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2419 | } |
| 2420 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2421 | static void d40_terminate_all(struct dma_chan *chan) |
| 2422 | { |
| 2423 | unsigned long flags; |
| 2424 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2425 | int ret; |
| 2426 | |
| 2427 | spin_lock_irqsave(&d40c->lock, flags); |
| 2428 | |
| 2429 | pm_runtime_get_sync(d40c->base->dev); |
| 2430 | ret = d40_channel_execute_command(d40c, D40_DMA_STOP); |
| 2431 | if (ret) |
| 2432 | chan_err(d40c, "Failed to stop channel\n"); |
| 2433 | |
| 2434 | d40_term_all(d40c); |
| 2435 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2436 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2437 | if (d40c->busy) { |
| 2438 | pm_runtime_mark_last_busy(d40c->base->dev); |
| 2439 | pm_runtime_put_autosuspend(d40c->base->dev); |
| 2440 | } |
| 2441 | d40c->busy = false; |
| 2442 | |
| 2443 | spin_unlock_irqrestore(&d40c->lock, flags); |
| 2444 | } |
| 2445 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2446 | static int |
| 2447 | dma40_config_to_halfchannel(struct d40_chan *d40c, |
| 2448 | struct stedma40_half_channel_info *info, |
| 2449 | enum dma_slave_buswidth width, |
| 2450 | u32 maxburst) |
| 2451 | { |
| 2452 | enum stedma40_periph_data_width addr_width; |
| 2453 | int psize; |
| 2454 | |
| 2455 | switch (width) { |
| 2456 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
| 2457 | addr_width = STEDMA40_BYTE_WIDTH; |
| 2458 | break; |
| 2459 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
| 2460 | addr_width = STEDMA40_HALFWORD_WIDTH; |
| 2461 | break; |
| 2462 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
| 2463 | addr_width = STEDMA40_WORD_WIDTH; |
| 2464 | break; |
| 2465 | case DMA_SLAVE_BUSWIDTH_8_BYTES: |
| 2466 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; |
| 2467 | break; |
| 2468 | default: |
| 2469 | dev_err(d40c->base->dev, |
| 2470 | "illegal peripheral address width " |
| 2471 | "requested (%d)\n", |
| 2472 | width); |
| 2473 | return -EINVAL; |
| 2474 | } |
| 2475 | |
| 2476 | if (chan_is_logical(d40c)) { |
| 2477 | if (maxburst >= 16) |
| 2478 | psize = STEDMA40_PSIZE_LOG_16; |
| 2479 | else if (maxburst >= 8) |
| 2480 | psize = STEDMA40_PSIZE_LOG_8; |
| 2481 | else if (maxburst >= 4) |
| 2482 | psize = STEDMA40_PSIZE_LOG_4; |
| 2483 | else |
| 2484 | psize = STEDMA40_PSIZE_LOG_1; |
| 2485 | } else { |
| 2486 | if (maxburst >= 16) |
| 2487 | psize = STEDMA40_PSIZE_PHY_16; |
| 2488 | else if (maxburst >= 8) |
| 2489 | psize = STEDMA40_PSIZE_PHY_8; |
| 2490 | else if (maxburst >= 4) |
| 2491 | psize = STEDMA40_PSIZE_PHY_4; |
| 2492 | else |
| 2493 | psize = STEDMA40_PSIZE_PHY_1; |
| 2494 | } |
| 2495 | |
| 2496 | info->data_width = addr_width; |
| 2497 | info->psize = psize; |
| 2498 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; |
| 2499 | |
| 2500 | return 0; |
| 2501 | } |
| 2502 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2503 | /* Runtime reconfiguration extension */ |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2504 | static int d40_set_runtime_config(struct dma_chan *chan, |
| 2505 | struct dma_slave_config *config) |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2506 | { |
| 2507 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2508 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2509 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2510 | dma_addr_t config_addr; |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2511 | u32 src_maxburst, dst_maxburst; |
| 2512 | int ret; |
| 2513 | |
| 2514 | src_addr_width = config->src_addr_width; |
| 2515 | src_maxburst = config->src_maxburst; |
| 2516 | dst_addr_width = config->dst_addr_width; |
| 2517 | dst_maxburst = config->dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2518 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2519 | if (config->direction == DMA_DEV_TO_MEM) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2520 | dma_addr_t dev_addr_rx = |
| 2521 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; |
| 2522 | |
| 2523 | config_addr = config->src_addr; |
| 2524 | if (dev_addr_rx) |
| 2525 | dev_dbg(d40c->base->dev, |
| 2526 | "channel has a pre-wired RX address %08x " |
| 2527 | "overriding with %08x\n", |
| 2528 | dev_addr_rx, config_addr); |
| 2529 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) |
| 2530 | dev_dbg(d40c->base->dev, |
| 2531 | "channel was not configured for peripheral " |
| 2532 | "to memory transfer (%d) overriding\n", |
| 2533 | cfg->dir); |
| 2534 | cfg->dir = STEDMA40_PERIPH_TO_MEM; |
| 2535 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2536 | /* Configure the memory side */ |
| 2537 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2538 | dst_addr_width = src_addr_width; |
| 2539 | if (dst_maxburst == 0) |
| 2540 | dst_maxburst = src_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2541 | |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2542 | } else if (config->direction == DMA_MEM_TO_DEV) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2543 | dma_addr_t dev_addr_tx = |
| 2544 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; |
| 2545 | |
| 2546 | config_addr = config->dst_addr; |
| 2547 | if (dev_addr_tx) |
| 2548 | dev_dbg(d40c->base->dev, |
| 2549 | "channel has a pre-wired TX address %08x " |
| 2550 | "overriding with %08x\n", |
| 2551 | dev_addr_tx, config_addr); |
| 2552 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) |
| 2553 | dev_dbg(d40c->base->dev, |
| 2554 | "channel was not configured for memory " |
| 2555 | "to peripheral transfer (%d) overriding\n", |
| 2556 | cfg->dir); |
| 2557 | cfg->dir = STEDMA40_MEM_TO_PERIPH; |
| 2558 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2559 | /* Configure the memory side */ |
| 2560 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) |
| 2561 | src_addr_width = dst_addr_width; |
| 2562 | if (src_maxburst == 0) |
| 2563 | src_maxburst = dst_maxburst; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2564 | } else { |
| 2565 | dev_err(d40c->base->dev, |
| 2566 | "unrecognized channel direction %d\n", |
| 2567 | config->direction); |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2568 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2569 | } |
| 2570 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2571 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2572 | dev_err(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2573 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
| 2574 | src_maxburst, |
| 2575 | src_addr_width, |
| 2576 | dst_maxburst, |
| 2577 | dst_addr_width); |
| 2578 | return -EINVAL; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2579 | } |
| 2580 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2581 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
| 2582 | src_addr_width, |
| 2583 | src_maxburst); |
| 2584 | if (ret) |
| 2585 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2586 | |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2587 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
| 2588 | dst_addr_width, |
| 2589 | dst_maxburst); |
| 2590 | if (ret) |
| 2591 | return ret; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2592 | |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2593 | /* Fill in register values */ |
Rabin Vincent | 724a857 | 2011-01-25 11:18:08 +0100 | [diff] [blame] | 2594 | if (chan_is_logical(d40c)) |
Per Forlin | a59670a | 2010-10-06 09:05:27 +0000 | [diff] [blame] | 2595 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
| 2596 | else |
| 2597 | d40_phy_cfg(cfg, &d40c->src_def_cfg, |
| 2598 | &d40c->dst_def_cfg, false); |
| 2599 | |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2600 | /* These settings will take precedence later */ |
| 2601 | d40c->runtime_addr = config_addr; |
| 2602 | d40c->runtime_direction = config->direction; |
| 2603 | dev_dbg(d40c->base->dev, |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2604 | "configured channel %s for %s, data width %d/%d, " |
| 2605 | "maxburst %d/%d elements, LE, no flow control\n", |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2606 | dma_chan_name(chan), |
Vinod Koul | db8196d | 2011-10-13 22:34:23 +0530 | [diff] [blame] | 2607 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2608 | src_addr_width, dst_addr_width, |
| 2609 | src_maxburst, dst_maxburst); |
| 2610 | |
| 2611 | return 0; |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2612 | } |
| 2613 | |
Linus Walleij | 0582763 | 2010-05-17 16:30:42 -0700 | [diff] [blame] | 2614 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 2615 | unsigned long arg) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2616 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2617 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
| 2618 | |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2619 | if (d40c->phy_chan == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2620 | chan_err(d40c, "Channel is not allocated!\n"); |
Jonas Aaberg | 0d0f6b8 | 2010-06-20 21:25:31 +0000 | [diff] [blame] | 2621 | return -EINVAL; |
| 2622 | } |
| 2623 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2624 | switch (cmd) { |
| 2625 | case DMA_TERMINATE_ALL: |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2626 | d40_terminate_all(chan); |
| 2627 | return 0; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2628 | case DMA_PAUSE: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2629 | return d40_pause(d40c); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2630 | case DMA_RESUME: |
Rabin Vincent | 86eb5fb | 2011-01-25 11:18:34 +0100 | [diff] [blame] | 2631 | return d40_resume(d40c); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2632 | case DMA_SLAVE_CONFIG: |
Rabin Vincent | 98ca528 | 2011-06-27 11:33:38 +0200 | [diff] [blame] | 2633 | return d40_set_runtime_config(chan, |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2634 | (struct dma_slave_config *) arg); |
Linus Walleij | 95e1400 | 2010-08-04 13:37:45 +0200 | [diff] [blame] | 2635 | default: |
| 2636 | break; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2637 | } |
| 2638 | |
| 2639 | /* Other commands are unimplemented */ |
| 2640 | return -ENXIO; |
| 2641 | } |
| 2642 | |
| 2643 | /* Initialization functions */ |
| 2644 | |
| 2645 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, |
| 2646 | struct d40_chan *chans, int offset, |
| 2647 | int num_chans) |
| 2648 | { |
| 2649 | int i = 0; |
| 2650 | struct d40_chan *d40c; |
| 2651 | |
| 2652 | INIT_LIST_HEAD(&dma->channels); |
| 2653 | |
| 2654 | for (i = offset; i < offset + num_chans; i++) { |
| 2655 | d40c = &chans[i]; |
| 2656 | d40c->base = base; |
| 2657 | d40c->chan.device = dma; |
| 2658 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2659 | spin_lock_init(&d40c->lock); |
| 2660 | |
| 2661 | d40c->log_num = D40_PHY_CHAN; |
| 2662 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2663 | INIT_LIST_HEAD(&d40c->active); |
| 2664 | INIT_LIST_HEAD(&d40c->queue); |
Per Forlin | a8f3067 | 2011-06-26 23:29:52 +0200 | [diff] [blame] | 2665 | INIT_LIST_HEAD(&d40c->pending_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2666 | INIT_LIST_HEAD(&d40c->client); |
Per Forlin | 82babbb36 | 2011-08-29 13:33:35 +0200 | [diff] [blame] | 2667 | INIT_LIST_HEAD(&d40c->prepare_queue); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2668 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2669 | tasklet_init(&d40c->tasklet, dma_tasklet, |
| 2670 | (unsigned long) d40c); |
| 2671 | |
| 2672 | list_add_tail(&d40c->chan.device_node, |
| 2673 | &dma->channels); |
| 2674 | } |
| 2675 | } |
| 2676 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2677 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
| 2678 | { |
| 2679 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) |
| 2680 | dev->device_prep_slave_sg = d40_prep_slave_sg; |
| 2681 | |
| 2682 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { |
| 2683 | dev->device_prep_dma_memcpy = d40_prep_memcpy; |
| 2684 | |
| 2685 | /* |
| 2686 | * This controller can only access address at even |
| 2687 | * 32bit boundaries, i.e. 2^2 |
| 2688 | */ |
| 2689 | dev->copy_align = 2; |
| 2690 | } |
| 2691 | |
| 2692 | if (dma_has_cap(DMA_SG, dev->cap_mask)) |
| 2693 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; |
| 2694 | |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2695 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
| 2696 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; |
| 2697 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2698 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
| 2699 | dev->device_free_chan_resources = d40_free_chan_resources; |
| 2700 | dev->device_issue_pending = d40_issue_pending; |
| 2701 | dev->device_tx_status = d40_tx_status; |
| 2702 | dev->device_control = d40_control; |
| 2703 | dev->dev = base->dev; |
| 2704 | } |
| 2705 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2706 | static int __init d40_dmaengine_init(struct d40_base *base, |
| 2707 | int num_reserved_chans) |
| 2708 | { |
| 2709 | int err ; |
| 2710 | |
| 2711 | d40_chan_init(base, &base->dma_slave, base->log_chans, |
| 2712 | 0, base->num_log_chans); |
| 2713 | |
| 2714 | dma_cap_zero(base->dma_slave.cap_mask); |
| 2715 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2716 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2717 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2718 | d40_ops_init(base, &base->dma_slave); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2719 | |
| 2720 | err = dma_async_device_register(&base->dma_slave); |
| 2721 | |
| 2722 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2723 | d40_err(base->dev, "Failed to register slave channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2724 | goto failure1; |
| 2725 | } |
| 2726 | |
| 2727 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, |
| 2728 | base->num_log_chans, base->plat_data->memcpy_len); |
| 2729 | |
| 2730 | dma_cap_zero(base->dma_memcpy.cap_mask); |
| 2731 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2732 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2733 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2734 | d40_ops_init(base, &base->dma_memcpy); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2735 | |
| 2736 | err = dma_async_device_register(&base->dma_memcpy); |
| 2737 | |
| 2738 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2739 | d40_err(base->dev, |
| 2740 | "Failed to regsiter memcpy only channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2741 | goto failure2; |
| 2742 | } |
| 2743 | |
| 2744 | d40_chan_init(base, &base->dma_both, base->phy_chans, |
| 2745 | 0, num_reserved_chans); |
| 2746 | |
| 2747 | dma_cap_zero(base->dma_both.cap_mask); |
| 2748 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); |
| 2749 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2750 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
Rabin Vincent | 0c842b5 | 2011-01-25 11:18:35 +0100 | [diff] [blame] | 2751 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2752 | |
Rabin Vincent | 7ad74a7 | 2011-01-25 11:18:33 +0100 | [diff] [blame] | 2753 | d40_ops_init(base, &base->dma_both); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2754 | err = dma_async_device_register(&base->dma_both); |
| 2755 | |
| 2756 | if (err) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2757 | d40_err(base->dev, |
| 2758 | "Failed to register logical and physical capable channels\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2759 | goto failure3; |
| 2760 | } |
| 2761 | return 0; |
| 2762 | failure3: |
| 2763 | dma_async_device_unregister(&base->dma_memcpy); |
| 2764 | failure2: |
| 2765 | dma_async_device_unregister(&base->dma_slave); |
| 2766 | failure1: |
| 2767 | return err; |
| 2768 | } |
| 2769 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2770 | /* Suspend resume functionality */ |
| 2771 | #ifdef CONFIG_PM |
| 2772 | static int dma40_pm_suspend(struct device *dev) |
| 2773 | { |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2774 | struct platform_device *pdev = to_platform_device(dev); |
| 2775 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2776 | int ret = 0; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2777 | if (!pm_runtime_suspended(dev)) |
| 2778 | return -EBUSY; |
| 2779 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2780 | if (base->lcpa_regulator) |
| 2781 | ret = regulator_disable(base->lcpa_regulator); |
| 2782 | return ret; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2783 | } |
| 2784 | |
| 2785 | static int dma40_runtime_suspend(struct device *dev) |
| 2786 | { |
| 2787 | struct platform_device *pdev = to_platform_device(dev); |
| 2788 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2789 | |
| 2790 | d40_save_restore_registers(base, true); |
| 2791 | |
| 2792 | /* Don't disable/enable clocks for v1 due to HW bugs */ |
| 2793 | if (base->rev != 1) |
| 2794 | writel_relaxed(base->gcc_pwr_off_mask, |
| 2795 | base->virtbase + D40_DREG_GCC); |
| 2796 | |
| 2797 | return 0; |
| 2798 | } |
| 2799 | |
| 2800 | static int dma40_runtime_resume(struct device *dev) |
| 2801 | { |
| 2802 | struct platform_device *pdev = to_platform_device(dev); |
| 2803 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2804 | |
| 2805 | if (base->initialized) |
| 2806 | d40_save_restore_registers(base, false); |
| 2807 | |
| 2808 | writel_relaxed(D40_DREG_GCC_ENABLE_ALL, |
| 2809 | base->virtbase + D40_DREG_GCC); |
| 2810 | return 0; |
| 2811 | } |
| 2812 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2813 | static int dma40_resume(struct device *dev) |
| 2814 | { |
| 2815 | struct platform_device *pdev = to_platform_device(dev); |
| 2816 | struct d40_base *base = platform_get_drvdata(pdev); |
| 2817 | int ret = 0; |
| 2818 | |
| 2819 | if (base->lcpa_regulator) |
| 2820 | ret = regulator_enable(base->lcpa_regulator); |
| 2821 | |
| 2822 | return ret; |
| 2823 | } |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2824 | |
| 2825 | static const struct dev_pm_ops dma40_pm_ops = { |
| 2826 | .suspend = dma40_pm_suspend, |
| 2827 | .runtime_suspend = dma40_runtime_suspend, |
| 2828 | .runtime_resume = dma40_runtime_resume, |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 2829 | .resume = dma40_resume, |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2830 | }; |
| 2831 | #define DMA40_PM_OPS (&dma40_pm_ops) |
| 2832 | #else |
| 2833 | #define DMA40_PM_OPS NULL |
| 2834 | #endif |
| 2835 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2836 | /* Initialization functions. */ |
| 2837 | |
| 2838 | static int __init d40_phy_res_init(struct d40_base *base) |
| 2839 | { |
| 2840 | int i; |
| 2841 | int num_phy_chans_avail = 0; |
| 2842 | u32 val[2]; |
| 2843 | int odd_even_bit = -2; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2844 | int gcc = D40_DREG_GCC_ENA; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2845 | |
| 2846 | val[0] = readl(base->virtbase + D40_DREG_PRSME); |
| 2847 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); |
| 2848 | |
| 2849 | for (i = 0; i < base->num_phy_chans; i++) { |
| 2850 | base->phy_res[i].num = i; |
| 2851 | odd_even_bit += 2 * ((i % 2) == 0); |
| 2852 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { |
| 2853 | /* Mark security only channels as occupied */ |
| 2854 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; |
| 2855 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2856 | base->phy_res[i].reserved = true; |
| 2857 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 2858 | D40_DREG_GCC_SRC); |
| 2859 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), |
| 2860 | D40_DREG_GCC_DST); |
| 2861 | |
| 2862 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2863 | } else { |
| 2864 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; |
| 2865 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2866 | base->phy_res[i].reserved = false; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2867 | num_phy_chans_avail++; |
| 2868 | } |
| 2869 | spin_lock_init(&base->phy_res[i].lock); |
| 2870 | } |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 2871 | |
| 2872 | /* Mark disabled channels as occupied */ |
| 2873 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 2874 | int chan = base->plat_data->disabled_channels[i]; |
| 2875 | |
| 2876 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; |
| 2877 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2878 | base->phy_res[chan].reserved = true; |
| 2879 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 2880 | D40_DREG_GCC_SRC); |
| 2881 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), |
| 2882 | D40_DREG_GCC_DST); |
Rabin Vincent | f57b407 | 2010-10-06 08:20:35 +0000 | [diff] [blame] | 2883 | num_phy_chans_avail--; |
Jonas Aaberg | 6b7acd8 | 2010-06-20 21:26:59 +0000 | [diff] [blame] | 2884 | } |
| 2885 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2886 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
| 2887 | num_phy_chans_avail, base->num_phy_chans); |
| 2888 | |
| 2889 | /* Verify settings extended vs standard */ |
| 2890 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); |
| 2891 | |
| 2892 | for (i = 0; i < base->num_phy_chans; i++) { |
| 2893 | |
| 2894 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && |
| 2895 | (val[0] & 0x3) != 1) |
| 2896 | dev_info(base->dev, |
| 2897 | "[%s] INFO: channel %d is misconfigured (%d)\n", |
| 2898 | __func__, i, val[0] & 0x3); |
| 2899 | |
| 2900 | val[0] = val[0] >> 2; |
| 2901 | } |
| 2902 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 2903 | /* |
| 2904 | * To keep things simple, Enable all clocks initially. |
| 2905 | * The clocks will get managed later post channel allocation. |
| 2906 | * The clocks for the event lines on which reserved channels exists |
| 2907 | * are not managed here. |
| 2908 | */ |
| 2909 | writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); |
| 2910 | base->gcc_pwr_off_mask = gcc; |
| 2911 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2912 | return num_phy_chans_avail; |
| 2913 | } |
| 2914 | |
| 2915 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) |
| 2916 | { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2917 | struct stedma40_platform_data *plat_data; |
| 2918 | struct clk *clk = NULL; |
| 2919 | void __iomem *virtbase = NULL; |
| 2920 | struct resource *res = NULL; |
| 2921 | struct d40_base *base = NULL; |
| 2922 | int num_log_chans = 0; |
| 2923 | int num_phy_chans; |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 2924 | int clk_ret = -EINVAL; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2925 | int i; |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2926 | u32 pid; |
| 2927 | u32 cid; |
| 2928 | u8 rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2929 | |
| 2930 | clk = clk_get(&pdev->dev, NULL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2931 | if (IS_ERR(clk)) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 2932 | d40_err(&pdev->dev, "No matching clock found\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2933 | goto failure; |
| 2934 | } |
| 2935 | |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 2936 | clk_ret = clk_prepare_enable(clk); |
| 2937 | if (clk_ret) { |
| 2938 | d40_err(&pdev->dev, "Failed to prepare/enable clock\n"); |
| 2939 | goto failure; |
| 2940 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2941 | |
| 2942 | /* Get IO for DMAC base address */ |
| 2943 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); |
| 2944 | if (!res) |
| 2945 | goto failure; |
| 2946 | |
| 2947 | if (request_mem_region(res->start, resource_size(res), |
| 2948 | D40_NAME " I/O base") == NULL) |
| 2949 | goto failure; |
| 2950 | |
| 2951 | virtbase = ioremap(res->start, resource_size(res)); |
| 2952 | if (!virtbase) |
| 2953 | goto failure; |
| 2954 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2955 | /* This is just a regular AMBA PrimeCell ID actually */ |
| 2956 | for (pid = 0, i = 0; i < 4; i++) |
| 2957 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) |
| 2958 | & 255) << (i * 8); |
| 2959 | for (cid = 0, i = 0; i < 4; i++) |
| 2960 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) |
| 2961 | & 255) << (i * 8); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2962 | |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2963 | if (cid != AMBA_CID) { |
| 2964 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2965 | goto failure; |
| 2966 | } |
Linus Walleij | f4b8976 | 2011-06-27 11:33:46 +0200 | [diff] [blame] | 2967 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { |
| 2968 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
| 2969 | AMBA_MANF_BITS(pid), |
| 2970 | AMBA_VENDOR_ST); |
| 2971 | goto failure; |
| 2972 | } |
| 2973 | /* |
| 2974 | * HW revision: |
| 2975 | * DB8500ed has revision 0 |
| 2976 | * ? has revision 1 |
| 2977 | * DB8500v1 has revision 2 |
| 2978 | * DB8500v2 has revision 3 |
| 2979 | */ |
| 2980 | rev = AMBA_REV_BITS(pid); |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 2981 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2982 | /* The number of physical channels on this HW */ |
| 2983 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; |
| 2984 | |
| 2985 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 2986 | rev, res->start); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2987 | |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 2988 | if (rev < 2) { |
| 2989 | d40_err(&pdev->dev, "hardware revision: %d is not supported", |
| 2990 | rev); |
| 2991 | goto failure; |
| 2992 | } |
| 2993 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 2994 | plat_data = pdev->dev.platform_data; |
| 2995 | |
| 2996 | /* Count the number of logical channels in use */ |
| 2997 | for (i = 0; i < plat_data->dev_len; i++) |
| 2998 | if (plat_data->dev_rx[i] != 0) |
| 2999 | num_log_chans++; |
| 3000 | |
| 3001 | for (i = 0; i < plat_data->dev_len; i++) |
| 3002 | if (plat_data->dev_tx[i] != 0) |
| 3003 | num_log_chans++; |
| 3004 | |
| 3005 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + |
| 3006 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * |
| 3007 | sizeof(struct d40_chan), GFP_KERNEL); |
| 3008 | |
| 3009 | if (base == NULL) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3010 | d40_err(&pdev->dev, "Out of memory\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3011 | goto failure; |
| 3012 | } |
| 3013 | |
Jonas Aaberg | 3ae0267 | 2010-08-09 12:08:18 +0000 | [diff] [blame] | 3014 | base->rev = rev; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3015 | base->clk = clk; |
| 3016 | base->num_phy_chans = num_phy_chans; |
| 3017 | base->num_log_chans = num_log_chans; |
| 3018 | base->phy_start = res->start; |
| 3019 | base->phy_size = resource_size(res); |
| 3020 | base->virtbase = virtbase; |
| 3021 | base->plat_data = plat_data; |
| 3022 | base->dev = &pdev->dev; |
| 3023 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); |
| 3024 | base->log_chans = &base->phy_chans[num_phy_chans]; |
| 3025 | |
| 3026 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), |
| 3027 | GFP_KERNEL); |
| 3028 | if (!base->phy_res) |
| 3029 | goto failure; |
| 3030 | |
| 3031 | base->lookup_phy_chans = kzalloc(num_phy_chans * |
| 3032 | sizeof(struct d40_chan *), |
| 3033 | GFP_KERNEL); |
| 3034 | if (!base->lookup_phy_chans) |
| 3035 | goto failure; |
| 3036 | |
| 3037 | if (num_log_chans + plat_data->memcpy_len) { |
| 3038 | /* |
| 3039 | * The max number of logical channels are event lines for all |
| 3040 | * src devices and dst devices |
| 3041 | */ |
| 3042 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * |
| 3043 | sizeof(struct d40_chan *), |
| 3044 | GFP_KERNEL); |
| 3045 | if (!base->lookup_log_chans) |
| 3046 | goto failure; |
| 3047 | } |
Jonas Aaberg | 698e473 | 2010-08-09 12:08:56 +0000 | [diff] [blame] | 3048 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3049 | base->reg_val_backup_chan = kmalloc(base->num_phy_chans * |
| 3050 | sizeof(d40_backup_regs_chan), |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3051 | GFP_KERNEL); |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3052 | if (!base->reg_val_backup_chan) |
| 3053 | goto failure; |
| 3054 | |
| 3055 | base->lcla_pool.alloc_map = |
| 3056 | kzalloc(num_phy_chans * sizeof(struct d40_desc *) |
| 3057 | * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3058 | if (!base->lcla_pool.alloc_map) |
| 3059 | goto failure; |
| 3060 | |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 3061 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
| 3062 | 0, SLAB_HWCACHE_ALIGN, |
| 3063 | NULL); |
| 3064 | if (base->desc_slab == NULL) |
| 3065 | goto failure; |
| 3066 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3067 | return base; |
| 3068 | |
| 3069 | failure: |
Ulf Hansson | b707c658 | 2012-08-23 13:41:58 +0200 | [diff] [blame] | 3070 | if (!clk_ret) |
| 3071 | clk_disable_unprepare(clk); |
| 3072 | if (!IS_ERR(clk)) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3073 | clk_put(clk); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3074 | if (virtbase) |
| 3075 | iounmap(virtbase); |
| 3076 | if (res) |
| 3077 | release_mem_region(res->start, |
| 3078 | resource_size(res)); |
| 3079 | if (virtbase) |
| 3080 | iounmap(virtbase); |
| 3081 | |
| 3082 | if (base) { |
| 3083 | kfree(base->lcla_pool.alloc_map); |
Narayanan G | 1bdae6f | 2012-02-09 12:41:37 +0530 | [diff] [blame] | 3084 | kfree(base->reg_val_backup_chan); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3085 | kfree(base->lookup_log_chans); |
| 3086 | kfree(base->lookup_phy_chans); |
| 3087 | kfree(base->phy_res); |
| 3088 | kfree(base); |
| 3089 | } |
| 3090 | |
| 3091 | return NULL; |
| 3092 | } |
| 3093 | |
| 3094 | static void __init d40_hw_init(struct d40_base *base) |
| 3095 | { |
| 3096 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3097 | static struct d40_reg_val dma_init_reg[] = { |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3098 | /* Clock every part of the DMA block from start */ |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3099 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3100 | |
| 3101 | /* Interrupts on all logical channels */ |
| 3102 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, |
| 3103 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, |
| 3104 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, |
| 3105 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, |
| 3106 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, |
| 3107 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, |
| 3108 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, |
| 3109 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, |
| 3110 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, |
| 3111 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, |
| 3112 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, |
| 3113 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} |
| 3114 | }; |
| 3115 | int i; |
| 3116 | u32 prmseo[2] = {0, 0}; |
| 3117 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; |
| 3118 | u32 pcmis = 0; |
| 3119 | u32 pcicr = 0; |
| 3120 | |
| 3121 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) |
| 3122 | writel(dma_init_reg[i].val, |
| 3123 | base->virtbase + dma_init_reg[i].reg); |
| 3124 | |
| 3125 | /* Configure all our dma channels to default settings */ |
| 3126 | for (i = 0; i < base->num_phy_chans; i++) { |
| 3127 | |
| 3128 | activeo[i % 2] = activeo[i % 2] << 2; |
| 3129 | |
| 3130 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src |
| 3131 | == D40_ALLOC_PHY) { |
| 3132 | activeo[i % 2] |= 3; |
| 3133 | continue; |
| 3134 | } |
| 3135 | |
| 3136 | /* Enable interrupt # */ |
| 3137 | pcmis = (pcmis << 1) | 1; |
| 3138 | |
| 3139 | /* Clear interrupt # */ |
| 3140 | pcicr = (pcicr << 1) | 1; |
| 3141 | |
| 3142 | /* Set channel to physical mode */ |
| 3143 | prmseo[i % 2] = prmseo[i % 2] << 2; |
| 3144 | prmseo[i % 2] |= 1; |
| 3145 | |
| 3146 | } |
| 3147 | |
| 3148 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); |
| 3149 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); |
| 3150 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); |
| 3151 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); |
| 3152 | |
| 3153 | /* Write which interrupt to enable */ |
| 3154 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); |
| 3155 | |
| 3156 | /* Write which interrupt to clear */ |
| 3157 | writel(pcicr, base->virtbase + D40_DREG_PCICR); |
| 3158 | |
| 3159 | } |
| 3160 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3161 | static int __init d40_lcla_allocate(struct d40_base *base) |
| 3162 | { |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3163 | struct d40_lcla_pool *pool = &base->lcla_pool; |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3164 | unsigned long *page_list; |
| 3165 | int i, j; |
| 3166 | int ret = 0; |
| 3167 | |
| 3168 | /* |
| 3169 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, |
| 3170 | * To full fill this hardware requirement without wasting 256 kb |
| 3171 | * we allocate pages until we get an aligned one. |
| 3172 | */ |
| 3173 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, |
| 3174 | GFP_KERNEL); |
| 3175 | |
| 3176 | if (!page_list) { |
| 3177 | ret = -ENOMEM; |
| 3178 | goto failure; |
| 3179 | } |
| 3180 | |
| 3181 | /* Calculating how many pages that are required */ |
| 3182 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; |
| 3183 | |
| 3184 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { |
| 3185 | page_list[i] = __get_free_pages(GFP_KERNEL, |
| 3186 | base->lcla_pool.pages); |
| 3187 | if (!page_list[i]) { |
| 3188 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3189 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
| 3190 | base->lcla_pool.pages); |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3191 | |
| 3192 | for (j = 0; j < i; j++) |
| 3193 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3194 | goto failure; |
| 3195 | } |
| 3196 | |
| 3197 | if ((virt_to_phys((void *)page_list[i]) & |
| 3198 | (LCLA_ALIGNMENT - 1)) == 0) |
| 3199 | break; |
| 3200 | } |
| 3201 | |
| 3202 | for (j = 0; j < i; j++) |
| 3203 | free_pages(page_list[j], base->lcla_pool.pages); |
| 3204 | |
| 3205 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { |
| 3206 | base->lcla_pool.base = (void *)page_list[i]; |
| 3207 | } else { |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3208 | /* |
| 3209 | * After many attempts and no succees with finding the correct |
| 3210 | * alignment, try with allocating a big buffer. |
| 3211 | */ |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3212 | dev_warn(base->dev, |
| 3213 | "[%s] Failed to get %d pages @ 18 bit align.\n", |
| 3214 | __func__, base->lcla_pool.pages); |
| 3215 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * |
| 3216 | base->num_phy_chans + |
| 3217 | LCLA_ALIGNMENT, |
| 3218 | GFP_KERNEL); |
| 3219 | if (!base->lcla_pool.base_unaligned) { |
| 3220 | ret = -ENOMEM; |
| 3221 | goto failure; |
| 3222 | } |
| 3223 | |
| 3224 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, |
| 3225 | LCLA_ALIGNMENT); |
| 3226 | } |
| 3227 | |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3228 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
| 3229 | SZ_1K * base->num_phy_chans, |
| 3230 | DMA_TO_DEVICE); |
| 3231 | if (dma_mapping_error(base->dev, pool->dma_addr)) { |
| 3232 | pool->dma_addr = 0; |
| 3233 | ret = -ENOMEM; |
| 3234 | goto failure; |
| 3235 | } |
| 3236 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3237 | writel(virt_to_phys(base->lcla_pool.base), |
| 3238 | base->virtbase + D40_DREG_LCLA); |
| 3239 | failure: |
| 3240 | kfree(page_list); |
| 3241 | return ret; |
| 3242 | } |
| 3243 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3244 | static int __init d40_probe(struct platform_device *pdev) |
| 3245 | { |
| 3246 | int err; |
| 3247 | int ret = -ENOENT; |
| 3248 | struct d40_base *base; |
| 3249 | struct resource *res = NULL; |
| 3250 | int num_reserved_chans; |
| 3251 | u32 val; |
| 3252 | |
| 3253 | base = d40_hw_detect_init(pdev); |
| 3254 | |
| 3255 | if (!base) |
| 3256 | goto failure; |
| 3257 | |
| 3258 | num_reserved_chans = d40_phy_res_init(base); |
| 3259 | |
| 3260 | platform_set_drvdata(pdev, base); |
| 3261 | |
| 3262 | spin_lock_init(&base->interrupt_lock); |
| 3263 | spin_lock_init(&base->execmd_lock); |
| 3264 | |
| 3265 | /* Get IO for logical channel parameter address */ |
| 3266 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); |
| 3267 | if (!res) { |
| 3268 | ret = -ENOENT; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3269 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3270 | goto failure; |
| 3271 | } |
| 3272 | base->lcpa_size = resource_size(res); |
| 3273 | base->phy_lcpa = res->start; |
| 3274 | |
| 3275 | if (request_mem_region(res->start, resource_size(res), |
| 3276 | D40_NAME " I/O lcpa") == NULL) { |
| 3277 | ret = -EBUSY; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3278 | d40_err(&pdev->dev, |
| 3279 | "Failed to request LCPA region 0x%x-0x%x\n", |
| 3280 | res->start, res->end); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3281 | goto failure; |
| 3282 | } |
| 3283 | |
| 3284 | /* We make use of ESRAM memory for this. */ |
| 3285 | val = readl(base->virtbase + D40_DREG_LCPA); |
| 3286 | if (res->start != val && val != 0) { |
| 3287 | dev_warn(&pdev->dev, |
| 3288 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", |
| 3289 | __func__, val, res->start); |
| 3290 | } else |
| 3291 | writel(res->start, base->virtbase + D40_DREG_LCPA); |
| 3292 | |
| 3293 | base->lcpa_base = ioremap(res->start, resource_size(res)); |
| 3294 | if (!base->lcpa_base) { |
| 3295 | ret = -ENOMEM; |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3296 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3297 | goto failure; |
| 3298 | } |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3299 | /* If lcla has to be located in ESRAM we don't need to allocate */ |
| 3300 | if (base->plat_data->use_esram_lcla) { |
| 3301 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 3302 | "lcla_esram"); |
| 3303 | if (!res) { |
| 3304 | ret = -ENOENT; |
| 3305 | d40_err(&pdev->dev, |
| 3306 | "No \"lcla_esram\" memory resource\n"); |
| 3307 | goto failure; |
| 3308 | } |
| 3309 | base->lcla_pool.base = ioremap(res->start, |
| 3310 | resource_size(res)); |
| 3311 | if (!base->lcla_pool.base) { |
| 3312 | ret = -ENOMEM; |
| 3313 | d40_err(&pdev->dev, "Failed to ioremap LCLA region\n"); |
| 3314 | goto failure; |
| 3315 | } |
| 3316 | writel(res->start, base->virtbase + D40_DREG_LCLA); |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3317 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3318 | } else { |
| 3319 | ret = d40_lcla_allocate(base); |
| 3320 | if (ret) { |
| 3321 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); |
| 3322 | goto failure; |
| 3323 | } |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3324 | } |
| 3325 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3326 | spin_lock_init(&base->lcla_pool.lock); |
| 3327 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3328 | base->irq = platform_get_irq(pdev, 0); |
| 3329 | |
| 3330 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3331 | if (ret) { |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3332 | d40_err(&pdev->dev, "No IRQ defined\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3333 | goto failure; |
| 3334 | } |
| 3335 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3336 | pm_runtime_irq_safe(base->dev); |
| 3337 | pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); |
| 3338 | pm_runtime_use_autosuspend(base->dev); |
| 3339 | pm_runtime_enable(base->dev); |
| 3340 | pm_runtime_resume(base->dev); |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3341 | |
| 3342 | if (base->plat_data->use_esram_lcla) { |
| 3343 | |
| 3344 | base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); |
| 3345 | if (IS_ERR(base->lcpa_regulator)) { |
| 3346 | d40_err(&pdev->dev, "Failed to get lcpa_regulator\n"); |
| 3347 | base->lcpa_regulator = NULL; |
| 3348 | goto failure; |
| 3349 | } |
| 3350 | |
| 3351 | ret = regulator_enable(base->lcpa_regulator); |
| 3352 | if (ret) { |
| 3353 | d40_err(&pdev->dev, |
| 3354 | "Failed to enable lcpa_regulator\n"); |
| 3355 | regulator_put(base->lcpa_regulator); |
| 3356 | base->lcpa_regulator = NULL; |
| 3357 | goto failure; |
| 3358 | } |
| 3359 | } |
| 3360 | |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3361 | base->initialized = true; |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3362 | err = d40_dmaengine_init(base, num_reserved_chans); |
| 3363 | if (err) |
| 3364 | goto failure; |
| 3365 | |
| 3366 | d40_hw_init(base); |
| 3367 | |
| 3368 | dev_info(base->dev, "initialized\n"); |
| 3369 | return 0; |
| 3370 | |
| 3371 | failure: |
| 3372 | if (base) { |
Jonas Aaberg | c675b1b | 2010-06-20 21:25:08 +0000 | [diff] [blame] | 3373 | if (base->desc_slab) |
| 3374 | kmem_cache_destroy(base->desc_slab); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3375 | if (base->virtbase) |
| 3376 | iounmap(base->virtbase); |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3377 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3378 | if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { |
| 3379 | iounmap(base->lcla_pool.base); |
| 3380 | base->lcla_pool.base = NULL; |
| 3381 | } |
| 3382 | |
Rabin Vincent | 026cbc4 | 2011-01-25 11:18:14 +0100 | [diff] [blame] | 3383 | if (base->lcla_pool.dma_addr) |
| 3384 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, |
| 3385 | SZ_1K * base->num_phy_chans, |
| 3386 | DMA_TO_DEVICE); |
| 3387 | |
Linus Walleij | 508849a | 2010-06-20 21:26:07 +0000 | [diff] [blame] | 3388 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
| 3389 | free_pages((unsigned long)base->lcla_pool.base, |
| 3390 | base->lcla_pool.pages); |
Jonas Aaberg | 767a967 | 2010-08-09 12:08:34 +0000 | [diff] [blame] | 3391 | |
| 3392 | kfree(base->lcla_pool.base_unaligned); |
| 3393 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3394 | if (base->phy_lcpa) |
| 3395 | release_mem_region(base->phy_lcpa, |
| 3396 | base->lcpa_size); |
| 3397 | if (base->phy_start) |
| 3398 | release_mem_region(base->phy_start, |
| 3399 | base->phy_size); |
| 3400 | if (base->clk) { |
| 3401 | clk_disable(base->clk); |
| 3402 | clk_put(base->clk); |
| 3403 | } |
| 3404 | |
Narayanan G | 28c7a19 | 2011-11-22 13:56:55 +0530 | [diff] [blame] | 3405 | if (base->lcpa_regulator) { |
| 3406 | regulator_disable(base->lcpa_regulator); |
| 3407 | regulator_put(base->lcpa_regulator); |
| 3408 | } |
| 3409 | |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3410 | kfree(base->lcla_pool.alloc_map); |
| 3411 | kfree(base->lookup_log_chans); |
| 3412 | kfree(base->lookup_phy_chans); |
| 3413 | kfree(base->phy_res); |
| 3414 | kfree(base); |
| 3415 | } |
| 3416 | |
Rabin Vincent | 6db5a8b | 2011-01-25 11:18:09 +0100 | [diff] [blame] | 3417 | d40_err(&pdev->dev, "probe failed\n"); |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3418 | return ret; |
| 3419 | } |
| 3420 | |
| 3421 | static struct platform_driver d40_driver = { |
| 3422 | .driver = { |
| 3423 | .owner = THIS_MODULE, |
| 3424 | .name = D40_NAME, |
Narayanan G | 7fb3e75 | 2011-11-17 17:26:41 +0530 | [diff] [blame] | 3425 | .pm = DMA40_PM_OPS, |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3426 | }, |
| 3427 | }; |
| 3428 | |
Rabin Vincent | cb9ab2d | 2011-01-25 11:18:04 +0100 | [diff] [blame] | 3429 | static int __init stedma40_init(void) |
Linus Walleij | 8d318a5 | 2010-03-30 15:33:42 +0200 | [diff] [blame] | 3430 | { |
| 3431 | return platform_driver_probe(&d40_driver, d40_probe); |
| 3432 | } |
Linus Walleij | a0eb221 | 2011-05-18 14:18:57 +0200 | [diff] [blame] | 3433 | subsys_initcall(stedma40_init); |