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Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000011
Thierry Reding4aa3df72014-11-24 16:27:13 +010012#include <drm/drm_atomic_helper.h>
Thierry Reding3b0e5852014-12-16 18:30:16 +010013#include <drm/drm_panel.h>
14
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000015#include "drm.h"
16#include "dc.h"
17
18struct tegra_rgb {
19 struct tegra_output output;
Thierry Reding7602fa12013-10-30 09:55:33 +010020 struct tegra_dc *dc;
Dmitry Osipenkob1891532014-02-11 21:12:27 +040021 bool enabled;
Thierry Reding7602fa12013-10-30 09:55:33 +010022
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000023 struct clk *clk_parent;
24 struct clk *clk;
25};
26
27static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
28{
29 return container_of(output, struct tegra_rgb, output);
30}
31
32struct reg_entry {
33 unsigned long offset;
34 unsigned long value;
35};
36
37static const struct reg_entry rgb_enable[] = {
38 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
54 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
55 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
57};
58
59static const struct reg_entry rgb_disable[] = {
60 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
67 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
71 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
75 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
77 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
78 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
79};
80
81static void tegra_dc_write_regs(struct tegra_dc *dc,
82 const struct reg_entry *table,
83 unsigned int num)
84{
85 unsigned int i;
86
87 for (i = 0; i < num; i++)
88 tegra_dc_writel(dc, table[i].value, table[i].offset);
89}
90
Maarten Lankhorst9a69a9a2015-07-21 11:34:55 +020091static int tegra_rgb_connector_dpms(struct drm_connector *connector,
92 int mode)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000093{
Maarten Lankhorst9a69a9a2015-07-21 11:34:55 +020094 return 0;
Thierry Reding3b0e5852014-12-16 18:30:16 +010095}
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000096
Thierry Reding3b0e5852014-12-16 18:30:16 +010097static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
98 .dpms = tegra_rgb_connector_dpms,
Thierry Reding9d441892014-11-24 17:02:53 +010099 .reset = drm_atomic_helper_connector_reset,
Thierry Reding3b0e5852014-12-16 18:30:16 +0100100 .detect = tegra_output_connector_detect,
101 .fill_modes = drm_helper_probe_single_connector_modes,
102 .destroy = tegra_output_connector_destroy,
Thierry Reding9d441892014-11-24 17:02:53 +0100103 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
Thierry Reding4aa3df72014-11-24 16:27:13 +0100104 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
Thierry Reding3b0e5852014-12-16 18:30:16 +0100105};
106
107static enum drm_mode_status
108tegra_rgb_connector_mode_valid(struct drm_connector *connector,
109 struct drm_display_mode *mode)
110{
111 /*
112 * FIXME: For now, always assume that the mode is okay. There are
113 * unresolved issues with clk_round_rate(), which doesn't always
114 * reliably report whether a frequency can be set or not.
115 */
116 return MODE_OK;
117}
118
119static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
120 .get_modes = tegra_output_connector_get_modes,
121 .mode_valid = tegra_rgb_connector_mode_valid,
122 .best_encoder = tegra_output_connector_best_encoder,
123};
124
125static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
126 .destroy = tegra_output_encoder_destroy,
127};
128
129static void tegra_rgb_encoder_dpms(struct drm_encoder *encoder, int mode)
130{
131}
132
Thierry Reding3b0e5852014-12-16 18:30:16 +0100133static void tegra_rgb_encoder_prepare(struct drm_encoder *encoder)
134{
135}
136
137static void tegra_rgb_encoder_commit(struct drm_encoder *encoder)
138{
139}
140
141static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
142 struct drm_display_mode *mode,
143 struct drm_display_mode *adjusted)
144{
145 struct tegra_output *output = encoder_to_output(encoder);
146 struct tegra_rgb *rgb = to_rgb(output);
147 u32 value;
148
149 if (output->panel)
150 drm_panel_prepare(output->panel);
Dmitry Osipenkob1891532014-02-11 21:12:27 +0400151
Thierry Reding7602fa12013-10-30 09:55:33 +0100152 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000153
Thierry Reding72d30282013-12-12 11:06:55 +0100154 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
155 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
156
157 /* XXX: parameterize? */
158 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
159 value &= ~LVS_OUTPUT_POLARITY_LOW;
160 value &= ~LHS_OUTPUT_POLARITY_LOW;
161 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
162
163 /* XXX: parameterize? */
164 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
165 DISP_ORDER_RED_BLUE;
166 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
167
168 /* XXX: parameterize? */
169 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
170 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
171
Thierry Reding62b9e062014-11-21 17:33:33 +0100172 tegra_dc_commit(rgb->dc);
Thierry Reding72d30282013-12-12 11:06:55 +0100173
Thierry Reding3b0e5852014-12-16 18:30:16 +0100174 if (output->panel)
175 drm_panel_enable(output->panel);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000176}
177
Thierry Reding3b0e5852014-12-16 18:30:16 +0100178static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000179{
Thierry Reding3b0e5852014-12-16 18:30:16 +0100180 struct tegra_output *output = encoder_to_output(encoder);
Thierry Reding7602fa12013-10-30 09:55:33 +0100181 struct tegra_rgb *rgb = to_rgb(output);
Thierry Reding72d30282013-12-12 11:06:55 +0100182
Thierry Reding3b0e5852014-12-16 18:30:16 +0100183 if (output->panel)
184 drm_panel_disable(output->panel);
Thierry Reding72d30282013-12-12 11:06:55 +0100185
Thierry Reding7602fa12013-10-30 09:55:33 +0100186 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
Thierry Reding666cb872014-12-08 16:32:47 +0100187 tegra_dc_commit(rgb->dc);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000188
Thierry Reding3b0e5852014-12-16 18:30:16 +0100189 if (output->panel)
190 drm_panel_unprepare(output->panel);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000191}
192
Thierry Reding3cebae62014-12-17 17:04:36 +0100193static int
194tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
195 struct drm_crtc_state *crtc_state,
196 struct drm_connector_state *conn_state)
197{
198 struct tegra_output *output = encoder_to_output(encoder);
199 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
200 unsigned long pclk = crtc_state->mode.clock * 1000;
201 struct tegra_rgb *rgb = to_rgb(output);
202 unsigned int div;
203 int err;
204
205 /*
206 * We may not want to change the frequency of the parent clock, since
207 * it may be a parent for other peripherals. This is due to the fact
208 * that on Tegra20 there's only a single clock dedicated to display
209 * (pll_d_out0), whereas later generations have a second one that can
210 * be used to independently drive a second output (pll_d2_out0).
211 *
212 * As a way to support multiple outputs on Tegra20 as well, pll_p is
213 * typically used as the parent clock for the display controllers.
214 * But this comes at a cost: pll_p is the parent of several other
215 * peripherals, so its frequency shouldn't change out of the blue.
216 *
217 * The best we can do at this point is to use the shift clock divider
218 * and hope that the desired frequency can be matched (or at least
219 * matched sufficiently close that the panel will still work).
220 */
221 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
222 pclk = 0;
223
224 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
225 pclk, div);
226 if (err < 0) {
227 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
228 return err;
229 }
230
231 return err;
232}
233
Thierry Reding3b0e5852014-12-16 18:30:16 +0100234static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
235 .dpms = tegra_rgb_encoder_dpms,
Thierry Reding3b0e5852014-12-16 18:30:16 +0100236 .prepare = tegra_rgb_encoder_prepare,
237 .commit = tegra_rgb_encoder_commit,
238 .mode_set = tegra_rgb_encoder_mode_set,
239 .disable = tegra_rgb_encoder_disable,
Thierry Reding3cebae62014-12-17 17:04:36 +0100240 .atomic_check = tegra_rgb_encoder_atomic_check,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000241};
242
243int tegra_dc_rgb_probe(struct tegra_dc *dc)
244{
245 struct device_node *np;
246 struct tegra_rgb *rgb;
247 int err;
248
249 np = of_get_child_by_name(dc->dev->of_node, "rgb");
250 if (!np || !of_device_is_available(np))
251 return -ENODEV;
252
253 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
254 if (!rgb)
255 return -ENOMEM;
256
Thierry Reding03da0e72013-08-30 15:27:16 +0200257 rgb->output.dev = dc->dev;
258 rgb->output.of_node = np;
Thierry Reding7602fa12013-10-30 09:55:33 +0100259 rgb->dc = dc;
Thierry Reding03da0e72013-08-30 15:27:16 +0200260
Thierry Reding59d29c02013-10-14 14:26:42 +0200261 err = tegra_output_probe(&rgb->output);
Thierry Reding03da0e72013-08-30 15:27:16 +0200262 if (err < 0)
263 return err;
264
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000265 rgb->clk = devm_clk_get(dc->dev, NULL);
266 if (IS_ERR(rgb->clk)) {
267 dev_err(dc->dev, "failed to get clock\n");
268 return PTR_ERR(rgb->clk);
269 }
270
271 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
272 if (IS_ERR(rgb->clk_parent)) {
273 dev_err(dc->dev, "failed to get parent clock\n");
274 return PTR_ERR(rgb->clk_parent);
275 }
276
277 err = clk_set_parent(rgb->clk, rgb->clk_parent);
278 if (err < 0) {
279 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
280 return err;
281 }
282
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000283 dc->rgb = &rgb->output;
284
285 return 0;
286}
287
Thierry Reding59d29c02013-10-14 14:26:42 +0200288int tegra_dc_rgb_remove(struct tegra_dc *dc)
289{
Thierry Reding59d29c02013-10-14 14:26:42 +0200290 if (!dc->rgb)
291 return 0;
292
Thierry Reding328ec692014-12-19 15:55:08 +0100293 tegra_output_remove(dc->rgb);
Thierry Reding3b0e5852014-12-16 18:30:16 +0100294 dc->rgb = NULL;
295
Thierry Reding59d29c02013-10-14 14:26:42 +0200296 return 0;
297}
298
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000299int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
300{
Thierry Reding3b0e5852014-12-16 18:30:16 +0100301 struct tegra_output *output = dc->rgb;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000302 int err;
303
304 if (!dc->rgb)
305 return -ENODEV;
306
Thierry Reding3b0e5852014-12-16 18:30:16 +0100307 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
308 DRM_MODE_CONNECTOR_LVDS);
309 drm_connector_helper_add(&output->connector,
310 &tegra_rgb_connector_helper_funcs);
311 output->connector.dpms = DRM_MODE_DPMS_OFF;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000312
Thierry Reding3b0e5852014-12-16 18:30:16 +0100313 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
314 DRM_MODE_ENCODER_LVDS);
315 drm_encoder_helper_add(&output->encoder,
316 &tegra_rgb_encoder_helper_funcs);
317
318 drm_mode_connector_attach_encoder(&output->connector,
319 &output->encoder);
320 drm_connector_register(&output->connector);
321
Thierry Redingea130b22014-12-19 15:51:35 +0100322 err = tegra_output_init(drm, output);
323 if (err < 0) {
324 dev_err(output->dev, "failed to initialize output: %d\n", err);
325 return err;
326 }
327
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000328 /*
Thierry Reding3b0e5852014-12-16 18:30:16 +0100329 * Other outputs can be attached to either display controller. The RGB
330 * outputs are an exception and work only with their parent display
331 * controller.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000332 */
Thierry Reding3b0e5852014-12-16 18:30:16 +0100333 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000334
335 return 0;
336}
337
338int tegra_dc_rgb_exit(struct tegra_dc *dc)
339{
Thierry Reding328ec692014-12-19 15:55:08 +0100340 if (dc->rgb)
341 tegra_output_exit(dc->rgb);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000342
Thierry Reding328ec692014-12-19 15:55:08 +0100343 return 0;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000344}