blob: f747ca26998624752cf1fbb6f9c051c477c49198 [file] [log] [blame]
Grant Likelyca632f52011-06-06 01:16:30 -06001/*
Ben Dooks7fba5342006-05-20 15:00:18 -07002 * Copyright (c) 2006 Ben Dooks
Ben Dooksbec08062009-12-14 22:20:24 -08003 * Copyright 2006-2009 Simtec Electronics
Ben Dooks7fba5342006-05-20 15:00:18 -07004 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10*/
11
Ben Dooks7fba5342006-05-20 15:00:18 -070012#include <linux/spinlock.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070013#include <linux/interrupt.h>
14#include <linux/delay.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
Ben Dooksee9c1fb2009-01-06 14:41:44 -080019#include <linux/gpio.h>
Ben Dooks1a0c2202009-09-22 16:46:12 -070020#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070022
23#include <linux/spi/spi.h>
24#include <linux/spi/spi_bitbang.h>
Heiko Stuebnerf35ef7c2012-01-31 20:06:07 +090025#include <linux/spi/s3c24xx.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040026#include <linux/module.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070027
Ben Dooks13622702008-10-30 10:14:38 +000028#include <plat/regs-spi.h>
Ben Dooks7fba5342006-05-20 15:00:18 -070029
Ben Dooksbec08062009-12-14 22:20:24 -080030#include <asm/fiq.h>
31
Grant Likelyca632f52011-06-06 01:16:30 -060032#include "spi-s3c24xx-fiq.h"
Ben Dooksbec08062009-12-14 22:20:24 -080033
Ben Dooks570327d2009-09-22 16:46:14 -070034/**
35 * s3c24xx_spi_devstate - per device data
36 * @hz: Last frequency calculated for @sppre field.
37 * @mode: Last mode setting for the @spcon field.
38 * @spcon: Value to write to the SPCON register.
39 * @sppre: Value to write to the SPPRE register.
40 */
41struct s3c24xx_spi_devstate {
42 unsigned int hz;
43 unsigned int mode;
44 u8 spcon;
45 u8 sppre;
46};
47
Ben Dooksbec08062009-12-14 22:20:24 -080048enum spi_fiq_mode {
49 FIQ_MODE_NONE = 0,
50 FIQ_MODE_TX = 1,
51 FIQ_MODE_RX = 2,
52 FIQ_MODE_TXRX = 3,
53};
54
Ben Dooks7fba5342006-05-20 15:00:18 -070055struct s3c24xx_spi {
56 /* bitbang has to be first */
57 struct spi_bitbang bitbang;
58 struct completion done;
59
60 void __iomem *regs;
61 int irq;
62 int len;
63 int count;
64
Ben Dooksbec08062009-12-14 22:20:24 -080065 struct fiq_handler fiq_handler;
66 enum spi_fiq_mode fiq_mode;
67 unsigned char fiq_inuse;
68 unsigned char fiq_claimed;
69
Arnaud Patard (Rtp6c912a32007-03-16 13:38:36 -080070 void (*set_cs)(struct s3c2410_spi_info *spi,
Ben Dooks8736b922007-01-26 00:56:43 -080071 int cs, int pol);
72
Ben Dooks7fba5342006-05-20 15:00:18 -070073 /* data buffers */
74 const unsigned char *tx;
75 unsigned char *rx;
76
77 struct clk *clk;
Ben Dooks7fba5342006-05-20 15:00:18 -070078 struct spi_master *master;
79 struct spi_device *curdev;
80 struct device *dev;
81 struct s3c2410_spi_info *pdata;
82};
83
84#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
85#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
86
87static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
88{
89 return spi_master_get_devdata(sdev->master);
90}
91
Ben Dooks8736b922007-01-26 00:56:43 -080092static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
93{
Ben Dooksee9c1fb2009-01-06 14:41:44 -080094 gpio_set_value(spi->pin_cs, pol);
Ben Dooks8736b922007-01-26 00:56:43 -080095}
96
Ben Dooks7fba5342006-05-20 15:00:18 -070097static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
98{
Ben Dooks570327d2009-09-22 16:46:14 -070099 struct s3c24xx_spi_devstate *cs = spi->controller_state;
Ben Dooks7fba5342006-05-20 15:00:18 -0700100 struct s3c24xx_spi *hw = to_hw(spi);
101 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
Ben Dooks570327d2009-09-22 16:46:14 -0700102
103 /* change the chipselect state and the state of the spi engine clock */
Ben Dooks7fba5342006-05-20 15:00:18 -0700104
105 switch (value) {
106 case BITBANG_CS_INACTIVE:
Ben Dooks3d2c5b42007-04-16 22:53:22 -0700107 hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
Ben Dooks570327d2009-09-22 16:46:14 -0700108 writeb(cs->spcon, hw->regs + S3C2410_SPCON);
Ben Dooks7fba5342006-05-20 15:00:18 -0700109 break;
110
111 case BITBANG_CS_ACTIVE:
Ben Dooks570327d2009-09-22 16:46:14 -0700112 writeb(cs->spcon | S3C2410_SPCON_ENSCK,
113 hw->regs + S3C2410_SPCON);
Ben Dooks3d2c5b42007-04-16 22:53:22 -0700114 hw->set_cs(hw->pdata, spi->chip_select, cspol);
Ben Dooks7fba5342006-05-20 15:00:18 -0700115 break;
Ben Dooks7fba5342006-05-20 15:00:18 -0700116 }
117}
118
Ben Dooks570327d2009-09-22 16:46:14 -0700119static int s3c24xx_spi_update_state(struct spi_device *spi,
120 struct spi_transfer *t)
Ben Dooks7fba5342006-05-20 15:00:18 -0700121{
122 struct s3c24xx_spi *hw = to_hw(spi);
Ben Dooks570327d2009-09-22 16:46:14 -0700123 struct s3c24xx_spi_devstate *cs = spi->controller_state;
Ben Dooks7fba5342006-05-20 15:00:18 -0700124 unsigned int hz;
125 unsigned int div;
Ben Dooksb8978782009-08-18 14:11:16 -0700126 unsigned long clk;
Ben Dooks7fba5342006-05-20 15:00:18 -0700127
Ben Dooks7fba5342006-05-20 15:00:18 -0700128 hz = t ? t->speed_hz : spi->max_speed_hz;
129
Ben Dooks19152972009-08-18 14:11:17 -0700130 if (!hz)
131 hz = spi->max_speed_hz;
132
Ben Dooks570327d2009-09-22 16:46:14 -0700133 if (spi->mode != cs->mode) {
Ben Dooksbec08062009-12-14 22:20:24 -0800134 u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
Ben Dooks7fba5342006-05-20 15:00:18 -0700135
Ben Dooks570327d2009-09-22 16:46:14 -0700136 if (spi->mode & SPI_CPHA)
137 spcon |= S3C2410_SPCON_CPHA_FMTB;
Ben Dooks7fba5342006-05-20 15:00:18 -0700138
Ben Dooks570327d2009-09-22 16:46:14 -0700139 if (spi->mode & SPI_CPOL)
140 spcon |= S3C2410_SPCON_CPOL_HIGH;
Ben Dooksb8978782009-08-18 14:11:16 -0700141
Ben Dooks570327d2009-09-22 16:46:14 -0700142 cs->mode = spi->mode;
143 cs->spcon = spcon;
144 }
Ben Dooksb8978782009-08-18 14:11:16 -0700145
Ben Dooks570327d2009-09-22 16:46:14 -0700146 if (cs->hz != hz) {
147 clk = clk_get_rate(hw->clk);
148 div = DIV_ROUND_UP(clk, hz * 2) - 1;
149
150 if (div > 255)
151 div = 255;
152
153 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
154 div, hz, clk / (2 * (div + 1)));
155
156 cs->hz = hz;
157 cs->sppre = div;
158 }
159
160 return 0;
161}
162
163static int s3c24xx_spi_setupxfer(struct spi_device *spi,
164 struct spi_transfer *t)
165{
166 struct s3c24xx_spi_devstate *cs = spi->controller_state;
167 struct s3c24xx_spi *hw = to_hw(spi);
168 int ret;
169
170 ret = s3c24xx_spi_update_state(spi, t);
171 if (!ret)
172 writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
173
174 return ret;
175}
176
177static int s3c24xx_spi_setup(struct spi_device *spi)
178{
179 struct s3c24xx_spi_devstate *cs = spi->controller_state;
180 struct s3c24xx_spi *hw = to_hw(spi);
181 int ret;
182
183 /* allocate settings on the first call */
184 if (!cs) {
Axel Linc586feb2014-03-31 11:37:29 +0800185 cs = devm_kzalloc(&spi->dev,
186 sizeof(struct s3c24xx_spi_devstate),
187 GFP_KERNEL);
Jingoo Han0375cff2014-04-29 17:20:02 +0900188 if (!cs)
Ben Dooks570327d2009-09-22 16:46:14 -0700189 return -ENOMEM;
Ben Dooks570327d2009-09-22 16:46:14 -0700190
191 cs->spcon = SPCON_DEFAULT;
192 cs->hz = -1;
193 spi->controller_state = cs;
194 }
195
196 /* initialise the state from the device */
197 ret = s3c24xx_spi_update_state(spi, NULL);
198 if (ret)
199 return ret;
Ben Dooks7fba5342006-05-20 15:00:18 -0700200
201 spin_lock(&hw->bitbang.lock);
202 if (!hw->bitbang.busy) {
203 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
204 /* need to ndelay for 0.5 clocktick ? */
205 }
206 spin_unlock(&hw->bitbang.lock);
207
208 return 0;
209}
210
Ben Dooks7fba5342006-05-20 15:00:18 -0700211static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
212{
David Brownell4b1badf2006-12-29 16:48:39 -0800213 return hw->tx ? hw->tx[count] : 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700214}
215
Ben Dooksbec08062009-12-14 22:20:24 -0800216#ifdef CONFIG_SPI_S3C24XX_FIQ
217/* Support for FIQ based pseudo-DMA to improve the transfer speed.
218 *
219 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
220 * used by the FIQ core to move data between main memory and the peripheral
221 * block. Since this is code running on the processor, there is no problem
222 * with cache coherency of the buffers, so we can use any buffer we like.
223 */
224
225/**
226 * struct spi_fiq_code - FIQ code and header
227 * @length: The length of the code fragment, excluding this header.
228 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
229 * @data: The code itself to install as a FIQ handler.
230 */
231struct spi_fiq_code {
232 u32 length;
233 u32 ack_offset;
234 u8 data[0];
235};
236
237extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
238extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
239extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
240
241/**
242 * ack_bit - turn IRQ into IRQ acknowledgement bit
243 * @irq: The interrupt number
244 *
245 * Returns the bit to write to the interrupt acknowledge register.
246 */
247static inline u32 ack_bit(unsigned int irq)
248{
249 return 1 << (irq - IRQ_EINT0);
250}
251
252/**
253 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
254 * @hw: The hardware state.
255 *
256 * Claim the FIQ handler (only one can be active at any one time) and
257 * then setup the correct transfer code for this transfer.
258 *
Daniel Mack3ad2f3f2010-02-03 08:01:28 +0800259 * This call updates all the necessary state information if successful,
Ben Dooksbec08062009-12-14 22:20:24 -0800260 * so the caller does not need to do anything more than start the transfer
261 * as normal, since the IRQ will have been re-routed to the FIQ handler.
262*/
Sachin Kamatcfeb3312013-09-10 11:20:13 +0530263static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
Ben Dooksbec08062009-12-14 22:20:24 -0800264{
265 struct pt_regs regs;
266 enum spi_fiq_mode mode;
267 struct spi_fiq_code *code;
268 int ret;
269
270 if (!hw->fiq_claimed) {
271 /* try and claim fiq if we haven't got it, and if not
272 * then return and simply use another transfer method */
273
274 ret = claim_fiq(&hw->fiq_handler);
275 if (ret)
276 return;
277 }
278
279 if (hw->tx && !hw->rx)
280 mode = FIQ_MODE_TX;
281 else if (hw->rx && !hw->tx)
282 mode = FIQ_MODE_RX;
283 else
284 mode = FIQ_MODE_TXRX;
285
286 regs.uregs[fiq_rspi] = (long)hw->regs;
287 regs.uregs[fiq_rrx] = (long)hw->rx;
288 regs.uregs[fiq_rtx] = (long)hw->tx + 1;
289 regs.uregs[fiq_rcount] = hw->len - 1;
290 regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
291
292 set_fiq_regs(&regs);
293
294 if (hw->fiq_mode != mode) {
295 u32 *ack_ptr;
296
297 hw->fiq_mode = mode;
298
299 switch (mode) {
300 case FIQ_MODE_TX:
301 code = &s3c24xx_spi_fiq_tx;
302 break;
303 case FIQ_MODE_RX:
304 code = &s3c24xx_spi_fiq_rx;
305 break;
306 case FIQ_MODE_TXRX:
307 code = &s3c24xx_spi_fiq_txrx;
308 break;
309 default:
310 code = NULL;
311 }
312
313 BUG_ON(!code);
314
315 ack_ptr = (u32 *)&code->data[code->ack_offset];
316 *ack_ptr = ack_bit(hw->irq);
317
318 set_fiq_handler(&code->data, code->length);
319 }
320
321 s3c24xx_set_fiq(hw->irq, true);
322
323 hw->fiq_mode = mode;
324 hw->fiq_inuse = 1;
325}
326
327/**
328 * s3c24xx_spi_fiqop - FIQ core code callback
329 * @pw: Data registered with the handler
330 * @release: Whether this is a release or a return.
331 *
332 * Called by the FIQ code when another module wants to use the FIQ, so
333 * return whether we are currently using this or not and then update our
334 * internal state.
335 */
336static int s3c24xx_spi_fiqop(void *pw, int release)
337{
338 struct s3c24xx_spi *hw = pw;
339 int ret = 0;
340
341 if (release) {
342 if (hw->fiq_inuse)
343 ret = -EBUSY;
344
345 /* note, we do not need to unroute the FIQ, as the FIQ
346 * vector code de-routes it to signal the end of transfer */
347
348 hw->fiq_mode = FIQ_MODE_NONE;
349 hw->fiq_claimed = 0;
350 } else {
351 hw->fiq_claimed = 1;
352 }
353
354 return ret;
355}
356
357/**
358 * s3c24xx_spi_initfiq - setup the information for the FIQ core
359 * @hw: The hardware state.
360 *
361 * Setup the fiq_handler block to pass to the FIQ core.
362 */
363static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
364{
365 hw->fiq_handler.dev_id = hw;
366 hw->fiq_handler.name = dev_name(hw->dev);
367 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
368}
369
370/**
371 * s3c24xx_spi_usefiq - return if we should be using FIQ.
372 * @hw: The hardware state.
373 *
374 * Return true if the platform data specifies whether this channel is
375 * allowed to use the FIQ.
376 */
377static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
378{
379 return hw->pdata->use_fiq;
380}
381
382/**
383 * s3c24xx_spi_usingfiq - return if channel is using FIQ
384 * @spi: The hardware state.
385 *
386 * Return whether the channel is currently using the FIQ (separate from
387 * whether the FIQ is claimed).
388 */
389static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
390{
391 return spi->fiq_inuse;
392}
393#else
394
395static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
396static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
397static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
398static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
399
400#endif /* CONFIG_SPI_S3C24XX_FIQ */
401
Ben Dooks7fba5342006-05-20 15:00:18 -0700402static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
403{
404 struct s3c24xx_spi *hw = to_hw(spi);
405
Ben Dooks7fba5342006-05-20 15:00:18 -0700406 hw->tx = t->tx_buf;
407 hw->rx = t->rx_buf;
408 hw->len = t->len;
409 hw->count = 0;
410
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700411 init_completion(&hw->done);
412
Ben Dooksbec08062009-12-14 22:20:24 -0800413 hw->fiq_inuse = 0;
414 if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
415 s3c24xx_spi_tryfiq(hw);
416
Ben Dooks7fba5342006-05-20 15:00:18 -0700417 /* send the first byte */
418 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
Ben Dooks4bb5eba2008-04-15 14:34:44 -0700419
Ben Dooks7fba5342006-05-20 15:00:18 -0700420 wait_for_completion(&hw->done);
Ben Dooks7fba5342006-05-20 15:00:18 -0700421 return hw->count;
422}
423
David Howells7d12e782006-10-05 14:55:46 +0100424static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700425{
426 struct s3c24xx_spi *hw = dev;
427 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
428 unsigned int count = hw->count;
429
430 if (spsta & S3C2410_SPSTA_DCOL) {
431 dev_dbg(hw->dev, "data-collision\n");
432 complete(&hw->done);
433 goto irq_done;
434 }
435
436 if (!(spsta & S3C2410_SPSTA_READY)) {
437 dev_dbg(hw->dev, "spi not ready for tx?\n");
438 complete(&hw->done);
439 goto irq_done;
440 }
441
Ben Dooksbec08062009-12-14 22:20:24 -0800442 if (!s3c24xx_spi_usingfiq(hw)) {
443 hw->count++;
Ben Dooks7fba5342006-05-20 15:00:18 -0700444
Ben Dooksbec08062009-12-14 22:20:24 -0800445 if (hw->rx)
446 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
Ben Dooks7fba5342006-05-20 15:00:18 -0700447
Ben Dooksbec08062009-12-14 22:20:24 -0800448 count++;
Ben Dooks7fba5342006-05-20 15:00:18 -0700449
Ben Dooksbec08062009-12-14 22:20:24 -0800450 if (count < hw->len)
451 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
452 else
453 complete(&hw->done);
454 } else {
455 hw->count = hw->len;
456 hw->fiq_inuse = 0;
457
458 if (hw->rx)
459 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
460
Ben Dooks7fba5342006-05-20 15:00:18 -0700461 complete(&hw->done);
Ben Dooksbec08062009-12-14 22:20:24 -0800462 }
Ben Dooks7fba5342006-05-20 15:00:18 -0700463
464 irq_done:
465 return IRQ_HANDLED;
466}
467
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700468static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
469{
470 /* for the moment, permanently enable the clock */
471
472 clk_enable(hw->clk);
473
474 /* program defaults into the registers */
475
476 writeb(0xff, hw->regs + S3C2410_SPPRE);
477 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
478 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
Ben Dookscf46b972008-10-15 22:02:41 -0700479
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800480 if (hw->pdata) {
481 if (hw->set_cs == s3c24xx_spi_gpiocs)
482 gpio_direction_output(hw->pdata->pin_cs, 1);
483
484 if (hw->pdata->gpio_setup)
485 hw->pdata->gpio_setup(hw->pdata, 1);
486 }
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700487}
488
Grant Likelyfd4a3192012-12-07 16:57:14 +0000489static int s3c24xx_spi_probe(struct platform_device *pdev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700490{
Ben Dooks50f426b2008-04-15 14:34:45 -0700491 struct s3c2410_spi_info *pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700492 struct s3c24xx_spi *hw;
493 struct spi_master *master;
Ben Dooks7fba5342006-05-20 15:00:18 -0700494 struct resource *res;
495 int err = 0;
Ben Dooks7fba5342006-05-20 15:00:18 -0700496
497 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
498 if (master == NULL) {
499 dev_err(&pdev->dev, "No memory for spi_master\n");
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900500 return -ENOMEM;
Ben Dooks7fba5342006-05-20 15:00:18 -0700501 }
502
503 hw = spi_master_get_devdata(master);
504 memset(hw, 0, sizeof(struct s3c24xx_spi));
505
Axel Lin94c69f72013-09-10 15:43:41 +0800506 hw->master = master;
Jingoo Han8074cf02013-07-30 16:58:59 +0900507 hw->pdata = pdata = dev_get_platdata(&pdev->dev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700508 hw->dev = &pdev->dev;
509
Ben Dooks50f426b2008-04-15 14:34:45 -0700510 if (pdata == NULL) {
Ben Dooks7fba5342006-05-20 15:00:18 -0700511 dev_err(&pdev->dev, "No platform data supplied\n");
512 err = -ENOENT;
513 goto err_no_pdata;
514 }
515
516 platform_set_drvdata(pdev, hw);
517 init_completion(&hw->done);
518
Ben Dooksbec08062009-12-14 22:20:24 -0800519 /* initialise fiq handler */
520
521 s3c24xx_spi_initfiq(hw);
522
Ben Dooksd1e77802008-04-15 14:34:46 -0700523 /* setup the master state. */
524
David Brownelle7db06b2009-06-17 16:26:04 -0700525 /* the spi->mode bits understood by this driver: */
526 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
527
Ben Dooksd1e77802008-04-15 14:34:46 -0700528 master->num_chipselect = hw->pdata->num_cs;
Ben Dookscb1d0a72008-07-28 15:46:33 -0700529 master->bus_num = pdata->bus_num;
Axel Lin08850fa2014-02-14 20:38:16 +0800530 master->bits_per_word_mask = SPI_BPW_MASK(8);
Ben Dooksd1e77802008-04-15 14:34:46 -0700531
Ben Dooks7fba5342006-05-20 15:00:18 -0700532 /* setup the state for the bitbang driver */
533
534 hw->bitbang.master = hw->master;
535 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
536 hw->bitbang.chipselect = s3c24xx_spi_chipsel;
537 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
Ben Dooks570327d2009-09-22 16:46:14 -0700538
539 hw->master->setup = s3c24xx_spi_setup;
Ben Dooks7fba5342006-05-20 15:00:18 -0700540
541 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
542
543 /* find and map our resources */
Ben Dooks7fba5342006-05-20 15:00:18 -0700544 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900545 hw->regs = devm_ioremap_resource(&pdev->dev, res);
546 if (IS_ERR(hw->regs)) {
547 err = PTR_ERR(hw->regs);
548 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700549 }
550
551 hw->irq = platform_get_irq(pdev, 0);
552 if (hw->irq < 0) {
553 dev_err(&pdev->dev, "No IRQ specified\n");
554 err = -ENOENT;
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900555 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700556 }
557
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900558 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
559 pdev->name, hw);
Ben Dooks7fba5342006-05-20 15:00:18 -0700560 if (err) {
561 dev_err(&pdev->dev, "Cannot claim IRQ\n");
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900562 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700563 }
564
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900565 hw->clk = devm_clk_get(&pdev->dev, "spi");
Ben Dooks7fba5342006-05-20 15:00:18 -0700566 if (IS_ERR(hw->clk)) {
567 dev_err(&pdev->dev, "No clock for device\n");
568 err = PTR_ERR(hw->clk);
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900569 goto err_no_pdata;
Ben Dooks7fba5342006-05-20 15:00:18 -0700570 }
571
Ben Dooks7fba5342006-05-20 15:00:18 -0700572 /* setup any gpio we can */
573
Ben Dooks50f426b2008-04-15 14:34:45 -0700574 if (!pdata->set_cs) {
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800575 if (pdata->pin_cs < 0) {
576 dev_err(&pdev->dev, "No chipselect pin\n");
Julia Lawallb2af0452012-08-22 13:42:47 +0200577 err = -EINVAL;
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800578 goto err_register;
579 }
Ben Dooks8736b922007-01-26 00:56:43 -0800580
Jingoo Hanc9f722e2013-12-09 19:19:13 +0900581 err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
582 dev_name(&pdev->dev));
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800583 if (err) {
584 dev_err(&pdev->dev, "Failed to get gpio for cs\n");
585 goto err_register;
586 }
587
588 hw->set_cs = s3c24xx_spi_gpiocs;
589 gpio_direction_output(pdata->pin_cs, 1);
Ben Dooks8736b922007-01-26 00:56:43 -0800590 } else
Ben Dooks50f426b2008-04-15 14:34:45 -0700591 hw->set_cs = pdata->set_cs;
Ben Dooks7fba5342006-05-20 15:00:18 -0700592
Ben Dooksee9c1fb2009-01-06 14:41:44 -0800593 s3c24xx_spi_initialsetup(hw);
594
Ben Dooks7fba5342006-05-20 15:00:18 -0700595 /* register our spi controller */
596
597 err = spi_bitbang_start(&hw->bitbang);
598 if (err) {
599 dev_err(&pdev->dev, "Failed to register SPI master\n");
600 goto err_register;
601 }
602
Ben Dooks7fba5342006-05-20 15:00:18 -0700603 return 0;
604
605 err_register:
606 clk_disable(hw->clk);
Ben Dooks7fba5342006-05-20 15:00:18 -0700607
Ben Dooks7fba5342006-05-20 15:00:18 -0700608 err_no_pdata:
Joe Perchesa419aef2009-08-18 11:18:35 -0700609 spi_master_put(hw->master);
Ben Dooks7fba5342006-05-20 15:00:18 -0700610 return err;
611}
612
Grant Likelyfd4a3192012-12-07 16:57:14 +0000613static int s3c24xx_spi_remove(struct platform_device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700614{
615 struct s3c24xx_spi *hw = platform_get_drvdata(dev);
616
Axel Linc6e7b8c2011-05-15 07:35:16 +0800617 spi_bitbang_stop(&hw->bitbang);
Ben Dooks7fba5342006-05-20 15:00:18 -0700618 clk_disable(hw->clk);
Ben Dooks7fba5342006-05-20 15:00:18 -0700619 spi_master_put(hw->master);
620 return 0;
621}
622
623
624#ifdef CONFIG_PM
625
Ben Dooks6d613202009-09-22 16:46:13 -0700626static int s3c24xx_spi_suspend(struct device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700627{
Axel Lina12163942013-08-09 15:35:16 +0800628 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
Axel Lin38060372014-03-05 15:17:23 +0800629 int ret;
630
631 ret = spi_master_suspend(hw->master);
632 if (ret)
633 return ret;
Ben Dooks7fba5342006-05-20 15:00:18 -0700634
Ben Dookscf46b972008-10-15 22:02:41 -0700635 if (hw->pdata && hw->pdata->gpio_setup)
636 hw->pdata->gpio_setup(hw->pdata, 0);
637
Ben Dooks7fba5342006-05-20 15:00:18 -0700638 clk_disable(hw->clk);
639 return 0;
640}
641
Ben Dooks6d613202009-09-22 16:46:13 -0700642static int s3c24xx_spi_resume(struct device *dev)
Ben Dooks7fba5342006-05-20 15:00:18 -0700643{
Axel Lina12163942013-08-09 15:35:16 +0800644 struct s3c24xx_spi *hw = dev_get_drvdata(dev);
Ben Dooks7fba5342006-05-20 15:00:18 -0700645
Ben Dooks5aa6cf32008-08-04 13:41:10 -0700646 s3c24xx_spi_initialsetup(hw);
Axel Lin38060372014-03-05 15:17:23 +0800647 return spi_master_resume(hw->master);
Ben Dooks7fba5342006-05-20 15:00:18 -0700648}
649
Alexey Dobriyan47145212009-12-14 18:00:08 -0800650static const struct dev_pm_ops s3c24xx_spi_pmops = {
Ben Dooks6d613202009-09-22 16:46:13 -0700651 .suspend = s3c24xx_spi_suspend,
652 .resume = s3c24xx_spi_resume,
653};
654
655#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
Ben Dooks7fba5342006-05-20 15:00:18 -0700656#else
Ben Dooks6d613202009-09-22 16:46:13 -0700657#define S3C24XX_SPI_PMOPS NULL
658#endif /* CONFIG_PM */
Ben Dooks7fba5342006-05-20 15:00:18 -0700659
Kay Sievers7e38c3c2008-04-10 21:29:20 -0700660MODULE_ALIAS("platform:s3c2410-spi");
Ben Dooks42cde432008-09-13 02:33:24 -0700661static struct platform_driver s3c24xx_spi_driver = {
Grant Likely940ab882011-10-05 11:29:49 -0600662 .probe = s3c24xx_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +0000663 .remove = s3c24xx_spi_remove,
Ben Dooks7fba5342006-05-20 15:00:18 -0700664 .driver = {
665 .name = "s3c2410-spi",
Ben Dooks6d613202009-09-22 16:46:13 -0700666 .pm = S3C24XX_SPI_PMOPS,
Ben Dooks7fba5342006-05-20 15:00:18 -0700667 },
668};
Grant Likely940ab882011-10-05 11:29:49 -0600669module_platform_driver(s3c24xx_spi_driver);
Ben Dooks7fba5342006-05-20 15:00:18 -0700670
671MODULE_DESCRIPTION("S3C24XX SPI Driver");
672MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
673MODULE_LICENSE("GPL");