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Magnus Dammd28bdf02010-05-11 13:29:17 +00001#ifndef __SH_CLOCK_H
2#define __SH_CLOCK_H
3
4#include <linux/list.h>
5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
Paul Mundt28085bc2010-10-15 16:46:37 +09007#include <linux/types.h>
8#include <linux/kref.h>
Magnus Dammd28bdf02010-05-11 13:29:17 +00009#include <linux/clk.h>
10#include <linux/err.h>
11
12struct clk;
13
Paul Mundt28085bc2010-10-15 16:46:37 +090014struct clk_mapping {
15 phys_addr_t phys;
16 void __iomem *base;
17 unsigned long len;
18 struct kref ref;
19};
20
Magnus Damm84c36ff2012-02-29 22:18:19 +090021struct sh_clk_ops {
Paul Mundt549015c2010-11-15 18:48:25 +090022#ifdef CONFIG_SH_CLK_CPG_LEGACY
Magnus Dammd28bdf02010-05-11 13:29:17 +000023 void (*init)(struct clk *clk);
Paul Mundt549015c2010-11-15 18:48:25 +090024#endif
Magnus Dammd28bdf02010-05-11 13:29:17 +000025 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
Paul Mundt35a96c72010-11-15 18:18:32 +090028 int (*set_rate)(struct clk *clk, unsigned long rate);
Magnus Dammd28bdf02010-05-11 13:29:17 +000029 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
31};
32
Paul Mundt1111cc12012-05-25 15:21:43 +090033#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
34#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
35#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
36
Magnus Dammd28bdf02010-05-11 13:29:17 +000037struct clk {
38 struct list_head node;
Magnus Dammd28bdf02010-05-11 13:29:17 +000039 struct clk *parent;
Guennadi Liakhovetskib5272b502010-07-21 10:13:06 +000040 struct clk **parent_table; /* list of parents to */
41 unsigned short parent_num; /* choose between */
42 unsigned char src_shift; /* source clock field in the */
43 unsigned char src_width; /* configuration register */
Magnus Damm84c36ff2012-02-29 22:18:19 +090044 struct sh_clk_ops *ops;
Magnus Dammd28bdf02010-05-11 13:29:17 +000045
46 struct list_head children;
47 struct list_head sibling; /* node for children */
48
49 int usecount;
50
51 unsigned long rate;
52 unsigned long flags;
53
54 void __iomem *enable_reg;
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +010055 void __iomem *status_reg;
Magnus Dammd28bdf02010-05-11 13:29:17 +000056 unsigned int enable_bit;
Magnus Dammeda20302011-12-08 22:58:54 +090057 void __iomem *mapped_reg;
Magnus Dammd28bdf02010-05-11 13:29:17 +000058
Paul Mundt1111cc12012-05-25 15:21:43 +090059 unsigned int div_mask;
Magnus Dammd28bdf02010-05-11 13:29:17 +000060 unsigned long arch_flags;
61 void *priv;
Paul Mundt28085bc2010-10-15 16:46:37 +090062 struct clk_mapping *mapping;
Magnus Dammd28bdf02010-05-11 13:29:17 +000063 struct cpufreq_frequency_table *freq_table;
Paul Mundtf5869032010-10-15 18:17:35 +090064 unsigned int nr_freqs;
Magnus Dammd28bdf02010-05-11 13:29:17 +000065};
66
Paul Mundt4d6ddb02012-04-11 12:05:50 +090067#define CLK_ENABLE_ON_INIT BIT(0)
68
69#define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
70#define CLK_ENABLE_REG_16BIT BIT(2)
71#define CLK_ENABLE_REG_8BIT BIT(3)
72
Paul Mundt764f4e42012-05-25 16:34:48 +090073#define CLK_MASK_DIV_ON_DISABLE BIT(4)
74
Paul Mundt4d6ddb02012-04-11 12:05:50 +090075#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
76 CLK_ENABLE_REG_16BIT | \
77 CLK_ENABLE_REG_8BIT)
Magnus Dammd28bdf02010-05-11 13:29:17 +000078
Paul Mundta71ba092010-05-13 18:42:25 +090079/* drivers/sh/clk.c */
Magnus Dammd28bdf02010-05-11 13:29:17 +000080unsigned long followparent_recalc(struct clk *);
81void recalculate_root_clocks(void);
82void propagate_rate(struct clk *);
83int clk_reparent(struct clk *child, struct clk *parent);
84int clk_register(struct clk *);
85void clk_unregister(struct clk *);
Magnus Damm8b5ee112010-05-11 13:29:25 +000086void clk_enable_init_clocks(void);
Magnus Dammd28bdf02010-05-11 13:29:17 +000087
Magnus Dammd28bdf02010-05-11 13:29:17 +000088struct clk_div_mult_table {
89 unsigned int *divisors;
90 unsigned int nr_divisors;
91 unsigned int *multipliers;
92 unsigned int nr_multipliers;
93};
94
95struct cpufreq_frequency_table;
96void clk_rate_table_build(struct clk *clk,
97 struct cpufreq_frequency_table *freq_table,
98 int nr_freqs,
99 struct clk_div_mult_table *src_table,
100 unsigned long *bitmap);
101
102long clk_rate_table_round(struct clk *clk,
103 struct cpufreq_frequency_table *freq_table,
104 unsigned long rate);
105
106int clk_rate_table_find(struct clk *clk,
107 struct cpufreq_frequency_table *freq_table,
108 unsigned long rate);
109
Paul Mundt8e122db2010-10-15 18:33:24 +0900110long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
111 unsigned int div_max, unsigned long rate);
112
Kuninori Morimotodd2c0ca2011-09-19 18:51:13 -0700113long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
114 unsigned int mult_max, unsigned long rate);
115
Guennadi Liakhovetski6af26c62010-11-02 11:27:24 +0000116long clk_round_parent(struct clk *clk, unsigned long target,
117 unsigned long *best_freq, unsigned long *parent_freq,
118 unsigned int div_min, unsigned int div_max);
119
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +0100120#define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _status_reg, _flags) \
Magnus Dammd28bdf02010-05-11 13:29:17 +0000121{ \
122 .parent = _parent, \
123 .enable_reg = (void __iomem *)_enable_reg, \
124 .enable_bit = _enable_bit, \
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +0100125 .status_reg = _status_reg, \
Magnus Dammd28bdf02010-05-11 13:29:17 +0000126 .flags = _flags, \
127}
128
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +0100129#define SH_CLK_MSTP32(_p, _r, _b, _f) \
130 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_32BIT)
Paul Mundt4d6ddb02012-04-11 12:05:50 +0900131
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +0100132#define SH_CLK_MSTP32_STS(_p, _r, _b, _s, _f) \
133 SH_CLK_MSTP(_p, _r, _b, _s, _f | CLK_ENABLE_REG_32BIT)
Paul Mundt4d6ddb02012-04-11 12:05:50 +0900134
Guennadi Liakhovetskia028c6d2013-12-14 16:23:51 +0100135#define SH_CLK_MSTP16(_p, _r, _b, _f) \
136 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_16BIT)
137
138#define SH_CLK_MSTP8(_p, _r, _b, _f) \
139 SH_CLK_MSTP(_p, _r, _b, 0, _f | CLK_ENABLE_REG_8BIT)
Paul Mundt4d6ddb02012-04-11 12:05:50 +0900140
141int sh_clk_mstp_register(struct clk *clks, int nr);
142
143/*
144 * MSTP registration never really cared about access size, despite the
145 * original enable/disable pairs assuming a 32-bit access. Clocks are
146 * responsible for defining their access sizes either directly or via the
147 * clock definition wrappers.
148 */
149static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
150{
151 return sh_clk_mstp_register(clks, nr);
152}
Magnus Dammd28bdf02010-05-11 13:29:17 +0000153
154#define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
155{ \
156 .parent = _parent, \
157 .enable_reg = (void __iomem *)_reg, \
158 .enable_bit = _shift, \
159 .arch_flags = _div_bitmap, \
Paul Mundt1111cc12012-05-25 15:21:43 +0900160 .div_mask = SH_CLK_DIV4_MSK, \
Magnus Dammd28bdf02010-05-11 13:29:17 +0000161 .flags = _flags, \
162}
163
Paul Mundta60977a2012-05-25 14:59:26 +0900164struct clk_div_table {
Magnus Dammd28bdf02010-05-11 13:29:17 +0000165 struct clk_div_mult_table *div_mult_table;
166 void (*kick)(struct clk *clk);
167};
168
Paul Mundta60977a2012-05-25 14:59:26 +0900169#define clk_div4_table clk_div_table
170
Magnus Dammd28bdf02010-05-11 13:29:17 +0000171int sh_clk_div4_register(struct clk *clks, int nr,
172 struct clk_div4_table *table);
173int sh_clk_div4_enable_register(struct clk *clks, int nr,
174 struct clk_div4_table *table);
175int sh_clk_div4_reparent_register(struct clk *clks, int nr,
176 struct clk_div4_table *table);
177
Kuninori Morimoto56242a12011-11-21 21:33:18 -0800178#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000179 _num_parents, _src_shift, _src_width) \
180{ \
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000181 .enable_reg = (void __iomem *)_reg, \
Paul Mundt75f5f8a2012-05-25 15:26:01 +0900182 .enable_bit = 0, /* unused */ \
Paul Mundt764f4e42012-05-25 16:34:48 +0900183 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
Paul Mundt1111cc12012-05-25 15:21:43 +0900184 .div_mask = SH_CLK_DIV6_MSK, \
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000185 .parent_table = _parents, \
186 .parent_num = _num_parents, \
187 .src_shift = _src_shift, \
188 .src_width = _src_width, \
Magnus Dammd28bdf02010-05-11 13:29:17 +0000189}
190
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000191#define SH_CLK_DIV6(_parent, _reg, _flags) \
Kuninori Morimoto56242a12011-11-21 21:33:18 -0800192{ \
193 .parent = _parent, \
194 .enable_reg = (void __iomem *)_reg, \
Paul Mundt75f5f8a2012-05-25 15:26:01 +0900195 .enable_bit = 0, /* unused */ \
Paul Mundt1111cc12012-05-25 15:21:43 +0900196 .div_mask = SH_CLK_DIV6_MSK, \
Paul Mundt764f4e42012-05-25 16:34:48 +0900197 .flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
Kuninori Morimoto56242a12011-11-21 21:33:18 -0800198}
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000199
Magnus Dammd28bdf02010-05-11 13:29:17 +0000200int sh_clk_div6_register(struct clk *clks, int nr);
Guennadi Liakhovetskib3dd51a2010-07-21 10:13:10 +0000201int sh_clk_div6_reparent_register(struct clk *clks, int nr);
Magnus Dammd28bdf02010-05-11 13:29:17 +0000202
Kuninori Morimoto15220432011-07-06 02:54:11 +0000203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
205#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
206
Kuninori Morimoto9d626ec2012-10-30 20:06:55 -0700207/* .enable_reg will be updated to .mapping on sh_clk_fsidiv_register() */
208#define SH_CLK_FSIDIV(_reg, _parent) \
209{ \
210 .enable_reg = (void __iomem *)_reg, \
211 .parent = _parent, \
212}
213
214int sh_clk_fsidiv_register(struct clk *clks, int nr);
215
Magnus Dammd28bdf02010-05-11 13:29:17 +0000216#endif /* __SH_CLOCK_H */