blob: 84be70157ad6b6e9809bd007c422e223c359d429 [file] [log] [blame]
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01001/*
2 * TI DaVinci GPIO Support
3 *
David Brownelldce11152008-09-07 23:41:04 -07004 * Copyright (c) 2006-2007 David Brownell
Vladimir Barinov3d9edf02007-07-10 13:03:43 +01005 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
Russell King2f8163b2011-07-26 10:53:52 +010012#include <linux/gpio.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010013#include <linux/errno.h>
14#include <linux/kernel.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010015#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
KV Sujith118150f2013-08-18 10:48:58 +053018#include <linux/irq.h>
19#include <linux/platform_device.h>
20#include <linux/platform_data/gpio-davinci.h>
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010021
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040022struct davinci_gpio_regs {
23 u32 dir;
24 u32 out_data;
25 u32 set_data;
26 u32 clr_data;
27 u32 in_data;
28 u32 set_rising;
29 u32 clr_rising;
30 u32 set_falling;
31 u32 clr_falling;
32 u32 intstat;
33};
34
Philip Avinash131a10a2013-08-18 10:48:57 +053035#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
36
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040037#define chip2controller(chip) \
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040038 container_of(chip, struct davinci_gpio_controller, chip)
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040039
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040040static void __iomem *gpio_base;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010041
KV Sujith118150f2013-08-18 10:48:58 +053042static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010043{
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040044 void __iomem *ptr;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040045
46 if (gpio < 32 * 1)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040047 ptr = gpio_base + 0x10;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040048 else if (gpio < 32 * 2)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040049 ptr = gpio_base + 0x38;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040050 else if (gpio < 32 * 3)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040051 ptr = gpio_base + 0x60;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040052 else if (gpio < 32 * 4)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040053 ptr = gpio_base + 0x88;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040054 else if (gpio < 32 * 5)
Cyril Chemparathyb8d44292010-05-07 17:06:32 -040055 ptr = gpio_base + 0xb0;
Cyril Chemparathyc12f4152010-05-01 18:37:53 -040056 else
57 ptr = NULL;
58 return ptr;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010059}
60
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040061static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
Kevin Hilman21ce8732010-02-25 16:49:56 -080062{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040063 struct davinci_gpio_regs __iomem *g;
Kevin Hilman21ce8732010-02-25 16:49:56 -080064
Thomas Gleixner6845664a2011-03-24 13:25:22 +010065 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
Kevin Hilman21ce8732010-02-25 16:49:56 -080066
67 return g;
68}
69
KV Sujith118150f2013-08-18 10:48:58 +053070static int davinci_gpio_irq_setup(struct platform_device *pdev);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010071
72/*--------------------------------------------------------------------------*/
73
Cyril Chemparathy5b3a05c2010-05-01 18:38:27 -040074/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040075static inline int __davinci_direction(struct gpio_chip *chip,
76 unsigned offset, bool out, int value)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010077{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -040078 struct davinci_gpio_controller *d = chip2controller(chip);
79 struct davinci_gpio_regs __iomem *g = d->regs;
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040080 unsigned long flags;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010081 u32 temp;
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040082 u32 mask = 1 << offset;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010083
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040084 spin_lock_irqsave(&d->lock, flags);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010085 temp = __raw_readl(&g->dir);
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040086 if (out) {
87 temp &= ~mask;
88 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
89 } else {
90 temp |= mask;
91 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010092 __raw_writel(temp, &g->dir);
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -040093 spin_unlock_irqrestore(&d->lock, flags);
David Brownelldce11152008-09-07 23:41:04 -070094
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010095 return 0;
96}
Vladimir Barinov3d9edf02007-07-10 13:03:43 +010097
Cyril Chemparathyba4a9842010-05-01 18:37:51 -040098static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
99{
100 return __davinci_direction(chip, offset, false, 0);
101}
102
103static int
104davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
105{
106 return __davinci_direction(chip, offset, true, value);
107}
108
David Brownelldce11152008-09-07 23:41:04 -0700109/*
110 * Read the pin's value (works even if it's set up as output);
111 * returns zero/nonzero.
112 *
113 * Note that changes are synched to the GPIO clock, so reading values back
114 * right after you've set them may give old values.
115 */
116static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100117{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400118 struct davinci_gpio_controller *d = chip2controller(chip);
119 struct davinci_gpio_regs __iomem *g = d->regs;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100120
David Brownelldce11152008-09-07 23:41:04 -0700121 return (1 << offset) & __raw_readl(&g->in_data);
122}
123
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100124/*
David Brownelldce11152008-09-07 23:41:04 -0700125 * Assuming the pin is muxed as a gpio output, set its output value.
126 */
127static void
128davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
129{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400130 struct davinci_gpio_controller *d = chip2controller(chip);
131 struct davinci_gpio_regs __iomem *g = d->regs;
David Brownelldce11152008-09-07 23:41:04 -0700132
133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
134}
135
KV Sujith118150f2013-08-18 10:48:58 +0530136static int davinci_gpio_probe(struct platform_device *pdev)
David Brownelldce11152008-09-07 23:41:04 -0700137{
138 int i, base;
Mark A. Greera9949552009-04-15 12:40:35 -0700139 unsigned ngpio;
KV Sujith118150f2013-08-18 10:48:58 +0530140 struct davinci_gpio_controller *chips;
141 struct davinci_gpio_platform_data *pdata;
142 struct davinci_gpio_regs __iomem *regs;
143 struct device *dev = &pdev->dev;
144 struct resource *res;
David Brownelldce11152008-09-07 23:41:04 -0700145
KV Sujith118150f2013-08-18 10:48:58 +0530146 pdata = dev->platform_data;
147 if (!pdata) {
148 dev_err(dev, "No platform data found\n");
149 return -EINVAL;
150 }
Cyril Chemparathy686b6342010-05-01 18:37:54 -0400151
Mark A. Greera9949552009-04-15 12:40:35 -0700152 /*
153 * The gpio banks conceptually expose a segmented bitmap,
David Brownell474dad52008-12-07 11:46:23 -0800154 * and "ngpio" is one more than the largest zero-based
155 * bit index that's valid.
156 */
KV Sujith118150f2013-08-18 10:48:58 +0530157 ngpio = pdata->ngpio;
Mark A. Greera9949552009-04-15 12:40:35 -0700158 if (ngpio == 0) {
KV Sujith118150f2013-08-18 10:48:58 +0530159 dev_err(dev, "How many GPIOs?\n");
David Brownell474dad52008-12-07 11:46:23 -0800160 return -EINVAL;
161 }
162
163 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
164 ngpio = DAVINCI_N_GPIO;
165
KV Sujith118150f2013-08-18 10:48:58 +0530166 chips = devm_kzalloc(dev,
167 ngpio * sizeof(struct davinci_gpio_controller),
168 GFP_KERNEL);
169 if (!chips) {
170 dev_err(dev, "Memory allocation failed\n");
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400171 return -ENOMEM;
KV Sujith118150f2013-08-18 10:48:58 +0530172 }
173
174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175 if (!res) {
176 dev_err(dev, "Invalid memory resource\n");
177 return -EBUSY;
178 }
179
180 gpio_base = devm_ioremap_resource(dev, res);
181 if (IS_ERR(gpio_base))
182 return PTR_ERR(gpio_base);
Cyril Chemparathyb8d44292010-05-07 17:06:32 -0400183
David Brownell474dad52008-12-07 11:46:23 -0800184 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
David Brownelldce11152008-09-07 23:41:04 -0700185 chips[i].chip.label = "DaVinci";
186
187 chips[i].chip.direction_input = davinci_direction_in;
188 chips[i].chip.get = davinci_gpio_get;
189 chips[i].chip.direction_output = davinci_direction_out;
190 chips[i].chip.set = davinci_gpio_set;
191
192 chips[i].chip.base = base;
David Brownell474dad52008-12-07 11:46:23 -0800193 chips[i].chip.ngpio = ngpio - base;
David Brownelldce11152008-09-07 23:41:04 -0700194 if (chips[i].chip.ngpio > 32)
195 chips[i].chip.ngpio = 32;
196
Cyril Chemparathyb27b6d02010-05-01 18:37:55 -0400197 spin_lock_init(&chips[i].lock);
198
Cyril Chemparathyc12f4152010-05-01 18:37:53 -0400199 regs = gpio2regs(base);
200 chips[i].regs = regs;
201 chips[i].set_data = &regs->set_data;
202 chips[i].clr_data = &regs->clr_data;
203 chips[i].in_data = &regs->in_data;
David Brownelldce11152008-09-07 23:41:04 -0700204
205 gpiochip_add(&chips[i].chip);
206 }
207
KV Sujith118150f2013-08-18 10:48:58 +0530208 platform_set_drvdata(pdev, chips);
209 davinci_gpio_irq_setup(pdev);
David Brownelldce11152008-09-07 23:41:04 -0700210 return 0;
211}
David Brownelldce11152008-09-07 23:41:04 -0700212
213/*--------------------------------------------------------------------------*/
214/*
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100215 * We expect irqs will normally be set up as input pins, but they can also be
216 * used as output pins ... which is convenient for testing.
217 *
David Brownell474dad52008-12-07 11:46:23 -0800218 * NOTE: The first few GPIOs also have direct INTC hookups in addition
David Brownell7a360712009-06-25 17:01:31 -0700219 * to their GPIOBNK0 irq, with a bit less overhead.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100220 *
David Brownell474dad52008-12-07 11:46:23 -0800221 * All those INTC hookups (direct, plus several IRQ banks) can also
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100222 * serve as EDMA event triggers.
223 */
224
Lennert Buytenhek23265442010-11-29 10:27:27 +0100225static void gpio_irq_disable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100226{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100227 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100228 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100229
230 __raw_writel(mask, &g->clr_falling);
231 __raw_writel(mask, &g->clr_rising);
232}
233
Lennert Buytenhek23265442010-11-29 10:27:27 +0100234static void gpio_irq_enable(struct irq_data *d)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100235{
Lennert Buytenhek23265442010-11-29 10:27:27 +0100236 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100237 u32 mask = (u32) irq_data_get_irq_handler_data(d);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100238 unsigned status = irqd_get_trigger_type(d);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100239
David Brownelldf4aab42009-05-04 13:14:27 -0700240 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
241 if (!status)
242 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
243
244 if (status & IRQ_TYPE_EDGE_FALLING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100245 __raw_writel(mask, &g->set_falling);
David Brownelldf4aab42009-05-04 13:14:27 -0700246 if (status & IRQ_TYPE_EDGE_RISING)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100247 __raw_writel(mask, &g->set_rising);
248}
249
Lennert Buytenhek23265442010-11-29 10:27:27 +0100250static int gpio_irq_type(struct irq_data *d, unsigned trigger)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100251{
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100252 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
253 return -EINVAL;
254
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100255 return 0;
256}
257
258static struct irq_chip gpio_irqchip = {
259 .name = "GPIO",
Lennert Buytenhek23265442010-11-29 10:27:27 +0100260 .irq_enable = gpio_irq_enable,
261 .irq_disable = gpio_irq_disable,
262 .irq_set_type = gpio_irq_type,
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100263 .flags = IRQCHIP_SET_TYPE_MASKED,
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100264};
265
266static void
267gpio_irq_handler(unsigned irq, struct irq_desc *desc)
268{
Thomas Gleixner74164012011-06-06 11:51:43 +0200269 struct davinci_gpio_regs __iomem *g;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100270 u32 mask = 0xffff;
Ido Yarivf299bb92011-07-12 00:03:11 +0300271 struct davinci_gpio_controller *d;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100272
Ido Yarivf299bb92011-07-12 00:03:11 +0300273 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
274 g = (struct davinci_gpio_regs __iomem *)d->regs;
Thomas Gleixner74164012011-06-06 11:51:43 +0200275
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100276 /* we only care about one bank */
277 if (irq & 1)
278 mask <<= 16;
279
280 /* temporarily mask (level sensitive) parent IRQ */
Lennert Buytenhek23265442010-11-29 10:27:27 +0100281 desc->irq_data.chip->irq_mask(&desc->irq_data);
282 desc->irq_data.chip->irq_ack(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100283 while (1) {
284 u32 status;
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100285 int n;
286 int res;
287
288 /* ack any irqs */
289 status = __raw_readl(&g->intstat) & mask;
290 if (!status)
291 break;
292 __raw_writel(status, &g->intstat);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100293
294 /* now demux them to the right lowlevel handler */
Ido Yarivf299bb92011-07-12 00:03:11 +0300295 n = d->irq_base;
296 if (irq & 1) {
297 n += 16;
298 status >>= 16;
299 }
300
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100301 while (status) {
302 res = ffs(status);
303 n += res;
Dmitry Baryshkovd8aa0252008-10-09 13:36:24 +0100304 generic_handle_irq(n - 1);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100305 status >>= res;
306 }
307 }
Lennert Buytenhek23265442010-11-29 10:27:27 +0100308 desc->irq_data.chip->irq_unmask(&desc->irq_data);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100309 /* now it may re-trigger */
310}
311
David Brownell7a360712009-06-25 17:01:31 -0700312static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
313{
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400314 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700315
316 if (d->irq_base >= 0)
317 return d->irq_base + offset;
318 else
319 return -ENODEV;
320}
321
322static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
323{
KV Sujith118150f2013-08-18 10:48:58 +0530324 struct davinci_gpio_controller *d = chip2controller(chip);
David Brownell7a360712009-06-25 17:01:31 -0700325
Philip Avinash131a10a2013-08-18 10:48:57 +0530326 /*
327 * NOTE: we assume for now that only irqs in the first gpio_chip
David Brownell7a360712009-06-25 17:01:31 -0700328 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
329 */
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530330 if (offset < d->gpio_unbanked)
KV Sujith118150f2013-08-18 10:48:58 +0530331 return d->gpio_irq + offset;
David Brownell7a360712009-06-25 17:01:31 -0700332 else
333 return -ENODEV;
334}
335
Sekhar Noriab2dde92012-03-11 18:16:11 +0530336static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
David Brownell7a360712009-06-25 17:01:31 -0700337{
Sekhar Noriab2dde92012-03-11 18:16:11 +0530338 struct davinci_gpio_controller *d;
339 struct davinci_gpio_regs __iomem *g;
Sekhar Noriab2dde92012-03-11 18:16:11 +0530340 u32 mask;
341
342 d = (struct davinci_gpio_controller *)data->handler_data;
343 g = (struct davinci_gpio_regs __iomem *)d->regs;
KV Sujith118150f2013-08-18 10:48:58 +0530344 mask = __gpio_mask(data->irq - d->gpio_irq);
David Brownell7a360712009-06-25 17:01:31 -0700345
346 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
347 return -EINVAL;
348
349 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
350 ? &g->set_falling : &g->clr_falling);
351 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
352 ? &g->set_rising : &g->clr_rising);
353
354 return 0;
355}
356
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100357/*
David Brownell474dad52008-12-07 11:46:23 -0800358 * NOTE: for suspend/resume, probably best to make a platform_device with
359 * suspend_late/resume_resume calls hooking into results of the set_wake()
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100360 * calls ... so if no gpios are wakeup events the clock can be disabled,
361 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
David Brownell474dad52008-12-07 11:46:23 -0800362 * (dm6446) can be set appropriately for GPIOV33 pins.
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100363 */
364
KV Sujith118150f2013-08-18 10:48:58 +0530365static int davinci_gpio_irq_setup(struct platform_device *pdev)
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100366{
367 unsigned gpio, irq, bank;
368 struct clk *clk;
David Brownell474dad52008-12-07 11:46:23 -0800369 u32 binten = 0;
Mark A. Greera9949552009-04-15 12:40:35 -0700370 unsigned ngpio, bank_irq;
KV Sujith118150f2013-08-18 10:48:58 +0530371 struct device *dev = &pdev->dev;
372 struct resource *res;
373 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
374 struct davinci_gpio_platform_data *pdata = dev->platform_data;
375 struct davinci_gpio_regs __iomem *g;
David Brownell474dad52008-12-07 11:46:23 -0800376
KV Sujith118150f2013-08-18 10:48:58 +0530377 ngpio = pdata->ngpio;
378 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
379 if (!res) {
380 dev_err(dev, "Invalid IRQ resource\n");
381 return -EBUSY;
David Brownell474dad52008-12-07 11:46:23 -0800382 }
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100383
KV Sujith118150f2013-08-18 10:48:58 +0530384 bank_irq = res->start;
385
386 if (!bank_irq) {
387 dev_err(dev, "Invalid IRQ resource\n");
388 return -ENODEV;
389 }
390
391 clk = devm_clk_get(dev, "gpio");
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100392 if (IS_ERR(clk)) {
393 printk(KERN_ERR "Error %ld getting gpio clock?\n",
394 PTR_ERR(clk));
David Brownell474dad52008-12-07 11:46:23 -0800395 return PTR_ERR(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100396 }
Murali Karicherice6b6582012-08-30 14:03:57 -0400397 clk_prepare_enable(clk);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100398
Philip Avinash131a10a2013-08-18 10:48:57 +0530399 /*
400 * Arrange gpio_to_irq() support, handling either direct IRQs or
David Brownell7a360712009-06-25 17:01:31 -0700401 * banked IRQs. Having GPIOs in the first GPIO bank use direct
402 * IRQs, while the others use banked IRQs, would need some setup
403 * tweaks to recognize hardware which can do that.
404 */
405 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
406 chips[bank].chip.to_irq = gpio_to_irq_banked;
KV Sujith118150f2013-08-18 10:48:58 +0530407 chips[bank].irq_base = pdata->gpio_unbanked
David Brownell7a360712009-06-25 17:01:31 -0700408 ? -EINVAL
KV Sujith118150f2013-08-18 10:48:58 +0530409 : (pdata->intc_irq_num + gpio);
David Brownell7a360712009-06-25 17:01:31 -0700410 }
411
412 /*
413 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
414 * controller only handling trigger modes. We currently assume no
415 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
416 */
KV Sujith118150f2013-08-18 10:48:58 +0530417 if (pdata->gpio_unbanked) {
Sekhar Nori81b279d2012-03-11 18:16:12 +0530418 static struct irq_chip_type gpio_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700419
420 /* pass "bank 0" GPIO IRQs to AINTC */
421 chips[0].chip.to_irq = gpio_to_irq_unbanked;
Lad, Prabhakar34af1ab2013-11-08 12:15:55 +0530422 chips[0].gpio_irq = bank_irq;
423 chips[0].gpio_unbanked = pdata->gpio_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700424 binten = BIT(0);
425
426 /* AINTC handles mask/unmask; GPIO handles triggering */
427 irq = bank_irq;
Sekhar Nori81b279d2012-03-11 18:16:12 +0530428 gpio_unbanked = *container_of(irq_get_chip(irq),
429 struct irq_chip_type, chip);
430 gpio_unbanked.chip.name = "GPIO-AINTC";
431 gpio_unbanked.chip.irq_set_type = gpio_irq_type_unbanked;
David Brownell7a360712009-06-25 17:01:31 -0700432
433 /* default trigger: both edges */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400434 g = gpio2regs(0);
David Brownell7a360712009-06-25 17:01:31 -0700435 __raw_writel(~0, &g->set_falling);
436 __raw_writel(~0, &g->set_rising);
437
438 /* set the direct IRQs up to use that irqchip */
KV Sujith118150f2013-08-18 10:48:58 +0530439 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
Sekhar Nori81b279d2012-03-11 18:16:12 +0530440 irq_set_chip(irq, &gpio_unbanked.chip);
Sekhar Noriab2dde92012-03-11 18:16:11 +0530441 irq_set_handler_data(irq, &chips[gpio / 32]);
Thomas Gleixner5093aec2011-03-24 12:47:04 +0100442 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
David Brownell7a360712009-06-25 17:01:31 -0700443 }
444
445 goto done;
446 }
447
448 /*
449 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
450 * then chain through our own handler.
451 */
David Brownell474dad52008-12-07 11:46:23 -0800452 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
453 gpio < ngpio;
454 bank++, bank_irq++) {
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100455 unsigned i;
456
David Brownell7a360712009-06-25 17:01:31 -0700457 /* disabled by default, enabled only as needed */
Cyril Chemparathy99e9e522010-05-01 18:37:52 -0400458 g = gpio2regs(gpio);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100459 __raw_writel(~0, &g->clr_falling);
460 __raw_writel(~0, &g->clr_rising);
461
462 /* set up all irqs in this bank */
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100463 irq_set_chained_handler(bank_irq, gpio_irq_handler);
Ido Yarivf299bb92011-07-12 00:03:11 +0300464
465 /*
466 * Each chip handles 32 gpios, and each irq bank consists of 16
467 * gpio irqs. Pass the irq bank's corresponding controller to
468 * the chained irq handler.
469 */
470 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100471
David Brownell474dad52008-12-07 11:46:23 -0800472 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100473 irq_set_chip(irq, &gpio_irqchip);
474 irq_set_chip_data(irq, (__force void *)g);
475 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
476 irq_set_handler(irq, handle_simple_irq);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100477 set_irq_flags(irq, IRQF_VALID);
478 }
David Brownell474dad52008-12-07 11:46:23 -0800479
480 binten |= BIT(bank);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100481 }
482
David Brownell7a360712009-06-25 17:01:31 -0700483done:
Philip Avinash131a10a2013-08-18 10:48:57 +0530484 /*
485 * BINTEN -- per-bank interrupt enable. genirq would also let these
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100486 * bits be set/cleared dynamically.
487 */
Philip Avinash131a10a2013-08-18 10:48:57 +0530488 __raw_writel(binten, gpio_base + BINTEN);
Vladimir Barinov3d9edf02007-07-10 13:03:43 +0100489
490 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
491
492 return 0;
493}
KV Sujith118150f2013-08-18 10:48:58 +0530494
495static struct platform_driver davinci_gpio_driver = {
496 .probe = davinci_gpio_probe,
497 .driver = {
498 .name = "davinci_gpio",
499 .owner = THIS_MODULE,
500 },
501};
502
503/**
504 * GPIO driver registration needs to be done before machine_init functions
505 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
506 */
507static int __init davinci_gpio_drv_reg(void)
508{
509 return platform_driver_register(&davinci_gpio_driver);
510}
511postcore_initcall(davinci_gpio_drv_reg);