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Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301/*
2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
4 *
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
Sreekanth Reddya4ffce02014-09-12 15:35:29 +05306 * Copyright (C) 2012-2014 LSI Corporation
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05307 * (mailto:DL-MPTFusionLinux@lsi.com)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * NO WARRANTY
20 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
21 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
23 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
24 * solely responsible for determining the appropriateness of using and
25 * distributing the Program and assumes all risks associated with its
26 * exercise of rights under this Agreement, including but not limited to
27 * the risks and costs of program errors, damage to or loss of data,
28 * programs or equipment, and unavailability or interruption of operations.
29
30 * DISCLAIMER OF LIABILITY
31 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
32 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
34 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
35 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
36 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
37 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
38
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
42 * USA.
43 */
44
Sreekanth Reddyf92363d2012-11-30 07:44:21 +053045#include <linux/kernel.h>
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/init.h>
49#include <linux/slab.h>
50#include <linux/types.h>
51#include <linux/pci.h>
52#include <linux/kdev_t.h>
53#include <linux/blkdev.h>
54#include <linux/delay.h>
55#include <linux/interrupt.h>
56#include <linux/dma-mapping.h>
57#include <linux/io.h>
58#include <linux/time.h>
59#include <linux/kthread.h>
60#include <linux/aer.h>
61
62
63#include "mpt3sas_base.h"
64
65static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
66
67
68#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
69
70 /* maximum controller queue depth */
71#define MAX_HBA_QUEUE_DEPTH 30000
72#define MAX_CHAIN_DEPTH 100000
73static int max_queue_depth = -1;
74module_param(max_queue_depth, int, 0);
75MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
76
77static int max_sgl_entries = -1;
78module_param(max_sgl_entries, int, 0);
79MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
80
81static int msix_disable = -1;
82module_param(msix_disable, int, 0);
83MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
84
Sreekanth Reddy9c500062013-08-14 18:23:20 +053085static int max_msix_vectors = 8;
86module_param(max_msix_vectors, int, 0);
87MODULE_PARM_DESC(max_msix_vectors,
88 " max msix vectors - (default=8)");
Sreekanth Reddyf92363d2012-11-30 07:44:21 +053089
90static int mpt3sas_fwfault_debug;
91MODULE_PARM_DESC(mpt3sas_fwfault_debug,
92 " enable detection of firmware fault and halt firmware - (default=0)");
93
Sreekanth Reddy9b05c912014-09-12 15:35:31 +053094static int
95_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +053096
97/**
98 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
99 *
100 */
101static int
102_scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
103{
104 int ret = param_set_int(val, kp);
105 struct MPT3SAS_ADAPTER *ioc;
106
107 if (ret)
108 return ret;
109
110 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
111 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
112 ioc->fwfault_debug = mpt3sas_fwfault_debug;
113 return 0;
114}
115module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
116 param_get_int, &mpt3sas_fwfault_debug, 0644);
117
118/**
119 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
120 * @arg: input argument, used to derive ioc
121 *
122 * Return 0 if controller is removed from pci subsystem.
123 * Return -1 for other case.
124 */
125static int mpt3sas_remove_dead_ioc_func(void *arg)
126{
127 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
128 struct pci_dev *pdev;
129
130 if ((ioc == NULL))
131 return -1;
132
133 pdev = ioc->pdev;
134 if ((pdev == NULL))
135 return -1;
Rafael J. Wysocki64cdb412014-01-10 15:27:56 +0100136 pci_stop_and_remove_bus_device_locked(pdev);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530137 return 0;
138}
139
140/**
141 * _base_fault_reset_work - workq handling ioc fault conditions
142 * @work: input argument, used to derive ioc
143 * Context: sleep.
144 *
145 * Return nothing.
146 */
147static void
148_base_fault_reset_work(struct work_struct *work)
149{
150 struct MPT3SAS_ADAPTER *ioc =
151 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
152 unsigned long flags;
153 u32 doorbell;
154 int rc;
155 struct task_struct *p;
156
157
158 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
159 if (ioc->shost_recovery)
160 goto rearm_timer;
161 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
162
163 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
164 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
165 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
166 ioc->name);
167
168 /*
169 * Call _scsih_flush_pending_cmds callback so that we flush all
170 * pending commands back to OS. This call is required to aovid
171 * deadlock at block layer. Dead IOC will fail to do diag reset,
172 * and this call is safe since dead ioc will never return any
173 * command back from HW.
174 */
175 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
176 /*
177 * Set remove_host flag early since kernel thread will
178 * take some time to execute.
179 */
180 ioc->remove_host = 1;
181 /*Remove the Dead Host */
182 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
183 "mpt3sas_dead_ioc_%d", ioc->id);
184 if (IS_ERR(p))
185 pr_err(MPT3SAS_FMT
186 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
187 ioc->name, __func__);
188 else
189 pr_err(MPT3SAS_FMT
190 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
191 ioc->name, __func__);
192 return; /* don't rearm timer */
193 }
194
195 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
196 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
197 FORCE_BIG_HAMMER);
198 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
199 __func__, (rc == 0) ? "success" : "failed");
200 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
201 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
202 mpt3sas_base_fault_info(ioc, doorbell &
203 MPI2_DOORBELL_DATA_MASK);
204 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
205 MPI2_IOC_STATE_OPERATIONAL)
206 return; /* don't rearm timer */
207 }
208
209 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
210 rearm_timer:
211 if (ioc->fault_reset_work_q)
212 queue_delayed_work(ioc->fault_reset_work_q,
213 &ioc->fault_reset_work,
214 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
215 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
216}
217
218/**
219 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
220 * @ioc: per adapter object
221 * Context: sleep.
222 *
223 * Return nothing.
224 */
225void
226mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
227{
228 unsigned long flags;
229
230 if (ioc->fault_reset_work_q)
231 return;
232
233 /* initialize fault polling */
234
235 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
236 snprintf(ioc->fault_reset_work_q_name,
237 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
238 ioc->fault_reset_work_q =
239 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
240 if (!ioc->fault_reset_work_q) {
241 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
242 ioc->name, __func__, __LINE__);
243 return;
244 }
245 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
246 if (ioc->fault_reset_work_q)
247 queue_delayed_work(ioc->fault_reset_work_q,
248 &ioc->fault_reset_work,
249 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
250 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
251}
252
253/**
254 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
255 * @ioc: per adapter object
256 * Context: sleep.
257 *
258 * Return nothing.
259 */
260void
261mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
262{
263 unsigned long flags;
264 struct workqueue_struct *wq;
265
266 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
267 wq = ioc->fault_reset_work_q;
268 ioc->fault_reset_work_q = NULL;
269 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
270 if (wq) {
Reddy, Sreekanth4dc06fd2014-07-14 12:01:35 +0530271 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530272 flush_workqueue(wq);
273 destroy_workqueue(wq);
274 }
275}
276
277/**
278 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
279 * @ioc: per adapter object
280 * @fault_code: fault code
281 *
282 * Return nothing.
283 */
284void
285mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
286{
287 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
288 ioc->name, fault_code);
289}
290
291/**
292 * mpt3sas_halt_firmware - halt's mpt controller firmware
293 * @ioc: per adapter object
294 *
295 * For debugging timeout related issues. Writing 0xCOFFEE00
296 * to the doorbell register will halt controller firmware. With
297 * the purpose to stop both driver and firmware, the enduser can
298 * obtain a ring buffer from controller UART.
299 */
300void
301mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
302{
303 u32 doorbell;
304
305 if (!ioc->fwfault_debug)
306 return;
307
308 dump_stack();
309
310 doorbell = readl(&ioc->chip->Doorbell);
311 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
312 mpt3sas_base_fault_info(ioc , doorbell);
313 else {
314 writel(0xC0FFEE00, &ioc->chip->Doorbell);
315 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
316 ioc->name);
317 }
318
319 if (ioc->fwfault_debug == 2)
320 for (;;)
321 ;
322 else
323 panic("panic in %s\n", __func__);
324}
325
326#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
327/**
328 * _base_sas_ioc_info - verbose translation of the ioc status
329 * @ioc: per adapter object
330 * @mpi_reply: reply mf payload returned from firmware
331 * @request_hdr: request mf
332 *
333 * Return nothing.
334 */
335static void
336_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
337 MPI2RequestHeader_t *request_hdr)
338{
339 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
340 MPI2_IOCSTATUS_MASK;
341 char *desc = NULL;
342 u16 frame_sz;
343 char *func_str = NULL;
344
345 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
346 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
347 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
348 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
349 return;
350
351 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
352 return;
353
354 switch (ioc_status) {
355
356/****************************************************************************
357* Common IOCStatus values for all replies
358****************************************************************************/
359
360 case MPI2_IOCSTATUS_INVALID_FUNCTION:
361 desc = "invalid function";
362 break;
363 case MPI2_IOCSTATUS_BUSY:
364 desc = "busy";
365 break;
366 case MPI2_IOCSTATUS_INVALID_SGL:
367 desc = "invalid sgl";
368 break;
369 case MPI2_IOCSTATUS_INTERNAL_ERROR:
370 desc = "internal error";
371 break;
372 case MPI2_IOCSTATUS_INVALID_VPID:
373 desc = "invalid vpid";
374 break;
375 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
376 desc = "insufficient resources";
377 break;
378 case MPI2_IOCSTATUS_INVALID_FIELD:
379 desc = "invalid field";
380 break;
381 case MPI2_IOCSTATUS_INVALID_STATE:
382 desc = "invalid state";
383 break;
384 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
385 desc = "op state not supported";
386 break;
387
388/****************************************************************************
389* Config IOCStatus values
390****************************************************************************/
391
392 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
393 desc = "config invalid action";
394 break;
395 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
396 desc = "config invalid type";
397 break;
398 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
399 desc = "config invalid page";
400 break;
401 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
402 desc = "config invalid data";
403 break;
404 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
405 desc = "config no defaults";
406 break;
407 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
408 desc = "config cant commit";
409 break;
410
411/****************************************************************************
412* SCSI IO Reply
413****************************************************************************/
414
415 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
416 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
417 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
418 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
419 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
420 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
421 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
422 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
423 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
424 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
425 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
426 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
427 break;
428
429/****************************************************************************
430* For use by SCSI Initiator and SCSI Target end-to-end data protection
431****************************************************************************/
432
433 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
434 desc = "eedp guard error";
435 break;
436 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
437 desc = "eedp ref tag error";
438 break;
439 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
440 desc = "eedp app tag error";
441 break;
442
443/****************************************************************************
444* SCSI Target values
445****************************************************************************/
446
447 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
448 desc = "target invalid io index";
449 break;
450 case MPI2_IOCSTATUS_TARGET_ABORTED:
451 desc = "target aborted";
452 break;
453 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
454 desc = "target no conn retryable";
455 break;
456 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
457 desc = "target no connection";
458 break;
459 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
460 desc = "target xfer count mismatch";
461 break;
462 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
463 desc = "target data offset error";
464 break;
465 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
466 desc = "target too much write data";
467 break;
468 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
469 desc = "target iu too short";
470 break;
471 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
472 desc = "target ack nak timeout";
473 break;
474 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
475 desc = "target nak received";
476 break;
477
478/****************************************************************************
479* Serial Attached SCSI values
480****************************************************************************/
481
482 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
483 desc = "smp request failed";
484 break;
485 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
486 desc = "smp data overrun";
487 break;
488
489/****************************************************************************
490* Diagnostic Buffer Post / Diagnostic Release values
491****************************************************************************/
492
493 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
494 desc = "diagnostic released";
495 break;
496 default:
497 break;
498 }
499
500 if (!desc)
501 return;
502
503 switch (request_hdr->Function) {
504 case MPI2_FUNCTION_CONFIG:
505 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
506 func_str = "config_page";
507 break;
508 case MPI2_FUNCTION_SCSI_TASK_MGMT:
509 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
510 func_str = "task_mgmt";
511 break;
512 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
513 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
514 func_str = "sas_iounit_ctl";
515 break;
516 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
517 frame_sz = sizeof(Mpi2SepRequest_t);
518 func_str = "enclosure";
519 break;
520 case MPI2_FUNCTION_IOC_INIT:
521 frame_sz = sizeof(Mpi2IOCInitRequest_t);
522 func_str = "ioc_init";
523 break;
524 case MPI2_FUNCTION_PORT_ENABLE:
525 frame_sz = sizeof(Mpi2PortEnableRequest_t);
526 func_str = "port_enable";
527 break;
528 case MPI2_FUNCTION_SMP_PASSTHROUGH:
529 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
530 func_str = "smp_passthru";
531 break;
532 default:
533 frame_sz = 32;
534 func_str = "unknown";
535 break;
536 }
537
538 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
539 ioc->name, desc, ioc_status, request_hdr, func_str);
540
541 _debug_dump_mf(request_hdr, frame_sz/4);
542}
543
544/**
545 * _base_display_event_data - verbose translation of firmware asyn events
546 * @ioc: per adapter object
547 * @mpi_reply: reply mf payload returned from firmware
548 *
549 * Return nothing.
550 */
551static void
552_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
553 Mpi2EventNotificationReply_t *mpi_reply)
554{
555 char *desc = NULL;
556 u16 event;
557
558 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
559 return;
560
561 event = le16_to_cpu(mpi_reply->Event);
562
563 switch (event) {
564 case MPI2_EVENT_LOG_DATA:
565 desc = "Log Data";
566 break;
567 case MPI2_EVENT_STATE_CHANGE:
568 desc = "Status Change";
569 break;
570 case MPI2_EVENT_HARD_RESET_RECEIVED:
571 desc = "Hard Reset Received";
572 break;
573 case MPI2_EVENT_EVENT_CHANGE:
574 desc = "Event Change";
575 break;
576 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
577 desc = "Device Status Change";
578 break;
579 case MPI2_EVENT_IR_OPERATION_STATUS:
580 desc = "IR Operation Status";
581 break;
582 case MPI2_EVENT_SAS_DISCOVERY:
583 {
584 Mpi2EventDataSasDiscovery_t *event_data =
585 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
586 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
587 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
588 "start" : "stop");
589 if (event_data->DiscoveryStatus)
590 pr_info("discovery_status(0x%08x)",
591 le32_to_cpu(event_data->DiscoveryStatus));
592 pr_info("\n");
593 return;
594 }
595 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
596 desc = "SAS Broadcast Primitive";
597 break;
598 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
599 desc = "SAS Init Device Status Change";
600 break;
601 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
602 desc = "SAS Init Table Overflow";
603 break;
604 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
605 desc = "SAS Topology Change List";
606 break;
607 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
608 desc = "SAS Enclosure Device Status Change";
609 break;
610 case MPI2_EVENT_IR_VOLUME:
611 desc = "IR Volume";
612 break;
613 case MPI2_EVENT_IR_PHYSICAL_DISK:
614 desc = "IR Physical Disk";
615 break;
616 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
617 desc = "IR Configuration Change List";
618 break;
619 case MPI2_EVENT_LOG_ENTRY_ADDED:
620 desc = "Log Entry Added";
621 break;
Sreekanth Reddy2d8ce8c2015-01-12 11:38:56 +0530622 case MPI2_EVENT_TEMP_THRESHOLD:
623 desc = "Temperature Threshold";
624 break;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530625 }
626
627 if (!desc)
628 return;
629
630 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
631}
632#endif
633
634/**
635 * _base_sas_log_info - verbose translation of firmware log info
636 * @ioc: per adapter object
637 * @log_info: log info
638 *
639 * Return nothing.
640 */
641static void
642_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
643{
644 union loginfo_type {
645 u32 loginfo;
646 struct {
647 u32 subcode:16;
648 u32 code:8;
649 u32 originator:4;
650 u32 bus_type:4;
651 } dw;
652 };
653 union loginfo_type sas_loginfo;
654 char *originator_str = NULL;
655
656 sas_loginfo.loginfo = log_info;
657 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
658 return;
659
660 /* each nexus loss loginfo */
661 if (log_info == 0x31170000)
662 return;
663
664 /* eat the loginfos associated with task aborts */
665 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
666 0x31140000 || log_info == 0x31130000))
667 return;
668
669 switch (sas_loginfo.dw.originator) {
670 case 0:
671 originator_str = "IOP";
672 break;
673 case 1:
674 originator_str = "PL";
675 break;
676 case 2:
677 originator_str = "IR";
678 break;
679 }
680
681 pr_warn(MPT3SAS_FMT
682 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
683 ioc->name, log_info,
684 originator_str, sas_loginfo.dw.code,
685 sas_loginfo.dw.subcode);
686}
687
688/**
689 * _base_display_reply_info -
690 * @ioc: per adapter object
691 * @smid: system request message index
692 * @msix_index: MSIX table index supplied by the OS
693 * @reply: reply message frame(lower 32bit addr)
694 *
695 * Return nothing.
696 */
697static void
698_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
699 u32 reply)
700{
701 MPI2DefaultReply_t *mpi_reply;
702 u16 ioc_status;
703 u32 loginfo = 0;
704
705 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
706 if (unlikely(!mpi_reply)) {
707 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
708 ioc->name, __FILE__, __LINE__, __func__);
709 return;
710 }
711 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
712#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
713 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
714 (ioc->logging_level & MPT_DEBUG_REPLY)) {
715 _base_sas_ioc_info(ioc , mpi_reply,
716 mpt3sas_base_get_msg_frame(ioc, smid));
717 }
718#endif
719 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
720 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
721 _base_sas_log_info(ioc, loginfo);
722 }
723
724 if (ioc_status || loginfo) {
725 ioc_status &= MPI2_IOCSTATUS_MASK;
726 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
727 }
728}
729
730/**
731 * mpt3sas_base_done - base internal command completion routine
732 * @ioc: per adapter object
733 * @smid: system request message index
734 * @msix_index: MSIX table index supplied by the OS
735 * @reply: reply message frame(lower 32bit addr)
736 *
737 * Return 1 meaning mf should be freed from _base_interrupt
738 * 0 means the mf is freed from this function.
739 */
740u8
741mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
742 u32 reply)
743{
744 MPI2DefaultReply_t *mpi_reply;
745
746 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
747 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
748 return 1;
749
750 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
751 return 1;
752
753 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
754 if (mpi_reply) {
755 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
756 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
757 }
758 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
759
760 complete(&ioc->base_cmds.done);
761 return 1;
762}
763
764/**
765 * _base_async_event - main callback handler for firmware asyn events
766 * @ioc: per adapter object
767 * @msix_index: MSIX table index supplied by the OS
768 * @reply: reply message frame(lower 32bit addr)
769 *
770 * Return 1 meaning mf should be freed from _base_interrupt
771 * 0 means the mf is freed from this function.
772 */
773static u8
774_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
775{
776 Mpi2EventNotificationReply_t *mpi_reply;
777 Mpi2EventAckRequest_t *ack_request;
778 u16 smid;
779
780 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
781 if (!mpi_reply)
782 return 1;
783 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
784 return 1;
785#ifdef CONFIG_SCSI_MPT3SAS_LOGGING
786 _base_display_event_data(ioc, mpi_reply);
787#endif
788 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
789 goto out;
790 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
791 if (!smid) {
792 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
793 ioc->name, __func__);
794 goto out;
795 }
796
797 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
798 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
799 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
800 ack_request->Event = mpi_reply->Event;
801 ack_request->EventContext = mpi_reply->EventContext;
802 ack_request->VF_ID = 0; /* TODO */
803 ack_request->VP_ID = 0;
804 mpt3sas_base_put_smid_default(ioc, smid);
805
806 out:
807
808 /* scsih callback handler */
809 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
810
811 /* ctl callback handler */
812 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
813
814 return 1;
815}
816
817/**
818 * _base_get_cb_idx - obtain the callback index
819 * @ioc: per adapter object
820 * @smid: system request message index
821 *
822 * Return callback index.
823 */
824static u8
825_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
826{
827 int i;
828 u8 cb_idx;
829
830 if (smid < ioc->hi_priority_smid) {
831 i = smid - 1;
832 cb_idx = ioc->scsi_lookup[i].cb_idx;
833 } else if (smid < ioc->internal_smid) {
834 i = smid - ioc->hi_priority_smid;
835 cb_idx = ioc->hpr_lookup[i].cb_idx;
836 } else if (smid <= ioc->hba_queue_depth) {
837 i = smid - ioc->internal_smid;
838 cb_idx = ioc->internal_lookup[i].cb_idx;
839 } else
840 cb_idx = 0xFF;
841 return cb_idx;
842}
843
844/**
845 * _base_mask_interrupts - disable interrupts
846 * @ioc: per adapter object
847 *
848 * Disabling ResetIRQ, Reply and Doorbell Interrupts
849 *
850 * Return nothing.
851 */
852static void
853_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
854{
855 u32 him_register;
856
857 ioc->mask_interrupts = 1;
858 him_register = readl(&ioc->chip->HostInterruptMask);
859 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
860 writel(him_register, &ioc->chip->HostInterruptMask);
861 readl(&ioc->chip->HostInterruptMask);
862}
863
864/**
865 * _base_unmask_interrupts - enable interrupts
866 * @ioc: per adapter object
867 *
868 * Enabling only Reply Interrupts
869 *
870 * Return nothing.
871 */
872static void
873_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
874{
875 u32 him_register;
876
877 him_register = readl(&ioc->chip->HostInterruptMask);
878 him_register &= ~MPI2_HIM_RIM;
879 writel(him_register, &ioc->chip->HostInterruptMask);
880 ioc->mask_interrupts = 0;
881}
882
883union reply_descriptor {
884 u64 word;
885 struct {
886 u32 low;
887 u32 high;
888 } u;
889};
890
891/**
892 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
893 * @irq: irq number (not used)
894 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
895 * @r: pt_regs pointer (not used)
896 *
897 * Return IRQ_HANDLE if processed, else IRQ_NONE.
898 */
899static irqreturn_t
900_base_interrupt(int irq, void *bus_id)
901{
902 struct adapter_reply_queue *reply_q = bus_id;
903 union reply_descriptor rd;
904 u32 completed_cmds;
905 u8 request_desript_type;
906 u16 smid;
907 u8 cb_idx;
908 u32 reply;
909 u8 msix_index = reply_q->msix_index;
910 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
911 Mpi2ReplyDescriptorsUnion_t *rpf;
912 u8 rc;
913
914 if (ioc->mask_interrupts)
915 return IRQ_NONE;
916
917 if (!atomic_add_unless(&reply_q->busy, 1, 1))
918 return IRQ_NONE;
919
920 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
921 request_desript_type = rpf->Default.ReplyFlags
922 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
923 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
924 atomic_dec(&reply_q->busy);
925 return IRQ_NONE;
926 }
927
928 completed_cmds = 0;
929 cb_idx = 0xFF;
930 do {
931 rd.word = le64_to_cpu(rpf->Words);
932 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
933 goto out;
934 reply = 0;
935 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
936 if (request_desript_type ==
937 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
938 request_desript_type ==
939 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
940 cb_idx = _base_get_cb_idx(ioc, smid);
941 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
942 (likely(mpt_callbacks[cb_idx] != NULL))) {
943 rc = mpt_callbacks[cb_idx](ioc, smid,
944 msix_index, 0);
945 if (rc)
946 mpt3sas_base_free_smid(ioc, smid);
947 }
948 } else if (request_desript_type ==
949 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
950 reply = le32_to_cpu(
951 rpf->AddressReply.ReplyFrameAddress);
952 if (reply > ioc->reply_dma_max_address ||
953 reply < ioc->reply_dma_min_address)
954 reply = 0;
955 if (smid) {
956 cb_idx = _base_get_cb_idx(ioc, smid);
957 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
958 (likely(mpt_callbacks[cb_idx] != NULL))) {
959 rc = mpt_callbacks[cb_idx](ioc, smid,
960 msix_index, reply);
961 if (reply)
962 _base_display_reply_info(ioc,
963 smid, msix_index, reply);
964 if (rc)
965 mpt3sas_base_free_smid(ioc,
966 smid);
967 }
968 } else {
969 _base_async_event(ioc, msix_index, reply);
970 }
971
972 /* reply free queue handling */
973 if (reply) {
974 ioc->reply_free_host_index =
975 (ioc->reply_free_host_index ==
976 (ioc->reply_free_queue_depth - 1)) ?
977 0 : ioc->reply_free_host_index + 1;
978 ioc->reply_free[ioc->reply_free_host_index] =
979 cpu_to_le32(reply);
980 wmb();
981 writel(ioc->reply_free_host_index,
982 &ioc->chip->ReplyFreeHostIndex);
983 }
984 }
985
986 rpf->Words = cpu_to_le64(ULLONG_MAX);
987 reply_q->reply_post_host_index =
988 (reply_q->reply_post_host_index ==
989 (ioc->reply_post_queue_depth - 1)) ? 0 :
990 reply_q->reply_post_host_index + 1;
991 request_desript_type =
992 reply_q->reply_post_free[reply_q->reply_post_host_index].
993 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
994 completed_cmds++;
995 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
996 goto out;
997 if (!reply_q->reply_post_host_index)
998 rpf = reply_q->reply_post_free;
999 else
1000 rpf++;
1001 } while (1);
1002
1003 out:
1004
1005 if (!completed_cmds) {
1006 atomic_dec(&reply_q->busy);
1007 return IRQ_NONE;
1008 }
1009
1010 wmb();
1011 writel(reply_q->reply_post_host_index | (msix_index <<
1012 MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex);
1013 atomic_dec(&reply_q->busy);
1014 return IRQ_HANDLED;
1015}
1016
1017/**
1018 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1019 * @ioc: per adapter object
1020 *
1021 */
1022static inline int
1023_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1024{
1025 return (ioc->facts.IOCCapabilities &
1026 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1027}
1028
1029/**
1030 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1031 * @ioc: per adapter object
1032 * Context: ISR conext
1033 *
1034 * Called when a Task Management request has completed. We want
1035 * to flush the other reply queues so all the outstanding IO has been
1036 * completed back to OS before we process the TM completetion.
1037 *
1038 * Return nothing.
1039 */
1040void
1041mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1042{
1043 struct adapter_reply_queue *reply_q;
1044
1045 /* If MSIX capability is turned off
1046 * then multi-queues are not enabled
1047 */
1048 if (!_base_is_controller_msix_enabled(ioc))
1049 return;
1050
1051 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1052 if (ioc->shost_recovery)
1053 return;
1054 /* TMs are on msix_index == 0 */
1055 if (reply_q->msix_index == 0)
1056 continue;
1057 _base_interrupt(reply_q->vector, (void *)reply_q);
1058 }
1059}
1060
1061/**
1062 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1063 * @cb_idx: callback index
1064 *
1065 * Return nothing.
1066 */
1067void
1068mpt3sas_base_release_callback_handler(u8 cb_idx)
1069{
1070 mpt_callbacks[cb_idx] = NULL;
1071}
1072
1073/**
1074 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1075 * @cb_func: callback function
1076 *
1077 * Returns cb_func.
1078 */
1079u8
1080mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1081{
1082 u8 cb_idx;
1083
1084 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1085 if (mpt_callbacks[cb_idx] == NULL)
1086 break;
1087
1088 mpt_callbacks[cb_idx] = cb_func;
1089 return cb_idx;
1090}
1091
1092/**
1093 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1094 *
1095 * Return nothing.
1096 */
1097void
1098mpt3sas_base_initialize_callback_handler(void)
1099{
1100 u8 cb_idx;
1101
1102 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1103 mpt3sas_base_release_callback_handler(cb_idx);
1104}
1105
1106
1107/**
1108 * _base_build_zero_len_sge - build zero length sg entry
1109 * @ioc: per adapter object
1110 * @paddr: virtual address for SGE
1111 *
1112 * Create a zero length scatter gather entry to insure the IOCs hardware has
1113 * something to use if the target device goes brain dead and tries
1114 * to send data even when none is asked for.
1115 *
1116 * Return nothing.
1117 */
1118static void
1119_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1120{
1121 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1122 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1123 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1124 MPI2_SGE_FLAGS_SHIFT);
1125 ioc->base_add_sg_single(paddr, flags_length, -1);
1126}
1127
1128/**
1129 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1130 * @paddr: virtual address for SGE
1131 * @flags_length: SGE flags and data transfer length
1132 * @dma_addr: Physical address
1133 *
1134 * Return nothing.
1135 */
1136static void
1137_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1138{
1139 Mpi2SGESimple32_t *sgel = paddr;
1140
1141 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1142 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1143 sgel->FlagsLength = cpu_to_le32(flags_length);
1144 sgel->Address = cpu_to_le32(dma_addr);
1145}
1146
1147
1148/**
1149 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1150 * @paddr: virtual address for SGE
1151 * @flags_length: SGE flags and data transfer length
1152 * @dma_addr: Physical address
1153 *
1154 * Return nothing.
1155 */
1156static void
1157_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1158{
1159 Mpi2SGESimple64_t *sgel = paddr;
1160
1161 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1162 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1163 sgel->FlagsLength = cpu_to_le32(flags_length);
1164 sgel->Address = cpu_to_le64(dma_addr);
1165}
1166
1167/**
1168 * _base_get_chain_buffer_tracker - obtain chain tracker
1169 * @ioc: per adapter object
1170 * @smid: smid associated to an IO request
1171 *
1172 * Returns chain tracker(from ioc->free_chain_list)
1173 */
1174static struct chain_tracker *
1175_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1176{
1177 struct chain_tracker *chain_req;
1178 unsigned long flags;
1179
1180 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1181 if (list_empty(&ioc->free_chain_list)) {
1182 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1183 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1184 "chain buffers not available\n", ioc->name));
1185 return NULL;
1186 }
1187 chain_req = list_entry(ioc->free_chain_list.next,
1188 struct chain_tracker, tracker_list);
1189 list_del_init(&chain_req->tracker_list);
1190 list_add_tail(&chain_req->tracker_list,
1191 &ioc->scsi_lookup[smid - 1].chain_list);
1192 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1193 return chain_req;
1194}
1195
1196
1197/**
1198 * _base_build_sg - build generic sg
1199 * @ioc: per adapter object
1200 * @psge: virtual address for SGE
1201 * @data_out_dma: physical address for WRITES
1202 * @data_out_sz: data xfer size for WRITES
1203 * @data_in_dma: physical address for READS
1204 * @data_in_sz: data xfer size for READS
1205 *
1206 * Return nothing.
1207 */
1208static void
1209_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1210 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1211 size_t data_in_sz)
1212{
1213 u32 sgl_flags;
1214
1215 if (!data_out_sz && !data_in_sz) {
1216 _base_build_zero_len_sge(ioc, psge);
1217 return;
1218 }
1219
1220 if (data_out_sz && data_in_sz) {
1221 /* WRITE sgel first */
1222 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1223 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1224 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1225 ioc->base_add_sg_single(psge, sgl_flags |
1226 data_out_sz, data_out_dma);
1227
1228 /* incr sgel */
1229 psge += ioc->sge_size;
1230
1231 /* READ sgel last */
1232 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1233 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1234 MPI2_SGE_FLAGS_END_OF_LIST);
1235 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1236 ioc->base_add_sg_single(psge, sgl_flags |
1237 data_in_sz, data_in_dma);
1238 } else if (data_out_sz) /* WRITE */ {
1239 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1240 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1241 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1242 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1243 ioc->base_add_sg_single(psge, sgl_flags |
1244 data_out_sz, data_out_dma);
1245 } else if (data_in_sz) /* READ */ {
1246 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1247 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1248 MPI2_SGE_FLAGS_END_OF_LIST);
1249 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1250 ioc->base_add_sg_single(psge, sgl_flags |
1251 data_in_sz, data_in_dma);
1252 }
1253}
1254
1255/* IEEE format sgls */
1256
1257/**
1258 * _base_add_sg_single_ieee - add sg element for IEEE format
1259 * @paddr: virtual address for SGE
1260 * @flags: SGE flags
1261 * @chain_offset: number of 128 byte elements from start of segment
1262 * @length: data transfer length
1263 * @dma_addr: Physical address
1264 *
1265 * Return nothing.
1266 */
1267static void
1268_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1269 dma_addr_t dma_addr)
1270{
1271 Mpi25IeeeSgeChain64_t *sgel = paddr;
1272
1273 sgel->Flags = flags;
1274 sgel->NextChainOffset = chain_offset;
1275 sgel->Length = cpu_to_le32(length);
1276 sgel->Address = cpu_to_le64(dma_addr);
1277}
1278
1279/**
1280 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1281 * @ioc: per adapter object
1282 * @paddr: virtual address for SGE
1283 *
1284 * Create a zero length scatter gather entry to insure the IOCs hardware has
1285 * something to use if the target device goes brain dead and tries
1286 * to send data even when none is asked for.
1287 *
1288 * Return nothing.
1289 */
1290static void
1291_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1292{
1293 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1294 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1295 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1296 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1297}
1298
1299/**
1300 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1301 * @ioc: per adapter object
1302 * @scmd: scsi command
1303 * @smid: system request message index
1304 * Context: none.
1305 *
1306 * The main routine that builds scatter gather table from a given
1307 * scsi request sent via the .queuecommand main handler.
1308 *
1309 * Returns 0 success, anything else error
1310 */
1311static int
1312_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1313 struct scsi_cmnd *scmd, u16 smid)
1314{
1315 Mpi2SCSIIORequest_t *mpi_request;
1316 dma_addr_t chain_dma;
1317 struct scatterlist *sg_scmd;
1318 void *sg_local, *chain;
1319 u32 chain_offset;
1320 u32 chain_length;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301321 int sges_left;
1322 u32 sges_in_segment;
1323 u8 simple_sgl_flags;
1324 u8 simple_sgl_flags_last;
1325 u8 chain_sgl_flags;
1326 struct chain_tracker *chain_req;
1327
1328 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1329
1330 /* init scatter gather flags */
1331 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1332 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1333 simple_sgl_flags_last = simple_sgl_flags |
1334 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1335 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1336 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1337
1338 sg_scmd = scsi_sglist(scmd);
1339 sges_left = scsi_dma_map(scmd);
1340 if (!sges_left) {
1341 sdev_printk(KERN_ERR, scmd->device,
1342 "pci_map_sg failed: request for %d bytes!\n",
1343 scsi_bufflen(scmd));
1344 return -ENOMEM;
1345 }
1346
1347 sg_local = &mpi_request->SGL;
1348 sges_in_segment = (ioc->request_sz -
1349 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1350 if (sges_left <= sges_in_segment)
1351 goto fill_in_last_segment;
1352
1353 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1354 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1355
1356 /* fill in main message segment when there is a chain following */
1357 while (sges_in_segment > 1) {
1358 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1359 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1360 sg_scmd = sg_next(sg_scmd);
1361 sg_local += ioc->sge_size_ieee;
1362 sges_left--;
1363 sges_in_segment--;
1364 }
1365
Wei Yongjun25ef16d2012-12-12 02:26:51 +05301366 /* initializing the pointers */
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301367 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1368 if (!chain_req)
1369 return -1;
1370 chain = chain_req->chain_buffer;
1371 chain_dma = chain_req->chain_buffer_dma;
1372 do {
1373 sges_in_segment = (sges_left <=
1374 ioc->max_sges_in_chain_message) ? sges_left :
1375 ioc->max_sges_in_chain_message;
1376 chain_offset = (sges_left == sges_in_segment) ?
1377 0 : sges_in_segment;
1378 chain_length = sges_in_segment * ioc->sge_size_ieee;
1379 if (chain_offset)
1380 chain_length += ioc->sge_size_ieee;
1381 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1382 chain_offset, chain_length, chain_dma);
1383
1384 sg_local = chain;
1385 if (!chain_offset)
1386 goto fill_in_last_segment;
1387
1388 /* fill in chain segments */
1389 while (sges_in_segment) {
1390 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1391 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1392 sg_scmd = sg_next(sg_scmd);
1393 sg_local += ioc->sge_size_ieee;
1394 sges_left--;
1395 sges_in_segment--;
1396 }
1397
1398 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1399 if (!chain_req)
1400 return -1;
1401 chain = chain_req->chain_buffer;
1402 chain_dma = chain_req->chain_buffer_dma;
1403 } while (1);
1404
1405
1406 fill_in_last_segment:
1407
1408 /* fill the last segment */
1409 while (sges_left) {
1410 if (sges_left == 1)
1411 _base_add_sg_single_ieee(sg_local,
1412 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1413 sg_dma_address(sg_scmd));
1414 else
1415 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1416 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1417 sg_scmd = sg_next(sg_scmd);
1418 sg_local += ioc->sge_size_ieee;
1419 sges_left--;
1420 }
1421
1422 return 0;
1423}
1424
1425/**
1426 * _base_build_sg_ieee - build generic sg for IEEE format
1427 * @ioc: per adapter object
1428 * @psge: virtual address for SGE
1429 * @data_out_dma: physical address for WRITES
1430 * @data_out_sz: data xfer size for WRITES
1431 * @data_in_dma: physical address for READS
1432 * @data_in_sz: data xfer size for READS
1433 *
1434 * Return nothing.
1435 */
1436static void
1437_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1438 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1439 size_t data_in_sz)
1440{
1441 u8 sgl_flags;
1442
1443 if (!data_out_sz && !data_in_sz) {
1444 _base_build_zero_len_sge_ieee(ioc, psge);
1445 return;
1446 }
1447
1448 if (data_out_sz && data_in_sz) {
1449 /* WRITE sgel first */
1450 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1451 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1452 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1453 data_out_dma);
1454
1455 /* incr sgel */
1456 psge += ioc->sge_size_ieee;
1457
1458 /* READ sgel last */
1459 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1460 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1461 data_in_dma);
1462 } else if (data_out_sz) /* WRITE */ {
1463 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1464 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1465 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1466 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1467 data_out_dma);
1468 } else if (data_in_sz) /* READ */ {
1469 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1470 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1471 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1472 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1473 data_in_dma);
1474 }
1475}
1476
1477#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1478
1479/**
1480 * _base_config_dma_addressing - set dma addressing
1481 * @ioc: per adapter object
1482 * @pdev: PCI device struct
1483 *
1484 * Returns 0 for success, non-zero for failure.
1485 */
1486static int
1487_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1488{
1489 struct sysinfo s;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301490 u64 consistent_dma_mask;
1491
1492 if (ioc->dma_mask)
1493 consistent_dma_mask = DMA_BIT_MASK(64);
1494 else
1495 consistent_dma_mask = DMA_BIT_MASK(32);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301496
1497 if (sizeof(dma_addr_t) > 4) {
1498 const uint64_t required_mask =
1499 dma_get_required_mask(&pdev->dev);
1500 if ((required_mask > DMA_BIT_MASK(32)) &&
1501 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301502 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301503 ioc->base_add_sg_single = &_base_add_sg_single_64;
1504 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301505 ioc->dma_mask = 64;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301506 goto out;
1507 }
1508 }
1509
1510 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1511 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1512 ioc->base_add_sg_single = &_base_add_sg_single_32;
1513 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301514 ioc->dma_mask = 32;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301515 } else
1516 return -ENODEV;
1517
1518 out:
1519 si_meminfo(&s);
1520 pr_info(MPT3SAS_FMT
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301521 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1522 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301523
1524 return 0;
1525}
1526
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301527static int
1528_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1529 struct pci_dev *pdev)
1530{
1531 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1532 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1533 return -ENODEV;
1534 }
1535 return 0;
1536}
1537
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301538/**
1539 * _base_check_enable_msix - checks MSIX capabable.
1540 * @ioc: per adapter object
1541 *
1542 * Check to see if card is capable of MSIX, and set number
1543 * of available msix vectors
1544 */
1545static int
1546_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1547{
1548 int base;
1549 u16 message_control;
1550
1551 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1552 if (!base) {
1553 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1554 ioc->name));
1555 return -EINVAL;
1556 }
1557
1558 /* get msix vector count */
1559
1560 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1561 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1562 if (ioc->msix_vector_count > 8)
1563 ioc->msix_vector_count = 8;
1564 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1565 "msix is supported, vector_count(%d)\n",
1566 ioc->name, ioc->msix_vector_count));
1567 return 0;
1568}
1569
1570/**
1571 * _base_free_irq - free irq
1572 * @ioc: per adapter object
1573 *
1574 * Freeing respective reply_queue from the list.
1575 */
1576static void
1577_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1578{
1579 struct adapter_reply_queue *reply_q, *next;
1580
1581 if (list_empty(&ioc->reply_queue_list))
1582 return;
1583
1584 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1585 list_del(&reply_q->list);
1586 synchronize_irq(reply_q->vector);
1587 free_irq(reply_q->vector, reply_q);
1588 kfree(reply_q);
1589 }
1590}
1591
1592/**
1593 * _base_request_irq - request irq
1594 * @ioc: per adapter object
1595 * @index: msix index into vector table
1596 * @vector: irq vector
1597 *
1598 * Inserting respective reply_queue into the list.
1599 */
1600static int
1601_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1602{
1603 struct adapter_reply_queue *reply_q;
1604 int r;
1605
1606 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1607 if (!reply_q) {
1608 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1609 ioc->name, (int)sizeof(struct adapter_reply_queue));
1610 return -ENOMEM;
1611 }
1612 reply_q->ioc = ioc;
1613 reply_q->msix_index = index;
1614 reply_q->vector = vector;
1615 atomic_set(&reply_q->busy, 0);
1616 if (ioc->msix_enable)
1617 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1618 MPT3SAS_DRIVER_NAME, ioc->id, index);
1619 else
1620 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1621 MPT3SAS_DRIVER_NAME, ioc->id);
1622 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1623 reply_q);
1624 if (r) {
1625 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1626 reply_q->name, vector);
1627 kfree(reply_q);
1628 return -EBUSY;
1629 }
1630
1631 INIT_LIST_HEAD(&reply_q->list);
1632 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1633 return 0;
1634}
1635
1636/**
1637 * _base_assign_reply_queues - assigning msix index for each cpu
1638 * @ioc: per adapter object
1639 *
1640 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1641 *
1642 * It would nice if we could call irq_set_affinity, however it is not
1643 * an exported symbol
1644 */
1645static void
1646_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1647{
Martin K. Petersen91b265b2014-01-03 19:16:56 -05001648 unsigned int cpu, nr_cpus, nr_msix, index = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301649
1650 if (!_base_is_controller_msix_enabled(ioc))
1651 return;
1652
1653 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1654
Martin K. Petersen91b265b2014-01-03 19:16:56 -05001655 nr_cpus = num_online_cpus();
1656 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1657 ioc->facts.MaxMSIxVectors);
1658 if (!nr_msix)
1659 return;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301660
Martin K. Petersen91b265b2014-01-03 19:16:56 -05001661 cpu = cpumask_first(cpu_online_mask);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301662
Martin K. Petersen91b265b2014-01-03 19:16:56 -05001663 do {
1664 unsigned int i, group = nr_cpus / nr_msix;
1665
1666 if (index < nr_cpus % nr_msix)
1667 group++;
1668
1669 for (i = 0 ; i < group ; i++) {
1670 ioc->cpu_msix_table[cpu] = index;
1671 cpu = cpumask_next(cpu, cpu_online_mask);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301672 }
Martin K. Petersen91b265b2014-01-03 19:16:56 -05001673
1674 index++;
1675
1676 } while (cpu < nr_cpus);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301677}
1678
1679/**
1680 * _base_disable_msix - disables msix
1681 * @ioc: per adapter object
1682 *
1683 */
1684static void
1685_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1686{
1687 if (!ioc->msix_enable)
1688 return;
1689 pci_disable_msix(ioc->pdev);
1690 ioc->msix_enable = 0;
1691}
1692
1693/**
1694 * _base_enable_msix - enables msix, failback to io_apic
1695 * @ioc: per adapter object
1696 *
1697 */
1698static int
1699_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1700{
1701 struct msix_entry *entries, *a;
1702 int r;
1703 int i;
1704 u8 try_msix = 0;
1705
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301706 if (msix_disable == -1 || msix_disable == 0)
1707 try_msix = 1;
1708
1709 if (!try_msix)
1710 goto try_ioapic;
1711
1712 if (_base_check_enable_msix(ioc) != 0)
1713 goto try_ioapic;
1714
1715 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1716 ioc->msix_vector_count);
1717
Sreekanth Reddy9c500062013-08-14 18:23:20 +05301718 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1719 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1720 ioc->cpu_count, max_msix_vectors);
1721
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301722 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1723 max_msix_vectors = 8;
1724
Sreekanth Reddy9c500062013-08-14 18:23:20 +05301725 if (max_msix_vectors > 0) {
1726 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1727 ioc->reply_queue_count);
1728 ioc->msix_vector_count = ioc->reply_queue_count;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301729 } else if (max_msix_vectors == 0)
1730 goto try_ioapic;
Sreekanth Reddy9c500062013-08-14 18:23:20 +05301731
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301732 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1733 GFP_KERNEL);
1734 if (!entries) {
1735 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1736 "kcalloc failed @ at %s:%d/%s() !!!\n",
1737 ioc->name, __FILE__, __LINE__, __func__));
1738 goto try_ioapic;
1739 }
1740
1741 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1742 a->entry = i;
1743
Alexander Gordeev6bfa6902014-08-18 08:01:46 +02001744 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301745 if (r) {
1746 dfailprintk(ioc, pr_info(MPT3SAS_FMT
Alexander Gordeev6bfa6902014-08-18 08:01:46 +02001747 "pci_enable_msix_exact failed (r=%d) !!!\n",
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301748 ioc->name, r));
1749 kfree(entries);
1750 goto try_ioapic;
1751 }
1752
1753 ioc->msix_enable = 1;
1754 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1755 r = _base_request_irq(ioc, i, a->vector);
1756 if (r) {
1757 _base_free_irq(ioc);
1758 _base_disable_msix(ioc);
1759 kfree(entries);
1760 goto try_ioapic;
1761 }
1762 }
1763
1764 kfree(entries);
1765 return 0;
1766
1767/* failback to io_apic interrupt routing */
1768 try_ioapic:
1769
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301770 ioc->reply_queue_count = 1;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301771 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1772
1773 return r;
1774}
1775
1776/**
1777 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
1778 * @ioc: per adapter object
1779 *
1780 * Returns 0 for success, non-zero for failure.
1781 */
1782int
1783mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
1784{
1785 struct pci_dev *pdev = ioc->pdev;
1786 u32 memap_sz;
1787 u32 pio_sz;
1788 int i, r = 0;
1789 u64 pio_chip = 0;
1790 u64 chip_phys = 0;
1791 struct adapter_reply_queue *reply_q;
1792
1793 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
1794 ioc->name, __func__));
1795
1796 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1797 if (pci_enable_device_mem(pdev)) {
1798 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
1799 ioc->name);
Joe Lawrencecf9bd21a2013-08-08 16:45:39 -04001800 ioc->bars = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301801 return -ENODEV;
1802 }
1803
1804
1805 if (pci_request_selected_regions(pdev, ioc->bars,
1806 MPT3SAS_DRIVER_NAME)) {
1807 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
1808 ioc->name);
Joe Lawrencecf9bd21a2013-08-08 16:45:39 -04001809 ioc->bars = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301810 r = -ENODEV;
1811 goto out_fail;
1812 }
1813
1814/* AER (Advanced Error Reporting) hooks */
1815 pci_enable_pcie_error_reporting(pdev);
1816
1817 pci_set_master(pdev);
1818
1819
1820 if (_base_config_dma_addressing(ioc, pdev) != 0) {
1821 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
1822 ioc->name, pci_name(pdev));
1823 r = -ENODEV;
1824 goto out_fail;
1825 }
1826
1827 for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
1828 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1829 if (pio_sz)
1830 continue;
1831 pio_chip = (u64)pci_resource_start(pdev, i);
1832 pio_sz = pci_resource_len(pdev, i);
1833 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1834 if (memap_sz)
1835 continue;
1836 ioc->chip_phys = pci_resource_start(pdev, i);
1837 chip_phys = (u64)ioc->chip_phys;
1838 memap_sz = pci_resource_len(pdev, i);
1839 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
1840 if (ioc->chip == NULL) {
1841 pr_err(MPT3SAS_FMT "unable to map adapter memory!\n",
1842 ioc->name);
1843 r = -EINVAL;
1844 goto out_fail;
1845 }
1846 }
1847 }
1848
1849 _base_mask_interrupts(ioc);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05301850
1851 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
1852 if (r)
1853 goto out_fail;
1854
1855 if (!ioc->rdpq_array_enable_assigned) {
1856 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
1857 ioc->rdpq_array_enable_assigned = 1;
1858 }
1859
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05301860 r = _base_enable_msix(ioc);
1861 if (r)
1862 goto out_fail;
1863
1864 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
1865 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
1866 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1867 "IO-APIC enabled"), reply_q->vector);
1868
1869 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1870 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1871 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
1872 ioc->name, (unsigned long long)pio_chip, pio_sz);
1873
1874 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
1875 pci_save_state(pdev);
1876 return 0;
1877
1878 out_fail:
1879 if (ioc->chip_phys)
1880 iounmap(ioc->chip);
1881 ioc->chip_phys = 0;
1882 pci_release_selected_regions(ioc->pdev, ioc->bars);
1883 pci_disable_pcie_error_reporting(pdev);
1884 pci_disable_device(pdev);
1885 return r;
1886}
1887
1888/**
1889 * mpt3sas_base_get_msg_frame - obtain request mf pointer
1890 * @ioc: per adapter object
1891 * @smid: system request message index(smid zero is invalid)
1892 *
1893 * Returns virt pointer to message frame.
1894 */
1895void *
1896mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1897{
1898 return (void *)(ioc->request + (smid * ioc->request_sz));
1899}
1900
1901/**
1902 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
1903 * @ioc: per adapter object
1904 * @smid: system request message index
1905 *
1906 * Returns virt pointer to sense buffer.
1907 */
1908void *
1909mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1910{
1911 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
1912}
1913
1914/**
1915 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
1916 * @ioc: per adapter object
1917 * @smid: system request message index
1918 *
1919 * Returns phys pointer to the low 32bit address of the sense buffer.
1920 */
1921__le32
1922mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1923{
1924 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
1925 SCSI_SENSE_BUFFERSIZE));
1926}
1927
1928/**
1929 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
1930 * @ioc: per adapter object
1931 * @phys_addr: lower 32 physical addr of the reply
1932 *
1933 * Converts 32bit lower physical addr into a virt address.
1934 */
1935void *
1936mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
1937{
1938 if (!phys_addr)
1939 return NULL;
1940 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
1941}
1942
1943/**
1944 * mpt3sas_base_get_smid - obtain a free smid from internal queue
1945 * @ioc: per adapter object
1946 * @cb_idx: callback index
1947 *
1948 * Returns smid (zero is invalid)
1949 */
1950u16
1951mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
1952{
1953 unsigned long flags;
1954 struct request_tracker *request;
1955 u16 smid;
1956
1957 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1958 if (list_empty(&ioc->internal_free_list)) {
1959 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1960 pr_err(MPT3SAS_FMT "%s: smid not available\n",
1961 ioc->name, __func__);
1962 return 0;
1963 }
1964
1965 request = list_entry(ioc->internal_free_list.next,
1966 struct request_tracker, tracker_list);
1967 request->cb_idx = cb_idx;
1968 smid = request->smid;
1969 list_del(&request->tracker_list);
1970 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1971 return smid;
1972}
1973
1974/**
1975 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
1976 * @ioc: per adapter object
1977 * @cb_idx: callback index
1978 * @scmd: pointer to scsi command object
1979 *
1980 * Returns smid (zero is invalid)
1981 */
1982u16
1983mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
1984 struct scsi_cmnd *scmd)
1985{
1986 unsigned long flags;
1987 struct scsiio_tracker *request;
1988 u16 smid;
1989
1990 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1991 if (list_empty(&ioc->free_list)) {
1992 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1993 pr_err(MPT3SAS_FMT "%s: smid not available\n",
1994 ioc->name, __func__);
1995 return 0;
1996 }
1997
1998 request = list_entry(ioc->free_list.next,
1999 struct scsiio_tracker, tracker_list);
2000 request->scmd = scmd;
2001 request->cb_idx = cb_idx;
2002 smid = request->smid;
2003 list_del(&request->tracker_list);
2004 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2005 return smid;
2006}
2007
2008/**
2009 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2010 * @ioc: per adapter object
2011 * @cb_idx: callback index
2012 *
2013 * Returns smid (zero is invalid)
2014 */
2015u16
2016mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2017{
2018 unsigned long flags;
2019 struct request_tracker *request;
2020 u16 smid;
2021
2022 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2023 if (list_empty(&ioc->hpr_free_list)) {
2024 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2025 return 0;
2026 }
2027
2028 request = list_entry(ioc->hpr_free_list.next,
2029 struct request_tracker, tracker_list);
2030 request->cb_idx = cb_idx;
2031 smid = request->smid;
2032 list_del(&request->tracker_list);
2033 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2034 return smid;
2035}
2036
2037/**
2038 * mpt3sas_base_free_smid - put smid back on free_list
2039 * @ioc: per adapter object
2040 * @smid: system request message index
2041 *
2042 * Return nothing.
2043 */
2044void
2045mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2046{
2047 unsigned long flags;
2048 int i;
2049 struct chain_tracker *chain_req, *next;
2050
2051 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2052 if (smid < ioc->hi_priority_smid) {
2053 /* scsiio queue */
2054 i = smid - 1;
2055 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2056 list_for_each_entry_safe(chain_req, next,
2057 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2058 list_del_init(&chain_req->tracker_list);
2059 list_add(&chain_req->tracker_list,
2060 &ioc->free_chain_list);
2061 }
2062 }
2063 ioc->scsi_lookup[i].cb_idx = 0xFF;
2064 ioc->scsi_lookup[i].scmd = NULL;
2065 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2066 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2067
2068 /*
2069 * See _wait_for_commands_to_complete() call with regards
2070 * to this code.
2071 */
2072 if (ioc->shost_recovery && ioc->pending_io_count) {
2073 if (ioc->pending_io_count == 1)
2074 wake_up(&ioc->reset_wq);
2075 ioc->pending_io_count--;
2076 }
2077 return;
2078 } else if (smid < ioc->internal_smid) {
2079 /* hi-priority */
2080 i = smid - ioc->hi_priority_smid;
2081 ioc->hpr_lookup[i].cb_idx = 0xFF;
2082 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2083 } else if (smid <= ioc->hba_queue_depth) {
2084 /* internal queue */
2085 i = smid - ioc->internal_smid;
2086 ioc->internal_lookup[i].cb_idx = 0xFF;
2087 list_add(&ioc->internal_lookup[i].tracker_list,
2088 &ioc->internal_free_list);
2089 }
2090 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2091}
2092
2093/**
2094 * _base_writeq - 64 bit write to MMIO
2095 * @ioc: per adapter object
2096 * @b: data payload
2097 * @addr: address in MMIO space
2098 * @writeq_lock: spin lock
2099 *
2100 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2101 * care of 32 bit environment where its not quarenteed to send the entire word
2102 * in one transfer.
2103 */
2104#if defined(writeq) && defined(CONFIG_64BIT)
2105static inline void
2106_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2107{
2108 writeq(cpu_to_le64(b), addr);
2109}
2110#else
2111static inline void
2112_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2113{
2114 unsigned long flags;
2115 __u64 data_out = cpu_to_le64(b);
2116
2117 spin_lock_irqsave(writeq_lock, flags);
2118 writel((u32)(data_out), addr);
2119 writel((u32)(data_out >> 32), (addr + 4));
2120 spin_unlock_irqrestore(writeq_lock, flags);
2121}
2122#endif
2123
2124static inline u8
2125_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2126{
2127 return ioc->cpu_msix_table[raw_smp_processor_id()];
2128}
2129
2130/**
2131 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2132 * @ioc: per adapter object
2133 * @smid: system request message index
2134 * @handle: device handle
2135 *
2136 * Return nothing.
2137 */
2138void
2139mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2140{
2141 Mpi2RequestDescriptorUnion_t descriptor;
2142 u64 *request = (u64 *)&descriptor;
2143
2144
2145 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2146 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2147 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2148 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2149 descriptor.SCSIIO.LMID = 0;
2150 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2151 &ioc->scsi_lookup_lock);
2152}
2153
2154/**
2155 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2156 * @ioc: per adapter object
2157 * @smid: system request message index
2158 * @handle: device handle
2159 *
2160 * Return nothing.
2161 */
2162void
2163mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2164 u16 handle)
2165{
2166 Mpi2RequestDescriptorUnion_t descriptor;
2167 u64 *request = (u64 *)&descriptor;
2168
2169 descriptor.SCSIIO.RequestFlags =
2170 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2171 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2172 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2173 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2174 descriptor.SCSIIO.LMID = 0;
2175 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2176 &ioc->scsi_lookup_lock);
2177}
2178
2179/**
2180 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2181 * @ioc: per adapter object
2182 * @smid: system request message index
2183 *
2184 * Return nothing.
2185 */
2186void
2187mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2188{
2189 Mpi2RequestDescriptorUnion_t descriptor;
2190 u64 *request = (u64 *)&descriptor;
2191
2192 descriptor.HighPriority.RequestFlags =
2193 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2194 descriptor.HighPriority.MSIxIndex = 0;
2195 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2196 descriptor.HighPriority.LMID = 0;
2197 descriptor.HighPriority.Reserved1 = 0;
2198 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2199 &ioc->scsi_lookup_lock);
2200}
2201
2202/**
2203 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2204 * @ioc: per adapter object
2205 * @smid: system request message index
2206 *
2207 * Return nothing.
2208 */
2209void
2210mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2211{
2212 Mpi2RequestDescriptorUnion_t descriptor;
2213 u64 *request = (u64 *)&descriptor;
2214
2215 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2216 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2217 descriptor.Default.SMID = cpu_to_le16(smid);
2218 descriptor.Default.LMID = 0;
2219 descriptor.Default.DescriptorTypeDependent = 0;
2220 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2221 &ioc->scsi_lookup_lock);
2222}
2223
Sreekanth Reddy1117b312014-09-12 15:35:30 +05302224/**
2225 * _base_display_intel_branding - Display branding string
2226 * @ioc: per adapter object
2227 *
2228 * Return nothing.
2229 */
2230static void
2231_base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc)
2232{
2233 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2234 return;
2235
2236 switch (ioc->pdev->device) {
2237 case MPI25_MFGPAGE_DEVID_SAS3008:
2238 switch (ioc->pdev->subsystem_device) {
2239 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2240 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2241 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2242 break;
2243
2244 case MPT3SAS_INTEL_RS3GC008_SSDID:
2245 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2246 MPT3SAS_INTEL_RS3GC008_BRANDING);
2247 break;
2248 case MPT3SAS_INTEL_RS3FC044_SSDID:
2249 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2250 MPT3SAS_INTEL_RS3FC044_BRANDING);
2251 break;
2252 case MPT3SAS_INTEL_RS3UC080_SSDID:
2253 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2254 MPT3SAS_INTEL_RS3UC080_BRANDING);
2255 break;
2256 default:
2257 pr_info(MPT3SAS_FMT
2258 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2259 ioc->name, ioc->pdev->subsystem_device);
2260 break;
2261 }
2262 break;
2263 default:
2264 pr_info(MPT3SAS_FMT
2265 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2266 ioc->name, ioc->pdev->subsystem_device);
2267 break;
2268 }
2269}
2270
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302271
2272
2273/**
2274 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2275 * @ioc: per adapter object
2276 *
2277 * Return nothing.
2278 */
2279static void
2280_base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2281{
2282 int i = 0;
2283 char desc[16];
2284 u32 iounit_pg1_flags;
2285 u32 bios_version;
2286
2287 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2288 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2289 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2290 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2291 ioc->name, desc,
2292 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2293 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2294 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2295 ioc->facts.FWVersion.Word & 0x000000FF,
2296 ioc->pdev->revision,
2297 (bios_version & 0xFF000000) >> 24,
2298 (bios_version & 0x00FF0000) >> 16,
2299 (bios_version & 0x0000FF00) >> 8,
2300 bios_version & 0x000000FF);
2301
Sreekanth Reddy1117b312014-09-12 15:35:30 +05302302 _base_display_intel_branding(ioc);
2303
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302304 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2305
2306 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2307 pr_info("Initiator");
2308 i++;
2309 }
2310
2311 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2312 pr_info("%sTarget", i ? "," : "");
2313 i++;
2314 }
2315
2316 i = 0;
2317 pr_info("), ");
2318 pr_info("Capabilities=(");
2319
2320 if (ioc->facts.IOCCapabilities &
2321 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2322 pr_info("Raid");
2323 i++;
2324 }
2325
2326 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2327 pr_info("%sTLR", i ? "," : "");
2328 i++;
2329 }
2330
2331 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2332 pr_info("%sMulticast", i ? "," : "");
2333 i++;
2334 }
2335
2336 if (ioc->facts.IOCCapabilities &
2337 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2338 pr_info("%sBIDI Target", i ? "," : "");
2339 i++;
2340 }
2341
2342 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2343 pr_info("%sEEDP", i ? "," : "");
2344 i++;
2345 }
2346
2347 if (ioc->facts.IOCCapabilities &
2348 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2349 pr_info("%sSnapshot Buffer", i ? "," : "");
2350 i++;
2351 }
2352
2353 if (ioc->facts.IOCCapabilities &
2354 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2355 pr_info("%sDiag Trace Buffer", i ? "," : "");
2356 i++;
2357 }
2358
2359 if (ioc->facts.IOCCapabilities &
2360 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2361 pr_info("%sDiag Extended Buffer", i ? "," : "");
2362 i++;
2363 }
2364
2365 if (ioc->facts.IOCCapabilities &
2366 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2367 pr_info("%sTask Set Full", i ? "," : "");
2368 i++;
2369 }
2370
2371 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2372 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2373 pr_info("%sNCQ", i ? "," : "");
2374 i++;
2375 }
2376
2377 pr_info(")\n");
2378}
2379
2380/**
2381 * mpt3sas_base_update_missing_delay - change the missing delay timers
2382 * @ioc: per adapter object
2383 * @device_missing_delay: amount of time till device is reported missing
2384 * @io_missing_delay: interval IO is returned when there is a missing device
2385 *
2386 * Return nothing.
2387 *
2388 * Passed on the command line, this function will modify the device missing
2389 * delay, as well as the io missing delay. This should be called at driver
2390 * load time.
2391 */
2392void
2393mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2394 u16 device_missing_delay, u8 io_missing_delay)
2395{
2396 u16 dmd, dmd_new, dmd_orignal;
2397 u8 io_missing_delay_original;
2398 u16 sz;
2399 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2400 Mpi2ConfigReply_t mpi_reply;
2401 u8 num_phys = 0;
2402 u16 ioc_status;
2403
2404 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2405 if (!num_phys)
2406 return;
2407
2408 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2409 sizeof(Mpi2SasIOUnit1PhyData_t));
2410 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2411 if (!sas_iounit_pg1) {
2412 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2413 ioc->name, __FILE__, __LINE__, __func__);
2414 goto out;
2415 }
2416 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2417 sas_iounit_pg1, sz))) {
2418 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2419 ioc->name, __FILE__, __LINE__, __func__);
2420 goto out;
2421 }
2422 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2423 MPI2_IOCSTATUS_MASK;
2424 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2425 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2426 ioc->name, __FILE__, __LINE__, __func__);
2427 goto out;
2428 }
2429
2430 /* device missing delay */
2431 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2432 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2433 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2434 else
2435 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2436 dmd_orignal = dmd;
2437 if (device_missing_delay > 0x7F) {
2438 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2439 device_missing_delay;
2440 dmd = dmd / 16;
2441 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2442 } else
2443 dmd = device_missing_delay;
2444 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2445
2446 /* io missing delay */
2447 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2448 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2449
2450 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2451 sz)) {
2452 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2453 dmd_new = (dmd &
2454 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2455 else
2456 dmd_new =
2457 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2458 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2459 ioc->name, dmd_orignal, dmd_new);
2460 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2461 ioc->name, io_missing_delay_original,
2462 io_missing_delay);
2463 ioc->device_missing_delay = dmd_new;
2464 ioc->io_missing_delay = io_missing_delay;
2465 }
2466
2467out:
2468 kfree(sas_iounit_pg1);
2469}
2470/**
2471 * _base_static_config_pages - static start of day config pages
2472 * @ioc: per adapter object
2473 *
2474 * Return nothing.
2475 */
2476static void
2477_base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2478{
2479 Mpi2ConfigReply_t mpi_reply;
2480 u32 iounit_pg1_flags;
2481
2482 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2483 if (ioc->ir_firmware)
2484 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2485 &ioc->manu_pg10);
2486
2487 /*
2488 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2489 * flag unset in NVDATA.
2490 */
2491 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2492 if (ioc->manu_pg11.EEDPTagMode == 0) {
2493 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2494 ioc->name);
2495 ioc->manu_pg11.EEDPTagMode &= ~0x3;
2496 ioc->manu_pg11.EEDPTagMode |= 0x1;
2497 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2498 &ioc->manu_pg11);
2499 }
2500
2501 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2502 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2503 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2504 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2505 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
Sreekanth Reddy2d8ce8c2015-01-12 11:38:56 +05302506 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302507 _base_display_ioc_capabilities(ioc);
2508
2509 /*
2510 * Enable task_set_full handling in iounit_pg1 when the
2511 * facts capabilities indicate that its supported.
2512 */
2513 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2514 if ((ioc->facts.IOCCapabilities &
2515 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2516 iounit_pg1_flags &=
2517 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2518 else
2519 iounit_pg1_flags |=
2520 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2521 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2522 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
Sreekanth Reddy2d8ce8c2015-01-12 11:38:56 +05302523
2524 if (ioc->iounit_pg8.NumSensors)
2525 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302526}
2527
2528/**
2529 * _base_release_memory_pools - release memory
2530 * @ioc: per adapter object
2531 *
2532 * Free memory allocated from _base_allocate_memory_pools.
2533 *
2534 * Return nothing.
2535 */
2536static void
2537_base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
2538{
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05302539 int i = 0;
2540 struct reply_post_struct *rps;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302541
2542 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2543 __func__));
2544
2545 if (ioc->request) {
2546 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2547 ioc->request, ioc->request_dma);
2548 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2549 "request_pool(0x%p): free\n",
2550 ioc->name, ioc->request));
2551 ioc->request = NULL;
2552 }
2553
2554 if (ioc->sense) {
2555 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2556 if (ioc->sense_dma_pool)
2557 pci_pool_destroy(ioc->sense_dma_pool);
2558 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2559 "sense_pool(0x%p): free\n",
2560 ioc->name, ioc->sense));
2561 ioc->sense = NULL;
2562 }
2563
2564 if (ioc->reply) {
2565 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2566 if (ioc->reply_dma_pool)
2567 pci_pool_destroy(ioc->reply_dma_pool);
2568 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2569 "reply_pool(0x%p): free\n",
2570 ioc->name, ioc->reply));
2571 ioc->reply = NULL;
2572 }
2573
2574 if (ioc->reply_free) {
2575 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2576 ioc->reply_free_dma);
2577 if (ioc->reply_free_dma_pool)
2578 pci_pool_destroy(ioc->reply_free_dma_pool);
2579 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2580 "reply_free_pool(0x%p): free\n",
2581 ioc->name, ioc->reply_free));
2582 ioc->reply_free = NULL;
2583 }
2584
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05302585 if (ioc->reply_post) {
2586 do {
2587 rps = &ioc->reply_post[i];
2588 if (rps->reply_post_free) {
2589 pci_pool_free(
2590 ioc->reply_post_free_dma_pool,
2591 rps->reply_post_free,
2592 rps->reply_post_free_dma);
2593 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2594 "reply_post_free_pool(0x%p): free\n",
2595 ioc->name, rps->reply_post_free));
2596 rps->reply_post_free = NULL;
2597 }
2598 } while (ioc->rdpq_array_enable &&
2599 (++i < ioc->reply_queue_count));
2600
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302601 if (ioc->reply_post_free_dma_pool)
2602 pci_pool_destroy(ioc->reply_post_free_dma_pool);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05302603 kfree(ioc->reply_post);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302604 }
2605
2606 if (ioc->config_page) {
2607 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2608 "config_page(0x%p): free\n", ioc->name,
2609 ioc->config_page));
2610 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2611 ioc->config_page, ioc->config_page_dma);
2612 }
2613
2614 if (ioc->scsi_lookup) {
2615 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2616 ioc->scsi_lookup = NULL;
2617 }
2618 kfree(ioc->hpr_lookup);
2619 kfree(ioc->internal_lookup);
2620 if (ioc->chain_lookup) {
2621 for (i = 0; i < ioc->chain_depth; i++) {
2622 if (ioc->chain_lookup[i].chain_buffer)
2623 pci_pool_free(ioc->chain_dma_pool,
2624 ioc->chain_lookup[i].chain_buffer,
2625 ioc->chain_lookup[i].chain_buffer_dma);
2626 }
2627 if (ioc->chain_dma_pool)
2628 pci_pool_destroy(ioc->chain_dma_pool);
2629 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2630 ioc->chain_lookup = NULL;
2631 }
2632}
2633
2634/**
2635 * _base_allocate_memory_pools - allocate start of day memory pools
2636 * @ioc: per adapter object
2637 * @sleep_flag: CAN_SLEEP or NO_SLEEP
2638 *
2639 * Returns 0 success, anything else error
2640 */
2641static int
2642_base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
2643{
2644 struct mpt3sas_facts *facts;
2645 u16 max_sge_elements;
2646 u16 chains_needed_per_io;
2647 u32 sz, total_sz, reply_post_free_sz;
2648 u32 retry_sz;
2649 u16 max_request_credit;
2650 unsigned short sg_tablesize;
2651 u16 sge_size;
2652 int i;
2653
2654 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2655 __func__));
2656
2657
2658 retry_sz = 0;
2659 facts = &ioc->facts;
2660
2661 /* command line tunables for max sgl entries */
2662 if (max_sgl_entries != -1)
2663 sg_tablesize = max_sgl_entries;
2664 else
2665 sg_tablesize = MPT3SAS_SG_DEPTH;
2666
2667 if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS)
2668 sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS;
Sreekanth Reddyad666a02015-01-12 11:39:00 +05302669 else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS) {
2670 sg_tablesize = min_t(unsigned short, sg_tablesize,
2671 SCSI_MAX_SG_CHAIN_SEGMENTS);
2672 pr_warn(MPT3SAS_FMT
2673 "sg_tablesize(%u) is bigger than kernel"
2674 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
2675 sg_tablesize, MPT3SAS_MAX_PHYS_SEGMENTS);
2676 }
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302677 ioc->shost->sg_tablesize = sg_tablesize;
2678
2679 ioc->hi_priority_depth = facts->HighPriorityCredit;
2680 ioc->internal_depth = ioc->hi_priority_depth + (5);
2681 /* command line tunables for max controller queue depth */
2682 if (max_queue_depth != -1 && max_queue_depth != 0) {
2683 max_request_credit = min_t(u16, max_queue_depth +
2684 ioc->hi_priority_depth + ioc->internal_depth,
2685 facts->RequestCredit);
2686 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
2687 max_request_credit = MAX_HBA_QUEUE_DEPTH;
2688 } else
2689 max_request_credit = min_t(u16, facts->RequestCredit,
2690 MAX_HBA_QUEUE_DEPTH);
2691
2692 ioc->hba_queue_depth = max_request_credit;
2693
2694 /* request frame size */
2695 ioc->request_sz = facts->IOCRequestFrameSize * 4;
2696
2697 /* reply frame size */
2698 ioc->reply_sz = facts->ReplyFrameSize * 4;
2699
2700 /* calculate the max scatter element size */
2701 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
2702
2703 retry_allocation:
2704 total_sz = 0;
2705 /* calculate number of sg elements left over in the 1st frame */
2706 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
2707 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
2708 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
2709
2710 /* now do the same for a chain buffer */
2711 max_sge_elements = ioc->request_sz - sge_size;
2712 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
2713
2714 /*
2715 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
2716 */
2717 chains_needed_per_io = ((ioc->shost->sg_tablesize -
2718 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2719 + 1;
2720 if (chains_needed_per_io > facts->MaxChainDepth) {
2721 chains_needed_per_io = facts->MaxChainDepth;
2722 ioc->shost->sg_tablesize = min_t(u16,
2723 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2724 * chains_needed_per_io), ioc->shost->sg_tablesize);
2725 }
2726 ioc->chains_needed_per_io = chains_needed_per_io;
2727
2728 /* reply free queue sizing - taking into account for 64 FW events */
2729 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2730
2731 /* calculate reply descriptor post queue depth */
2732 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
2733 ioc->reply_free_queue_depth + 1 ;
2734 /* align the reply post queue on the next 16 count boundary */
2735 if (ioc->reply_post_queue_depth % 16)
2736 ioc->reply_post_queue_depth += 16 -
2737 (ioc->reply_post_queue_depth % 16);
2738
2739
2740 if (ioc->reply_post_queue_depth >
2741 facts->MaxReplyDescriptorPostQueueDepth) {
2742 ioc->reply_post_queue_depth =
2743 facts->MaxReplyDescriptorPostQueueDepth -
2744 (facts->MaxReplyDescriptorPostQueueDepth % 16);
2745 ioc->hba_queue_depth =
2746 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
2747 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2748 }
2749
2750 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
2751 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2752 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2753 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2754 ioc->chains_needed_per_io));
2755
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05302756 /* reply post queue, 16 byte align */
2757 reply_post_free_sz = ioc->reply_post_queue_depth *
2758 sizeof(Mpi2DefaultReplyDescriptor_t);
2759
2760 sz = reply_post_free_sz;
2761 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
2762 sz *= ioc->reply_queue_count;
2763
2764 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
2765 (ioc->reply_queue_count):1,
2766 sizeof(struct reply_post_struct), GFP_KERNEL);
2767
2768 if (!ioc->reply_post) {
2769 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
2770 ioc->name);
2771 goto out;
2772 }
2773 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2774 ioc->pdev, sz, 16, 0);
2775 if (!ioc->reply_post_free_dma_pool) {
2776 pr_err(MPT3SAS_FMT
2777 "reply_post_free pool: pci_pool_create failed\n",
2778 ioc->name);
2779 goto out;
2780 }
2781 i = 0;
2782 do {
2783 ioc->reply_post[i].reply_post_free =
2784 pci_pool_alloc(ioc->reply_post_free_dma_pool,
2785 GFP_KERNEL,
2786 &ioc->reply_post[i].reply_post_free_dma);
2787 if (!ioc->reply_post[i].reply_post_free) {
2788 pr_err(MPT3SAS_FMT
2789 "reply_post_free pool: pci_pool_alloc failed\n",
2790 ioc->name);
2791 goto out;
2792 }
2793 memset(ioc->reply_post[i].reply_post_free, 0, sz);
2794 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2795 "reply post free pool (0x%p): depth(%d),"
2796 "element_size(%d), pool_size(%d kB)\n", ioc->name,
2797 ioc->reply_post[i].reply_post_free,
2798 ioc->reply_post_queue_depth, 8, sz/1024));
2799 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2800 "reply_post_free_dma = (0x%llx)\n", ioc->name,
2801 (unsigned long long)
2802 ioc->reply_post[i].reply_post_free_dma));
2803 total_sz += sz;
2804 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
2805
2806 if (ioc->dma_mask == 64) {
2807 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
2808 pr_warn(MPT3SAS_FMT
2809 "no suitable consistent DMA mask for %s\n",
2810 ioc->name, pci_name(ioc->pdev));
2811 goto out;
2812 }
2813 }
2814
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05302815 ioc->scsiio_depth = ioc->hba_queue_depth -
2816 ioc->hi_priority_depth - ioc->internal_depth;
2817
2818 /* set the scsi host can_queue depth
2819 * with some internal commands that could be outstanding
2820 */
2821 ioc->shost->can_queue = ioc->scsiio_depth;
2822 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2823 "scsi host: can_queue depth (%d)\n",
2824 ioc->name, ioc->shost->can_queue));
2825
2826
2827 /* contiguous pool for request and chains, 16 byte align, one extra "
2828 * "frame for smid=0
2829 */
2830 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
2831 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
2832
2833 /* hi-priority queue */
2834 sz += (ioc->hi_priority_depth * ioc->request_sz);
2835
2836 /* internal queue */
2837 sz += (ioc->internal_depth * ioc->request_sz);
2838
2839 ioc->request_dma_sz = sz;
2840 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
2841 if (!ioc->request) {
2842 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2843 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2844 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
2845 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2846 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
2847 goto out;
2848 retry_sz += 64;
2849 ioc->hba_queue_depth = max_request_credit - retry_sz;
2850 goto retry_allocation;
2851 }
2852
2853 if (retry_sz)
2854 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2855 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2856 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
2857 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2858
2859 /* hi-priority queue */
2860 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
2861 ioc->request_sz);
2862 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
2863 ioc->request_sz);
2864
2865 /* internal queue */
2866 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
2867 ioc->request_sz);
2868 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
2869 ioc->request_sz);
2870
2871 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2872 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
2873 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
2874 (ioc->hba_queue_depth * ioc->request_sz)/1024));
2875
2876 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
2877 ioc->name, (unsigned long long) ioc->request_dma));
2878 total_sz += sz;
2879
2880 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
2881 ioc->scsi_lookup_pages = get_order(sz);
2882 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
2883 GFP_KERNEL, ioc->scsi_lookup_pages);
2884 if (!ioc->scsi_lookup) {
2885 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
2886 ioc->name, (int)sz);
2887 goto out;
2888 }
2889
2890 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
2891 ioc->name, ioc->request, ioc->scsiio_depth));
2892
2893 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
2894 sz = ioc->chain_depth * sizeof(struct chain_tracker);
2895 ioc->chain_pages = get_order(sz);
2896 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
2897 GFP_KERNEL, ioc->chain_pages);
2898 if (!ioc->chain_lookup) {
2899 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
2900 ioc->name);
2901 goto out;
2902 }
2903 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
2904 ioc->request_sz, 16, 0);
2905 if (!ioc->chain_dma_pool) {
2906 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
2907 ioc->name);
2908 goto out;
2909 }
2910 for (i = 0; i < ioc->chain_depth; i++) {
2911 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
2912 ioc->chain_dma_pool , GFP_KERNEL,
2913 &ioc->chain_lookup[i].chain_buffer_dma);
2914 if (!ioc->chain_lookup[i].chain_buffer) {
2915 ioc->chain_depth = i;
2916 goto chain_done;
2917 }
2918 total_sz += ioc->request_sz;
2919 }
2920 chain_done:
2921 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2922 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
2923 ioc->name, ioc->chain_depth, ioc->request_sz,
2924 ((ioc->chain_depth * ioc->request_sz))/1024));
2925
2926 /* initialize hi-priority queue smid's */
2927 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
2928 sizeof(struct request_tracker), GFP_KERNEL);
2929 if (!ioc->hpr_lookup) {
2930 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
2931 ioc->name);
2932 goto out;
2933 }
2934 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
2935 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2936 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
2937 ioc->name, ioc->hi_priority,
2938 ioc->hi_priority_depth, ioc->hi_priority_smid));
2939
2940 /* initialize internal queue smid's */
2941 ioc->internal_lookup = kcalloc(ioc->internal_depth,
2942 sizeof(struct request_tracker), GFP_KERNEL);
2943 if (!ioc->internal_lookup) {
2944 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
2945 ioc->name);
2946 goto out;
2947 }
2948 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
2949 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2950 "internal(0x%p): depth(%d), start smid(%d)\n",
2951 ioc->name, ioc->internal,
2952 ioc->internal_depth, ioc->internal_smid));
2953
2954 /* sense buffers, 4 byte align */
2955 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
2956 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
2957 0);
2958 if (!ioc->sense_dma_pool) {
2959 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
2960 ioc->name);
2961 goto out;
2962 }
2963 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
2964 &ioc->sense_dma);
2965 if (!ioc->sense) {
2966 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
2967 ioc->name);
2968 goto out;
2969 }
2970 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2971 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
2972 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
2973 SCSI_SENSE_BUFFERSIZE, sz/1024));
2974 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
2975 ioc->name, (unsigned long long)ioc->sense_dma));
2976 total_sz += sz;
2977
2978 /* reply pool, 4 byte align */
2979 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
2980 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
2981 0);
2982 if (!ioc->reply_dma_pool) {
2983 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
2984 ioc->name);
2985 goto out;
2986 }
2987 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
2988 &ioc->reply_dma);
2989 if (!ioc->reply) {
2990 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
2991 ioc->name);
2992 goto out;
2993 }
2994 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
2995 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
2996 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2997 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
2998 ioc->name, ioc->reply,
2999 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3000 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3001 ioc->name, (unsigned long long)ioc->reply_dma));
3002 total_sz += sz;
3003
3004 /* reply free queue, 16 byte align */
3005 sz = ioc->reply_free_queue_depth * 4;
3006 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3007 ioc->pdev, sz, 16, 0);
3008 if (!ioc->reply_free_dma_pool) {
3009 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3010 ioc->name);
3011 goto out;
3012 }
3013 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3014 &ioc->reply_free_dma);
3015 if (!ioc->reply_free) {
3016 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3017 ioc->name);
3018 goto out;
3019 }
3020 memset(ioc->reply_free, 0, sz);
3021 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3022 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3023 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3024 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3025 "reply_free_dma (0x%llx)\n",
3026 ioc->name, (unsigned long long)ioc->reply_free_dma));
3027 total_sz += sz;
3028
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303029 ioc->config_page_sz = 512;
3030 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3031 ioc->config_page_sz, &ioc->config_page_dma);
3032 if (!ioc->config_page) {
3033 pr_err(MPT3SAS_FMT
3034 "config page: pci_pool_alloc failed\n",
3035 ioc->name);
3036 goto out;
3037 }
3038 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3039 "config page(0x%p): size(%d)\n",
3040 ioc->name, ioc->config_page, ioc->config_page_sz));
3041 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3042 ioc->name, (unsigned long long)ioc->config_page_dma));
3043 total_sz += ioc->config_page_sz;
3044
3045 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3046 ioc->name, total_sz/1024);
3047 pr_info(MPT3SAS_FMT
3048 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3049 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3050 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3051 ioc->name, ioc->shost->sg_tablesize);
3052 return 0;
3053
3054 out:
3055 return -ENOMEM;
3056}
3057
3058/**
3059 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3060 * @ioc: Pointer to MPT_ADAPTER structure
3061 * @cooked: Request raw or cooked IOC state
3062 *
3063 * Returns all IOC Doorbell register bits if cooked==0, else just the
3064 * Doorbell bits in MPI_IOC_STATE_MASK.
3065 */
3066u32
3067mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3068{
3069 u32 s, sc;
3070
3071 s = readl(&ioc->chip->Doorbell);
3072 sc = s & MPI2_IOC_STATE_MASK;
3073 return cooked ? sc : s;
3074}
3075
3076/**
3077 * _base_wait_on_iocstate - waiting on a particular ioc state
3078 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3079 * @timeout: timeout in second
3080 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3081 *
3082 * Returns 0 for success, non-zero for failure.
3083 */
3084static int
3085_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3086 int sleep_flag)
3087{
3088 u32 count, cntdn;
3089 u32 current_state;
3090
3091 count = 0;
3092 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3093 do {
3094 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3095 if (current_state == ioc_state)
3096 return 0;
3097 if (count && current_state == MPI2_IOC_STATE_FAULT)
3098 break;
3099 if (sleep_flag == CAN_SLEEP)
3100 usleep_range(1000, 1500);
3101 else
3102 udelay(500);
3103 count++;
3104 } while (--cntdn);
3105
3106 return current_state;
3107}
3108
3109/**
3110 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3111 * a write to the doorbell)
3112 * @ioc: per adapter object
3113 * @timeout: timeout in second
3114 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3115 *
3116 * Returns 0 for success, non-zero for failure.
3117 *
3118 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3119 */
3120static int
3121_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3122 int sleep_flag)
3123{
3124 u32 cntdn, count;
3125 u32 int_status;
3126
3127 count = 0;
3128 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3129 do {
3130 int_status = readl(&ioc->chip->HostInterruptStatus);
3131 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3132 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3133 "%s: successful count(%d), timeout(%d)\n",
3134 ioc->name, __func__, count, timeout));
3135 return 0;
3136 }
3137 if (sleep_flag == CAN_SLEEP)
3138 usleep_range(1000, 1500);
3139 else
3140 udelay(500);
3141 count++;
3142 } while (--cntdn);
3143
3144 pr_err(MPT3SAS_FMT
3145 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3146 ioc->name, __func__, count, int_status);
3147 return -EFAULT;
3148}
3149
3150/**
3151 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3152 * @ioc: per adapter object
3153 * @timeout: timeout in second
3154 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3155 *
3156 * Returns 0 for success, non-zero for failure.
3157 *
3158 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3159 * doorbell.
3160 */
3161static int
3162_base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3163 int sleep_flag)
3164{
3165 u32 cntdn, count;
3166 u32 int_status;
3167 u32 doorbell;
3168
3169 count = 0;
3170 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3171 do {
3172 int_status = readl(&ioc->chip->HostInterruptStatus);
3173 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3174 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3175 "%s: successful count(%d), timeout(%d)\n",
3176 ioc->name, __func__, count, timeout));
3177 return 0;
3178 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3179 doorbell = readl(&ioc->chip->Doorbell);
3180 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3181 MPI2_IOC_STATE_FAULT) {
3182 mpt3sas_base_fault_info(ioc , doorbell);
3183 return -EFAULT;
3184 }
3185 } else if (int_status == 0xFFFFFFFF)
3186 goto out;
3187
3188 if (sleep_flag == CAN_SLEEP)
3189 usleep_range(1000, 1500);
3190 else
3191 udelay(500);
3192 count++;
3193 } while (--cntdn);
3194
3195 out:
3196 pr_err(MPT3SAS_FMT
3197 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3198 ioc->name, __func__, count, int_status);
3199 return -EFAULT;
3200}
3201
3202/**
3203 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3204 * @ioc: per adapter object
3205 * @timeout: timeout in second
3206 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3207 *
3208 * Returns 0 for success, non-zero for failure.
3209 *
3210 */
3211static int
3212_base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3213 int sleep_flag)
3214{
3215 u32 cntdn, count;
3216 u32 doorbell_reg;
3217
3218 count = 0;
3219 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3220 do {
3221 doorbell_reg = readl(&ioc->chip->Doorbell);
3222 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3223 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3224 "%s: successful count(%d), timeout(%d)\n",
3225 ioc->name, __func__, count, timeout));
3226 return 0;
3227 }
3228 if (sleep_flag == CAN_SLEEP)
3229 usleep_range(1000, 1500);
3230 else
3231 udelay(500);
3232 count++;
3233 } while (--cntdn);
3234
3235 pr_err(MPT3SAS_FMT
3236 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3237 ioc->name, __func__, count, doorbell_reg);
3238 return -EFAULT;
3239}
3240
3241/**
3242 * _base_send_ioc_reset - send doorbell reset
3243 * @ioc: per adapter object
3244 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3245 * @timeout: timeout in second
3246 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3247 *
3248 * Returns 0 for success, non-zero for failure.
3249 */
3250static int
3251_base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3252 int sleep_flag)
3253{
3254 u32 ioc_state;
3255 int r = 0;
3256
3257 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3258 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3259 ioc->name, __func__);
3260 return -EFAULT;
3261 }
3262
3263 if (!(ioc->facts.IOCCapabilities &
3264 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3265 return -EFAULT;
3266
3267 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3268
3269 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3270 &ioc->chip->Doorbell);
3271 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3272 r = -EFAULT;
3273 goto out;
3274 }
3275 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3276 timeout, sleep_flag);
3277 if (ioc_state) {
3278 pr_err(MPT3SAS_FMT
3279 "%s: failed going to ready state (ioc_state=0x%x)\n",
3280 ioc->name, __func__, ioc_state);
3281 r = -EFAULT;
3282 goto out;
3283 }
3284 out:
3285 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3286 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3287 return r;
3288}
3289
3290/**
3291 * _base_handshake_req_reply_wait - send request thru doorbell interface
3292 * @ioc: per adapter object
3293 * @request_bytes: request length
3294 * @request: pointer having request payload
3295 * @reply_bytes: reply length
3296 * @reply: pointer to reply payload
3297 * @timeout: timeout in second
3298 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3299 *
3300 * Returns 0 for success, non-zero for failure.
3301 */
3302static int
3303_base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3304 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3305{
3306 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3307 int i;
3308 u8 failed;
3309 u16 dummy;
3310 __le32 *mfp;
3311
3312 /* make sure doorbell is not in use */
3313 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3314 pr_err(MPT3SAS_FMT
3315 "doorbell is in use (line=%d)\n",
3316 ioc->name, __LINE__);
3317 return -EFAULT;
3318 }
3319
3320 /* clear pending doorbell interrupts from previous state changes */
3321 if (readl(&ioc->chip->HostInterruptStatus) &
3322 MPI2_HIS_IOC2SYS_DB_STATUS)
3323 writel(0, &ioc->chip->HostInterruptStatus);
3324
3325 /* send message to ioc */
3326 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3327 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3328 &ioc->chip->Doorbell);
3329
3330 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3331 pr_err(MPT3SAS_FMT
3332 "doorbell handshake int failed (line=%d)\n",
3333 ioc->name, __LINE__);
3334 return -EFAULT;
3335 }
3336 writel(0, &ioc->chip->HostInterruptStatus);
3337
3338 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3339 pr_err(MPT3SAS_FMT
3340 "doorbell handshake ack failed (line=%d)\n",
3341 ioc->name, __LINE__);
3342 return -EFAULT;
3343 }
3344
3345 /* send message 32-bits at a time */
3346 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3347 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3348 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3349 failed = 1;
3350 }
3351
3352 if (failed) {
3353 pr_err(MPT3SAS_FMT
3354 "doorbell handshake sending request failed (line=%d)\n",
3355 ioc->name, __LINE__);
3356 return -EFAULT;
3357 }
3358
3359 /* now wait for the reply */
3360 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3361 pr_err(MPT3SAS_FMT
3362 "doorbell handshake int failed (line=%d)\n",
3363 ioc->name, __LINE__);
3364 return -EFAULT;
3365 }
3366
3367 /* read the first two 16-bits, it gives the total length of the reply */
3368 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3369 & MPI2_DOORBELL_DATA_MASK);
3370 writel(0, &ioc->chip->HostInterruptStatus);
3371 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3372 pr_err(MPT3SAS_FMT
3373 "doorbell handshake int failed (line=%d)\n",
3374 ioc->name, __LINE__);
3375 return -EFAULT;
3376 }
3377 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3378 & MPI2_DOORBELL_DATA_MASK);
3379 writel(0, &ioc->chip->HostInterruptStatus);
3380
3381 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3382 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3383 pr_err(MPT3SAS_FMT
3384 "doorbell handshake int failed (line=%d)\n",
3385 ioc->name, __LINE__);
3386 return -EFAULT;
3387 }
3388 if (i >= reply_bytes/2) /* overflow case */
3389 dummy = readl(&ioc->chip->Doorbell);
3390 else
3391 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3392 & MPI2_DOORBELL_DATA_MASK);
3393 writel(0, &ioc->chip->HostInterruptStatus);
3394 }
3395
3396 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3397 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3398 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3399 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3400 }
3401 writel(0, &ioc->chip->HostInterruptStatus);
3402
3403 if (ioc->logging_level & MPT_DEBUG_INIT) {
3404 mfp = (__le32 *)reply;
3405 pr_info("\toffset:data\n");
3406 for (i = 0; i < reply_bytes/4; i++)
3407 pr_info("\t[0x%02x]:%08x\n", i*4,
3408 le32_to_cpu(mfp[i]));
3409 }
3410 return 0;
3411}
3412
3413/**
3414 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3415 * @ioc: per adapter object
3416 * @mpi_reply: the reply payload from FW
3417 * @mpi_request: the request payload sent to FW
3418 *
3419 * The SAS IO Unit Control Request message allows the host to perform low-level
3420 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3421 * to obtain the IOC assigned device handles for a device if it has other
3422 * identifying information about the device, in addition allows the host to
3423 * remove IOC resources associated with the device.
3424 *
3425 * Returns 0 for success, non-zero for failure.
3426 */
3427int
3428mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3429 Mpi2SasIoUnitControlReply_t *mpi_reply,
3430 Mpi2SasIoUnitControlRequest_t *mpi_request)
3431{
3432 u16 smid;
3433 u32 ioc_state;
3434 unsigned long timeleft;
Dan Carpentereb445522014-12-04 13:57:05 +03003435 bool issue_reset = false;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303436 int rc;
3437 void *request;
3438 u16 wait_state_count;
3439
3440 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3441 __func__));
3442
3443 mutex_lock(&ioc->base_cmds.mutex);
3444
3445 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3446 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3447 ioc->name, __func__);
3448 rc = -EAGAIN;
3449 goto out;
3450 }
3451
3452 wait_state_count = 0;
3453 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3454 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3455 if (wait_state_count++ == 10) {
3456 pr_err(MPT3SAS_FMT
3457 "%s: failed due to ioc not operational\n",
3458 ioc->name, __func__);
3459 rc = -EFAULT;
3460 goto out;
3461 }
3462 ssleep(1);
3463 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3464 pr_info(MPT3SAS_FMT
3465 "%s: waiting for operational state(count=%d)\n",
3466 ioc->name, __func__, wait_state_count);
3467 }
3468
3469 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3470 if (!smid) {
3471 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3472 ioc->name, __func__);
3473 rc = -EAGAIN;
3474 goto out;
3475 }
3476
3477 rc = 0;
3478 ioc->base_cmds.status = MPT3_CMD_PENDING;
3479 request = mpt3sas_base_get_msg_frame(ioc, smid);
3480 ioc->base_cmds.smid = smid;
3481 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3482 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3483 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3484 ioc->ioc_link_reset_in_progress = 1;
3485 init_completion(&ioc->base_cmds.done);
3486 mpt3sas_base_put_smid_default(ioc, smid);
3487 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3488 msecs_to_jiffies(10000));
3489 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3490 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3491 ioc->ioc_link_reset_in_progress)
3492 ioc->ioc_link_reset_in_progress = 0;
3493 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3494 pr_err(MPT3SAS_FMT "%s: timeout\n",
3495 ioc->name, __func__);
3496 _debug_dump_mf(mpi_request,
3497 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3498 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
Dan Carpentereb445522014-12-04 13:57:05 +03003499 issue_reset = true;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303500 goto issue_host_reset;
3501 }
3502 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3503 memcpy(mpi_reply, ioc->base_cmds.reply,
3504 sizeof(Mpi2SasIoUnitControlReply_t));
3505 else
3506 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3507 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3508 goto out;
3509
3510 issue_host_reset:
3511 if (issue_reset)
3512 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3513 FORCE_BIG_HAMMER);
3514 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3515 rc = -EFAULT;
3516 out:
3517 mutex_unlock(&ioc->base_cmds.mutex);
3518 return rc;
3519}
3520
3521/**
3522 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
3523 * @ioc: per adapter object
3524 * @mpi_reply: the reply payload from FW
3525 * @mpi_request: the request payload sent to FW
3526 *
3527 * The SCSI Enclosure Processor request message causes the IOC to
3528 * communicate with SES devices to control LED status signals.
3529 *
3530 * Returns 0 for success, non-zero for failure.
3531 */
3532int
3533mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
3534 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3535{
3536 u16 smid;
3537 u32 ioc_state;
3538 unsigned long timeleft;
Dan Carpentereb445522014-12-04 13:57:05 +03003539 bool issue_reset = false;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303540 int rc;
3541 void *request;
3542 u16 wait_state_count;
3543
3544 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3545 __func__));
3546
3547 mutex_lock(&ioc->base_cmds.mutex);
3548
3549 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3550 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3551 ioc->name, __func__);
3552 rc = -EAGAIN;
3553 goto out;
3554 }
3555
3556 wait_state_count = 0;
3557 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3558 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3559 if (wait_state_count++ == 10) {
3560 pr_err(MPT3SAS_FMT
3561 "%s: failed due to ioc not operational\n",
3562 ioc->name, __func__);
3563 rc = -EFAULT;
3564 goto out;
3565 }
3566 ssleep(1);
3567 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3568 pr_info(MPT3SAS_FMT
3569 "%s: waiting for operational state(count=%d)\n",
3570 ioc->name,
3571 __func__, wait_state_count);
3572 }
3573
3574 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3575 if (!smid) {
3576 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3577 ioc->name, __func__);
3578 rc = -EAGAIN;
3579 goto out;
3580 }
3581
3582 rc = 0;
3583 ioc->base_cmds.status = MPT3_CMD_PENDING;
3584 request = mpt3sas_base_get_msg_frame(ioc, smid);
3585 ioc->base_cmds.smid = smid;
3586 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3587 init_completion(&ioc->base_cmds.done);
3588 mpt3sas_base_put_smid_default(ioc, smid);
3589 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3590 msecs_to_jiffies(10000));
3591 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3592 pr_err(MPT3SAS_FMT "%s: timeout\n",
3593 ioc->name, __func__);
3594 _debug_dump_mf(mpi_request,
3595 sizeof(Mpi2SepRequest_t)/4);
3596 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
Dan Carpentereb445522014-12-04 13:57:05 +03003597 issue_reset = false;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303598 goto issue_host_reset;
3599 }
3600 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3601 memcpy(mpi_reply, ioc->base_cmds.reply,
3602 sizeof(Mpi2SepReply_t));
3603 else
3604 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3605 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3606 goto out;
3607
3608 issue_host_reset:
3609 if (issue_reset)
3610 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3611 FORCE_BIG_HAMMER);
3612 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3613 rc = -EFAULT;
3614 out:
3615 mutex_unlock(&ioc->base_cmds.mutex);
3616 return rc;
3617}
3618
3619/**
3620 * _base_get_port_facts - obtain port facts reply and save in ioc
3621 * @ioc: per adapter object
3622 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3623 *
3624 * Returns 0 for success, non-zero for failure.
3625 */
3626static int
3627_base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
3628{
3629 Mpi2PortFactsRequest_t mpi_request;
3630 Mpi2PortFactsReply_t mpi_reply;
3631 struct mpt3sas_port_facts *pfacts;
3632 int mpi_reply_sz, mpi_request_sz, r;
3633
3634 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3635 __func__));
3636
3637 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
3638 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
3639 memset(&mpi_request, 0, mpi_request_sz);
3640 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
3641 mpi_request.PortNumber = port;
3642 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3643 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3644
3645 if (r != 0) {
3646 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3647 ioc->name, __func__, r);
3648 return r;
3649 }
3650
3651 pfacts = &ioc->pfacts[port];
3652 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
3653 pfacts->PortNumber = mpi_reply.PortNumber;
3654 pfacts->VP_ID = mpi_reply.VP_ID;
3655 pfacts->VF_ID = mpi_reply.VF_ID;
3656 pfacts->MaxPostedCmdBuffers =
3657 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
3658
3659 return 0;
3660}
3661
3662/**
3663 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
3664 * @ioc: per adapter object
3665 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3666 *
3667 * Returns 0 for success, non-zero for failure.
3668 */
3669static int
3670_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3671{
3672 Mpi2IOCFactsRequest_t mpi_request;
3673 Mpi2IOCFactsReply_t mpi_reply;
3674 struct mpt3sas_facts *facts;
3675 int mpi_reply_sz, mpi_request_sz, r;
3676
3677 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3678 __func__));
3679
3680 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
3681 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
3682 memset(&mpi_request, 0, mpi_request_sz);
3683 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
3684 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3685 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3686
3687 if (r != 0) {
3688 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3689 ioc->name, __func__, r);
3690 return r;
3691 }
3692
3693 facts = &ioc->facts;
3694 memset(facts, 0, sizeof(struct mpt3sas_facts));
3695 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
3696 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
3697 facts->VP_ID = mpi_reply.VP_ID;
3698 facts->VF_ID = mpi_reply.VF_ID;
3699 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
3700 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
3701 facts->WhoInit = mpi_reply.WhoInit;
3702 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
3703 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
3704 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
3705 facts->MaxReplyDescriptorPostQueueDepth =
3706 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
3707 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
3708 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
3709 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
3710 ioc->ir_firmware = 1;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303711 if ((facts->IOCCapabilities &
3712 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
3713 ioc->rdpq_array_capable = 1;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303714 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
3715 facts->IOCRequestFrameSize =
3716 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
3717 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
3718 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
3719 ioc->shost->max_id = -1;
3720 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
3721 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
3722 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
3723 facts->HighPriorityCredit =
3724 le16_to_cpu(mpi_reply.HighPriorityCredit);
3725 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
3726 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
3727
3728 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3729 "hba queue depth(%d), max chains per io(%d)\n",
3730 ioc->name, facts->RequestCredit,
3731 facts->MaxChainDepth));
3732 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3733 "request frame size(%d), reply frame size(%d)\n", ioc->name,
3734 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
3735 return 0;
3736}
3737
3738/**
3739 * _base_send_ioc_init - send ioc_init to firmware
3740 * @ioc: per adapter object
3741 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3742 *
3743 * Returns 0 for success, non-zero for failure.
3744 */
3745static int
3746_base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3747{
3748 Mpi2IOCInitRequest_t mpi_request;
3749 Mpi2IOCInitReply_t mpi_reply;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303750 int i, r = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303751 struct timeval current_time;
3752 u16 ioc_status;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303753 u32 reply_post_free_array_sz = 0;
3754 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
3755 dma_addr_t reply_post_free_array_dma;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303756
3757 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3758 __func__));
3759
3760 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
3761 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
3762 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
3763 mpi_request.VF_ID = 0; /* TODO */
3764 mpi_request.VP_ID = 0;
3765 mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
3766 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
3767
3768 if (_base_is_controller_msix_enabled(ioc))
3769 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
3770 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
3771 mpi_request.ReplyDescriptorPostQueueDepth =
3772 cpu_to_le16(ioc->reply_post_queue_depth);
3773 mpi_request.ReplyFreeQueueDepth =
3774 cpu_to_le16(ioc->reply_free_queue_depth);
3775
3776 mpi_request.SenseBufferAddressHigh =
3777 cpu_to_le32((u64)ioc->sense_dma >> 32);
3778 mpi_request.SystemReplyAddressHigh =
3779 cpu_to_le32((u64)ioc->reply_dma >> 32);
3780 mpi_request.SystemRequestFrameBaseAddress =
3781 cpu_to_le64((u64)ioc->request_dma);
3782 mpi_request.ReplyFreeQueueAddress =
3783 cpu_to_le64((u64)ioc->reply_free_dma);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303784
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303785 if (ioc->rdpq_array_enable) {
3786 reply_post_free_array_sz = ioc->reply_queue_count *
3787 sizeof(Mpi2IOCInitRDPQArrayEntry);
3788 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
3789 reply_post_free_array_sz, &reply_post_free_array_dma);
3790 if (!reply_post_free_array) {
3791 pr_err(MPT3SAS_FMT
3792 "reply_post_free_array: pci_alloc_consistent failed\n",
3793 ioc->name);
3794 r = -ENOMEM;
3795 goto out;
3796 }
3797 memset(reply_post_free_array, 0, reply_post_free_array_sz);
3798 for (i = 0; i < ioc->reply_queue_count; i++)
3799 reply_post_free_array[i].RDPQBaseAddress =
3800 cpu_to_le64(
3801 (u64)ioc->reply_post[i].reply_post_free_dma);
3802 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
3803 mpi_request.ReplyDescriptorPostQueueAddress =
3804 cpu_to_le64((u64)reply_post_free_array_dma);
3805 } else {
3806 mpi_request.ReplyDescriptorPostQueueAddress =
3807 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
3808 }
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303809
3810 /* This time stamp specifies number of milliseconds
3811 * since epoch ~ midnight January 1, 1970.
3812 */
3813 do_gettimeofday(&current_time);
3814 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
3815 (current_time.tv_usec / 1000));
3816
3817 if (ioc->logging_level & MPT_DEBUG_INIT) {
3818 __le32 *mfp;
3819 int i;
3820
3821 mfp = (__le32 *)&mpi_request;
3822 pr_info("\toffset:data\n");
3823 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
3824 pr_info("\t[0x%02x]:%08x\n", i*4,
3825 le32_to_cpu(mfp[i]));
3826 }
3827
3828 r = _base_handshake_req_reply_wait(ioc,
3829 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
3830 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
3831 sleep_flag);
3832
3833 if (r != 0) {
3834 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3835 ioc->name, __func__, r);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303836 goto out;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303837 }
3838
3839 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
3840 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
3841 mpi_reply.IOCLogInfo) {
3842 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
3843 r = -EIO;
3844 }
3845
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05303846out:
3847 if (reply_post_free_array)
3848 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
3849 reply_post_free_array,
3850 reply_post_free_array_dma);
3851 return r;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05303852}
3853
3854/**
3855 * mpt3sas_port_enable_done - command completion routine for port enable
3856 * @ioc: per adapter object
3857 * @smid: system request message index
3858 * @msix_index: MSIX table index supplied by the OS
3859 * @reply: reply message frame(lower 32bit addr)
3860 *
3861 * Return 1 meaning mf should be freed from _base_interrupt
3862 * 0 means the mf is freed from this function.
3863 */
3864u8
3865mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
3866 u32 reply)
3867{
3868 MPI2DefaultReply_t *mpi_reply;
3869 u16 ioc_status;
3870
3871 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
3872 return 1;
3873
3874 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
3875 if (!mpi_reply)
3876 return 1;
3877
3878 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
3879 return 1;
3880
3881 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
3882 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
3883 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
3884 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
3885 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3886 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
3887 ioc->port_enable_failed = 1;
3888
3889 if (ioc->is_driver_loading) {
3890 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3891 mpt3sas_port_enable_complete(ioc);
3892 return 1;
3893 } else {
3894 ioc->start_scan_failed = ioc_status;
3895 ioc->start_scan = 0;
3896 return 1;
3897 }
3898 }
3899 complete(&ioc->port_enable_cmds.done);
3900 return 1;
3901}
3902
3903/**
3904 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
3905 * @ioc: per adapter object
3906 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3907 *
3908 * Returns 0 for success, non-zero for failure.
3909 */
3910static int
3911_base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3912{
3913 Mpi2PortEnableRequest_t *mpi_request;
3914 Mpi2PortEnableReply_t *mpi_reply;
3915 unsigned long timeleft;
3916 int r = 0;
3917 u16 smid;
3918 u16 ioc_status;
3919
3920 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
3921
3922 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
3923 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
3924 ioc->name, __func__);
3925 return -EAGAIN;
3926 }
3927
3928 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
3929 if (!smid) {
3930 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3931 ioc->name, __func__);
3932 return -EAGAIN;
3933 }
3934
3935 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
3936 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
3937 ioc->port_enable_cmds.smid = smid;
3938 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
3939 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
3940
3941 init_completion(&ioc->port_enable_cmds.done);
3942 mpt3sas_base_put_smid_default(ioc, smid);
3943 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
3944 300*HZ);
3945 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
3946 pr_err(MPT3SAS_FMT "%s: timeout\n",
3947 ioc->name, __func__);
3948 _debug_dump_mf(mpi_request,
3949 sizeof(Mpi2PortEnableRequest_t)/4);
3950 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
3951 r = -EFAULT;
3952 else
3953 r = -ETIME;
3954 goto out;
3955 }
3956
3957 mpi_reply = ioc->port_enable_cmds.reply;
3958 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
3959 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
3960 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
3961 ioc->name, __func__, ioc_status);
3962 r = -EFAULT;
3963 goto out;
3964 }
3965
3966 out:
3967 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
3968 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
3969 "SUCCESS" : "FAILED"));
3970 return r;
3971}
3972
3973/**
3974 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
3975 * @ioc: per adapter object
3976 *
3977 * Returns 0 for success, non-zero for failure.
3978 */
3979int
3980mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
3981{
3982 Mpi2PortEnableRequest_t *mpi_request;
3983 u16 smid;
3984
3985 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
3986
3987 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
3988 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
3989 ioc->name, __func__);
3990 return -EAGAIN;
3991 }
3992
3993 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
3994 if (!smid) {
3995 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3996 ioc->name, __func__);
3997 return -EAGAIN;
3998 }
3999
4000 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4001 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4002 ioc->port_enable_cmds.smid = smid;
4003 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4004 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4005
4006 mpt3sas_base_put_smid_default(ioc, smid);
4007 return 0;
4008}
4009
4010/**
4011 * _base_determine_wait_on_discovery - desposition
4012 * @ioc: per adapter object
4013 *
4014 * Decide whether to wait on discovery to complete. Used to either
4015 * locate boot device, or report volumes ahead of physical devices.
4016 *
4017 * Returns 1 for wait, 0 for don't wait
4018 */
4019static int
4020_base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4021{
4022 /* We wait for discovery to complete if IR firmware is loaded.
4023 * The sas topology events arrive before PD events, so we need time to
4024 * turn on the bit in ioc->pd_handles to indicate PD
4025 * Also, it maybe required to report Volumes ahead of physical
4026 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4027 */
4028 if (ioc->ir_firmware)
4029 return 1;
4030
4031 /* if no Bios, then we don't need to wait */
4032 if (!ioc->bios_pg3.BiosVersion)
4033 return 0;
4034
4035 /* Bios is present, then we drop down here.
4036 *
4037 * If there any entries in the Bios Page 2, then we wait
4038 * for discovery to complete.
4039 */
4040
4041 /* Current Boot Device */
4042 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4043 MPI2_BIOSPAGE2_FORM_MASK) ==
4044 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4045 /* Request Boot Device */
4046 (ioc->bios_pg2.ReqBootDeviceForm &
4047 MPI2_BIOSPAGE2_FORM_MASK) ==
4048 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4049 /* Alternate Request Boot Device */
4050 (ioc->bios_pg2.ReqAltBootDeviceForm &
4051 MPI2_BIOSPAGE2_FORM_MASK) ==
4052 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4053 return 0;
4054
4055 return 1;
4056}
4057
4058/**
4059 * _base_unmask_events - turn on notification for this event
4060 * @ioc: per adapter object
4061 * @event: firmware event
4062 *
4063 * The mask is stored in ioc->event_masks.
4064 */
4065static void
4066_base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4067{
4068 u32 desired_event;
4069
4070 if (event >= 128)
4071 return;
4072
4073 desired_event = (1 << (event % 32));
4074
4075 if (event < 32)
4076 ioc->event_masks[0] &= ~desired_event;
4077 else if (event < 64)
4078 ioc->event_masks[1] &= ~desired_event;
4079 else if (event < 96)
4080 ioc->event_masks[2] &= ~desired_event;
4081 else if (event < 128)
4082 ioc->event_masks[3] &= ~desired_event;
4083}
4084
4085/**
4086 * _base_event_notification - send event notification
4087 * @ioc: per adapter object
4088 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4089 *
4090 * Returns 0 for success, non-zero for failure.
4091 */
4092static int
4093_base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4094{
4095 Mpi2EventNotificationRequest_t *mpi_request;
4096 unsigned long timeleft;
4097 u16 smid;
4098 int r = 0;
4099 int i;
4100
4101 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4102 __func__));
4103
4104 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4105 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4106 ioc->name, __func__);
4107 return -EAGAIN;
4108 }
4109
4110 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4111 if (!smid) {
4112 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4113 ioc->name, __func__);
4114 return -EAGAIN;
4115 }
4116 ioc->base_cmds.status = MPT3_CMD_PENDING;
4117 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4118 ioc->base_cmds.smid = smid;
4119 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4120 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4121 mpi_request->VF_ID = 0; /* TODO */
4122 mpi_request->VP_ID = 0;
4123 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4124 mpi_request->EventMasks[i] =
4125 cpu_to_le32(ioc->event_masks[i]);
4126 init_completion(&ioc->base_cmds.done);
4127 mpt3sas_base_put_smid_default(ioc, smid);
4128 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4129 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4130 pr_err(MPT3SAS_FMT "%s: timeout\n",
4131 ioc->name, __func__);
4132 _debug_dump_mf(mpi_request,
4133 sizeof(Mpi2EventNotificationRequest_t)/4);
4134 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4135 r = -EFAULT;
4136 else
4137 r = -ETIME;
4138 } else
4139 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4140 ioc->name, __func__));
4141 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4142 return r;
4143}
4144
4145/**
4146 * mpt3sas_base_validate_event_type - validating event types
4147 * @ioc: per adapter object
4148 * @event: firmware event
4149 *
4150 * This will turn on firmware event notification when application
4151 * ask for that event. We don't mask events that are already enabled.
4152 */
4153void
4154mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4155{
4156 int i, j;
4157 u32 event_mask, desired_event;
4158 u8 send_update_to_fw;
4159
4160 for (i = 0, send_update_to_fw = 0; i <
4161 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4162 event_mask = ~event_type[i];
4163 desired_event = 1;
4164 for (j = 0; j < 32; j++) {
4165 if (!(event_mask & desired_event) &&
4166 (ioc->event_masks[i] & desired_event)) {
4167 ioc->event_masks[i] &= ~desired_event;
4168 send_update_to_fw = 1;
4169 }
4170 desired_event = (desired_event << 1);
4171 }
4172 }
4173
4174 if (!send_update_to_fw)
4175 return;
4176
4177 mutex_lock(&ioc->base_cmds.mutex);
4178 _base_event_notification(ioc, CAN_SLEEP);
4179 mutex_unlock(&ioc->base_cmds.mutex);
4180}
4181
4182/**
4183 * _base_diag_reset - the "big hammer" start of day reset
4184 * @ioc: per adapter object
4185 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4186 *
4187 * Returns 0 for success, non-zero for failure.
4188 */
4189static int
4190_base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4191{
4192 u32 host_diagnostic;
4193 u32 ioc_state;
4194 u32 count;
4195 u32 hcb_size;
4196
4197 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4198
4199 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4200 ioc->name));
4201
4202 count = 0;
4203 do {
4204 /* Write magic sequence to WriteSequence register
4205 * Loop until in diagnostic mode
4206 */
4207 drsprintk(ioc, pr_info(MPT3SAS_FMT
4208 "write magic sequence\n", ioc->name));
4209 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4210 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4211 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4212 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4213 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4214 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4215 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4216
4217 /* wait 100 msec */
4218 if (sleep_flag == CAN_SLEEP)
4219 msleep(100);
4220 else
4221 mdelay(100);
4222
4223 if (count++ > 20)
4224 goto out;
4225
4226 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4227 drsprintk(ioc, pr_info(MPT3SAS_FMT
4228 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4229 ioc->name, count, host_diagnostic));
4230
4231 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4232
4233 hcb_size = readl(&ioc->chip->HCBSize);
4234
4235 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4236 ioc->name));
4237 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4238 &ioc->chip->HostDiagnostic);
4239
Sreekanth Reddyb453ff82013-06-29 03:51:19 +05304240 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4241 if (sleep_flag == CAN_SLEEP)
4242 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4243 else
4244 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304245
Sreekanth Reddyb453ff82013-06-29 03:51:19 +05304246 /* Approximately 300 second max wait */
4247 for (count = 0; count < (300000000 /
4248 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304249
4250 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4251
4252 if (host_diagnostic == 0xFFFFFFFF)
4253 goto out;
4254 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4255 break;
4256
Sreekanth Reddyb453ff82013-06-29 03:51:19 +05304257 /* Wait to pass the second read delay window */
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304258 if (sleep_flag == CAN_SLEEP)
Sreekanth Reddyb453ff82013-06-29 03:51:19 +05304259 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4260 / 1000);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304261 else
Sreekanth Reddyb453ff82013-06-29 03:51:19 +05304262 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4263 / 1000);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304264 }
4265
4266 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4267
4268 drsprintk(ioc, pr_info(MPT3SAS_FMT
4269 "restart the adapter assuming the HCB Address points to good F/W\n",
4270 ioc->name));
4271 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4272 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4273 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4274
4275 drsprintk(ioc, pr_info(MPT3SAS_FMT
4276 "re-enable the HCDW\n", ioc->name));
4277 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4278 &ioc->chip->HCBSize);
4279 }
4280
4281 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4282 ioc->name));
4283 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4284 &ioc->chip->HostDiagnostic);
4285
4286 drsprintk(ioc, pr_info(MPT3SAS_FMT
4287 "disable writes to the diagnostic register\n", ioc->name));
4288 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4289
4290 drsprintk(ioc, pr_info(MPT3SAS_FMT
4291 "Wait for FW to go to the READY state\n", ioc->name));
4292 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4293 sleep_flag);
4294 if (ioc_state) {
4295 pr_err(MPT3SAS_FMT
4296 "%s: failed going to ready state (ioc_state=0x%x)\n",
4297 ioc->name, __func__, ioc_state);
4298 goto out;
4299 }
4300
4301 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4302 return 0;
4303
4304 out:
4305 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4306 return -EFAULT;
4307}
4308
4309/**
4310 * _base_make_ioc_ready - put controller in READY state
4311 * @ioc: per adapter object
4312 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4313 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4314 *
4315 * Returns 0 for success, non-zero for failure.
4316 */
4317static int
4318_base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4319 enum reset_type type)
4320{
4321 u32 ioc_state;
4322 int rc;
4323 int count;
4324
4325 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4326 __func__));
4327
4328 if (ioc->pci_error_recovery)
4329 return 0;
4330
4331 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4332 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4333 ioc->name, __func__, ioc_state));
4334
4335 /* if in RESET state, it should move to READY state shortly */
4336 count = 0;
4337 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4338 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4339 MPI2_IOC_STATE_READY) {
4340 if (count++ == 10) {
4341 pr_err(MPT3SAS_FMT
4342 "%s: failed going to ready state (ioc_state=0x%x)\n",
4343 ioc->name, __func__, ioc_state);
4344 return -EFAULT;
4345 }
4346 if (sleep_flag == CAN_SLEEP)
4347 ssleep(1);
4348 else
4349 mdelay(1000);
4350 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4351 }
4352 }
4353
4354 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4355 return 0;
4356
4357 if (ioc_state & MPI2_DOORBELL_USED) {
4358 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4359 "unexpected doorbell active!\n",
4360 ioc->name));
4361 goto issue_diag_reset;
4362 }
4363
4364 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4365 mpt3sas_base_fault_info(ioc, ioc_state &
4366 MPI2_DOORBELL_DATA_MASK);
4367 goto issue_diag_reset;
4368 }
4369
4370 if (type == FORCE_BIG_HAMMER)
4371 goto issue_diag_reset;
4372
4373 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4374 if (!(_base_send_ioc_reset(ioc,
4375 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4376 return 0;
4377 }
4378
4379 issue_diag_reset:
4380 rc = _base_diag_reset(ioc, CAN_SLEEP);
4381 return rc;
4382}
4383
4384/**
4385 * _base_make_ioc_operational - put controller in OPERATIONAL state
4386 * @ioc: per adapter object
4387 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4388 *
4389 * Returns 0 for success, non-zero for failure.
4390 */
4391static int
4392_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4393{
4394 int r, i;
4395 unsigned long flags;
4396 u32 reply_address;
4397 u16 smid;
4398 struct _tr_list *delayed_tr, *delayed_tr_next;
4399 struct adapter_reply_queue *reply_q;
4400 long reply_post_free;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05304401 u32 reply_post_free_sz, index = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304402
4403 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4404 __func__));
4405
4406 /* clean the delayed target reset list */
4407 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4408 &ioc->delayed_tr_list, list) {
4409 list_del(&delayed_tr->list);
4410 kfree(delayed_tr);
4411 }
4412
4413
4414 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4415 &ioc->delayed_tr_volume_list, list) {
4416 list_del(&delayed_tr->list);
4417 kfree(delayed_tr);
4418 }
4419
4420 /* initialize the scsi lookup free list */
4421 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4422 INIT_LIST_HEAD(&ioc->free_list);
4423 smid = 1;
4424 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4425 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4426 ioc->scsi_lookup[i].cb_idx = 0xFF;
4427 ioc->scsi_lookup[i].smid = smid;
4428 ioc->scsi_lookup[i].scmd = NULL;
4429 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4430 &ioc->free_list);
4431 }
4432
4433 /* hi-priority queue */
4434 INIT_LIST_HEAD(&ioc->hpr_free_list);
4435 smid = ioc->hi_priority_smid;
4436 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4437 ioc->hpr_lookup[i].cb_idx = 0xFF;
4438 ioc->hpr_lookup[i].smid = smid;
4439 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4440 &ioc->hpr_free_list);
4441 }
4442
4443 /* internal queue */
4444 INIT_LIST_HEAD(&ioc->internal_free_list);
4445 smid = ioc->internal_smid;
4446 for (i = 0; i < ioc->internal_depth; i++, smid++) {
4447 ioc->internal_lookup[i].cb_idx = 0xFF;
4448 ioc->internal_lookup[i].smid = smid;
4449 list_add_tail(&ioc->internal_lookup[i].tracker_list,
4450 &ioc->internal_free_list);
4451 }
4452
4453 /* chain pool */
4454 INIT_LIST_HEAD(&ioc->free_chain_list);
4455 for (i = 0; i < ioc->chain_depth; i++)
4456 list_add_tail(&ioc->chain_lookup[i].tracker_list,
4457 &ioc->free_chain_list);
4458
4459 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4460
4461 /* initialize Reply Free Queue */
4462 for (i = 0, reply_address = (u32)ioc->reply_dma ;
4463 i < ioc->reply_free_queue_depth ; i++, reply_address +=
4464 ioc->reply_sz)
4465 ioc->reply_free[i] = cpu_to_le32(reply_address);
4466
4467 /* initialize reply queues */
4468 if (ioc->is_driver_loading)
4469 _base_assign_reply_queues(ioc);
4470
4471 /* initialize Reply Post Free Queue */
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304472 reply_post_free_sz = ioc->reply_post_queue_depth *
4473 sizeof(Mpi2DefaultReplyDescriptor_t);
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05304474 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304475 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4476 reply_q->reply_post_host_index = 0;
4477 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4478 reply_post_free;
4479 for (i = 0; i < ioc->reply_post_queue_depth; i++)
4480 reply_q->reply_post_free[i].Words =
4481 cpu_to_le64(ULLONG_MAX);
4482 if (!_base_is_controller_msix_enabled(ioc))
4483 goto skip_init_reply_post_free_queue;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05304484 /*
4485 * If RDPQ is enabled, switch to the next allocation.
4486 * Otherwise advance within the contiguous region.
4487 */
4488 if (ioc->rdpq_array_enable)
4489 reply_post_free = (long)
4490 ioc->reply_post[++index].reply_post_free;
4491 else
4492 reply_post_free += reply_post_free_sz;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304493 }
4494 skip_init_reply_post_free_queue:
4495
4496 r = _base_send_ioc_init(ioc, sleep_flag);
4497 if (r)
4498 return r;
4499
4500 /* initialize reply free host index */
4501 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4502 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4503
4504 /* initialize reply post host index */
4505 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4506 writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT,
4507 &ioc->chip->ReplyPostHostIndex);
4508 if (!_base_is_controller_msix_enabled(ioc))
4509 goto skip_init_reply_post_host_index;
4510 }
4511
4512 skip_init_reply_post_host_index:
4513
4514 _base_unmask_interrupts(ioc);
4515 r = _base_event_notification(ioc, sleep_flag);
4516 if (r)
4517 return r;
4518
4519 if (sleep_flag == CAN_SLEEP)
4520 _base_static_config_pages(ioc);
4521
4522
4523 if (ioc->is_driver_loading) {
4524 ioc->wait_for_discovery_to_complete =
4525 _base_determine_wait_on_discovery(ioc);
4526
4527 return r; /* scan_start and scan_finished support */
4528 }
4529
4530 r = _base_send_port_enable(ioc, sleep_flag);
4531 if (r)
4532 return r;
4533
4534 return r;
4535}
4536
4537/**
4538 * mpt3sas_base_free_resources - free resources controller resources
4539 * @ioc: per adapter object
4540 *
4541 * Return nothing.
4542 */
4543void
4544mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
4545{
4546 struct pci_dev *pdev = ioc->pdev;
4547
4548 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4549 __func__));
4550
Joe Lawrencecf9bd21a2013-08-08 16:45:39 -04004551 if (ioc->chip_phys && ioc->chip) {
4552 _base_mask_interrupts(ioc);
4553 ioc->shost_recovery = 1;
4554 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4555 ioc->shost_recovery = 0;
4556 }
4557
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304558 _base_free_irq(ioc);
4559 _base_disable_msix(ioc);
Joe Lawrencecf9bd21a2013-08-08 16:45:39 -04004560
4561 if (ioc->chip_phys && ioc->chip)
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304562 iounmap(ioc->chip);
4563 ioc->chip_phys = 0;
Joe Lawrencecf9bd21a2013-08-08 16:45:39 -04004564
4565 if (pci_is_enabled(pdev)) {
4566 pci_release_selected_regions(ioc->pdev, ioc->bars);
4567 pci_disable_pcie_error_reporting(pdev);
4568 pci_disable_device(pdev);
4569 }
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304570 return;
4571}
4572
4573/**
4574 * mpt3sas_base_attach - attach controller instance
4575 * @ioc: per adapter object
4576 *
4577 * Returns 0 for success, non-zero for failure.
4578 */
4579int
4580mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
4581{
4582 int r, i;
4583 int cpu_id, last_cpu_id = 0;
4584
4585 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4586 __func__));
4587
4588 /* setup cpu_msix_table */
4589 ioc->cpu_count = num_online_cpus();
4590 for_each_online_cpu(cpu_id)
4591 last_cpu_id = cpu_id;
4592 ioc->cpu_msix_table_sz = last_cpu_id + 1;
4593 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
4594 ioc->reply_queue_count = 1;
4595 if (!ioc->cpu_msix_table) {
4596 dfailprintk(ioc, pr_info(MPT3SAS_FMT
4597 "allocation for cpu_msix_table failed!!!\n",
4598 ioc->name));
4599 r = -ENOMEM;
4600 goto out_free_resources;
4601 }
4602
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05304603 ioc->rdpq_array_enable_assigned = 0;
4604 ioc->dma_mask = 0;
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304605 r = mpt3sas_base_map_resources(ioc);
4606 if (r)
4607 goto out_free_resources;
4608
4609
4610 pci_set_drvdata(ioc->pdev, ioc->shost);
4611 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4612 if (r)
4613 goto out_free_resources;
4614
4615 /*
4616 * In SAS3.0,
4617 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
4618 * Target Status - all require the IEEE formated scatter gather
4619 * elements.
4620 */
4621
4622 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
4623 ioc->build_sg = &_base_build_sg_ieee;
4624 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
4625 ioc->mpi25 = 1;
4626 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
4627
4628 /*
4629 * These function pointers for other requests that don't
4630 * the require IEEE scatter gather elements.
4631 *
4632 * For example Configuration Pages and SAS IOUNIT Control don't.
4633 */
4634 ioc->build_sg_mpi = &_base_build_sg;
4635 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
4636
4637 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4638 if (r)
4639 goto out_free_resources;
4640
4641 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
4642 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
4643 if (!ioc->pfacts) {
4644 r = -ENOMEM;
4645 goto out_free_resources;
4646 }
4647
4648 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
4649 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
4650 if (r)
4651 goto out_free_resources;
4652 }
4653
4654 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
4655 if (r)
4656 goto out_free_resources;
4657
4658 init_waitqueue_head(&ioc->reset_wq);
4659
4660 /* allocate memory pd handle bitmask list */
4661 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
4662 if (ioc->facts.MaxDevHandle % 8)
4663 ioc->pd_handles_sz++;
4664 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
4665 GFP_KERNEL);
4666 if (!ioc->pd_handles) {
4667 r = -ENOMEM;
4668 goto out_free_resources;
4669 }
4670 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
4671 GFP_KERNEL);
4672 if (!ioc->blocking_handles) {
4673 r = -ENOMEM;
4674 goto out_free_resources;
4675 }
4676
4677 ioc->fwfault_debug = mpt3sas_fwfault_debug;
4678
4679 /* base internal command bits */
4680 mutex_init(&ioc->base_cmds.mutex);
4681 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4682 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4683
4684 /* port_enable command bits */
4685 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4686 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4687
4688 /* transport internal command bits */
4689 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4690 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
4691 mutex_init(&ioc->transport_cmds.mutex);
4692
4693 /* scsih internal command bits */
4694 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4695 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
4696 mutex_init(&ioc->scsih_cmds.mutex);
4697
4698 /* task management internal command bits */
4699 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4700 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
4701 mutex_init(&ioc->tm_cmds.mutex);
4702
4703 /* config page internal command bits */
4704 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4705 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
4706 mutex_init(&ioc->config_cmds.mutex);
4707
4708 /* ctl module internal command bits */
4709 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4710 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4711 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
4712 mutex_init(&ioc->ctl_cmds.mutex);
4713
4714 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4715 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4716 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
4717 !ioc->ctl_cmds.sense) {
4718 r = -ENOMEM;
4719 goto out_free_resources;
4720 }
4721
4722 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4723 ioc->event_masks[i] = -1;
4724
4725 /* here we enable the events we care about */
4726 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
4727 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
4728 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4729 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
4730 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
4731 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
4732 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
4733 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
4734 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
4735 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
Sreekanth Reddy2d8ce8c2015-01-12 11:38:56 +05304736 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304737
4738 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
4739 if (r)
4740 goto out_free_resources;
4741
4742 return 0;
4743
4744 out_free_resources:
4745
4746 ioc->remove_host = 1;
4747
4748 mpt3sas_base_free_resources(ioc);
4749 _base_release_memory_pools(ioc);
4750 pci_set_drvdata(ioc->pdev, NULL);
4751 kfree(ioc->cpu_msix_table);
4752 kfree(ioc->pd_handles);
4753 kfree(ioc->blocking_handles);
4754 kfree(ioc->tm_cmds.reply);
4755 kfree(ioc->transport_cmds.reply);
4756 kfree(ioc->scsih_cmds.reply);
4757 kfree(ioc->config_cmds.reply);
4758 kfree(ioc->base_cmds.reply);
4759 kfree(ioc->port_enable_cmds.reply);
4760 kfree(ioc->ctl_cmds.reply);
4761 kfree(ioc->ctl_cmds.sense);
4762 kfree(ioc->pfacts);
4763 ioc->ctl_cmds.reply = NULL;
4764 ioc->base_cmds.reply = NULL;
4765 ioc->tm_cmds.reply = NULL;
4766 ioc->scsih_cmds.reply = NULL;
4767 ioc->transport_cmds.reply = NULL;
4768 ioc->config_cmds.reply = NULL;
4769 ioc->pfacts = NULL;
4770 return r;
4771}
4772
4773
4774/**
4775 * mpt3sas_base_detach - remove controller instance
4776 * @ioc: per adapter object
4777 *
4778 * Return nothing.
4779 */
4780void
4781mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
4782{
4783 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4784 __func__));
4785
4786 mpt3sas_base_stop_watchdog(ioc);
4787 mpt3sas_base_free_resources(ioc);
4788 _base_release_memory_pools(ioc);
4789 pci_set_drvdata(ioc->pdev, NULL);
4790 kfree(ioc->cpu_msix_table);
4791 kfree(ioc->pd_handles);
4792 kfree(ioc->blocking_handles);
4793 kfree(ioc->pfacts);
4794 kfree(ioc->ctl_cmds.reply);
4795 kfree(ioc->ctl_cmds.sense);
4796 kfree(ioc->base_cmds.reply);
4797 kfree(ioc->port_enable_cmds.reply);
4798 kfree(ioc->tm_cmds.reply);
4799 kfree(ioc->transport_cmds.reply);
4800 kfree(ioc->scsih_cmds.reply);
4801 kfree(ioc->config_cmds.reply);
4802}
4803
4804/**
4805 * _base_reset_handler - reset callback handler (for base)
4806 * @ioc: per adapter object
4807 * @reset_phase: phase
4808 *
4809 * The handler for doing any required cleanup or initialization.
4810 *
4811 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
4812 * MPT3_IOC_DONE_RESET
4813 *
4814 * Return nothing.
4815 */
4816static void
4817_base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
4818{
4819 mpt3sas_scsih_reset_handler(ioc, reset_phase);
4820 mpt3sas_ctl_reset_handler(ioc, reset_phase);
4821 switch (reset_phase) {
4822 case MPT3_IOC_PRE_RESET:
4823 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4824 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
4825 break;
4826 case MPT3_IOC_AFTER_RESET:
4827 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4828 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
4829 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
4830 ioc->transport_cmds.status |= MPT3_CMD_RESET;
4831 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
4832 complete(&ioc->transport_cmds.done);
4833 }
4834 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4835 ioc->base_cmds.status |= MPT3_CMD_RESET;
4836 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
4837 complete(&ioc->base_cmds.done);
4838 }
4839 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4840 ioc->port_enable_failed = 1;
4841 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
4842 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
4843 if (ioc->is_driver_loading) {
4844 ioc->start_scan_failed =
4845 MPI2_IOCSTATUS_INTERNAL_ERROR;
4846 ioc->start_scan = 0;
4847 ioc->port_enable_cmds.status =
4848 MPT3_CMD_NOT_USED;
4849 } else
4850 complete(&ioc->port_enable_cmds.done);
4851 }
4852 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
4853 ioc->config_cmds.status |= MPT3_CMD_RESET;
4854 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
4855 ioc->config_cmds.smid = USHRT_MAX;
4856 complete(&ioc->config_cmds.done);
4857 }
4858 break;
4859 case MPT3_IOC_DONE_RESET:
4860 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4861 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
4862 break;
4863 }
4864}
4865
4866/**
4867 * _wait_for_commands_to_complete - reset controller
4868 * @ioc: Pointer to MPT_ADAPTER structure
4869 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4870 *
4871 * This function waiting(3s) for all pending commands to complete
4872 * prior to putting controller in reset.
4873 */
4874static void
4875_wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4876{
4877 u32 ioc_state;
4878 unsigned long flags;
4879 u16 i;
4880
4881 ioc->pending_io_count = 0;
4882 if (sleep_flag != CAN_SLEEP)
4883 return;
4884
4885 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4886 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
4887 return;
4888
4889 /* pending command count */
4890 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4891 for (i = 0; i < ioc->scsiio_depth; i++)
4892 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
4893 ioc->pending_io_count++;
4894 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4895
4896 if (!ioc->pending_io_count)
4897 return;
4898
4899 /* wait for pending commands to complete */
4900 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
4901}
4902
4903/**
4904 * mpt3sas_base_hard_reset_handler - reset controller
4905 * @ioc: Pointer to MPT_ADAPTER structure
4906 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4907 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4908 *
4909 * Returns 0 for success, non-zero for failure.
4910 */
4911int
4912mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4913 enum reset_type type)
4914{
4915 int r;
4916 unsigned long flags;
4917 u32 ioc_state;
4918 u8 is_fault = 0, is_trigger = 0;
4919
4920 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
4921 __func__));
4922
4923 if (ioc->pci_error_recovery) {
4924 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
4925 ioc->name, __func__);
4926 r = 0;
4927 goto out_unlocked;
4928 }
4929
4930 if (mpt3sas_fwfault_debug)
4931 mpt3sas_halt_firmware(ioc);
4932
4933 /* TODO - What we really should be doing is pulling
4934 * out all the code associated with NO_SLEEP; its never used.
4935 * That is legacy code from mpt fusion driver, ported over.
4936 * I will leave this BUG_ON here for now till its been resolved.
4937 */
4938 BUG_ON(sleep_flag == NO_SLEEP);
4939
4940 /* wait for an active reset in progress to complete */
4941 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
4942 do {
4943 ssleep(1);
4944 } while (ioc->shost_recovery == 1);
4945 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
4946 __func__));
4947 return ioc->ioc_reset_in_progress_status;
4948 }
4949
4950 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
4951 ioc->shost_recovery = 1;
4952 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
4953
4954 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
4955 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
4956 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
4957 MPT3_DIAG_BUFFER_IS_RELEASED))) {
4958 is_trigger = 1;
4959 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4960 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
4961 is_fault = 1;
4962 }
4963 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
4964 _wait_for_commands_to_complete(ioc, sleep_flag);
4965 _base_mask_interrupts(ioc);
4966 r = _base_make_ioc_ready(ioc, sleep_flag, type);
4967 if (r)
4968 goto out;
4969 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
4970
4971 /* If this hard reset is called while port enable is active, then
4972 * there is no reason to call make_ioc_operational
4973 */
4974 if (ioc->is_driver_loading && ioc->port_enable_failed) {
4975 ioc->remove_host = 1;
4976 r = -EFAULT;
4977 goto out;
4978 }
4979 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4980 if (r)
4981 goto out;
Sreekanth Reddy9b05c912014-09-12 15:35:31 +05304982
4983 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
4984 panic("%s: Issue occurred with flashing controller firmware."
4985 "Please reboot the system and ensure that the correct"
4986 " firmware version is running\n", ioc->name);
4987
Sreekanth Reddyf92363d2012-11-30 07:44:21 +05304988 r = _base_make_ioc_operational(ioc, sleep_flag);
4989 if (!r)
4990 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
4991
4992 out:
4993 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
4994 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
4995
4996 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
4997 ioc->ioc_reset_in_progress_status = r;
4998 ioc->shost_recovery = 0;
4999 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5000 ioc->ioc_reset_count++;
5001 mutex_unlock(&ioc->reset_in_progress_mutex);
5002
5003 out_unlocked:
5004 if ((r == 0) && is_trigger) {
5005 if (is_fault)
5006 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5007 else
5008 mpt3sas_trigger_master(ioc,
5009 MASTER_TRIGGER_ADAPTER_RESET);
5010 }
5011 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5012 __func__));
5013 return r;
5014}