blob: ff44082a0827d60ff14a00e40001d5900adc8e92 [file] [log] [blame]
Changhwan Youn30d8bea2011-03-11 10:39:57 +09001/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
Stephen Boydee98d272013-02-15 16:40:51 -080019#include <linux/cpu.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090020#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
Kukjin Kim2edb36c2012-11-15 15:48:56 +090023#include <linux/of.h>
Thomas Abraham36ba5d52013-03-09 16:01:52 +090024#include <linux/of_irq.h>
25#include <linux/of_address.h>
Thomas Abraham9fbf0c82013-03-09 16:10:03 +090026#include <linux/clocksource.h>
Vincent Guittot93bfb762014-05-02 22:27:01 +090027#include <linux/sched_clock.h>
Changhwan Youn30d8bea2011-03-11 10:39:57 +090028
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090029#define EXYNOS4_MCTREG(x) (x)
30#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
31#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
32#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
33#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
34#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
35#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
36#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
37#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
38#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
39#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
40#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
41#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
42#define EXYNOS4_MCT_L_MASK (0xffffff00)
43
44#define MCT_L_TCNTB_OFFSET (0x00)
45#define MCT_L_ICNTB_OFFSET (0x08)
46#define MCT_L_TCON_OFFSET (0x20)
47#define MCT_L_INT_CSTAT_OFFSET (0x30)
48#define MCT_L_INT_ENB_OFFSET (0x34)
49#define MCT_L_WSTAT_OFFSET (0x40)
50#define MCT_G_TCON_START (1 << 8)
51#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
52#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
53#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
54#define MCT_L_TCON_INT_START (1 << 1)
55#define MCT_L_TCON_TIMER_START (1 << 0)
56
Changhwan Youn4d2e4d72012-03-09 15:09:21 -080057#define TICK_BASE_CNT 1
58
Changhwan Youn3a062282011-10-04 17:02:58 +090059enum {
60 MCT_INT_SPI,
61 MCT_INT_PPI
62};
63
Thomas Abrahamc371dc62013-03-09 16:01:50 +090064enum {
65 MCT_G0_IRQ,
66 MCT_G1_IRQ,
67 MCT_G2_IRQ,
68 MCT_G3_IRQ,
69 MCT_L0_IRQ,
70 MCT_L1_IRQ,
71 MCT_L2_IRQ,
72 MCT_L3_IRQ,
Chander Kashyap6c16ded2013-12-02 07:48:23 +090073 MCT_L4_IRQ,
74 MCT_L5_IRQ,
75 MCT_L6_IRQ,
76 MCT_L7_IRQ,
Thomas Abrahamc371dc62013-03-09 16:01:50 +090077 MCT_NR_IRQS,
78};
79
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090080static void __iomem *reg_base;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090081static unsigned long clk_rate;
Changhwan Youn3a062282011-10-04 17:02:58 +090082static unsigned int mct_int_type;
Thomas Abrahamc371dc62013-03-09 16:01:50 +090083static int mct_irqs[MCT_NR_IRQS];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090084
85struct mct_clock_event_device {
Stephen Boydee98d272013-02-15 16:40:51 -080086 struct clock_event_device evt;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090087 unsigned long base;
Changhwan Younc8987472011-10-04 17:09:26 +090088 char name[10];
Changhwan Youn30d8bea2011-03-11 10:39:57 +090089};
90
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090091static void exynos4_mct_write(unsigned int value, unsigned long offset)
Changhwan Youn30d8bea2011-03-11 10:39:57 +090092{
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090093 unsigned long stat_addr;
Changhwan Youn30d8bea2011-03-11 10:39:57 +090094 u32 mask;
95 u32 i;
96
Doug Andersonfdb06f62014-07-05 06:43:20 +090097 writel_relaxed(value, reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +090098
Thomas Abrahama1ba7a72013-03-09 16:01:47 +090099 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
Tobias Jakobi8c38d282014-10-22 03:37:08 +0200100 stat_addr = (offset & EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101 switch (offset & ~EXYNOS4_MCT_L_MASK) {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900102 case MCT_L_TCON_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900103 mask = 1 << 3; /* L_TCON write status */
104 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900105 case MCT_L_ICNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900106 mask = 1 << 1; /* L_ICNTB write status */
107 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900108 case MCT_L_TCNTB_OFFSET:
Changhwan Younc8987472011-10-04 17:09:26 +0900109 mask = 1 << 0; /* L_TCNTB write status */
110 break;
111 default:
112 return;
113 }
114 } else {
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900115 switch (offset) {
116 case EXYNOS4_MCT_G_TCON:
Changhwan Younc8987472011-10-04 17:09:26 +0900117 stat_addr = EXYNOS4_MCT_G_WSTAT;
118 mask = 1 << 16; /* G_TCON write status */
119 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900120 case EXYNOS4_MCT_G_COMP0_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900121 stat_addr = EXYNOS4_MCT_G_WSTAT;
122 mask = 1 << 0; /* G_COMP0_L write status */
123 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900124 case EXYNOS4_MCT_G_COMP0_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900125 stat_addr = EXYNOS4_MCT_G_WSTAT;
126 mask = 1 << 1; /* G_COMP0_U write status */
127 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900128 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
Changhwan Younc8987472011-10-04 17:09:26 +0900129 stat_addr = EXYNOS4_MCT_G_WSTAT;
130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
131 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900132 case EXYNOS4_MCT_G_CNT_L:
Changhwan Younc8987472011-10-04 17:09:26 +0900133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134 mask = 1 << 0; /* G_CNT_L write status */
135 break;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900136 case EXYNOS4_MCT_G_CNT_U:
Changhwan Younc8987472011-10-04 17:09:26 +0900137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138 mask = 1 << 1; /* G_CNT_U write status */
139 break;
140 default:
141 return;
142 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900143 }
144
145 /* Wait maximum 1 ms until written values are applied */
146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
Doug Andersonfdb06f62014-07-05 06:43:20 +0900147 if (readl_relaxed(reg_base + stat_addr) & mask) {
148 writel_relaxed(mask, reg_base + stat_addr);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900149 return;
150 }
151
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900153}
154
155/* Clocksource handling */
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900156static void exynos4_mct_frc_start(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900157{
158 u32 reg;
159
Doug Andersonfdb06f62014-07-05 06:43:20 +0900160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163}
164
Doug Anderson3252a642014-07-05 06:43:26 +0900165/**
166 * exynos4_read_count_64 - Read all 64-bits of the global counter
167 *
168 * This will read all 64-bits of the global counter taking care to make sure
169 * that the upper and lower half match. Note that reading the MCT can be quite
170 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
171 * only) version when possible.
172 *
173 * Returns the number of cycles in the global counter.
174 */
175static u64 exynos4_read_count_64(void)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900176{
177 unsigned int lo, hi;
Doug Andersonfdb06f62014-07-05 06:43:20 +0900178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900179
180 do {
181 hi = hi2;
Doug Andersonfdb06f62014-07-05 06:43:20 +0900182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900184 } while (hi != hi2);
185
186 return ((cycle_t)hi << 32) | lo;
187}
188
Doug Anderson3252a642014-07-05 06:43:26 +0900189/**
190 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
191 *
192 * This will read just the lower 32-bits of the global counter. This is marked
193 * as notrace so it can be used by the scheduler clock.
194 *
195 * Returns the number of cycles in the global counter (lower 32 bits).
196 */
197static u32 notrace exynos4_read_count_32(void)
198{
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
200}
201
Doug Anderson89e6a132014-07-05 06:38:55 +0900202static cycle_t exynos4_frc_read(struct clocksource *cs)
203{
Doug Anderson3252a642014-07-05 06:43:26 +0900204 return exynos4_read_count_32();
Doug Anderson89e6a132014-07-05 06:38:55 +0900205}
206
Changhwan Younaa421c12011-09-02 14:10:52 +0900207static void exynos4_frc_resume(struct clocksource *cs)
208{
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900209 exynos4_mct_frc_start();
Changhwan Younaa421c12011-09-02 14:10:52 +0900210}
211
Krzysztof Kozlowski6c10bf62015-04-30 13:42:52 +0900212static struct clocksource mct_frc = {
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900213 .name = "mct-frc",
214 .rating = 400,
215 .read = exynos4_frc_read,
Doug Anderson3252a642014-07-05 06:43:26 +0900216 .mask = CLOCKSOURCE_MASK(32),
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900217 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Changhwan Younaa421c12011-09-02 14:10:52 +0900218 .resume = exynos4_frc_resume,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900219};
220
Vincent Guittot93bfb762014-05-02 22:27:01 +0900221static u64 notrace exynos4_read_sched_clock(void)
222{
Doug Anderson3252a642014-07-05 06:43:26 +0900223 return exynos4_read_count_32();
Vincent Guittot93bfb762014-05-02 22:27:01 +0900224}
225
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900226static struct delay_timer exynos4_delay_timer;
227
228static cycles_t exynos4_read_current_timer(void)
229{
Doug Anderson3252a642014-07-05 06:43:26 +0900230 BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
231 "cycles_t needs to move to 32-bit for ARM64 usage");
232 return exynos4_read_count_32();
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900233}
234
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900235static void __init exynos4_clocksource_init(void)
236{
Chirantan Ekbote1d804152014-06-12 00:18:48 +0900237 exynos4_mct_frc_start();
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900238
Amit Daniel Kachhap8bf13a42014-07-05 06:40:23 +0900239 exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
240 exynos4_delay_timer.freq = clk_rate;
241 register_current_timer_delay(&exynos4_delay_timer);
242
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900243 if (clocksource_register_hz(&mct_frc, clk_rate))
244 panic("%s: can't register clocksource\n", mct_frc.name);
Vincent Guittot93bfb762014-05-02 22:27:01 +0900245
Doug Anderson3252a642014-07-05 06:43:26 +0900246 sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900247}
248
249static void exynos4_mct_comp0_stop(void)
250{
251 unsigned int tcon;
252
Doug Andersonfdb06f62014-07-05 06:43:20 +0900253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900254 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
255
256 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
257 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
258}
259
Viresh Kumar79e436d2015-06-18 16:24:20 +0530260static void exynos4_mct_comp0_start(bool periodic, unsigned long cycles)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900261{
262 unsigned int tcon;
263 cycle_t comp_cycle;
264
Doug Andersonfdb06f62014-07-05 06:43:20 +0900265 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900266
Viresh Kumar79e436d2015-06-18 16:24:20 +0530267 if (periodic) {
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900268 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
269 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
270 }
271
Doug Anderson3252a642014-07-05 06:43:26 +0900272 comp_cycle = exynos4_read_count_64() + cycles;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900273 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
274 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
275
276 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
277
278 tcon |= MCT_G_TCON_COMP0_ENABLE;
279 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
280}
281
282static int exynos4_comp_set_next_event(unsigned long cycles,
283 struct clock_event_device *evt)
284{
Viresh Kumar79e436d2015-06-18 16:24:20 +0530285 exynos4_mct_comp0_start(false, cycles);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900286
287 return 0;
288}
289
Viresh Kumar79e436d2015-06-18 16:24:20 +0530290static int mct_set_state_shutdown(struct clock_event_device *evt)
291{
292 exynos4_mct_comp0_stop();
293 return 0;
294}
295
296static int mct_set_state_periodic(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900297{
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800298 unsigned long cycles_per_jiffy;
Viresh Kumar79e436d2015-06-18 16:24:20 +0530299
300 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
301 >> evt->shift);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900302 exynos4_mct_comp0_stop();
Viresh Kumar79e436d2015-06-18 16:24:20 +0530303 exynos4_mct_comp0_start(true, cycles_per_jiffy);
304 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900305}
306
307static struct clock_event_device mct_comp_device = {
Viresh Kumar79e436d2015-06-18 16:24:20 +0530308 .name = "mct-comp",
309 .features = CLOCK_EVT_FEAT_PERIODIC |
310 CLOCK_EVT_FEAT_ONESHOT,
311 .rating = 250,
312 .set_next_event = exynos4_comp_set_next_event,
313 .set_state_periodic = mct_set_state_periodic,
314 .set_state_shutdown = mct_set_state_shutdown,
315 .set_state_oneshot = mct_set_state_shutdown,
316 .tick_resume = mct_set_state_shutdown,
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900317};
318
319static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
320{
321 struct clock_event_device *evt = dev_id;
322
323 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
324
325 evt->event_handler(evt);
326
327 return IRQ_HANDLED;
328}
329
330static struct irqaction mct_comp_event_irq = {
331 .name = "mct_comp_irq",
332 .flags = IRQF_TIMER | IRQF_IRQPOLL,
333 .handler = exynos4_mct_comp_isr,
334 .dev_id = &mct_comp_device,
335};
336
337static void exynos4_clockevent_init(void)
338{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900339 mct_comp_device.cpumask = cpumask_of(0);
Shawn Guo838a2ae2013-01-12 11:50:05 +0000340 clockevents_config_and_register(&mct_comp_device, clk_rate,
341 0xf, 0xffffffff);
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900342 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900343}
344
Kukjin Kim991a6c72011-12-08 10:04:49 +0900345static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
346
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900347/* Clock event handling */
348static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
349{
350 unsigned long tmp;
351 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900352 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900353
Doug Andersonfdb06f62014-07-05 06:43:20 +0900354 tmp = readl_relaxed(reg_base + offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900355 if (tmp & mask) {
356 tmp &= ~mask;
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900357 exynos4_mct_write(tmp, offset);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900358 }
359}
360
361static void exynos4_mct_tick_start(unsigned long cycles,
362 struct mct_clock_event_device *mevt)
363{
364 unsigned long tmp;
365
366 exynos4_mct_tick_stop(mevt);
367
368 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
369
370 /* update interrupt count buffer */
371 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
372
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300373 /* enable MCT tick interrupt */
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900374 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
375
Doug Andersonfdb06f62014-07-05 06:43:20 +0900376 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900377 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
378 MCT_L_TCON_INTERVAL_MODE;
379 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
380}
381
382static int exynos4_tick_set_next_event(unsigned long cycles,
383 struct clock_event_device *evt)
384{
Alexey Klimov31f79872015-09-04 02:49:58 +0300385 struct mct_clock_event_device *mevt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900386
Alexey Klimov31f79872015-09-04 02:49:58 +0300387 mevt = container_of(evt, struct mct_clock_event_device, evt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900388 exynos4_mct_tick_start(cycles, mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900389 return 0;
390}
391
Viresh Kumar79e436d2015-06-18 16:24:20 +0530392static int set_state_shutdown(struct clock_event_device *evt)
393{
Alexey Klimov31f79872015-09-04 02:49:58 +0300394 struct mct_clock_event_device *mevt;
395
396 mevt = container_of(evt, struct mct_clock_event_device, evt);
397 exynos4_mct_tick_stop(mevt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530398 return 0;
399}
400
401static int set_state_periodic(struct clock_event_device *evt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900402{
Alexey Klimov31f79872015-09-04 02:49:58 +0300403 struct mct_clock_event_device *mevt;
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800404 unsigned long cycles_per_jiffy;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900405
Alexey Klimov31f79872015-09-04 02:49:58 +0300406 mevt = container_of(evt, struct mct_clock_event_device, evt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530407 cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)
408 >> evt->shift);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900409 exynos4_mct_tick_stop(mevt);
Viresh Kumar79e436d2015-06-18 16:24:20 +0530410 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
411 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900412}
413
Krzysztof Kozlowski37285672015-04-30 13:42:51 +0900414static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900415{
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900416 /*
417 * This is for supporting oneshot mode.
418 * Mct would generate interrupt periodically
419 * without explicit stopping.
420 */
Viresh Kumar79e436d2015-06-18 16:24:20 +0530421 if (!clockevent_state_periodic(&mevt->evt))
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900422 exynos4_mct_tick_stop(mevt);
423
424 /* Clear the MCT tick interrupt */
Krzysztof Kozlowski37285672015-04-30 13:42:51 +0900425 if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)
Changhwan Youn3a062282011-10-04 17:02:58 +0900426 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
Changhwan Youn3a062282011-10-04 17:02:58 +0900427}
428
429static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
430{
431 struct mct_clock_event_device *mevt = dev_id;
Stephen Boydee98d272013-02-15 16:40:51 -0800432 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn3a062282011-10-04 17:02:58 +0900433
434 exynos4_mct_tick_clear(mevt);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900435
436 evt->event_handler(evt);
437
438 return IRQ_HANDLED;
439}
440
Alexey Klimov479a9322015-06-21 23:41:39 +0300441static int exynos4_local_timer_setup(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900442{
Alexey Klimov479a9322015-06-21 23:41:39 +0300443 struct clock_event_device *evt = &mevt->evt;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900444 unsigned int cpu = smp_processor_id();
445
Marc Zyngiere700e412011-11-03 11:13:12 +0900446 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
Dan Carpenter09e15172014-03-01 16:57:14 +0300447 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900448
Marc Zyngiere700e412011-11-03 11:13:12 +0900449 evt->name = mevt->name;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900450 evt->cpumask = cpumask_of(cpu);
451 evt->set_next_event = exynos4_tick_set_next_event;
Viresh Kumar79e436d2015-06-18 16:24:20 +0530452 evt->set_state_periodic = set_state_periodic;
453 evt->set_state_shutdown = set_state_shutdown;
454 evt->set_state_oneshot = set_state_shutdown;
455 evt->tick_resume = set_state_shutdown;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900456 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
457 evt->rating = 450;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900458
Changhwan Youn4d2e4d72012-03-09 15:09:21 -0800459 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900460
Changhwan Youn3a062282011-10-04 17:02:58 +0900461 if (mct_int_type == MCT_INT_SPI) {
Damian Eppel56a94f12015-06-26 15:23:04 +0200462
463 if (evt->irq == -1)
Chander Kashyap7114cd72013-06-19 00:29:35 +0900464 return -EIO;
Damian Eppel56a94f12015-06-26 15:23:04 +0200465
466 irq_force_affinity(evt->irq, cpumask_of(cpu));
467 enable_irq(evt->irq);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900468 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900469 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900470 }
Krzysztof Kozlowski8db6e512014-04-16 14:36:45 +0000471 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
472 0xf, 0x7fffffff);
Kukjin Kim4d487d72011-08-24 16:07:39 +0900473
474 return 0;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900475}
476
Alexey Klimov479a9322015-06-21 23:41:39 +0300477static void exynos4_local_timer_stop(struct mct_clock_event_device *mevt)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900478{
Alexey Klimov479a9322015-06-21 23:41:39 +0300479 struct clock_event_device *evt = &mevt->evt;
480
Viresh Kumar79e436d2015-06-18 16:24:20 +0530481 evt->set_state_shutdown(evt);
Damian Eppel56a94f12015-06-26 15:23:04 +0200482 if (mct_int_type == MCT_INT_SPI) {
483 if (evt->irq != -1)
484 disable_irq_nosync(evt->irq);
485 } else {
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900486 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
Damian Eppel56a94f12015-06-26 15:23:04 +0200487 }
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900488}
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000489
Olof Johansson47dcd352013-07-23 14:51:34 -0700490static int exynos4_mct_cpu_notify(struct notifier_block *self,
Stephen Boydee98d272013-02-15 16:40:51 -0800491 unsigned long action, void *hcpu)
492{
493 struct mct_clock_event_device *mevt;
494
495 /*
496 * Grab cpu pointer in each case to avoid spurious
497 * preemptible warnings
498 */
499 switch (action & ~CPU_TASKS_FROZEN) {
500 case CPU_STARTING:
501 mevt = this_cpu_ptr(&percpu_mct_tick);
Alexey Klimov479a9322015-06-21 23:41:39 +0300502 exynos4_local_timer_setup(mevt);
Stephen Boydee98d272013-02-15 16:40:51 -0800503 break;
504 case CPU_DYING:
505 mevt = this_cpu_ptr(&percpu_mct_tick);
Alexey Klimov479a9322015-06-21 23:41:39 +0300506 exynos4_local_timer_stop(mevt);
Stephen Boydee98d272013-02-15 16:40:51 -0800507 break;
508 }
509
510 return NOTIFY_OK;
511}
512
Olof Johansson47dcd352013-07-23 14:51:34 -0700513static struct notifier_block exynos4_mct_cpu_nb = {
Stephen Boydee98d272013-02-15 16:40:51 -0800514 .notifier_call = exynos4_mct_cpu_notify,
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000515};
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900516
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200517static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900518{
Damian Eppel56a94f12015-06-26 15:23:04 +0200519 int err, cpu;
Stephen Boydee98d272013-02-15 16:40:51 -0800520 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900521 struct clk *mct_clk, *tick_clk;
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900522
Thomas Abraham415ac2e2013-03-09 17:10:31 +0900523 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
524 clk_get(NULL, "fin_pll");
525 if (IS_ERR(tick_clk))
526 panic("%s: unable to determine tick clock rate\n", __func__);
527 clk_rate = clk_get_rate(tick_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900528
Thomas Abrahamca9048e2013-03-09 17:10:37 +0900529 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
530 if (IS_ERR(mct_clk))
531 panic("%s: unable to retrieve mct clock instance\n", __func__);
532 clk_prepare_enable(mct_clk);
Marc Zyngiere700e412011-11-03 11:13:12 +0900533
Arnd Bergmann228e3022013-04-09 22:07:37 +0200534 reg_base = base;
Thomas Abraham36ba5d52013-03-09 16:01:52 +0900535 if (!reg_base)
536 panic("%s: unable to ioremap mct address space\n", __func__);
Thomas Abrahama1ba7a72013-03-09 16:01:47 +0900537
Marc Zyngiere700e412011-11-03 11:13:12 +0900538 if (mct_int_type == MCT_INT_PPI) {
Marc Zyngiere700e412011-11-03 11:13:12 +0900539
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900540 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
Marc Zyngiere700e412011-11-03 11:13:12 +0900541 exynos4_mct_tick_isr, "MCT",
542 &percpu_mct_tick);
543 WARN(err, "MCT: can't request IRQ %d (%d)\n",
Thomas Abrahamc371dc62013-03-09 16:01:50 +0900544 mct_irqs[MCT_L0_IRQ], err);
Tomasz Figa5df718d2013-09-25 12:00:59 +0200545 } else {
Damian Eppel56a94f12015-06-26 15:23:04 +0200546 for_each_possible_cpu(cpu) {
547 int mct_irq = mct_irqs[MCT_L0_IRQ + cpu];
548 struct mct_clock_event_device *pcpu_mevt =
549 per_cpu_ptr(&percpu_mct_tick, cpu);
550
551 pcpu_mevt->evt.irq = -1;
552
553 irq_set_status_flags(mct_irq, IRQ_NOAUTOEN);
554 if (request_irq(mct_irq,
555 exynos4_mct_tick_isr,
556 IRQF_TIMER | IRQF_NOBALANCING,
557 pcpu_mevt->name, pcpu_mevt)) {
558 pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",
559 cpu);
560
561 continue;
562 }
563 pcpu_mevt->evt.irq = mct_irq;
564 }
Marc Zyngiere700e412011-11-03 11:13:12 +0900565 }
Marc Zyngiera8cb6042012-01-10 19:44:19 +0000566
Stephen Boydee98d272013-02-15 16:40:51 -0800567 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
568 if (err)
569 goto out_irq;
570
571 /* Immediately configure the timer on the boot CPU */
Alexey Klimov479a9322015-06-21 23:41:39 +0300572 exynos4_local_timer_setup(mevt);
Stephen Boydee98d272013-02-15 16:40:51 -0800573 return;
574
575out_irq:
576 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
Changhwan Youn30d8bea2011-03-11 10:39:57 +0900577}
578
Arnd Bergmann228e3022013-04-09 22:07:37 +0200579static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
580{
581 u32 nr_irqs, i;
582
583 mct_int_type = int_type;
584
585 /* This driver uses only one global timer interrupt */
586 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
587
588 /*
589 * Find out the number of local irqs specified. The local
590 * timer irqs are specified after the four global timer
591 * irqs are specified.
592 */
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200593#ifdef CONFIG_OF
Arnd Bergmann228e3022013-04-09 22:07:37 +0200594 nr_irqs = of_irq_count(np);
Arnd Bergmannf4636d02013-04-19 22:00:04 +0200595#else
596 nr_irqs = 0;
597#endif
Arnd Bergmann228e3022013-04-09 22:07:37 +0200598 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
599 mct_irqs[i] = irq_of_parse_and_map(np, i);
600
Arnd Bergmann19ce4f42013-04-09 22:24:06 +0200601 exynos4_timer_resources(np, of_iomap(np, 0));
Arnd Bergmann228e3022013-04-09 22:07:37 +0200602 exynos4_clocksource_init();
603 exynos4_clockevent_init();
604}
605
606
607static void __init mct_init_spi(struct device_node *np)
608{
609 return mct_init_dt(np, MCT_INT_SPI);
610}
611
612static void __init mct_init_ppi(struct device_node *np)
613{
614 return mct_init_dt(np, MCT_INT_PPI);
615}
616CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
617CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);