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Catalin Marinas4f04d8f2012-03-05 11:49:27 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_PGTABLE_H
17#define __ASM_PGTABLE_H
18
19#include <asm/proc-fns.h>
20
21#include <asm/memory.h>
22#include <asm/pgtable-hwdef.h>
23
24/*
25 * Software defined PTE bits definition.
26 */
Will Deacona6fadf72012-12-18 14:15:15 +000027#define PTE_VALID (_AT(pteval_t, 1) << 0)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000028#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
29#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
Steve Capperc2c93e52014-01-15 14:07:13 +000030#define PTE_WRITE (_AT(pteval_t, 1) << 57)
Catalin Marinas3676f9e2013-11-27 16:59:27 +000031#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000032
33/*
34 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
Catalin Marinas08375192014-07-16 17:42:43 +010035 *
36 * VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
37 * (rounded up to PUD_SIZE).
38 * VMALLOC_START: beginning of the kernel VA space
39 * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
40 * fixed mappings and modules
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000041 */
Catalin Marinas08375192014-07-16 17:42:43 +010042#define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
Catalin Marinas847264fb2013-10-23 16:50:07 +010043#define VMALLOC_START (UL(0xffffffffffffffff) << VA_BITS)
Catalin Marinas08375192014-07-16 17:42:43 +010044#define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000045
46#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
47
Kirill A. Shutemovd016bf72015-02-11 15:26:41 -080048#define FIRST_USER_ADDRESS 0UL
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000049
50#ifndef __ASSEMBLY__
51extern void __pte_error(const char *file, int line, unsigned long val);
52extern void __pmd_error(const char *file, int line, unsigned long val);
Jungseok Leec79b9542014-05-12 18:40:51 +090053extern void __pud_error(const char *file, int line, unsigned long val);
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000054extern void __pgd_error(const char *file, int line, unsigned long val);
55
Catalin Marinasa501e322014-04-03 15:57:15 +010056#ifdef CONFIG_SMP
57#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
58#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
59#else
60#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF)
61#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF)
62#endif
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000063
Catalin Marinasa501e322014-04-03 15:57:15 +010064#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
65#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
66#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000067
Catalin Marinasa501e322014-04-03 15:57:15 +010068#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
69#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
70#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000071
Catalin Marinasa501e322014-04-03 15:57:15 +010072#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
Will Deacona6fadf72012-12-18 14:15:15 +000073
Catalin Marinasa501e322014-04-03 15:57:15 +010074#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
75#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000076
Catalin Marinasa501e322014-04-03 15:57:15 +010077#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
Marc Zyngier36311602012-12-07 18:35:41 +000078#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
79
Catalin Marinasa501e322014-04-03 15:57:15 +010080#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
Ard Biesheuvel4a513fb2014-09-17 14:56:20 -070081#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
Marc Zyngier36311602012-12-07 18:35:41 +000082
Catalin Marinasa501e322014-04-03 15:57:15 +010083#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
84#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
85#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
86#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
87#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
88#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
89#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000090
Catalin Marinasa501e322014-04-03 15:57:15 +010091#define __P000 PAGE_NONE
92#define __P001 PAGE_READONLY
93#define __P010 PAGE_COPY
94#define __P011 PAGE_COPY
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +010095#define __P100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +010096#define __P101 PAGE_READONLY_EXEC
97#define __P110 PAGE_COPY_EXEC
98#define __P111 PAGE_COPY_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +000099
Catalin Marinasa501e322014-04-03 15:57:15 +0100100#define __S000 PAGE_NONE
101#define __S001 PAGE_READONLY
102#define __S010 PAGE_SHARED
103#define __S011 PAGE_SHARED
Catalin Marinas5a0fdfa2014-05-16 16:44:32 +0100104#define __S100 PAGE_READONLY_EXEC
Catalin Marinasa501e322014-04-03 15:57:15 +0100105#define __S101 PAGE_READONLY_EXEC
106#define __S110 PAGE_SHARED_EXEC
107#define __S111 PAGE_SHARED_EXEC
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000108
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000109/*
110 * ZERO_PAGE is a global shared page that is always zero: used
111 * for zero-mapped memory areas etc..
112 */
113extern struct page *empty_zero_page;
114#define ZERO_PAGE(vaddr) (empty_zero_page)
115
Catalin Marinas7078db42014-07-21 14:52:49 +0100116#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
117
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000118#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
119
120#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
121
122#define pte_none(pte) (!pte_val(pte))
123#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
124#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
Catalin Marinas7078db42014-07-21 14:52:49 +0100125
126/* Find an entry in the third-level page table. */
127#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
128
Will Deacon9ab6d022013-06-10 19:34:41 +0100129#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000130
131#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
132#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
133#define pte_unmap(pte) do { } while (0)
134#define pte_unmap_nested(pte) do { } while (0)
135
136/*
137 * The following only work if pte_present(). Undefined behaviour otherwise.
138 */
Steve Capper84fe6822014-02-25 11:38:53 +0000139#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
140#define pte_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
141#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
142#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
143#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
Catalin Marinas8e620b02012-11-15 17:21:16 +0000144#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000145
Will Deacona6fadf72012-12-18 14:15:15 +0000146#define pte_valid_user(pte) \
Will Deacon02522462013-01-09 11:08:10 +0000147 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER))
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100148#define pte_valid_not_user(pte) \
149 ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000150
Laura Abbottb6d4f282014-08-19 20:41:42 +0100151static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
152{
153 pte_val(pte) &= ~pgprot_val(prot);
154 return pte;
155}
156
157static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
158{
159 pte_val(pte) |= pgprot_val(prot);
160 return pte;
161}
162
Steve Capper44b6dfc2014-01-15 14:07:12 +0000163static inline pte_t pte_wrprotect(pte_t pte)
164{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100165 return clear_pte_bit(pte, __pgprot(PTE_WRITE));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000166}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000167
Steve Capper44b6dfc2014-01-15 14:07:12 +0000168static inline pte_t pte_mkwrite(pte_t pte)
169{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100170 return set_pte_bit(pte, __pgprot(PTE_WRITE));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000171}
172
173static inline pte_t pte_mkclean(pte_t pte)
174{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100175 return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000176}
177
178static inline pte_t pte_mkdirty(pte_t pte)
179{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100180 return set_pte_bit(pte, __pgprot(PTE_DIRTY));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000181}
182
183static inline pte_t pte_mkold(pte_t pte)
184{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100185 return clear_pte_bit(pte, __pgprot(PTE_AF));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000186}
187
188static inline pte_t pte_mkyoung(pte_t pte)
189{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100190 return set_pte_bit(pte, __pgprot(PTE_AF));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000191}
192
193static inline pte_t pte_mkspecial(pte_t pte)
194{
Laura Abbottb6d4f282014-08-19 20:41:42 +0100195 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
Steve Capper44b6dfc2014-01-15 14:07:12 +0000196}
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000197
198static inline void set_pte(pte_t *ptep, pte_t pte)
199{
200 *ptep = pte;
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100201
202 /*
203 * Only if the new pte is valid and kernel, otherwise TLB maintenance
204 * or update_mmu_cache() have the necessary barriers.
205 */
206 if (pte_valid_not_user(pte)) {
207 dsb(ishst);
208 isb();
209 }
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000210}
211
212extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
213
214static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
215 pte_t *ptep, pte_t pte)
216{
Will Deacona6fadf72012-12-18 14:15:15 +0000217 if (pte_valid_user(pte)) {
Catalin Marinas71fdb6b2014-03-12 16:28:09 +0000218 if (!pte_special(pte) && pte_exec(pte))
Will Deacon02522462013-01-09 11:08:10 +0000219 __sync_icache_dcache(pte, addr);
Steve Capperc2c93e52014-01-15 14:07:13 +0000220 if (pte_dirty(pte) && pte_write(pte))
221 pte_val(pte) &= ~PTE_RDONLY;
222 else
223 pte_val(pte) |= PTE_RDONLY;
Will Deacon02522462013-01-09 11:08:10 +0000224 }
225
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000226 set_pte(ptep, pte);
227}
228
229/*
230 * Huge pte definitions.
231 */
Steve Capper084bd292013-04-10 13:48:00 +0100232#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
233#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
234
235/*
236 * Hugetlb definitions.
237 */
238#define HUGE_MAX_HSTATE 2
239#define HPAGE_SHIFT PMD_SHIFT
240#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
241#define HPAGE_MASK (~(HPAGE_SIZE - 1))
242#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000243
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000244#define __HAVE_ARCH_PTE_SPECIAL
245
Steve Capper29e56942014-10-09 15:29:25 -0700246static inline pte_t pud_pte(pud_t pud)
247{
248 return __pte(pud_val(pud));
249}
250
251static inline pmd_t pud_pmd(pud_t pud)
252{
253 return __pmd(pud_val(pud));
254}
255
Steve Capper9c7e5352014-02-25 10:02:13 +0000256static inline pte_t pmd_pte(pmd_t pmd)
257{
258 return __pte(pmd_val(pmd));
259}
Steve Capperaf074842013-04-19 16:23:57 +0100260
Steve Capper9c7e5352014-02-25 10:02:13 +0000261static inline pmd_t pte_pmd(pte_t pte)
262{
263 return __pmd(pte_val(pte));
264}
Steve Capperaf074842013-04-19 16:23:57 +0100265
Ard Biesheuvel8ce837c2014-10-20 15:42:07 +0200266static inline pgprot_t mk_sect_prot(pgprot_t prot)
267{
268 return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
269}
270
Steve Capperaf074842013-04-19 16:23:57 +0100271/*
272 * THP definitions.
273 */
Steve Capperaf074842013-04-19 16:23:57 +0100274
275#ifdef CONFIG_TRANSPARENT_HUGEPAGE
276#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
Steve Capper9c7e5352014-02-25 10:02:13 +0000277#define pmd_trans_splitting(pmd) pte_special(pmd_pte(pmd))
Steve Capper29e56942014-10-09 15:29:25 -0700278#ifdef CONFIG_HAVE_RCU_TABLE_FREE
279#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
280struct vm_area_struct;
281void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
282 pmd_t *pmdp);
283#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
284#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
Steve Capperaf074842013-04-19 16:23:57 +0100285
Kirill A. Shutemovc164e032014-12-10 15:44:36 -0800286#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
Steve Capper9c7e5352014-02-25 10:02:13 +0000287#define pmd_young(pmd) pte_young(pmd_pte(pmd))
288#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
289#define pmd_mksplitting(pmd) pte_pmd(pte_mkspecial(pmd_pte(pmd)))
290#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
291#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
292#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
293#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
Will Deacone3a920a2014-06-18 14:06:27 +0100294#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
Steve Capperaf074842013-04-19 16:23:57 +0100295
Steve Capper9c7e5352014-02-25 10:02:13 +0000296#define __HAVE_ARCH_PMD_WRITE
297#define pmd_write(pmd) pte_write(pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100298
299#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
300
301#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
302#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
303#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
304
Steve Capper29e56942014-10-09 15:29:25 -0700305#define pud_write(pud) pte_write(pud_pte(pud))
Steve Capper206a2a72014-05-06 14:02:27 +0100306#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
Steve Capperaf074842013-04-19 16:23:57 +0100307
Will Deaconceb21832014-05-27 19:11:58 +0100308#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
Steve Capperaf074842013-04-19 16:23:57 +0100309
310static inline int has_transparent_hugepage(void)
311{
312 return 1;
313}
314
Catalin Marinasa501e322014-04-03 15:57:15 +0100315#define __pgprot_modify(prot,mask,bits) \
316 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
317
Steve Capperaf074842013-04-19 16:23:57 +0100318/*
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000319 * Mark the prot value as uncacheable and unbufferable.
320 */
321#define pgprot_noncached(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000322 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000323#define pgprot_writecombine(prot) \
Catalin Marinasde2db742014-03-12 16:07:06 +0000324 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
Liviu Dudaud1e6dc92014-09-29 15:29:31 +0100325#define pgprot_device(prot) \
326 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000327#define __HAVE_PHYS_MEM_ACCESS_PROT
328struct file;
329extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
330 unsigned long size, pgprot_t vma_prot);
331
332#define pmd_none(pmd) (!pmd_val(pmd))
333#define pmd_present(pmd) (pmd_val(pmd))
334
335#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
336
Marc Zyngier36311602012-12-07 18:35:41 +0000337#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
338 PMD_TYPE_TABLE)
339#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
340 PMD_TYPE_SECT)
341
Steve Capperf3b766a2014-06-25 08:41:45 +0100342#ifdef CONFIG_ARM64_64K_PAGES
Steve Capper206a2a72014-05-06 14:02:27 +0100343#define pud_sect(pud) (0)
zhichang.yuan523d6e92014-12-09 07:26:47 +0000344#define pud_table(pud) (1)
Steve Capper206a2a72014-05-06 14:02:27 +0100345#else
346#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
347 PUD_TYPE_SECT)
zhichang.yuan523d6e92014-12-09 07:26:47 +0000348#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
349 PUD_TYPE_TABLE)
Steve Capper206a2a72014-05-06 14:02:27 +0100350#endif
Marc Zyngier36311602012-12-07 18:35:41 +0000351
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000352static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
353{
354 *pmdp = pmd;
Will Deacon98f76852014-05-02 16:24:10 +0100355 dsb(ishst);
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100356 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000357}
358
359static inline void pmd_clear(pmd_t *pmdp)
360{
361 set_pmd(pmdp, __pmd(0));
362}
363
364static inline pte_t *pmd_page_vaddr(pmd_t pmd)
365{
366 return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
367}
368
369#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
370
371/*
372 * Conversion functions: convert a page and protection to a page entry,
373 * and a page entry and page directory to the page they refer to.
374 */
375#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
376
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700377#if CONFIG_PGTABLE_LEVELS > 2
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000378
Catalin Marinas7078db42014-07-21 14:52:49 +0100379#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
380
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000381#define pud_none(pud) (!pud_val(pud))
382#define pud_bad(pud) (!(pud_val(pud) & 2))
383#define pud_present(pud) (pud_val(pud))
384
385static inline void set_pud(pud_t *pudp, pud_t pud)
386{
387 *pudp = pud;
Will Deacon98f76852014-05-02 16:24:10 +0100388 dsb(ishst);
Catalin Marinas7f0b1bf2014-06-09 11:55:03 +0100389 isb();
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000390}
391
392static inline void pud_clear(pud_t *pudp)
393{
394 set_pud(pudp, __pud(0));
395}
396
397static inline pmd_t *pud_page_vaddr(pud_t pud)
398{
399 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
400}
401
Catalin Marinas7078db42014-07-21 14:52:49 +0100402/* Find an entry in the second-level page table. */
403#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
404
405static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
406{
407 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
408}
409
Jungseok Lee5d96e0c2014-12-20 00:49:40 +0000410#define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
Steve Capper29e56942014-10-09 15:29:25 -0700411
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700412#endif /* CONFIG_PGTABLE_LEVELS > 2 */
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000413
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700414#if CONFIG_PGTABLE_LEVELS > 3
Jungseok Leec79b9542014-05-12 18:40:51 +0900415
Catalin Marinas7078db42014-07-21 14:52:49 +0100416#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
417
Jungseok Leec79b9542014-05-12 18:40:51 +0900418#define pgd_none(pgd) (!pgd_val(pgd))
419#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
420#define pgd_present(pgd) (pgd_val(pgd))
421
422static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
423{
424 *pgdp = pgd;
425 dsb(ishst);
426}
427
428static inline void pgd_clear(pgd_t *pgdp)
429{
430 set_pgd(pgdp, __pgd(0));
431}
432
433static inline pud_t *pgd_page_vaddr(pgd_t pgd)
434{
435 return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
436}
437
Catalin Marinas7078db42014-07-21 14:52:49 +0100438/* Find an entry in the frst-level page table. */
439#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
440
441static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
442{
443 return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
444}
445
Jungseok Lee5d96e0c2014-12-20 00:49:40 +0000446#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
447
Kirill A. Shutemov9f25e6a2015-04-14 15:45:39 -0700448#endif /* CONFIG_PGTABLE_LEVELS > 3 */
Jungseok Leec79b9542014-05-12 18:40:51 +0900449
Catalin Marinas7078db42014-07-21 14:52:49 +0100450#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
451
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000452/* to find an entry in a page-table-directory */
453#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
454
455#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
456
457/* to find an entry in a kernel page-table-directory */
458#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
459
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000460static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
461{
Will Deacona6fadf72012-12-18 14:15:15 +0000462 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
Feng Kan6910fa12015-02-24 15:40:21 -0800463 PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000464 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
465 return pte;
466}
467
Steve Capper9c7e5352014-02-25 10:02:13 +0000468static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
469{
470 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
471}
472
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000473extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
474extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
475
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000476/*
477 * Encode and decode a swap entry:
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000478 * bits 0-1: present (must be zero)
Kirill A. Shutemov9b3e6612015-02-10 14:10:15 -0800479 * bits 2-7: swap type
480 * bits 8-57: swap offset
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000481 */
Kirill A. Shutemov9b3e6612015-02-10 14:10:15 -0800482#define __SWP_TYPE_SHIFT 2
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000483#define __SWP_TYPE_BITS 6
Kirill A. Shutemov9b3e6612015-02-10 14:10:15 -0800484#define __SWP_OFFSET_BITS 50
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000485#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
486#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000487#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000488
489#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
Catalin Marinas3676f9e2013-11-27 16:59:27 +0000490#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000491#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
492
493#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
494#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
495
496/*
497 * Ensure that there are not more swap files than can be encoded in the kernel
Geert Uytterhoevenaad90612014-03-11 11:23:39 +0100498 * PTEs.
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000499 */
500#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
501
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000502extern int kern_addr_valid(unsigned long addr);
503
504#include <asm-generic/pgtable.h>
505
Catalin Marinas4f04d8f2012-03-05 11:49:27 +0000506#define pgtable_cache_init() do { } while (0)
507
508#endif /* !__ASSEMBLY__ */
509
510#endif /* __ASM_PGTABLE_H */