Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 24 | #include "gf100.h" |
| 25 | #include "ctxgf100.h" |
| 26 | #include "fuc/os.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 27 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 28 | #include <core/client.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 29 | #include <core/option.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 30 | #include <subdev/fb.h> |
| 31 | #include <subdev/mc.h> |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 32 | #include <subdev/pmu.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 33 | #include <subdev/timer.h> |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 34 | #include <engine/fifo.h> |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 35 | |
| 36 | #include <nvif/class.h> |
| 37 | #include <nvif/unpack.h> |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
| 40 | * Zero Bandwidth Clear |
| 41 | ******************************************************************************/ |
| 42 | |
| 43 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 44 | gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 45 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 46 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 47 | if (gr->zbc_color[zbc].format) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 48 | nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); |
| 49 | nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); |
| 50 | nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); |
| 51 | nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 52 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 53 | nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); |
| 54 | nvkm_wr32(device, 0x405820, zbc); |
| 55 | nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | static int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 59 | gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 60 | const u32 ds[4], const u32 l2[4]) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 61 | { |
Ben Skeggs | 70bc718 | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 62 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 63 | int zbc = -ENOSPC, i; |
| 64 | |
| 65 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 66 | if (gr->zbc_color[i].format) { |
| 67 | if (gr->zbc_color[i].format != format) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 68 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 69 | if (memcmp(gr->zbc_color[i].ds, ds, sizeof( |
| 70 | gr->zbc_color[i].ds))) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 71 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 72 | if (memcmp(gr->zbc_color[i].l2, l2, sizeof( |
| 73 | gr->zbc_color[i].l2))) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 74 | WARN_ON(1); |
| 75 | return -EINVAL; |
| 76 | } |
| 77 | return i; |
| 78 | } else { |
| 79 | zbc = (zbc < 0) ? i : zbc; |
| 80 | } |
| 81 | } |
| 82 | |
| 83 | if (zbc < 0) |
| 84 | return zbc; |
| 85 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 86 | memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); |
| 87 | memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); |
| 88 | gr->zbc_color[zbc].format = format; |
Ben Skeggs | 70bc718 | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 89 | nvkm_ltc_zbc_color_get(ltc, zbc, l2); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 90 | gf100_gr_zbc_clear_color(gr, zbc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 91 | return zbc; |
| 92 | } |
| 93 | |
| 94 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 95 | gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 96 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 97 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 98 | if (gr->zbc_depth[zbc].format) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 99 | nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); |
| 100 | nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); |
| 101 | nvkm_wr32(device, 0x405820, zbc); |
| 102 | nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | static int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 106 | gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 107 | const u32 ds, const u32 l2) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 108 | { |
Ben Skeggs | 70bc718 | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 109 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 110 | int zbc = -ENOSPC, i; |
| 111 | |
| 112 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 113 | if (gr->zbc_depth[i].format) { |
| 114 | if (gr->zbc_depth[i].format != format) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 115 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 116 | if (gr->zbc_depth[i].ds != ds) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 117 | continue; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 118 | if (gr->zbc_depth[i].l2 != l2) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 119 | WARN_ON(1); |
| 120 | return -EINVAL; |
| 121 | } |
| 122 | return i; |
| 123 | } else { |
| 124 | zbc = (zbc < 0) ? i : zbc; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | if (zbc < 0) |
| 129 | return zbc; |
| 130 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 131 | gr->zbc_depth[zbc].format = format; |
| 132 | gr->zbc_depth[zbc].ds = ds; |
| 133 | gr->zbc_depth[zbc].l2 = l2; |
Ben Skeggs | 70bc718 | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 134 | nvkm_ltc_zbc_depth_get(ltc, zbc, l2); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 135 | gf100_gr_zbc_clear_depth(gr, zbc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 136 | return zbc; |
| 137 | } |
| 138 | |
| 139 | /******************************************************************************* |
| 140 | * Graphics object classes |
| 141 | ******************************************************************************/ |
| 142 | |
| 143 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 144 | gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 145 | { |
Ben Skeggs | 0d7fc24 | 2015-11-25 12:39:01 +1000 | [diff] [blame] | 146 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 147 | union { |
| 148 | struct fermi_a_zbc_color_v0 v0; |
| 149 | } *args = data; |
| 150 | int ret; |
| 151 | |
| 152 | if (nvif_unpack(args->v0, 0, 0, false)) { |
| 153 | switch (args->v0.format) { |
| 154 | case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: |
| 155 | case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: |
| 156 | case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: |
| 157 | case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: |
| 158 | case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: |
| 159 | case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: |
| 160 | case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: |
| 161 | case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: |
| 162 | case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: |
| 163 | case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: |
| 164 | case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: |
| 165 | case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: |
| 166 | case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: |
| 167 | case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: |
| 168 | case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: |
| 169 | case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: |
| 170 | case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: |
| 171 | case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: |
| 172 | case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 173 | ret = gf100_gr_zbc_color_get(gr, args->v0.format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 174 | args->v0.ds, |
| 175 | args->v0.l2); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 176 | if (ret >= 0) { |
| 177 | args->v0.index = ret; |
| 178 | return 0; |
| 179 | } |
| 180 | break; |
| 181 | default: |
| 182 | return -EINVAL; |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | return ret; |
| 187 | } |
| 188 | |
| 189 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 190 | gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 191 | { |
Ben Skeggs | 0d7fc24 | 2015-11-25 12:39:01 +1000 | [diff] [blame] | 192 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 193 | union { |
| 194 | struct fermi_a_zbc_depth_v0 v0; |
| 195 | } *args = data; |
| 196 | int ret; |
| 197 | |
| 198 | if (nvif_unpack(args->v0, 0, 0, false)) { |
| 199 | switch (args->v0.format) { |
| 200 | case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 201 | ret = gf100_gr_zbc_depth_get(gr, args->v0.format, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 202 | args->v0.ds, |
| 203 | args->v0.l2); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 204 | return (ret >= 0) ? 0 : -ENOSPC; |
| 205 | default: |
| 206 | return -EINVAL; |
| 207 | } |
| 208 | } |
| 209 | |
| 210 | return ret; |
| 211 | } |
| 212 | |
| 213 | static int |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 214 | gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 215 | { |
| 216 | switch (mthd) { |
| 217 | case FERMI_A_ZBC_COLOR: |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 218 | return gf100_fermi_mthd_zbc_color(object, data, size); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 219 | case FERMI_A_ZBC_DEPTH: |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 220 | return gf100_fermi_mthd_zbc_depth(object, data, size); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 221 | default: |
| 222 | break; |
| 223 | } |
| 224 | return -EINVAL; |
| 225 | } |
| 226 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 227 | const struct nvkm_object_func |
| 228 | gf100_fermi = { |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 229 | .mthd = gf100_fermi_mthd, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 230 | }; |
| 231 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 232 | static void |
| 233 | gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 234 | { |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 235 | nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); |
| 236 | nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 237 | } |
| 238 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 239 | static bool |
| 240 | gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) |
| 241 | { |
| 242 | switch (class & 0x00ff) { |
| 243 | case 0x97: |
| 244 | case 0xc0: |
| 245 | switch (mthd) { |
| 246 | case 0x1528: |
| 247 | gf100_gr_mthd_set_shader_exceptions(device, data); |
| 248 | return true; |
| 249 | default: |
| 250 | break; |
| 251 | } |
| 252 | break; |
| 253 | default: |
| 254 | break; |
| 255 | } |
| 256 | return false; |
| 257 | } |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 258 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 259 | static int |
| 260 | gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) |
| 261 | { |
| 262 | struct gf100_gr *gr = gf100_gr(base); |
| 263 | int c = 0; |
| 264 | |
| 265 | while (gr->func->sclass[c].oclass) { |
| 266 | if (c++ == index) { |
| 267 | *sclass = gr->func->sclass[index]; |
| 268 | return index; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | return c; |
| 273 | } |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 274 | |
| 275 | /******************************************************************************* |
| 276 | * PGRAPH context |
| 277 | ******************************************************************************/ |
| 278 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 279 | static int |
| 280 | gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, |
| 281 | int align, struct nvkm_gpuobj **pgpuobj) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 282 | { |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 283 | struct gf100_gr_chan *chan = gf100_gr_chan(object); |
| 284 | struct gf100_gr *gr = chan->gr; |
| 285 | int ret, i; |
| 286 | |
| 287 | ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, |
| 288 | align, false, parent, pgpuobj); |
| 289 | if (ret) |
| 290 | return ret; |
| 291 | |
| 292 | nvkm_kmap(*pgpuobj); |
| 293 | for (i = 0; i < gr->size; i += 4) |
| 294 | nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); |
| 295 | |
| 296 | if (!gr->firmware) { |
| 297 | nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); |
| 298 | nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); |
| 299 | } else { |
| 300 | nvkm_wo32(*pgpuobj, 0xf4, 0); |
| 301 | nvkm_wo32(*pgpuobj, 0xf8, 0); |
| 302 | nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); |
| 303 | nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); |
| 304 | nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); |
| 305 | nvkm_wo32(*pgpuobj, 0x1c, 1); |
| 306 | nvkm_wo32(*pgpuobj, 0x20, 0); |
| 307 | nvkm_wo32(*pgpuobj, 0x28, 0); |
| 308 | nvkm_wo32(*pgpuobj, 0x2c, 0); |
| 309 | } |
| 310 | nvkm_done(*pgpuobj); |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static void * |
| 315 | gf100_gr_chan_dtor(struct nvkm_object *object) |
| 316 | { |
| 317 | struct gf100_gr_chan *chan = gf100_gr_chan(object); |
| 318 | int i; |
| 319 | |
| 320 | for (i = 0; i < ARRAY_SIZE(chan->data); i++) { |
| 321 | if (chan->data[i].vma.node) { |
| 322 | nvkm_vm_unmap(&chan->data[i].vma); |
| 323 | nvkm_vm_put(&chan->data[i].vma); |
| 324 | } |
| 325 | nvkm_memory_del(&chan->data[i].mem); |
| 326 | } |
| 327 | |
| 328 | if (chan->mmio_vma.node) { |
| 329 | nvkm_vm_unmap(&chan->mmio_vma); |
| 330 | nvkm_vm_put(&chan->mmio_vma); |
| 331 | } |
| 332 | nvkm_memory_del(&chan->mmio); |
| 333 | return chan; |
| 334 | } |
| 335 | |
| 336 | static const struct nvkm_object_func |
| 337 | gf100_gr_chan = { |
| 338 | .dtor = gf100_gr_chan_dtor, |
| 339 | .bind = gf100_gr_chan_bind, |
| 340 | }; |
| 341 | |
| 342 | static int |
| 343 | gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, |
| 344 | const struct nvkm_oclass *oclass, |
| 345 | struct nvkm_object **pobject) |
| 346 | { |
| 347 | struct gf100_gr *gr = gf100_gr(base); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 348 | struct gf100_gr_data *data = gr->mmio_data; |
| 349 | struct gf100_gr_mmio *mmio = gr->mmio_list; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 350 | struct gf100_gr_chan *chan; |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 351 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 352 | int ret, i; |
| 353 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 354 | if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) |
| 355 | return -ENOMEM; |
| 356 | nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); |
| 357 | chan->gr = gr; |
| 358 | *pobject = &chan->object; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 359 | |
| 360 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
| 361 | * fuc to modify some per-context register settings on first load |
| 362 | * of the context. |
| 363 | */ |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 364 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, |
| 365 | false, &chan->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 366 | if (ret) |
| 367 | return ret; |
| 368 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 369 | ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 370 | NV_MEM_ACCESS_SYS, &chan->mmio_vma); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 371 | if (ret) |
| 372 | return ret; |
| 373 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 374 | nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); |
| 375 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 376 | /* allocate buffers referenced by mmio list */ |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 377 | for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 378 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, |
| 379 | data->size, data->align, false, |
| 380 | &chan->data[i].mem); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 381 | if (ret) |
| 382 | return ret; |
| 383 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 384 | ret = nvkm_vm_get(fifoch->vm, |
| 385 | nvkm_memory_size(chan->data[i].mem), 12, |
| 386 | data->access, &chan->data[i].vma); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 387 | if (ret) |
| 388 | return ret; |
| 389 | |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 390 | nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 391 | data++; |
| 392 | } |
| 393 | |
| 394 | /* finally, fill in the mmio list and point the context at it */ |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 395 | nvkm_kmap(chan->mmio); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 396 | for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 397 | u32 addr = mmio->addr; |
| 398 | u32 data = mmio->data; |
| 399 | |
| 400 | if (mmio->buffer >= 0) { |
| 401 | u64 info = chan->data[mmio->buffer].vma.offset; |
| 402 | data |= info >> mmio->shift; |
| 403 | } |
| 404 | |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 405 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); |
| 406 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 407 | mmio++; |
| 408 | } |
Ben Skeggs | 142ea05 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 409 | nvkm_done(chan->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 410 | return 0; |
| 411 | } |
| 412 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 413 | /******************************************************************************* |
| 414 | * PGRAPH register lists |
| 415 | ******************************************************************************/ |
| 416 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 417 | const struct gf100_gr_init |
| 418 | gf100_gr_init_main_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 419 | { 0x400080, 1, 0x04, 0x003083c2 }, |
| 420 | { 0x400088, 1, 0x04, 0x00006fe7 }, |
| 421 | { 0x40008c, 1, 0x04, 0x00000000 }, |
| 422 | { 0x400090, 1, 0x04, 0x00000030 }, |
| 423 | { 0x40013c, 1, 0x04, 0x013901f7 }, |
| 424 | { 0x400140, 1, 0x04, 0x00000100 }, |
| 425 | { 0x400144, 1, 0x04, 0x00000000 }, |
| 426 | { 0x400148, 1, 0x04, 0x00000110 }, |
| 427 | { 0x400138, 1, 0x04, 0x00000000 }, |
| 428 | { 0x400130, 2, 0x04, 0x00000000 }, |
| 429 | { 0x400124, 1, 0x04, 0x00000002 }, |
| 430 | {} |
| 431 | }; |
| 432 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 433 | const struct gf100_gr_init |
| 434 | gf100_gr_init_fe_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 435 | { 0x40415c, 1, 0x04, 0x00000000 }, |
| 436 | { 0x404170, 1, 0x04, 0x00000000 }, |
| 437 | {} |
| 438 | }; |
| 439 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 440 | const struct gf100_gr_init |
| 441 | gf100_gr_init_pri_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 442 | { 0x404488, 2, 0x04, 0x00000000 }, |
| 443 | {} |
| 444 | }; |
| 445 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 446 | const struct gf100_gr_init |
| 447 | gf100_gr_init_rstr2d_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 448 | { 0x407808, 1, 0x04, 0x00000000 }, |
| 449 | {} |
| 450 | }; |
| 451 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 452 | const struct gf100_gr_init |
| 453 | gf100_gr_init_pd_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 454 | { 0x406024, 1, 0x04, 0x00000000 }, |
| 455 | {} |
| 456 | }; |
| 457 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 458 | const struct gf100_gr_init |
| 459 | gf100_gr_init_ds_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 460 | { 0x405844, 1, 0x04, 0x00ffffff }, |
| 461 | { 0x405850, 1, 0x04, 0x00000000 }, |
| 462 | { 0x405908, 1, 0x04, 0x00000000 }, |
| 463 | {} |
| 464 | }; |
| 465 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 466 | const struct gf100_gr_init |
| 467 | gf100_gr_init_scc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 468 | { 0x40803c, 1, 0x04, 0x00000000 }, |
| 469 | {} |
| 470 | }; |
| 471 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 472 | const struct gf100_gr_init |
| 473 | gf100_gr_init_prop_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 474 | { 0x4184a0, 1, 0x04, 0x00000000 }, |
| 475 | {} |
| 476 | }; |
| 477 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 478 | const struct gf100_gr_init |
| 479 | gf100_gr_init_gpc_unk_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 480 | { 0x418604, 1, 0x04, 0x00000000 }, |
| 481 | { 0x418680, 1, 0x04, 0x00000000 }, |
| 482 | { 0x418714, 1, 0x04, 0x80000000 }, |
| 483 | { 0x418384, 1, 0x04, 0x00000000 }, |
| 484 | {} |
| 485 | }; |
| 486 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 487 | const struct gf100_gr_init |
| 488 | gf100_gr_init_setup_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 489 | { 0x418814, 3, 0x04, 0x00000000 }, |
| 490 | {} |
| 491 | }; |
| 492 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 493 | const struct gf100_gr_init |
| 494 | gf100_gr_init_crstr_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 495 | { 0x418b04, 1, 0x04, 0x00000000 }, |
| 496 | {} |
| 497 | }; |
| 498 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 499 | const struct gf100_gr_init |
| 500 | gf100_gr_init_setup_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 501 | { 0x4188c8, 1, 0x04, 0x80000000 }, |
| 502 | { 0x4188cc, 1, 0x04, 0x00000000 }, |
| 503 | { 0x4188d0, 1, 0x04, 0x00010000 }, |
| 504 | { 0x4188d4, 1, 0x04, 0x00000001 }, |
| 505 | {} |
| 506 | }; |
| 507 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 508 | const struct gf100_gr_init |
| 509 | gf100_gr_init_zcull_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 510 | { 0x418910, 1, 0x04, 0x00010001 }, |
| 511 | { 0x418914, 1, 0x04, 0x00000301 }, |
| 512 | { 0x418918, 1, 0x04, 0x00800000 }, |
| 513 | { 0x418980, 1, 0x04, 0x77777770 }, |
| 514 | { 0x418984, 3, 0x04, 0x77777777 }, |
| 515 | {} |
| 516 | }; |
| 517 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 518 | const struct gf100_gr_init |
| 519 | gf100_gr_init_gpm_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 520 | { 0x418c04, 1, 0x04, 0x00000000 }, |
| 521 | { 0x418c88, 1, 0x04, 0x00000000 }, |
| 522 | {} |
| 523 | }; |
| 524 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 525 | const struct gf100_gr_init |
| 526 | gf100_gr_init_gpc_unk_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 527 | { 0x418d00, 1, 0x04, 0x00000000 }, |
| 528 | { 0x418f08, 1, 0x04, 0x00000000 }, |
| 529 | { 0x418e00, 1, 0x04, 0x00000050 }, |
| 530 | { 0x418e08, 1, 0x04, 0x00000000 }, |
| 531 | {} |
| 532 | }; |
| 533 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 534 | const struct gf100_gr_init |
| 535 | gf100_gr_init_gcc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 536 | { 0x41900c, 1, 0x04, 0x00000000 }, |
| 537 | { 0x419018, 1, 0x04, 0x00000000 }, |
| 538 | {} |
| 539 | }; |
| 540 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 541 | const struct gf100_gr_init |
| 542 | gf100_gr_init_tpccs_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 543 | { 0x419d08, 2, 0x04, 0x00000000 }, |
| 544 | { 0x419d10, 1, 0x04, 0x00000014 }, |
| 545 | {} |
| 546 | }; |
| 547 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 548 | const struct gf100_gr_init |
| 549 | gf100_gr_init_tex_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 550 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
| 551 | { 0x419ab8, 1, 0x04, 0x000000e7 }, |
| 552 | { 0x419abc, 2, 0x04, 0x00000000 }, |
| 553 | {} |
| 554 | }; |
| 555 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 556 | const struct gf100_gr_init |
| 557 | gf100_gr_init_pe_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 558 | { 0x41980c, 3, 0x04, 0x00000000 }, |
| 559 | { 0x419844, 1, 0x04, 0x00000000 }, |
| 560 | { 0x41984c, 1, 0x04, 0x00005bc5 }, |
| 561 | { 0x419850, 4, 0x04, 0x00000000 }, |
| 562 | {} |
| 563 | }; |
| 564 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 565 | const struct gf100_gr_init |
| 566 | gf100_gr_init_l1c_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 567 | { 0x419c98, 1, 0x04, 0x00000000 }, |
| 568 | { 0x419ca8, 1, 0x04, 0x80000000 }, |
| 569 | { 0x419cb4, 1, 0x04, 0x00000000 }, |
| 570 | { 0x419cb8, 1, 0x04, 0x00008bf4 }, |
| 571 | { 0x419cbc, 1, 0x04, 0x28137606 }, |
| 572 | { 0x419cc0, 2, 0x04, 0x00000000 }, |
| 573 | {} |
| 574 | }; |
| 575 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 576 | const struct gf100_gr_init |
| 577 | gf100_gr_init_wwdx_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 578 | { 0x419bd4, 1, 0x04, 0x00800000 }, |
| 579 | { 0x419bdc, 1, 0x04, 0x00000000 }, |
| 580 | {} |
| 581 | }; |
| 582 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 583 | const struct gf100_gr_init |
| 584 | gf100_gr_init_tpccs_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 585 | { 0x419d2c, 1, 0x04, 0x00000000 }, |
| 586 | {} |
| 587 | }; |
| 588 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 589 | const struct gf100_gr_init |
| 590 | gf100_gr_init_mpc_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 591 | { 0x419c0c, 1, 0x04, 0x00000000 }, |
| 592 | {} |
| 593 | }; |
| 594 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 595 | static const struct gf100_gr_init |
| 596 | gf100_gr_init_sm_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 597 | { 0x419e00, 1, 0x04, 0x00000000 }, |
| 598 | { 0x419ea0, 1, 0x04, 0x00000000 }, |
| 599 | { 0x419ea4, 1, 0x04, 0x00000100 }, |
| 600 | { 0x419ea8, 1, 0x04, 0x00001100 }, |
| 601 | { 0x419eac, 1, 0x04, 0x11100702 }, |
| 602 | { 0x419eb0, 1, 0x04, 0x00000003 }, |
| 603 | { 0x419eb4, 4, 0x04, 0x00000000 }, |
| 604 | { 0x419ec8, 1, 0x04, 0x06060618 }, |
| 605 | { 0x419ed0, 1, 0x04, 0x0eff0e38 }, |
| 606 | { 0x419ed4, 1, 0x04, 0x011104f1 }, |
| 607 | { 0x419edc, 1, 0x04, 0x00000000 }, |
| 608 | { 0x419f00, 1, 0x04, 0x00000000 }, |
| 609 | { 0x419f2c, 1, 0x04, 0x00000000 }, |
| 610 | {} |
| 611 | }; |
| 612 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 613 | const struct gf100_gr_init |
| 614 | gf100_gr_init_be_0[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 615 | { 0x40880c, 1, 0x04, 0x00000000 }, |
| 616 | { 0x408910, 9, 0x04, 0x00000000 }, |
| 617 | { 0x408950, 1, 0x04, 0x00000000 }, |
| 618 | { 0x408954, 1, 0x04, 0x0000ffff }, |
| 619 | { 0x408984, 1, 0x04, 0x00000000 }, |
| 620 | { 0x408988, 1, 0x04, 0x08040201 }, |
| 621 | { 0x40898c, 1, 0x04, 0x80402010 }, |
| 622 | {} |
| 623 | }; |
| 624 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 625 | const struct gf100_gr_init |
| 626 | gf100_gr_init_fe_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 627 | { 0x4040f0, 1, 0x04, 0x00000000 }, |
| 628 | {} |
| 629 | }; |
| 630 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 631 | const struct gf100_gr_init |
| 632 | gf100_gr_init_pe_1[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 633 | { 0x419880, 1, 0x04, 0x00000002 }, |
| 634 | {} |
| 635 | }; |
| 636 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 637 | static const struct gf100_gr_pack |
| 638 | gf100_gr_pack_mmio[] = { |
| 639 | { gf100_gr_init_main_0 }, |
| 640 | { gf100_gr_init_fe_0 }, |
| 641 | { gf100_gr_init_pri_0 }, |
| 642 | { gf100_gr_init_rstr2d_0 }, |
| 643 | { gf100_gr_init_pd_0 }, |
| 644 | { gf100_gr_init_ds_0 }, |
| 645 | { gf100_gr_init_scc_0 }, |
| 646 | { gf100_gr_init_prop_0 }, |
| 647 | { gf100_gr_init_gpc_unk_0 }, |
| 648 | { gf100_gr_init_setup_0 }, |
| 649 | { gf100_gr_init_crstr_0 }, |
| 650 | { gf100_gr_init_setup_1 }, |
| 651 | { gf100_gr_init_zcull_0 }, |
| 652 | { gf100_gr_init_gpm_0 }, |
| 653 | { gf100_gr_init_gpc_unk_1 }, |
| 654 | { gf100_gr_init_gcc_0 }, |
| 655 | { gf100_gr_init_tpccs_0 }, |
| 656 | { gf100_gr_init_tex_0 }, |
| 657 | { gf100_gr_init_pe_0 }, |
| 658 | { gf100_gr_init_l1c_0 }, |
| 659 | { gf100_gr_init_wwdx_0 }, |
| 660 | { gf100_gr_init_tpccs_1 }, |
| 661 | { gf100_gr_init_mpc_0 }, |
| 662 | { gf100_gr_init_sm_0 }, |
| 663 | { gf100_gr_init_be_0 }, |
| 664 | { gf100_gr_init_fe_1 }, |
| 665 | { gf100_gr_init_pe_1 }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 666 | {} |
| 667 | }; |
| 668 | |
| 669 | /******************************************************************************* |
| 670 | * PGRAPH engine/subdev functions |
| 671 | ******************************************************************************/ |
| 672 | |
| 673 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 674 | gf100_gr_zbc_init(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 675 | { |
| 676 | const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 677 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; |
| 678 | const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, |
| 679 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; |
| 680 | const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 681 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; |
| 682 | const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, |
| 683 | 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; |
Ben Skeggs | 70bc718 | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 684 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 685 | int index; |
| 686 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 687 | if (!gr->zbc_color[0].format) { |
| 688 | gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); |
| 689 | gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); |
| 690 | gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); |
| 691 | gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); |
| 692 | gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); |
| 693 | gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 694 | } |
| 695 | |
| 696 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 697 | gf100_gr_zbc_clear_color(gr, index); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 698 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 699 | gf100_gr_zbc_clear_depth(gr, index); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 700 | } |
| 701 | |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 702 | /** |
| 703 | * Wait until GR goes idle. GR is considered idle if it is disabled by the |
| 704 | * MC (0x200) register, or GR is not busy and a context switch is not in |
| 705 | * progress. |
| 706 | */ |
| 707 | int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 708 | gf100_gr_wait_idle(struct gf100_gr *gr) |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 709 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 710 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 711 | struct nvkm_device *device = subdev->device; |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 712 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); |
| 713 | bool gr_enabled, ctxsw_active, gr_busy; |
| 714 | |
| 715 | do { |
| 716 | /* |
| 717 | * required to make sure FIFO_ENGINE_STATUS (0x2640) is |
| 718 | * up-to-date |
| 719 | */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 720 | nvkm_rd32(device, 0x400700); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 721 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 722 | gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; |
| 723 | ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; |
| 724 | gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 725 | |
| 726 | if (!gr_enabled || (!gr_busy && !ctxsw_active)) |
| 727 | return 0; |
| 728 | } while (time_before(jiffies, end_jiffies)); |
| 729 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 730 | nvkm_error(subdev, |
| 731 | "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", |
| 732 | gr_enabled, ctxsw_active, gr_busy); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 733 | return -EAGAIN; |
| 734 | } |
| 735 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 736 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 737 | gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 738 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 739 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 740 | const struct gf100_gr_pack *pack; |
| 741 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 742 | |
| 743 | pack_for_each_init(init, pack, p) { |
| 744 | u32 next = init->addr + init->count * init->pitch; |
| 745 | u32 addr = init->addr; |
| 746 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 747 | nvkm_wr32(device, addr, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 748 | addr += init->pitch; |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 754 | gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 755 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 756 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 757 | const struct gf100_gr_pack *pack; |
| 758 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 759 | u32 data = 0; |
| 760 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 761 | nvkm_wr32(device, 0x400208, 0x80000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 762 | |
| 763 | pack_for_each_init(init, pack, p) { |
| 764 | u32 next = init->addr + init->count * init->pitch; |
| 765 | u32 addr = init->addr; |
| 766 | |
| 767 | if ((pack == p && init == p->init) || data != init->data) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 768 | nvkm_wr32(device, 0x400204, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 769 | data = init->data; |
| 770 | } |
| 771 | |
| 772 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 773 | nvkm_wr32(device, 0x400200, addr); |
Alexandre Courbot | 4a8cf45 | 2015-04-27 17:25:11 +0900 | [diff] [blame] | 774 | /** |
| 775 | * Wait for GR to go idle after submitting a |
| 776 | * GO_IDLE bundle |
| 777 | */ |
| 778 | if ((addr & 0xffff) == 0xe100) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 779 | gf100_gr_wait_idle(gr); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 780 | nvkm_msec(device, 2000, |
| 781 | if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) |
| 782 | break; |
| 783 | ); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 784 | addr += init->pitch; |
| 785 | } |
| 786 | } |
| 787 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 788 | nvkm_wr32(device, 0x400208, 0x00000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 789 | } |
| 790 | |
| 791 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 792 | gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 793 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 794 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 795 | const struct gf100_gr_pack *pack; |
| 796 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 797 | u32 data = 0; |
| 798 | |
| 799 | pack_for_each_init(init, pack, p) { |
| 800 | u32 ctrl = 0x80000000 | pack->type; |
| 801 | u32 next = init->addr + init->count * init->pitch; |
| 802 | u32 addr = init->addr; |
| 803 | |
| 804 | if ((pack == p && init == p->init) || data != init->data) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 805 | nvkm_wr32(device, 0x40448c, init->data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 806 | data = init->data; |
| 807 | } |
| 808 | |
| 809 | while (addr < next) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 810 | nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 811 | addr += init->pitch; |
| 812 | } |
| 813 | } |
| 814 | } |
| 815 | |
| 816 | u64 |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 817 | gf100_gr_units(struct nvkm_gr *base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 818 | { |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 819 | struct gf100_gr *gr = gf100_gr(base); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 820 | u64 cfg; |
| 821 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 822 | cfg = (u32)gr->gpc_nr; |
| 823 | cfg |= (u32)gr->tpc_total << 8; |
| 824 | cfg |= (u64)gr->rop_nr << 32; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 825 | |
| 826 | return cfg; |
| 827 | } |
| 828 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 829 | static const struct nvkm_bitfield gk104_sked_error[] = { |
| 830 | { 0x00000080, "CONSTANT_BUFFER_SIZE" }, |
| 831 | { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, |
| 832 | { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, |
| 833 | { 0x00000800, "WARP_CSTACK_SIZE" }, |
| 834 | { 0x00001000, "TOTAL_TEMP_SIZE" }, |
| 835 | { 0x00002000, "REGISTER_COUNT" }, |
| 836 | { 0x00040000, "TOTAL_THREADS" }, |
| 837 | { 0x00100000, "PROGRAM_OFFSET" }, |
| 838 | { 0x00200000, "SHARED_MEMORY_SIZE" }, |
| 839 | { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, |
| 840 | { 0x04000000, "TOTAL_REGISTER_COUNT" }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 841 | {} |
| 842 | }; |
| 843 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 844 | static const struct nvkm_bitfield gf100_gpc_rop_error[] = { |
| 845 | { 0x00000002, "RT_PITCH_OVERRUN" }, |
| 846 | { 0x00000010, "RT_WIDTH_OVERRUN" }, |
| 847 | { 0x00000020, "RT_HEIGHT_OVERRUN" }, |
| 848 | { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, |
| 849 | { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, |
| 850 | { 0x00000400, "RT_LINEAR_MISMATCH" }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 851 | {} |
| 852 | }; |
| 853 | |
| 854 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 855 | gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 856 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 857 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 858 | struct nvkm_device *device = subdev->device; |
| 859 | char error[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 860 | u32 trap[4]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 861 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 862 | trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 863 | trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); |
| 864 | trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); |
| 865 | trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 866 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 867 | nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 868 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 869 | nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " |
| 870 | "format = %x, storage type = %x\n", |
| 871 | gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, |
| 872 | (trap[2] >> 8) & 0x3f, trap[3] & 0xff); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 873 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 874 | } |
| 875 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 876 | static const struct nvkm_enum gf100_mp_warp_error[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 877 | { 0x00, "NO_ERROR" }, |
| 878 | { 0x01, "STACK_MISMATCH" }, |
| 879 | { 0x05, "MISALIGNED_PC" }, |
| 880 | { 0x08, "MISALIGNED_GPR" }, |
| 881 | { 0x09, "INVALID_OPCODE" }, |
| 882 | { 0x0d, "GPR_OUT_OF_BOUNDS" }, |
| 883 | { 0x0e, "MEM_OUT_OF_BOUNDS" }, |
| 884 | { 0x0f, "UNALIGNED_MEM_ACCESS" }, |
Ilia Mirkin | 3988f64 | 2015-10-07 18:39:32 -0400 | [diff] [blame] | 885 | { 0x10, "INVALID_ADDR_SPACE" }, |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 886 | { 0x11, "INVALID_PARAM" }, |
| 887 | {} |
| 888 | }; |
| 889 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 890 | static const struct nvkm_bitfield gf100_mp_global_error[] = { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 891 | { 0x00000004, "MULTIPLE_WARP_ERRORS" }, |
| 892 | { 0x00000008, "OUT_OF_STACK_SPACE" }, |
| 893 | {} |
| 894 | }; |
| 895 | |
| 896 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 897 | gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 898 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 899 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 900 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 901 | u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); |
| 902 | u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 903 | const struct nvkm_enum *warp; |
| 904 | char glob[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 905 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 906 | nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); |
| 907 | warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); |
| 908 | |
| 909 | nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " |
| 910 | "global %08x [%s] warp %04x [%s]\n", |
| 911 | gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 912 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 913 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); |
| 914 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 918 | gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 919 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 920 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 921 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 922 | u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 923 | |
| 924 | if (stat & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 925 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 926 | nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 927 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 928 | stat &= ~0x00000001; |
| 929 | } |
| 930 | |
| 931 | if (stat & 0x00000002) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 932 | gf100_gr_trap_mp(gr, gpc, tpc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 933 | stat &= ~0x00000002; |
| 934 | } |
| 935 | |
| 936 | if (stat & 0x00000004) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 937 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 938 | nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 939 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 940 | stat &= ~0x00000004; |
| 941 | } |
| 942 | |
| 943 | if (stat & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 944 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 945 | nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 946 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 947 | stat &= ~0x00000008; |
| 948 | } |
| 949 | |
| 950 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 951 | nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 952 | } |
| 953 | } |
| 954 | |
| 955 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 956 | gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 957 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 958 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 959 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 960 | u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 961 | int tpc; |
| 962 | |
| 963 | if (stat & 0x00000001) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 964 | gf100_gr_trap_gpc_rop(gr, gpc); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 965 | stat &= ~0x00000001; |
| 966 | } |
| 967 | |
| 968 | if (stat & 0x00000002) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 969 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 970 | nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 971 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 972 | stat &= ~0x00000002; |
| 973 | } |
| 974 | |
| 975 | if (stat & 0x00000004) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 976 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 977 | nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 978 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 979 | stat &= ~0x00000004; |
| 980 | } |
| 981 | |
| 982 | if (stat & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 983 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 984 | nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 985 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 986 | stat &= ~0x00000009; |
| 987 | } |
| 988 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 989 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 990 | u32 mask = 0x00010000 << tpc; |
| 991 | if (stat & mask) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 992 | gf100_gr_trap_tpc(gr, gpc, tpc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 993 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 994 | stat &= ~mask; |
| 995 | } |
| 996 | } |
| 997 | |
| 998 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 999 | nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1004 | gf100_gr_trap_intr(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1005 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1006 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1007 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1008 | u32 trap = nvkm_rd32(device, 0x400108); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1009 | int rop, gpc; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1010 | |
| 1011 | if (trap & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1012 | u32 stat = nvkm_rd32(device, 0x404000); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1013 | nvkm_error(subdev, "DISPATCH %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1014 | nvkm_wr32(device, 0x404000, 0xc0000000); |
| 1015 | nvkm_wr32(device, 0x400108, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1016 | trap &= ~0x00000001; |
| 1017 | } |
| 1018 | |
| 1019 | if (trap & 0x00000002) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1020 | u32 stat = nvkm_rd32(device, 0x404600); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1021 | nvkm_error(subdev, "M2MF %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1022 | nvkm_wr32(device, 0x404600, 0xc0000000); |
| 1023 | nvkm_wr32(device, 0x400108, 0x00000002); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1024 | trap &= ~0x00000002; |
| 1025 | } |
| 1026 | |
| 1027 | if (trap & 0x00000008) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1028 | u32 stat = nvkm_rd32(device, 0x408030); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1029 | nvkm_error(subdev, "CCACHE %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1030 | nvkm_wr32(device, 0x408030, 0xc0000000); |
| 1031 | nvkm_wr32(device, 0x400108, 0x00000008); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1032 | trap &= ~0x00000008; |
| 1033 | } |
| 1034 | |
| 1035 | if (trap & 0x00000010) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1036 | u32 stat = nvkm_rd32(device, 0x405840); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1037 | nvkm_error(subdev, "SHADER %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1038 | nvkm_wr32(device, 0x405840, 0xc0000000); |
| 1039 | nvkm_wr32(device, 0x400108, 0x00000010); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1040 | trap &= ~0x00000010; |
| 1041 | } |
| 1042 | |
| 1043 | if (trap & 0x00000040) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1044 | u32 stat = nvkm_rd32(device, 0x40601c); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1045 | nvkm_error(subdev, "UNK6 %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1046 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
| 1047 | nvkm_wr32(device, 0x400108, 0x00000040); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1048 | trap &= ~0x00000040; |
| 1049 | } |
| 1050 | |
| 1051 | if (trap & 0x00000080) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1052 | u32 stat = nvkm_rd32(device, 0x404490); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1053 | nvkm_error(subdev, "MACRO %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1054 | nvkm_wr32(device, 0x404490, 0xc0000000); |
| 1055 | nvkm_wr32(device, 0x400108, 0x00000080); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1056 | trap &= ~0x00000080; |
| 1057 | } |
| 1058 | |
| 1059 | if (trap & 0x00000100) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1060 | u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; |
| 1061 | char sked[128]; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1062 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1063 | nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); |
| 1064 | nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1065 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1066 | if (stat) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1067 | nvkm_wr32(device, 0x407020, 0x40000000); |
| 1068 | nvkm_wr32(device, 0x400108, 0x00000100); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1069 | trap &= ~0x00000100; |
| 1070 | } |
| 1071 | |
| 1072 | if (trap & 0x01000000) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1073 | u32 stat = nvkm_rd32(device, 0x400118); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1074 | for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1075 | u32 mask = 0x00000001 << gpc; |
| 1076 | if (stat & mask) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1077 | gf100_gr_trap_gpc(gr, gpc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1078 | nvkm_wr32(device, 0x400118, mask); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1079 | stat &= ~mask; |
| 1080 | } |
| 1081 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1082 | nvkm_wr32(device, 0x400108, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1083 | trap &= ~0x01000000; |
| 1084 | } |
| 1085 | |
| 1086 | if (trap & 0x02000000) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1087 | for (rop = 0; rop < gr->rop_nr; rop++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1088 | u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); |
| 1089 | u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1090 | nvkm_error(subdev, "ROP%d %08x %08x\n", |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1091 | rop, statz, statc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1092 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
| 1093 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1094 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1095 | nvkm_wr32(device, 0x400108, 0x02000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1096 | trap &= ~0x02000000; |
| 1097 | } |
| 1098 | |
| 1099 | if (trap) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1100 | nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1101 | nvkm_wr32(device, 0x400108, trap); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1102 | } |
| 1103 | } |
| 1104 | |
| 1105 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1106 | gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1107 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1108 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1109 | struct nvkm_device *device = subdev->device; |
| 1110 | nvkm_error(subdev, "%06x - done %08x\n", base, |
| 1111 | nvkm_rd32(device, base + 0x400)); |
| 1112 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, |
| 1113 | nvkm_rd32(device, base + 0x800), |
| 1114 | nvkm_rd32(device, base + 0x804), |
| 1115 | nvkm_rd32(device, base + 0x808), |
| 1116 | nvkm_rd32(device, base + 0x80c)); |
| 1117 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, |
| 1118 | nvkm_rd32(device, base + 0x810), |
| 1119 | nvkm_rd32(device, base + 0x814), |
| 1120 | nvkm_rd32(device, base + 0x818), |
| 1121 | nvkm_rd32(device, base + 0x81c)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1122 | } |
| 1123 | |
| 1124 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1125 | gf100_gr_ctxctl_debug(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1126 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1127 | struct nvkm_device *device = gr->base.engine.subdev.device; |
| 1128 | u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1129 | u32 gpc; |
| 1130 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1131 | gf100_gr_ctxctl_debug_unit(gr, 0x409000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1132 | for (gpc = 0; gpc < gpcnr; gpc++) |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1133 | gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1134 | } |
| 1135 | |
| 1136 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1137 | gf100_gr_ctxctl_isr(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1138 | { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1139 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1140 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1141 | u32 stat = nvkm_rd32(device, 0x409c18); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1142 | |
| 1143 | if (stat & 0x00000001) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1144 | u32 code = nvkm_rd32(device, 0x409814); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1145 | if (code == E_BAD_FWMTHD) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1146 | u32 class = nvkm_rd32(device, 0x409808); |
| 1147 | u32 addr = nvkm_rd32(device, 0x40980c); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1148 | u32 subc = (addr & 0x00070000) >> 16; |
| 1149 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1150 | u32 data = nvkm_rd32(device, 0x409810); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1151 | |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1152 | nvkm_error(subdev, "FECS MTHD subc %d class %04x " |
| 1153 | "mthd %04x data %08x\n", |
| 1154 | subc, class, mthd, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1155 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1156 | nvkm_wr32(device, 0x409c20, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1157 | stat &= ~0x00000001; |
| 1158 | } else { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1159 | nvkm_error(subdev, "FECS ucode error %d\n", code); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | if (stat & 0x00080000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1164 | nvkm_error(subdev, "FECS watchdog timeout\n"); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1165 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1166 | nvkm_wr32(device, 0x409c20, 0x00080000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1167 | stat &= ~0x00080000; |
| 1168 | } |
| 1169 | |
| 1170 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1171 | nvkm_error(subdev, "FECS %08x\n", stat); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1172 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1173 | nvkm_wr32(device, 0x409c20, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1174 | } |
| 1175 | } |
| 1176 | |
| 1177 | static void |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1178 | gf100_gr_intr(struct nvkm_gr *base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1179 | { |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1180 | struct gf100_gr *gr = gf100_gr(base); |
| 1181 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1182 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1183 | struct nvkm_fifo_chan *chan; |
| 1184 | unsigned long flags; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1185 | u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; |
| 1186 | u32 stat = nvkm_rd32(device, 0x400100); |
| 1187 | u32 addr = nvkm_rd32(device, 0x400704); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1188 | u32 mthd = (addr & 0x00003ffc); |
| 1189 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1190 | u32 data = nvkm_rd32(device, 0x400708); |
| 1191 | u32 code = nvkm_rd32(device, 0x400110); |
Ben Skeggs | 91c772e | 2015-04-13 13:09:28 +1000 | [diff] [blame] | 1192 | u32 class; |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1193 | const char *name = "unknown"; |
| 1194 | int chid = -1; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1195 | |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1196 | chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1197 | if (chan) { |
| 1198 | name = chan->object.client->name; |
| 1199 | chid = chan->chid; |
| 1200 | } |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1201 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1202 | if (device->card_type < NV_E0 || subc < 4) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1203 | class = nvkm_rd32(device, 0x404200 + (subc * 4)); |
Ben Skeggs | 91c772e | 2015-04-13 13:09:28 +1000 | [diff] [blame] | 1204 | else |
| 1205 | class = 0x0000; |
| 1206 | |
Lauri Peltonen | c6a7b02 | 2015-02-26 13:16:48 +0900 | [diff] [blame] | 1207 | if (stat & 0x00000001) { |
| 1208 | /* |
| 1209 | * notifier interrupt, only needed for cyclestats |
| 1210 | * can be safely ignored |
| 1211 | */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1212 | nvkm_wr32(device, 0x400100, 0x00000001); |
Lauri Peltonen | c6a7b02 | 2015-02-26 13:16:48 +0900 | [diff] [blame] | 1213 | stat &= ~0x00000001; |
| 1214 | } |
| 1215 | |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1216 | if (stat & 0x00000010) { |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1217 | if (!gf100_gr_mthd_sw(device, class, mthd, data)) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1218 | nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " |
| 1219 | "subc %d class %04x mthd %04x data %08x\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1220 | chid, inst << 12, name, subc, |
| 1221 | class, mthd, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1222 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1223 | nvkm_wr32(device, 0x400100, 0x00000010); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1224 | stat &= ~0x00000010; |
| 1225 | } |
| 1226 | |
| 1227 | if (stat & 0x00000020) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1228 | nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " |
| 1229 | "subc %d class %04x mthd %04x data %08x\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1230 | chid, inst << 12, name, subc, class, mthd, data); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1231 | nvkm_wr32(device, 0x400100, 0x00000020); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1232 | stat &= ~0x00000020; |
| 1233 | } |
| 1234 | |
| 1235 | if (stat & 0x00100000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1236 | const struct nvkm_enum *en = |
| 1237 | nvkm_enum_find(nv50_data_error_names, code); |
| 1238 | nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " |
| 1239 | "subc %d class %04x mthd %04x data %08x\n", |
| 1240 | code, en ? en->name : "", chid, inst << 12, |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1241 | name, subc, class, mthd, data); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1242 | nvkm_wr32(device, 0x400100, 0x00100000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1243 | stat &= ~0x00100000; |
| 1244 | } |
| 1245 | |
| 1246 | if (stat & 0x00200000) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1247 | nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", |
Ben Skeggs | 8f0649b | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1248 | chid, inst << 12, name); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1249 | gf100_gr_trap_intr(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1250 | nvkm_wr32(device, 0x400100, 0x00200000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1251 | stat &= ~0x00200000; |
| 1252 | } |
| 1253 | |
| 1254 | if (stat & 0x00080000) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1255 | gf100_gr_ctxctl_isr(gr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1256 | nvkm_wr32(device, 0x400100, 0x00080000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1257 | stat &= ~0x00080000; |
| 1258 | } |
| 1259 | |
| 1260 | if (stat) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1261 | nvkm_error(subdev, "intr %08x\n", stat); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1262 | nvkm_wr32(device, 0x400100, stat); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1263 | } |
| 1264 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1265 | nvkm_wr32(device, 0x400500, 0x00010001); |
Ben Skeggs | a65955e | 2015-08-20 14:54:18 +1000 | [diff] [blame] | 1266 | nvkm_fifo_chan_put(device->fifo, flags, &chan); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1267 | } |
| 1268 | |
| 1269 | void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1270 | gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1271 | struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1272 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1273 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1274 | int i; |
| 1275 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1276 | nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1277 | for (i = 0; i < data->size / 4; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1278 | nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1279 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1280 | nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1281 | for (i = 0; i < code->size / 4; i++) { |
| 1282 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1283 | nvkm_wr32(device, fuc_base + 0x0188, i >> 6); |
| 1284 | nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1285 | } |
| 1286 | |
| 1287 | /* code must be padded to 0x40 words */ |
| 1288 | for (; i & 0x3f; i++) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1289 | nvkm_wr32(device, fuc_base + 0x0184, 0); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1290 | } |
| 1291 | |
| 1292 | static void |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1293 | gf100_gr_init_csdata(struct gf100_gr *gr, |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1294 | const struct gf100_gr_pack *pack, |
| 1295 | u32 falcon, u32 starstar, u32 base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1296 | { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1297 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1298 | const struct gf100_gr_pack *iter; |
| 1299 | const struct gf100_gr_init *init; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1300 | u32 addr = ~0, prev = ~0, xfer = 0; |
| 1301 | u32 star, temp; |
| 1302 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1303 | nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); |
| 1304 | star = nvkm_rd32(device, falcon + 0x01c4); |
| 1305 | temp = nvkm_rd32(device, falcon + 0x01c4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1306 | if (temp > star) |
| 1307 | star = temp; |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1308 | nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1309 | |
| 1310 | pack_for_each_init(init, iter, pack) { |
| 1311 | u32 head = init->addr - base; |
| 1312 | u32 tail = head + init->count * init->pitch; |
| 1313 | while (head < tail) { |
| 1314 | if (head != prev + 4 || xfer >= 32) { |
| 1315 | if (xfer) { |
| 1316 | u32 data = ((--xfer << 26) | addr); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1317 | nvkm_wr32(device, falcon + 0x01c4, data); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1318 | star += 4; |
| 1319 | } |
| 1320 | addr = head; |
| 1321 | xfer = 0; |
| 1322 | } |
| 1323 | prev = head; |
| 1324 | xfer = xfer + 1; |
| 1325 | head = head + init->pitch; |
| 1326 | } |
| 1327 | } |
| 1328 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1329 | nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); |
| 1330 | nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); |
| 1331 | nvkm_wr32(device, falcon + 0x01c4, star + 4); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1332 | } |
| 1333 | |
| 1334 | int |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1335 | gf100_gr_init_ctxctl(struct gf100_gr *gr) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1336 | { |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1337 | const struct gf100_grctx_func *grctx = gr->func->grctx; |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1338 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1339 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1340 | int i; |
| 1341 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1342 | if (gr->firmware) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1343 | /* load fuc microcode */ |
Ben Skeggs | 54dcadd | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 1344 | nvkm_mc_unk260(device->mc, 0); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1345 | gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); |
| 1346 | gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); |
Ben Skeggs | 54dcadd | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 1347 | nvkm_mc_unk260(device->mc, 1); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1348 | |
| 1349 | /* start both of them running */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1350 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1351 | nvkm_wr32(device, 0x41a10c, 0x00000000); |
| 1352 | nvkm_wr32(device, 0x40910c, 0x00000000); |
| 1353 | nvkm_wr32(device, 0x41a100, 0x00000002); |
| 1354 | nvkm_wr32(device, 0x409100, 0x00000002); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1355 | if (nvkm_msec(device, 2000, |
| 1356 | if (nvkm_rd32(device, 0x409800) & 0x00000001) |
| 1357 | break; |
| 1358 | ) < 0) |
| 1359 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1360 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1361 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1362 | nvkm_wr32(device, 0x409500, 0x7fffffff); |
| 1363 | nvkm_wr32(device, 0x409504, 0x00000021); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1364 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1365 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1366 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1367 | nvkm_wr32(device, 0x409504, 0x00000010); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1368 | if (nvkm_msec(device, 2000, |
| 1369 | if ((gr->size = nvkm_rd32(device, 0x409800))) |
| 1370 | break; |
| 1371 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1372 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1373 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1374 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1375 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1376 | nvkm_wr32(device, 0x409504, 0x00000016); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1377 | if (nvkm_msec(device, 2000, |
| 1378 | if (nvkm_rd32(device, 0x409800)) |
| 1379 | break; |
| 1380 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1381 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1382 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1383 | nvkm_wr32(device, 0x409840, 0xffffffff); |
| 1384 | nvkm_wr32(device, 0x409500, 0x00000000); |
| 1385 | nvkm_wr32(device, 0x409504, 0x00000025); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1386 | if (nvkm_msec(device, 2000, |
| 1387 | if (nvkm_rd32(device, 0x409800)) |
| 1388 | break; |
| 1389 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1390 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1391 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1392 | if (device->chipset >= 0xe0) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1393 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1394 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1395 | nvkm_wr32(device, 0x409504, 0x00000030); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1396 | if (nvkm_msec(device, 2000, |
| 1397 | if (nvkm_rd32(device, 0x409800)) |
| 1398 | break; |
| 1399 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1400 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1401 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1402 | nvkm_wr32(device, 0x409810, 0xb00095c8); |
| 1403 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1404 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1405 | nvkm_wr32(device, 0x409504, 0x00000031); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1406 | if (nvkm_msec(device, 2000, |
| 1407 | if (nvkm_rd32(device, 0x409800)) |
| 1408 | break; |
| 1409 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1410 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1411 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1412 | nvkm_wr32(device, 0x409810, 0x00080420); |
| 1413 | nvkm_wr32(device, 0x409800, 0x00000000); |
| 1414 | nvkm_wr32(device, 0x409500, 0x00000001); |
| 1415 | nvkm_wr32(device, 0x409504, 0x00000032); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1416 | if (nvkm_msec(device, 2000, |
| 1417 | if (nvkm_rd32(device, 0x409800)) |
| 1418 | break; |
| 1419 | ) < 0) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1420 | return -EBUSY; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1421 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1422 | nvkm_wr32(device, 0x409614, 0x00000070); |
| 1423 | nvkm_wr32(device, 0x409614, 0x00000770); |
| 1424 | nvkm_wr32(device, 0x40802c, 0x00000001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1425 | } |
| 1426 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1427 | if (gr->data == NULL) { |
| 1428 | int ret = gf100_grctx_generate(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1429 | if (ret) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1430 | nvkm_error(subdev, "failed to construct context\n"); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1431 | return ret; |
| 1432 | } |
| 1433 | } |
| 1434 | |
| 1435 | return 0; |
| 1436 | } else |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1437 | if (!gr->func->fecs.ucode) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1438 | return -ENOSYS; |
| 1439 | } |
| 1440 | |
| 1441 | /* load HUB microcode */ |
Ben Skeggs | 54dcadd | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 1442 | nvkm_mc_unk260(device->mc, 0); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1443 | nvkm_wr32(device, 0x4091c0, 0x01000000); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1444 | for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) |
| 1445 | nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1446 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1447 | nvkm_wr32(device, 0x409180, 0x01000000); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1448 | for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1449 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1450 | nvkm_wr32(device, 0x409188, i >> 6); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1451 | nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1452 | } |
| 1453 | |
| 1454 | /* load GPC microcode */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1455 | nvkm_wr32(device, 0x41a1c0, 0x01000000); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1456 | for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) |
| 1457 | nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1458 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1459 | nvkm_wr32(device, 0x41a180, 0x01000000); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1460 | for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1461 | if ((i & 0x3f) == 0) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1462 | nvkm_wr32(device, 0x41a188, i >> 6); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1463 | nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1464 | } |
Ben Skeggs | 54dcadd | 2015-08-20 14:54:21 +1000 | [diff] [blame] | 1465 | nvkm_mc_unk260(device->mc, 1); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1466 | |
| 1467 | /* load register lists */ |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1468 | gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); |
| 1469 | gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); |
| 1470 | gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); |
| 1471 | gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1472 | |
| 1473 | /* start HUB ucode running, it'll init the GPCs */ |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1474 | nvkm_wr32(device, 0x40910c, 0x00000000); |
| 1475 | nvkm_wr32(device, 0x409100, 0x00000002); |
Ben Skeggs | c4584ad | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 1476 | if (nvkm_msec(device, 2000, |
| 1477 | if (nvkm_rd32(device, 0x409800) & 0x80000000) |
| 1478 | break; |
| 1479 | ) < 0) { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1480 | gf100_gr_ctxctl_debug(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1481 | return -EBUSY; |
| 1482 | } |
| 1483 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1484 | gr->size = nvkm_rd32(device, 0x409804); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1485 | if (gr->data == NULL) { |
| 1486 | int ret = gf100_grctx_generate(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1487 | if (ret) { |
Ben Skeggs | 109c2f2 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 1488 | nvkm_error(subdev, "failed to construct context\n"); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1489 | return ret; |
| 1490 | } |
| 1491 | } |
| 1492 | |
| 1493 | return 0; |
| 1494 | } |
| 1495 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1496 | static int |
| 1497 | gf100_gr_oneinit(struct nvkm_gr *base) |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1498 | { |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1499 | struct gf100_gr *gr = gf100_gr(base); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1500 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1501 | int ret, i, j; |
| 1502 | |
| 1503 | nvkm_pmu_pgob(device->pmu, false); |
| 1504 | |
| 1505 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, |
| 1506 | &gr->unk4188b4); |
| 1507 | if (ret) |
| 1508 | return ret; |
| 1509 | |
| 1510 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, |
| 1511 | &gr->unk4188b8); |
| 1512 | if (ret) |
| 1513 | return ret; |
| 1514 | |
| 1515 | nvkm_kmap(gr->unk4188b4); |
| 1516 | for (i = 0; i < 0x1000; i += 4) |
| 1517 | nvkm_wo32(gr->unk4188b4, i, 0x00000010); |
| 1518 | nvkm_done(gr->unk4188b4); |
| 1519 | |
| 1520 | nvkm_kmap(gr->unk4188b8); |
| 1521 | for (i = 0; i < 0x1000; i += 4) |
| 1522 | nvkm_wo32(gr->unk4188b8, i, 0x00000010); |
| 1523 | nvkm_done(gr->unk4188b8); |
| 1524 | |
| 1525 | gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; |
| 1526 | gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; |
| 1527 | for (i = 0; i < gr->gpc_nr; i++) { |
| 1528 | gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); |
| 1529 | gr->tpc_total += gr->tpc_nr[i]; |
| 1530 | gr->ppc_nr[i] = gr->func->ppc_nr; |
| 1531 | for (j = 0; j < gr->ppc_nr[i]; j++) { |
| 1532 | u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); |
Ben Skeggs | 2fb2b3c | 2015-11-23 05:47:19 +1000 | [diff] [blame] | 1533 | if (mask) |
| 1534 | gr->ppc_mask[i] |= (1 << j); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1535 | gr->ppc_tpc_nr[i][j] = hweight8(mask); |
| 1536 | } |
| 1537 | } |
| 1538 | |
| 1539 | /*XXX: these need figuring out... though it might not even matter */ |
| 1540 | switch (device->chipset) { |
| 1541 | case 0xc0: |
| 1542 | if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ |
| 1543 | gr->magic_not_rop_nr = 0x07; |
| 1544 | } else |
| 1545 | if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ |
| 1546 | gr->magic_not_rop_nr = 0x05; |
| 1547 | } else |
| 1548 | if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ |
| 1549 | gr->magic_not_rop_nr = 0x06; |
| 1550 | } |
| 1551 | break; |
| 1552 | case 0xc3: /* 450, 4/0/0/0, 2 */ |
| 1553 | gr->magic_not_rop_nr = 0x03; |
| 1554 | break; |
| 1555 | case 0xc4: /* 460, 3/4/0/0, 4 */ |
| 1556 | gr->magic_not_rop_nr = 0x01; |
| 1557 | break; |
| 1558 | case 0xc1: /* 2/0/0/0, 1 */ |
| 1559 | gr->magic_not_rop_nr = 0x01; |
| 1560 | break; |
| 1561 | case 0xc8: /* 4/4/3/4, 5 */ |
| 1562 | gr->magic_not_rop_nr = 0x06; |
| 1563 | break; |
| 1564 | case 0xce: /* 4/4/0/0, 4 */ |
| 1565 | gr->magic_not_rop_nr = 0x03; |
| 1566 | break; |
| 1567 | case 0xcf: /* 4/0/0/0, 3 */ |
| 1568 | gr->magic_not_rop_nr = 0x03; |
| 1569 | break; |
| 1570 | case 0xd7: |
| 1571 | case 0xd9: /* 1/0/0/0, 1 */ |
| 1572 | case 0xea: /* gk20a */ |
| 1573 | case 0x12b: /* gm20b */ |
| 1574 | gr->magic_not_rop_nr = 0x01; |
| 1575 | break; |
| 1576 | } |
| 1577 | |
| 1578 | return 0; |
| 1579 | } |
| 1580 | |
| 1581 | int |
| 1582 | gf100_gr_init_(struct nvkm_gr *base) |
| 1583 | { |
| 1584 | struct gf100_gr *gr = gf100_gr(base); |
| 1585 | nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); |
| 1586 | return gr->func->init(gr); |
| 1587 | } |
| 1588 | |
| 1589 | void |
| 1590 | gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) |
| 1591 | { |
| 1592 | kfree(fuc->data); |
| 1593 | fuc->data = NULL; |
| 1594 | } |
| 1595 | |
| 1596 | void * |
| 1597 | gf100_gr_dtor(struct nvkm_gr *base) |
| 1598 | { |
| 1599 | struct gf100_gr *gr = gf100_gr(base); |
| 1600 | |
| 1601 | if (gr->func->dtor) |
| 1602 | gr->func->dtor(gr); |
| 1603 | kfree(gr->data); |
| 1604 | |
| 1605 | gf100_gr_dtor_fw(&gr->fuc409c); |
| 1606 | gf100_gr_dtor_fw(&gr->fuc409d); |
| 1607 | gf100_gr_dtor_fw(&gr->fuc41ac); |
| 1608 | gf100_gr_dtor_fw(&gr->fuc41ad); |
| 1609 | |
| 1610 | nvkm_memory_del(&gr->unk4188b8); |
| 1611 | nvkm_memory_del(&gr->unk4188b4); |
| 1612 | return gr; |
| 1613 | } |
| 1614 | |
| 1615 | static const struct nvkm_gr_func |
| 1616 | gf100_gr_ = { |
| 1617 | .dtor = gf100_gr_dtor, |
| 1618 | .oneinit = gf100_gr_oneinit, |
| 1619 | .init = gf100_gr_init_, |
| 1620 | .intr = gf100_gr_intr, |
| 1621 | .units = gf100_gr_units, |
| 1622 | .chan_new = gf100_gr_chan_new, |
| 1623 | .object_get = gf100_gr_object_get, |
| 1624 | }; |
| 1625 | |
| 1626 | int |
| 1627 | gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, |
| 1628 | struct gf100_gr_fuc *fuc) |
| 1629 | { |
| 1630 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
| 1631 | struct nvkm_device *device = subdev->device; |
| 1632 | const struct firmware *fw; |
| 1633 | char f[64]; |
| 1634 | char cname[16]; |
| 1635 | int ret; |
| 1636 | int i; |
| 1637 | |
| 1638 | /* Convert device name to lowercase */ |
| 1639 | strncpy(cname, device->chip->name, sizeof(cname)); |
| 1640 | cname[sizeof(cname) - 1] = '\0'; |
| 1641 | i = strlen(cname); |
| 1642 | while (i) { |
| 1643 | --i; |
| 1644 | cname[i] = tolower(cname[i]); |
| 1645 | } |
| 1646 | |
| 1647 | snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); |
Ben Skeggs | 26c9e8e | 2015-08-20 14:54:23 +1000 | [diff] [blame] | 1648 | ret = request_firmware(&fw, f, device->dev); |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1649 | if (ret) { |
| 1650 | nvkm_error(subdev, "failed to load %s\n", fwname); |
| 1651 | return ret; |
| 1652 | } |
| 1653 | |
| 1654 | fuc->size = fw->size; |
| 1655 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); |
| 1656 | release_firmware(fw); |
| 1657 | return (fuc->data != NULL) ? 0 : -ENOMEM; |
| 1658 | } |
| 1659 | |
| 1660 | int |
| 1661 | gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, |
| 1662 | int index, struct gf100_gr *gr) |
| 1663 | { |
| 1664 | int ret; |
| 1665 | |
| 1666 | gr->func = func; |
| 1667 | gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", |
| 1668 | func->fecs.ucode == NULL); |
| 1669 | |
| 1670 | ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, |
| 1671 | gr->firmware || func->fecs.ucode != NULL, |
| 1672 | &gr->base); |
| 1673 | if (ret) |
| 1674 | return ret; |
| 1675 | |
| 1676 | if (gr->firmware) { |
| 1677 | nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); |
| 1678 | if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || |
| 1679 | gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || |
| 1680 | gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || |
| 1681 | gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) |
| 1682 | return -ENODEV; |
| 1683 | } |
| 1684 | |
| 1685 | return 0; |
| 1686 | } |
| 1687 | |
| 1688 | int |
| 1689 | gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, |
| 1690 | int index, struct nvkm_gr **pgr) |
| 1691 | { |
| 1692 | struct gf100_gr *gr; |
| 1693 | if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) |
| 1694 | return -ENOMEM; |
| 1695 | *pgr = &gr->base; |
| 1696 | return gf100_gr_ctor(func, device, index, gr); |
| 1697 | } |
| 1698 | |
| 1699 | int |
| 1700 | gf100_gr_init(struct gf100_gr *gr) |
| 1701 | { |
| 1702 | struct nvkm_device *device = gr->base.engine.subdev.device; |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1703 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1704 | u32 data[TPC_MAX / 8] = {}; |
| 1705 | u8 tpcnr[GPC_MAX]; |
| 1706 | int gpc, tpc, rop; |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1707 | int i; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1708 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1709 | nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); |
| 1710 | nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); |
| 1711 | nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); |
| 1712 | nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); |
| 1713 | nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); |
| 1714 | nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); |
Ben Skeggs | 227c95d | 2015-08-20 14:54:17 +1000 | [diff] [blame] | 1715 | nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); |
| 1716 | nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1717 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1718 | gf100_gr_mmio(gr, gr->func->mmio); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1719 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1720 | memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); |
| 1721 | for (i = 0, gpc = -1; i < gr->tpc_total; i++) { |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1722 | do { |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1723 | gpc = (gpc + 1) % gr->gpc_nr; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1724 | } while (!tpcnr[gpc]); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1725 | tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1726 | |
| 1727 | data[i / 8] |= tpc << ((i % 8) * 4); |
| 1728 | } |
| 1729 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1730 | nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); |
| 1731 | nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); |
| 1732 | nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); |
| 1733 | nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1734 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1735 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1736 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1737 | gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1738 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1739 | gr->tpc_total); |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1740 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1741 | } |
| 1742 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1743 | if (device->chipset != 0xd7) |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1744 | nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1745 | else |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1746 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1747 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1748 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1749 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1750 | nvkm_wr32(device, 0x400500, 0x00010001); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1751 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1752 | nvkm_wr32(device, 0x400100, 0xffffffff); |
| 1753 | nvkm_wr32(device, 0x40013c, 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1754 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1755 | nvkm_wr32(device, 0x409c24, 0x000f0000); |
| 1756 | nvkm_wr32(device, 0x404000, 0xc0000000); |
| 1757 | nvkm_wr32(device, 0x404600, 0xc0000000); |
| 1758 | nvkm_wr32(device, 0x408030, 0xc0000000); |
| 1759 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
| 1760 | nvkm_wr32(device, 0x404490, 0xc0000000); |
| 1761 | nvkm_wr32(device, 0x406018, 0xc0000000); |
| 1762 | nvkm_wr32(device, 0x405840, 0xc0000000); |
| 1763 | nvkm_wr32(device, 0x405844, 0x00ffffff); |
| 1764 | nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); |
| 1765 | nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1766 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1767 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1768 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
| 1769 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
| 1770 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
| 1771 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1772 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1773 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); |
| 1774 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); |
| 1775 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); |
| 1776 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); |
| 1777 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); |
| 1778 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); |
| 1779 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1780 | } |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1781 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
| 1782 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1783 | } |
| 1784 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1785 | for (rop = 0; rop < gr->rop_nr; rop++) { |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1786 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
| 1787 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
| 1788 | nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); |
| 1789 | nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1790 | } |
| 1791 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1792 | nvkm_wr32(device, 0x400108, 0xffffffff); |
| 1793 | nvkm_wr32(device, 0x400138, 0xffffffff); |
| 1794 | nvkm_wr32(device, 0x400118, 0xffffffff); |
| 1795 | nvkm_wr32(device, 0x400130, 0xffffffff); |
| 1796 | nvkm_wr32(device, 0x40011c, 0xffffffff); |
| 1797 | nvkm_wr32(device, 0x400134, 0xffffffff); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1798 | |
Ben Skeggs | 276836d | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 1799 | nvkm_wr32(device, 0x400054, 0x34ce3464); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1800 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1801 | gf100_gr_zbc_init(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1802 | |
Ben Skeggs | bfee3f3 | 2015-08-20 14:54:08 +1000 | [diff] [blame] | 1803 | return gf100_gr_init_ctxctl(gr); |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1804 | } |
| 1805 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1806 | #include "fuc/hubgf100.fuc3.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1807 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1808 | struct gf100_gr_ucode |
| 1809 | gf100_gr_fecs_ucode = { |
| 1810 | .code.data = gf100_grhub_code, |
| 1811 | .code.size = sizeof(gf100_grhub_code), |
| 1812 | .data.data = gf100_grhub_data, |
| 1813 | .data.size = sizeof(gf100_grhub_data), |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1814 | }; |
| 1815 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1816 | #include "fuc/gpcgf100.fuc3.h" |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1817 | |
Ben Skeggs | e3c71eb | 2015-01-14 15:29:43 +1000 | [diff] [blame] | 1818 | struct gf100_gr_ucode |
| 1819 | gf100_gr_gpccs_ucode = { |
| 1820 | .code.data = gf100_grgpc_code, |
| 1821 | .code.size = sizeof(gf100_grgpc_code), |
| 1822 | .data.data = gf100_grgpc_data, |
| 1823 | .data.size = sizeof(gf100_grgpc_data), |
Ben Skeggs | c39f472 | 2015-01-13 22:13:14 +1000 | [diff] [blame] | 1824 | }; |
| 1825 | |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1826 | static const struct gf100_gr_func |
| 1827 | gf100_gr = { |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1828 | .init = gf100_gr_init, |
| 1829 | .mmio = gf100_gr_pack_mmio, |
| 1830 | .fecs.ucode = &gf100_gr_fecs_ucode, |
| 1831 | .gpccs.ucode = &gf100_gr_gpccs_ucode, |
Ben Skeggs | 27f3d6c | 2015-08-20 14:54:19 +1000 | [diff] [blame] | 1832 | .grctx = &gf100_grctx, |
| 1833 | .sclass = { |
| 1834 | { -1, -1, FERMI_TWOD_A }, |
| 1835 | { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, |
| 1836 | { -1, -1, FERMI_A, &gf100_fermi }, |
| 1837 | { -1, -1, FERMI_COMPUTE_A }, |
| 1838 | {} |
| 1839 | } |
| 1840 | }; |
| 1841 | |
Ben Skeggs | c85ee6c | 2015-08-20 14:54:22 +1000 | [diff] [blame] | 1842 | int |
| 1843 | gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) |
| 1844 | { |
| 1845 | return gf100_gr_new_(&gf100_gr, device, index, pgr); |
| 1846 | } |