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Marc Zyngier092bd142012-12-17 17:07:52 +00001/*
2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/linkage.h>
19
20#include <asm/assembler.h>
21#include <asm/kvm_arm.h>
22#include <asm/kvm_mmu.h>
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000023#include <asm/pgtable-hwdef.h>
Geoff Levande7227d02016-04-27 17:47:01 +010024#include <asm/sysreg.h>
Marc Zyngier092bd142012-12-17 17:07:52 +000025
26 .text
27 .pushsection .hyp.idmap.text, "ax"
28
29 .align 11
30
31ENTRY(__kvm_hyp_init)
32 ventry __invalid // Synchronous EL2t
33 ventry __invalid // IRQ EL2t
34 ventry __invalid // FIQ EL2t
35 ventry __invalid // Error EL2t
36
37 ventry __invalid // Synchronous EL2h
38 ventry __invalid // IRQ EL2h
39 ventry __invalid // FIQ EL2h
40 ventry __invalid // Error EL2h
41
42 ventry __do_hyp_init // Synchronous 64-bit EL1
43 ventry __invalid // IRQ 64-bit EL1
44 ventry __invalid // FIQ 64-bit EL1
45 ventry __invalid // Error 64-bit EL1
46
47 ventry __invalid // Synchronous 32-bit EL1
48 ventry __invalid // IRQ 32-bit EL1
49 ventry __invalid // FIQ 32-bit EL1
50 ventry __invalid // Error 32-bit EL1
51
52__invalid:
53 b .
54
55 /*
Marc Zyngier3421e9d2016-06-30 18:40:44 +010056 * x0: HYP pgd
57 * x1: HYP stack
58 * x2: HYP vectors
Marc Zyngier092bd142012-12-17 17:07:52 +000059 */
60__do_hyp_init:
61
62 msr ttbr0_el2, x0
63
64 mrs x4, tcr_el1
65 ldr x5, =TCR_EL2_MASK
66 and x4, x4, x5
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -080067 mov x5, #TCR_EL2_RES1
Marc Zyngier092bd142012-12-17 17:07:52 +000068 orr x4, x4, x5
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000069
70#ifndef CONFIG_ARM64_VA_BITS_48
71 /*
72 * If we are running with VA_BITS < 48, we may be running with an extra
73 * level of translation in the ID map. This is only the case if system
74 * RAM is out of range for the currently configured page size and number
75 * of translation levels, in which case we will also need the extra
76 * level for the HYP ID map, or we won't be able to enable the EL2 MMU.
77 *
78 * However, at EL2, there is only one TTBR register, and we can't switch
79 * between translation tables *and* update TCR_EL2.T0SZ at the same
80 * time. Bottom line: we need the extra level in *both* our translation
81 * tables.
82 *
83 * So use the same T0SZ value we use for the ID map.
84 */
85 ldr_l x5, idmap_t0sz
86 bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
87#endif
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -080088 /*
89 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
Marc Zyngier3a3604b2015-01-29 13:19:45 +000090 * TCR_EL2.
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -080091 */
92 mrs x5, ID_AA64MMFR0_EL1
93 bfi x4, x5, #16, #3
94
Marc Zyngier092bd142012-12-17 17:07:52 +000095 msr tcr_el2, x4
96
Marc Zyngier092bd142012-12-17 17:07:52 +000097 mrs x4, mair_el1
98 msr mair_el2, x4
99 isb
100
Pranavkumar Sawargaonkarf6edbbf2014-07-31 12:23:23 +0530101 /* Invalidate the stale TLBs from Bootloader */
102 tlbi alle2
103 dsb sy
104
Marc Zyngierb9824dd2017-06-06 19:08:33 +0100105 /*
106 * Preserve all the RES1 bits while setting the default flags,
Marc Zyngier8abce1e2017-06-06 19:08:34 +0100107 * as well as the EE bit on BE. Drop the A flag since the compiler
108 * is allowed to generate unaligned accesses.
Marc Zyngierb9824dd2017-06-06 19:08:33 +0100109 */
Marc Zyngier8abce1e2017-06-06 19:08:34 +0100110 ldr x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
Marc Zyngierb9824dd2017-06-06 19:08:33 +0100111CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
Marc Zyngier092bd142012-12-17 17:07:52 +0000112 msr sctlr_el2, x4
113 isb
114
Marc Zyngier092bd142012-12-17 17:07:52 +0000115 /* Set the stack and new vectors */
Marc Zyngier3421e9d2016-06-30 18:40:44 +0100116 kern_hyp_va x1
117 mov sp, x1
Marc Zyngier092bd142012-12-17 17:07:52 +0000118 kern_hyp_va x2
Marc Zyngier3421e9d2016-06-30 18:40:44 +0100119 msr vbar_el2, x2
Marc Zyngier092bd142012-12-17 17:07:52 +0000120
121 /* Hello, World! */
122 eret
123ENDPROC(__kvm_hyp_init)
124
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100125 /*
Marc Zyngier3421e9d2016-06-30 18:40:44 +0100126 * Reset kvm back to the hyp stub.
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100127 */
128ENTRY(__kvm_hyp_reset)
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100129 /* We're now in idmap, disable MMU */
Marc Zyngier3421e9d2016-06-30 18:40:44 +0100130 mrs x0, sctlr_el2
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100131 ldr x1, =SCTLR_ELx_FLAGS
132 bic x0, x0, x1 // Clear SCTL_M and etc
133 msr sctlr_el2, x0
134 isb
135
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100136 /* Install stub vectors */
137 adr_l x0, __hyp_stub_vectors
138 msr vbar_el2, x0
139
140 eret
141ENDPROC(__kvm_hyp_reset)
142
Marc Zyngier092bd142012-12-17 17:07:52 +0000143 .ltorg
144
145 .popsection