Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * OMAP DMAengine support |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 8 | #include <linux/delay.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 9 | #include <linux/dmaengine.h> |
| 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/err.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/list.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/omap-dma.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/spinlock.h> |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 20 | #include <linux/of_dma.h> |
| 21 | #include <linux/of_device.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 22 | |
| 23 | #include "virt-dma.h" |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 24 | |
Peter Ujfalusi | 341ce71 | 2015-04-09 12:35:50 +0300 | [diff] [blame] | 25 | #define OMAP_SDMA_REQUESTS 127 |
| 26 | #define OMAP_SDMA_CHANNELS 32 |
| 27 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 28 | struct omap_dmadev { |
| 29 | struct dma_device ddev; |
| 30 | spinlock_t lock; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 31 | void __iomem *base; |
| 32 | const struct omap_dma_reg *reg_map; |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 33 | struct omap_system_dma_plat_info *plat; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 34 | bool legacy; |
Peter Ujfalusi | de50608 | 2015-04-09 12:35:51 +0300 | [diff] [blame] | 35 | unsigned dma_requests; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 36 | spinlock_t irq_lock; |
| 37 | uint32_t irq_enable_mask; |
Peter Ujfalusi | 341ce71 | 2015-04-09 12:35:50 +0300 | [diff] [blame] | 38 | struct omap_chan *lch_map[OMAP_SDMA_CHANNELS]; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | struct omap_chan { |
| 42 | struct virt_dma_chan vc; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 43 | void __iomem *channel_base; |
| 44 | const struct omap_dma_reg *reg_map; |
Russell King | aa4c5b9 | 2014-01-14 23:58:10 +0000 | [diff] [blame] | 45 | uint32_t ccr; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 46 | |
| 47 | struct dma_slave_config cfg; |
| 48 | unsigned dma_sig; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 49 | bool cyclic; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 50 | bool paused; |
Peter Ujfalusi | 689d3c5 | 2016-04-05 15:20:20 +0300 | [diff] [blame] | 51 | bool running; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 52 | |
| 53 | int dma_ch; |
| 54 | struct omap_desc *desc; |
| 55 | unsigned sgidx; |
| 56 | }; |
| 57 | |
| 58 | struct omap_sg { |
| 59 | dma_addr_t addr; |
| 60 | uint32_t en; /* number of elements (24-bit) */ |
| 61 | uint32_t fn; /* number of frames (16-bit) */ |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 62 | int32_t fi; /* for double indexing */ |
| 63 | int16_t ei; /* for double indexing */ |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | struct omap_desc { |
| 67 | struct virt_dma_desc vd; |
| 68 | enum dma_transfer_direction dir; |
| 69 | dma_addr_t dev_addr; |
| 70 | |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 71 | int32_t fi; /* for OMAP_DMA_SYNC_PACKET / double indexing */ |
| 72 | int16_t ei; /* for double indexing */ |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 73 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 74 | uint32_t ccr; /* CCR value */ |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 75 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 76 | uint16_t cicr; /* CICR value */ |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 77 | uint32_t csdp; /* CSDP value */ |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 78 | |
| 79 | unsigned sglen; |
| 80 | struct omap_sg sg[0]; |
| 81 | }; |
| 82 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 83 | enum { |
| 84 | CCR_FS = BIT(5), |
| 85 | CCR_READ_PRIORITY = BIT(6), |
| 86 | CCR_ENABLE = BIT(7), |
| 87 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ |
| 88 | CCR_REPEAT = BIT(9), /* OMAP1 only */ |
| 89 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ |
| 90 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ |
| 91 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ |
| 92 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ |
| 93 | CCR_SRC_AMODE_CONSTANT = 0 << 12, |
| 94 | CCR_SRC_AMODE_POSTINC = 1 << 12, |
| 95 | CCR_SRC_AMODE_SGLIDX = 2 << 12, |
| 96 | CCR_SRC_AMODE_DBLIDX = 3 << 12, |
| 97 | CCR_DST_AMODE_CONSTANT = 0 << 14, |
| 98 | CCR_DST_AMODE_POSTINC = 1 << 14, |
| 99 | CCR_DST_AMODE_SGLIDX = 2 << 14, |
| 100 | CCR_DST_AMODE_DBLIDX = 3 << 14, |
| 101 | CCR_CONSTANT_FILL = BIT(16), |
| 102 | CCR_TRANSPARENT_COPY = BIT(17), |
| 103 | CCR_BS = BIT(18), |
| 104 | CCR_SUPERVISOR = BIT(22), |
| 105 | CCR_PREFETCH = BIT(23), |
| 106 | CCR_TRIGGER_SRC = BIT(24), |
| 107 | CCR_BUFFERING_DISABLE = BIT(25), |
| 108 | CCR_WRITE_PRIORITY = BIT(26), |
| 109 | CCR_SYNC_ELEMENT = 0, |
| 110 | CCR_SYNC_FRAME = CCR_FS, |
| 111 | CCR_SYNC_BLOCK = CCR_BS, |
| 112 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, |
| 113 | |
| 114 | CSDP_DATA_TYPE_8 = 0, |
| 115 | CSDP_DATA_TYPE_16 = 1, |
| 116 | CSDP_DATA_TYPE_32 = 2, |
| 117 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ |
| 118 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ |
| 119 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ |
| 120 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ |
| 121 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ |
| 122 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ |
| 123 | CSDP_SRC_PACKED = BIT(6), |
| 124 | CSDP_SRC_BURST_1 = 0 << 7, |
| 125 | CSDP_SRC_BURST_16 = 1 << 7, |
| 126 | CSDP_SRC_BURST_32 = 2 << 7, |
| 127 | CSDP_SRC_BURST_64 = 3 << 7, |
| 128 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ |
| 129 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ |
| 130 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ |
| 131 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ |
| 132 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ |
| 133 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ |
| 134 | CSDP_DST_PACKED = BIT(13), |
| 135 | CSDP_DST_BURST_1 = 0 << 14, |
| 136 | CSDP_DST_BURST_16 = 1 << 14, |
| 137 | CSDP_DST_BURST_32 = 2 << 14, |
| 138 | CSDP_DST_BURST_64 = 3 << 14, |
| 139 | |
| 140 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ |
| 141 | CICR_DROP_IE = BIT(1), |
| 142 | CICR_HALF_IE = BIT(2), |
| 143 | CICR_FRAME_IE = BIT(3), |
| 144 | CICR_LAST_IE = BIT(4), |
| 145 | CICR_BLOCK_IE = BIT(5), |
| 146 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ |
| 147 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ |
| 148 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ |
| 149 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ |
| 150 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ |
| 151 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ |
| 152 | |
| 153 | CLNK_CTRL_ENABLE_LNK = BIT(15), |
| 154 | }; |
| 155 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 156 | static const unsigned es_bytes[] = { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 157 | [CSDP_DATA_TYPE_8] = 1, |
| 158 | [CSDP_DATA_TYPE_16] = 2, |
| 159 | [CSDP_DATA_TYPE_32] = 4, |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 160 | }; |
| 161 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 162 | static struct of_dma_filter_info omap_dma_info = { |
| 163 | .filter_fn = omap_dma_filter_fn, |
| 164 | }; |
| 165 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 166 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
| 167 | { |
| 168 | return container_of(d, struct omap_dmadev, ddev); |
| 169 | } |
| 170 | |
| 171 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) |
| 172 | { |
| 173 | return container_of(c, struct omap_chan, vc.chan); |
| 174 | } |
| 175 | |
| 176 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) |
| 177 | { |
| 178 | return container_of(t, struct omap_desc, vd.tx); |
| 179 | } |
| 180 | |
| 181 | static void omap_dma_desc_free(struct virt_dma_desc *vd) |
| 182 | { |
| 183 | kfree(container_of(vd, struct omap_desc, vd)); |
| 184 | } |
| 185 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 186 | static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) |
| 187 | { |
| 188 | switch (type) { |
| 189 | case OMAP_DMA_REG_16BIT: |
| 190 | writew_relaxed(val, addr); |
| 191 | break; |
| 192 | case OMAP_DMA_REG_2X16BIT: |
| 193 | writew_relaxed(val, addr); |
| 194 | writew_relaxed(val >> 16, addr + 2); |
| 195 | break; |
| 196 | case OMAP_DMA_REG_32BIT: |
| 197 | writel_relaxed(val, addr); |
| 198 | break; |
| 199 | default: |
| 200 | WARN_ON(1); |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | static unsigned omap_dma_read(unsigned type, void __iomem *addr) |
| 205 | { |
| 206 | unsigned val; |
| 207 | |
| 208 | switch (type) { |
| 209 | case OMAP_DMA_REG_16BIT: |
| 210 | val = readw_relaxed(addr); |
| 211 | break; |
| 212 | case OMAP_DMA_REG_2X16BIT: |
| 213 | val = readw_relaxed(addr); |
| 214 | val |= readw_relaxed(addr + 2) << 16; |
| 215 | break; |
| 216 | case OMAP_DMA_REG_32BIT: |
| 217 | val = readl_relaxed(addr); |
| 218 | break; |
| 219 | default: |
| 220 | WARN_ON(1); |
| 221 | val = 0; |
| 222 | } |
| 223 | |
| 224 | return val; |
| 225 | } |
| 226 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 227 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
| 228 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 229 | const struct omap_dma_reg *r = od->reg_map + reg; |
| 230 | |
| 231 | WARN_ON(r->stride); |
| 232 | |
| 233 | omap_dma_write(val, r->type, od->base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 234 | } |
| 235 | |
| 236 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) |
| 237 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 238 | const struct omap_dma_reg *r = od->reg_map + reg; |
| 239 | |
| 240 | WARN_ON(r->stride); |
| 241 | |
| 242 | return omap_dma_read(r->type, od->base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) |
| 246 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 247 | const struct omap_dma_reg *r = c->reg_map + reg; |
| 248 | |
| 249 | omap_dma_write(val, r->type, c->channel_base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) |
| 253 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 254 | const struct omap_dma_reg *r = c->reg_map + reg; |
| 255 | |
| 256 | return omap_dma_read(r->type, c->channel_base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 257 | } |
| 258 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 259 | static void omap_dma_clear_csr(struct omap_chan *c) |
| 260 | { |
| 261 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 262 | omap_dma_chan_read(c, CSR); |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 263 | else |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 264 | omap_dma_chan_write(c, CSR, ~0); |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 265 | } |
| 266 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 267 | static unsigned omap_dma_get_csr(struct omap_chan *c) |
| 268 | { |
| 269 | unsigned val = omap_dma_chan_read(c, CSR); |
| 270 | |
| 271 | if (!dma_omap1()) |
| 272 | omap_dma_chan_write(c, CSR, val); |
| 273 | |
| 274 | return val; |
| 275 | } |
| 276 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 277 | static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, |
| 278 | unsigned lch) |
| 279 | { |
| 280 | c->channel_base = od->base + od->plat->channel_stride * lch; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 281 | |
| 282 | od->lch_map[lch] = c; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 283 | } |
| 284 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 285 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
| 286 | { |
| 287 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 288 | |
| 289 | if (__dma_omap15xx(od->plat->dma_attr)) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 290 | omap_dma_chan_write(c, CPC, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 291 | else |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 292 | omap_dma_chan_write(c, CDAC, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 293 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 294 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 295 | |
| 296 | /* Enable interrupts */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 297 | omap_dma_chan_write(c, CICR, d->cicr); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 298 | |
Russell King | 45da7b0 | 2013-11-06 17:18:42 +0000 | [diff] [blame] | 299 | /* Enable channel */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 300 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
Peter Ujfalusi | 689d3c5 | 2016-04-05 15:20:20 +0300 | [diff] [blame] | 301 | |
| 302 | c->running = true; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 303 | } |
| 304 | |
| 305 | static void omap_dma_stop(struct omap_chan *c) |
| 306 | { |
| 307 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 308 | uint32_t val; |
| 309 | |
| 310 | /* disable irq */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 311 | omap_dma_chan_write(c, CICR, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 312 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 313 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 314 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 315 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 316 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 317 | uint32_t sysconfig; |
| 318 | unsigned i; |
| 319 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 320 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 321 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
| 322 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 323 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 324 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 325 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 326 | val &= ~CCR_ENABLE; |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 327 | omap_dma_chan_write(c, CCR, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 328 | |
| 329 | /* Wait for sDMA FIFO to drain */ |
| 330 | for (i = 0; ; i++) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 331 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 332 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 333 | break; |
| 334 | |
| 335 | if (i > 100) |
| 336 | break; |
| 337 | |
| 338 | udelay(5); |
| 339 | } |
| 340 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 341 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 342 | dev_err(c->vc.chan.device->dev, |
| 343 | "DMA drain did not complete on lch %d\n", |
| 344 | c->dma_ch); |
| 345 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 346 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 347 | } else { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 348 | val &= ~CCR_ENABLE; |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 349 | omap_dma_chan_write(c, CCR, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | mb(); |
| 353 | |
| 354 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 355 | val = omap_dma_chan_read(c, CLNK_CTRL); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 356 | |
| 357 | if (dma_omap1()) |
| 358 | val |= 1 << 14; /* set the STOP_LNK bit */ |
| 359 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 360 | val &= ~CLNK_CTRL_ENABLE_LNK; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 361 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 362 | omap_dma_chan_write(c, CLNK_CTRL, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 363 | } |
Peter Ujfalusi | 689d3c5 | 2016-04-05 15:20:20 +0300 | [diff] [blame] | 364 | |
| 365 | c->running = false; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 366 | } |
| 367 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 368 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
| 369 | unsigned idx) |
| 370 | { |
| 371 | struct omap_sg *sg = d->sg + idx; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 372 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 373 | |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 374 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 375 | cxsa = CDSA; |
| 376 | cxei = CDEI; |
| 377 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 378 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 379 | cxsa = CSSA; |
| 380 | cxei = CSEI; |
| 381 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 382 | } |
| 383 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 384 | omap_dma_chan_write(c, cxsa, sg->addr); |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 385 | omap_dma_chan_write(c, cxei, sg->ei); |
| 386 | omap_dma_chan_write(c, cxfi, sg->fi); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 387 | omap_dma_chan_write(c, CEN, sg->en); |
| 388 | omap_dma_chan_write(c, CFN, sg->fn); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 389 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 390 | omap_dma_start(c, d); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 391 | } |
| 392 | |
| 393 | static void omap_dma_start_desc(struct omap_chan *c) |
| 394 | { |
| 395 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); |
| 396 | struct omap_desc *d; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 397 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 398 | |
| 399 | if (!vd) { |
| 400 | c->desc = NULL; |
| 401 | return; |
| 402 | } |
| 403 | |
| 404 | list_del(&vd->node); |
| 405 | |
| 406 | c->desc = d = to_omap_dma_desc(&vd->tx); |
| 407 | c->sgidx = 0; |
| 408 | |
Russell King | 5987190 | 2013-11-06 17:15:16 +0000 | [diff] [blame] | 409 | /* |
| 410 | * This provides the necessary barrier to ensure data held in |
| 411 | * DMA coherent memory is visible to the DMA engine prior to |
| 412 | * the transfer starting. |
| 413 | */ |
| 414 | mb(); |
| 415 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 416 | omap_dma_chan_write(c, CCR, d->ccr); |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 417 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 418 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 419 | |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 420 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 421 | cxsa = CSSA; |
| 422 | cxei = CSEI; |
| 423 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 424 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 425 | cxsa = CDSA; |
| 426 | cxei = CDEI; |
| 427 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 428 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 429 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 430 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 431 | omap_dma_chan_write(c, cxei, d->ei); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 432 | omap_dma_chan_write(c, cxfi, d->fi); |
| 433 | omap_dma_chan_write(c, CSDP, d->csdp); |
| 434 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); |
Russell King | 913a2d0 | 2013-11-02 14:41:42 +0000 | [diff] [blame] | 435 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 436 | omap_dma_start_sg(c, d, 0); |
| 437 | } |
| 438 | |
| 439 | static void omap_dma_callback(int ch, u16 status, void *data) |
| 440 | { |
| 441 | struct omap_chan *c = data; |
| 442 | struct omap_desc *d; |
| 443 | unsigned long flags; |
| 444 | |
| 445 | spin_lock_irqsave(&c->vc.lock, flags); |
| 446 | d = c->desc; |
| 447 | if (d) { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 448 | if (!c->cyclic) { |
| 449 | if (++c->sgidx < d->sglen) { |
| 450 | omap_dma_start_sg(c, d, c->sgidx); |
| 451 | } else { |
| 452 | omap_dma_start_desc(c); |
| 453 | vchan_cookie_complete(&d->vd); |
| 454 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 455 | } else { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 456 | vchan_cyclic_callback(&d->vd); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 457 | } |
| 458 | } |
| 459 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 460 | } |
| 461 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 462 | static irqreturn_t omap_dma_irq(int irq, void *devid) |
| 463 | { |
| 464 | struct omap_dmadev *od = devid; |
| 465 | unsigned status, channel; |
| 466 | |
| 467 | spin_lock(&od->irq_lock); |
| 468 | |
| 469 | status = omap_dma_glbl_read(od, IRQSTATUS_L1); |
| 470 | status &= od->irq_enable_mask; |
| 471 | if (status == 0) { |
| 472 | spin_unlock(&od->irq_lock); |
| 473 | return IRQ_NONE; |
| 474 | } |
| 475 | |
| 476 | while ((channel = ffs(status)) != 0) { |
| 477 | unsigned mask, csr; |
| 478 | struct omap_chan *c; |
| 479 | |
| 480 | channel -= 1; |
| 481 | mask = BIT(channel); |
| 482 | status &= ~mask; |
| 483 | |
| 484 | c = od->lch_map[channel]; |
| 485 | if (c == NULL) { |
| 486 | /* This should never happen */ |
| 487 | dev_err(od->ddev.dev, "invalid channel %u\n", channel); |
| 488 | continue; |
| 489 | } |
| 490 | |
| 491 | csr = omap_dma_get_csr(c); |
| 492 | omap_dma_glbl_write(od, IRQSTATUS_L1, mask); |
| 493 | |
| 494 | omap_dma_callback(channel, csr, c); |
| 495 | } |
| 496 | |
| 497 | spin_unlock(&od->irq_lock); |
| 498 | |
| 499 | return IRQ_HANDLED; |
| 500 | } |
| 501 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 502 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
| 503 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 504 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 505 | struct omap_chan *c = to_omap_dma_chan(chan); |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 506 | int ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 507 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 508 | if (od->legacy) { |
| 509 | ret = omap_request_dma(c->dma_sig, "DMA engine", |
| 510 | omap_dma_callback, c, &c->dma_ch); |
| 511 | } else { |
| 512 | ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL, |
| 513 | &c->dma_ch); |
| 514 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 515 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 516 | dev_dbg(od->ddev.dev, "allocating channel %u for %u\n", |
| 517 | c->dma_ch, c->dma_sig); |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 518 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 519 | if (ret >= 0) { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 520 | omap_dma_assign(od, c, c->dma_ch); |
| 521 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 522 | if (!od->legacy) { |
| 523 | unsigned val; |
| 524 | |
| 525 | spin_lock_irq(&od->irq_lock); |
| 526 | val = BIT(c->dma_ch); |
| 527 | omap_dma_glbl_write(od, IRQSTATUS_L1, val); |
| 528 | od->irq_enable_mask |= val; |
| 529 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); |
| 530 | |
| 531 | val = omap_dma_glbl_read(od, IRQENABLE_L0); |
| 532 | val &= ~BIT(c->dma_ch); |
| 533 | omap_dma_glbl_write(od, IRQENABLE_L0, val); |
| 534 | spin_unlock_irq(&od->irq_lock); |
| 535 | } |
| 536 | } |
| 537 | |
Russell King | aa4c5b9 | 2014-01-14 23:58:10 +0000 | [diff] [blame] | 538 | if (dma_omap1()) { |
| 539 | if (__dma_omap16xx(od->plat->dma_attr)) { |
| 540 | c->ccr = CCR_OMAP31_DISABLE; |
| 541 | /* Duplicate what plat-omap/dma.c does */ |
| 542 | c->ccr |= c->dma_ch + 1; |
| 543 | } else { |
| 544 | c->ccr = c->dma_sig & 0x1f; |
| 545 | } |
| 546 | } else { |
| 547 | c->ccr = c->dma_sig & 0x1f; |
| 548 | c->ccr |= (c->dma_sig & ~0x1f) << 14; |
| 549 | } |
| 550 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
| 551 | c->ccr |= CCR_BUFFERING_DISABLE; |
| 552 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 553 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | static void omap_dma_free_chan_resources(struct dma_chan *chan) |
| 557 | { |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 558 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 559 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 560 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 561 | if (!od->legacy) { |
| 562 | spin_lock_irq(&od->irq_lock); |
| 563 | od->irq_enable_mask &= ~BIT(c->dma_ch); |
| 564 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); |
| 565 | spin_unlock_irq(&od->irq_lock); |
| 566 | } |
| 567 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 568 | c->channel_base = NULL; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 569 | od->lch_map[c->dma_ch] = NULL; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 570 | vchan_free_chan_resources(&c->vc); |
| 571 | omap_free_dma(c->dma_ch); |
| 572 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 573 | dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig); |
Peter Ujfalusi | eea531e | 2015-04-09 12:35:52 +0300 | [diff] [blame] | 574 | c->dma_sig = 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 575 | } |
| 576 | |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 577 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
| 578 | { |
| 579 | return sg->en * sg->fn; |
| 580 | } |
| 581 | |
| 582 | static size_t omap_dma_desc_size(struct omap_desc *d) |
| 583 | { |
| 584 | unsigned i; |
| 585 | size_t size; |
| 586 | |
| 587 | for (size = i = 0; i < d->sglen; i++) |
| 588 | size += omap_dma_sg_size(&d->sg[i]); |
| 589 | |
| 590 | return size * es_bytes[d->es]; |
| 591 | } |
| 592 | |
| 593 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) |
| 594 | { |
| 595 | unsigned i; |
| 596 | size_t size, es_size = es_bytes[d->es]; |
| 597 | |
| 598 | for (size = i = 0; i < d->sglen; i++) { |
| 599 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; |
| 600 | |
| 601 | if (size) |
| 602 | size += this_size; |
| 603 | else if (addr >= d->sg[i].addr && |
| 604 | addr < d->sg[i].addr + this_size) |
| 605 | size += d->sg[i].addr + this_size - addr; |
| 606 | } |
| 607 | return size; |
| 608 | } |
| 609 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 610 | /* |
| 611 | * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is |
| 612 | * read before the DMA controller finished disabling the channel. |
| 613 | */ |
| 614 | static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) |
| 615 | { |
| 616 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 617 | uint32_t val; |
| 618 | |
| 619 | val = omap_dma_chan_read(c, reg); |
| 620 | if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) |
| 621 | val = omap_dma_chan_read(c, reg); |
| 622 | |
| 623 | return val; |
| 624 | } |
| 625 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 626 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
| 627 | { |
| 628 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 629 | dma_addr_t addr, cdac; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 630 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 631 | if (__dma_omap15xx(od->plat->dma_attr)) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 632 | addr = omap_dma_chan_read(c, CPC); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 633 | } else { |
| 634 | addr = omap_dma_chan_read_3_3(c, CSAC); |
| 635 | cdac = omap_dma_chan_read_3_3(c, CDAC); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 636 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 637 | /* |
| 638 | * CDAC == 0 indicates that the DMA transfer on the channel has |
| 639 | * not been started (no data has been transferred so far). |
| 640 | * Return the programmed source start address in this case. |
| 641 | */ |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 642 | if (cdac == 0) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 643 | addr = omap_dma_chan_read(c, CSSA); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 644 | } |
| 645 | |
| 646 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 647 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 648 | |
| 649 | return addr; |
| 650 | } |
| 651 | |
| 652 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) |
| 653 | { |
| 654 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 655 | dma_addr_t addr; |
| 656 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 657 | if (__dma_omap15xx(od->plat->dma_attr)) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 658 | addr = omap_dma_chan_read(c, CPC); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 659 | } else { |
| 660 | addr = omap_dma_chan_read_3_3(c, CDAC); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 661 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 662 | /* |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 663 | * CDAC == 0 indicates that the DMA transfer on the channel |
| 664 | * has not been started (no data has been transferred so |
| 665 | * far). Return the programmed destination start address in |
| 666 | * this case. |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 667 | */ |
| 668 | if (addr == 0) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 669 | addr = omap_dma_chan_read(c, CDSA); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 670 | } |
| 671 | |
| 672 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 673 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 674 | |
| 675 | return addr; |
| 676 | } |
| 677 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 678 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
| 679 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 680 | { |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 681 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 682 | struct virt_dma_desc *vd; |
| 683 | enum dma_status ret; |
| 684 | unsigned long flags; |
| 685 | |
| 686 | ret = dma_cookie_status(chan, cookie, txstate); |
Peter Ujfalusi | 689d3c5 | 2016-04-05 15:20:20 +0300 | [diff] [blame] | 687 | |
| 688 | if (!c->paused && c->running) { |
| 689 | uint32_t ccr = omap_dma_chan_read(c, CCR); |
| 690 | /* |
| 691 | * The channel is no longer active, set the return value |
| 692 | * accordingly |
| 693 | */ |
| 694 | if (!(ccr & CCR_ENABLE)) |
| 695 | ret = DMA_COMPLETE; |
| 696 | } |
| 697 | |
Vinod Koul | 7cce508 | 2013-10-16 20:51:54 +0530 | [diff] [blame] | 698 | if (ret == DMA_COMPLETE || !txstate) |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 699 | return ret; |
| 700 | |
| 701 | spin_lock_irqsave(&c->vc.lock, flags); |
| 702 | vd = vchan_find_desc(&c->vc, cookie); |
| 703 | if (vd) { |
| 704 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); |
| 705 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { |
| 706 | struct omap_desc *d = c->desc; |
| 707 | dma_addr_t pos; |
| 708 | |
| 709 | if (d->dir == DMA_MEM_TO_DEV) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 710 | pos = omap_dma_get_src_pos(c); |
Peter Ujfalusi | adf850b | 2015-11-11 12:37:55 +0200 | [diff] [blame] | 711 | else if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 712 | pos = omap_dma_get_dst_pos(c); |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 713 | else |
| 714 | pos = 0; |
| 715 | |
| 716 | txstate->residue = omap_dma_desc_size_pos(d, pos); |
| 717 | } else { |
| 718 | txstate->residue = 0; |
| 719 | } |
| 720 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 721 | |
| 722 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 723 | } |
| 724 | |
| 725 | static void omap_dma_issue_pending(struct dma_chan *chan) |
| 726 | { |
| 727 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 728 | unsigned long flags; |
| 729 | |
| 730 | spin_lock_irqsave(&c->vc.lock, flags); |
Peter Ujfalusi | 1c1d25f | 2015-11-11 12:37:57 +0200 | [diff] [blame] | 731 | if (vchan_issue_pending(&c->vc) && !c->desc) |
| 732 | omap_dma_start_desc(c); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 733 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 734 | } |
| 735 | |
| 736 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( |
| 737 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, |
| 738 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) |
| 739 | { |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 740 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 741 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 742 | enum dma_slave_buswidth dev_width; |
| 743 | struct scatterlist *sgent; |
| 744 | struct omap_desc *d; |
| 745 | dma_addr_t dev_addr; |
Peter Ujfalusi | e8a5e79 | 2015-11-11 12:37:56 +0200 | [diff] [blame] | 746 | unsigned i, es, en, frame_bytes; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 747 | u32 burst; |
| 748 | |
| 749 | if (dir == DMA_DEV_TO_MEM) { |
| 750 | dev_addr = c->cfg.src_addr; |
| 751 | dev_width = c->cfg.src_addr_width; |
| 752 | burst = c->cfg.src_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 753 | } else if (dir == DMA_MEM_TO_DEV) { |
| 754 | dev_addr = c->cfg.dst_addr; |
| 755 | dev_width = c->cfg.dst_addr_width; |
| 756 | burst = c->cfg.dst_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 757 | } else { |
| 758 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 759 | return NULL; |
| 760 | } |
| 761 | |
| 762 | /* Bus width translates to the element size (ES) */ |
| 763 | switch (dev_width) { |
| 764 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 765 | es = CSDP_DATA_TYPE_8; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 766 | break; |
| 767 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 768 | es = CSDP_DATA_TYPE_16; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 769 | break; |
| 770 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 771 | es = CSDP_DATA_TYPE_32; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 772 | break; |
| 773 | default: /* not reached */ |
| 774 | return NULL; |
| 775 | } |
| 776 | |
| 777 | /* Now allocate and setup the descriptor. */ |
| 778 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); |
| 779 | if (!d) |
| 780 | return NULL; |
| 781 | |
| 782 | d->dir = dir; |
| 783 | d->dev_addr = dev_addr; |
| 784 | d->es = es; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 785 | |
Russell King | aa4c5b9 | 2014-01-14 23:58:10 +0000 | [diff] [blame] | 786 | d->ccr = c->ccr | CCR_SYNC_FRAME; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 787 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 788 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 789 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 790 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 791 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 792 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 793 | d->csdp = es; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 794 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 795 | if (dma_omap1()) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 796 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 797 | |
| 798 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 799 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 800 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 801 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 802 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 803 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 804 | d->ccr |= CCR_TRIGGER_SRC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 805 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 806 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 807 | } |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 808 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
| 809 | d->clnk_ctrl = c->dma_ch; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 810 | |
| 811 | /* |
| 812 | * Build our scatterlist entries: each contains the address, |
| 813 | * the number of elements (EN) in each frame, and the number of |
| 814 | * frames (FN). Number of bytes for this entry = ES * EN * FN. |
| 815 | * |
| 816 | * Burst size translates to number of elements with frame sync. |
| 817 | * Note: DMA engine defines burst to be the number of dev-width |
| 818 | * transfers. |
| 819 | */ |
| 820 | en = burst; |
| 821 | frame_bytes = es_bytes[es] * en; |
| 822 | for_each_sg(sgl, sgent, sglen, i) { |
Peter Ujfalusi | e8a5e79 | 2015-11-11 12:37:56 +0200 | [diff] [blame] | 823 | d->sg[i].addr = sg_dma_address(sgent); |
| 824 | d->sg[i].en = en; |
| 825 | d->sg[i].fn = sg_dma_len(sgent) / frame_bytes; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 826 | } |
| 827 | |
Peter Ujfalusi | e8a5e79 | 2015-11-11 12:37:56 +0200 | [diff] [blame] | 828 | d->sglen = sglen; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 829 | |
| 830 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); |
| 831 | } |
| 832 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 833 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
| 834 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
Laurent Pinchart | 31c1e5a | 2014-08-01 12:20:10 +0200 | [diff] [blame] | 835 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags) |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 836 | { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 837 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 838 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 839 | enum dma_slave_buswidth dev_width; |
| 840 | struct omap_desc *d; |
| 841 | dma_addr_t dev_addr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 842 | unsigned es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 843 | u32 burst; |
| 844 | |
| 845 | if (dir == DMA_DEV_TO_MEM) { |
| 846 | dev_addr = c->cfg.src_addr; |
| 847 | dev_width = c->cfg.src_addr_width; |
| 848 | burst = c->cfg.src_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 849 | } else if (dir == DMA_MEM_TO_DEV) { |
| 850 | dev_addr = c->cfg.dst_addr; |
| 851 | dev_width = c->cfg.dst_addr_width; |
| 852 | burst = c->cfg.dst_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 853 | } else { |
| 854 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 855 | return NULL; |
| 856 | } |
| 857 | |
| 858 | /* Bus width translates to the element size (ES) */ |
| 859 | switch (dev_width) { |
| 860 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 861 | es = CSDP_DATA_TYPE_8; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 862 | break; |
| 863 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 864 | es = CSDP_DATA_TYPE_16; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 865 | break; |
| 866 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 867 | es = CSDP_DATA_TYPE_32; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 868 | break; |
| 869 | default: /* not reached */ |
| 870 | return NULL; |
| 871 | } |
| 872 | |
| 873 | /* Now allocate and setup the descriptor. */ |
| 874 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 875 | if (!d) |
| 876 | return NULL; |
| 877 | |
| 878 | d->dir = dir; |
| 879 | d->dev_addr = dev_addr; |
| 880 | d->fi = burst; |
| 881 | d->es = es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 882 | d->sg[0].addr = buf_addr; |
| 883 | d->sg[0].en = period_len / es_bytes[es]; |
| 884 | d->sg[0].fn = buf_len / period_len; |
| 885 | d->sglen = 1; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 886 | |
Russell King | aa4c5b9 | 2014-01-14 23:58:10 +0000 | [diff] [blame] | 887 | d->ccr = c->ccr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 888 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 889 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 890 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 891 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 892 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 893 | d->cicr = CICR_DROP_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 894 | if (flags & DMA_PREP_INTERRUPT) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 895 | d->cicr |= CICR_FRAME_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 896 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 897 | d->csdp = es; |
| 898 | |
| 899 | if (dma_omap1()) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 900 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 901 | |
| 902 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 903 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 904 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 905 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 906 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 907 | if (burst) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 908 | d->ccr |= CCR_SYNC_PACKET; |
| 909 | else |
| 910 | d->ccr |= CCR_SYNC_ELEMENT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 911 | |
Misael Lopez Cruz | 47fac24 | 2015-09-14 15:31:05 +0300 | [diff] [blame] | 912 | if (dir == DMA_DEV_TO_MEM) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 913 | d->ccr |= CCR_TRIGGER_SRC; |
Misael Lopez Cruz | 47fac24 | 2015-09-14 15:31:05 +0300 | [diff] [blame] | 914 | d->csdp |= CSDP_DST_PACKED; |
| 915 | } else { |
| 916 | d->csdp |= CSDP_SRC_PACKED; |
| 917 | } |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 918 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 919 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 920 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 921 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 922 | } |
| 923 | |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 924 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 925 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; |
| 926 | else |
| 927 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; |
| 928 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 929 | c->cyclic = true; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 930 | |
Peter Ujfalusi | 2dde5b9 | 2012-09-14 15:05:48 +0300 | [diff] [blame] | 931 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 932 | } |
| 933 | |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 934 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy( |
| 935 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
| 936 | size_t len, unsigned long tx_flags) |
| 937 | { |
| 938 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 939 | struct omap_desc *d; |
| 940 | uint8_t data_type; |
| 941 | |
| 942 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 943 | if (!d) |
| 944 | return NULL; |
| 945 | |
| 946 | data_type = __ffs((src | dest | len)); |
| 947 | if (data_type > CSDP_DATA_TYPE_32) |
| 948 | data_type = CSDP_DATA_TYPE_32; |
| 949 | |
| 950 | d->dir = DMA_MEM_TO_MEM; |
| 951 | d->dev_addr = src; |
| 952 | d->fi = 0; |
| 953 | d->es = data_type; |
| 954 | d->sg[0].en = len / BIT(data_type); |
| 955 | d->sg[0].fn = 1; |
| 956 | d->sg[0].addr = dest; |
| 957 | d->sglen = 1; |
| 958 | d->ccr = c->ccr; |
| 959 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC; |
| 960 | |
Peter Ujfalusi | b96c033 | 2016-04-05 15:20:21 +0300 | [diff] [blame] | 961 | d->cicr = CICR_DROP_IE | CICR_FRAME_IE; |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 962 | |
| 963 | d->csdp = data_type; |
| 964 | |
| 965 | if (dma_omap1()) { |
| 966 | d->cicr |= CICR_TOUT_IE; |
| 967 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF; |
| 968 | } else { |
| 969 | d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED; |
| 970 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
| 971 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
| 972 | } |
| 973 | |
| 974 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); |
| 975 | } |
| 976 | |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 977 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_interleaved( |
| 978 | struct dma_chan *chan, struct dma_interleaved_template *xt, |
| 979 | unsigned long flags) |
| 980 | { |
| 981 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 982 | struct omap_desc *d; |
| 983 | struct omap_sg *sg; |
| 984 | uint8_t data_type; |
| 985 | size_t src_icg, dst_icg; |
| 986 | |
| 987 | /* Slave mode is not supported */ |
| 988 | if (is_slave_direction(xt->dir)) |
| 989 | return NULL; |
| 990 | |
| 991 | if (xt->frame_size != 1 || xt->numf == 0) |
| 992 | return NULL; |
| 993 | |
| 994 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 995 | if (!d) |
| 996 | return NULL; |
| 997 | |
| 998 | data_type = __ffs((xt->src_start | xt->dst_start | xt->sgl[0].size)); |
| 999 | if (data_type > CSDP_DATA_TYPE_32) |
| 1000 | data_type = CSDP_DATA_TYPE_32; |
| 1001 | |
| 1002 | sg = &d->sg[0]; |
| 1003 | d->dir = DMA_MEM_TO_MEM; |
| 1004 | d->dev_addr = xt->src_start; |
| 1005 | d->es = data_type; |
| 1006 | sg->en = xt->sgl[0].size / BIT(data_type); |
| 1007 | sg->fn = xt->numf; |
| 1008 | sg->addr = xt->dst_start; |
| 1009 | d->sglen = 1; |
| 1010 | d->ccr = c->ccr; |
| 1011 | |
| 1012 | src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]); |
| 1013 | dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]); |
| 1014 | if (src_icg) { |
| 1015 | d->ccr |= CCR_SRC_AMODE_DBLIDX; |
| 1016 | d->ei = 1; |
| 1017 | d->fi = src_icg; |
| 1018 | } else if (xt->src_inc) { |
| 1019 | d->ccr |= CCR_SRC_AMODE_POSTINC; |
| 1020 | d->fi = 0; |
| 1021 | } else { |
| 1022 | dev_err(chan->device->dev, |
| 1023 | "%s: SRC constant addressing is not supported\n", |
| 1024 | __func__); |
| 1025 | kfree(d); |
| 1026 | return NULL; |
| 1027 | } |
| 1028 | |
| 1029 | if (dst_icg) { |
| 1030 | d->ccr |= CCR_DST_AMODE_DBLIDX; |
| 1031 | sg->ei = 1; |
| 1032 | sg->fi = dst_icg; |
| 1033 | } else if (xt->dst_inc) { |
| 1034 | d->ccr |= CCR_DST_AMODE_POSTINC; |
| 1035 | sg->fi = 0; |
| 1036 | } else { |
| 1037 | dev_err(chan->device->dev, |
| 1038 | "%s: DST constant addressing is not supported\n", |
| 1039 | __func__); |
| 1040 | kfree(d); |
| 1041 | return NULL; |
| 1042 | } |
| 1043 | |
| 1044 | d->cicr = CICR_DROP_IE | CICR_FRAME_IE; |
| 1045 | |
| 1046 | d->csdp = data_type; |
| 1047 | |
| 1048 | if (dma_omap1()) { |
| 1049 | d->cicr |= CICR_TOUT_IE; |
| 1050 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF; |
| 1051 | } else { |
| 1052 | d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED; |
| 1053 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
| 1054 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
| 1055 | } |
| 1056 | |
| 1057 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
| 1058 | } |
| 1059 | |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1060 | static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1061 | { |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1062 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1063 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1064 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 1065 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
| 1066 | return -EINVAL; |
| 1067 | |
| 1068 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); |
| 1069 | |
| 1070 | return 0; |
| 1071 | } |
| 1072 | |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1073 | static int omap_dma_terminate_all(struct dma_chan *chan) |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1074 | { |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1075 | struct omap_chan *c = to_omap_dma_chan(chan); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1076 | unsigned long flags; |
| 1077 | LIST_HEAD(head); |
| 1078 | |
| 1079 | spin_lock_irqsave(&c->vc.lock, flags); |
| 1080 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1081 | /* |
| 1082 | * Stop DMA activity: we assume the callback will not be called |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1083 | * after omap_dma_stop() returns (even if it does, it will see |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1084 | * c->desc is NULL and exit.) |
| 1085 | */ |
| 1086 | if (c->desc) { |
Peter Ujfalusi | 02d88b7 | 2015-03-27 13:35:52 +0200 | [diff] [blame] | 1087 | omap_dma_desc_free(&c->desc->vd); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1088 | c->desc = NULL; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1089 | /* Avoid stopping the dma twice */ |
| 1090 | if (!c->paused) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1091 | omap_dma_stop(c); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1092 | } |
| 1093 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1094 | if (c->cyclic) { |
| 1095 | c->cyclic = false; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1096 | c->paused = false; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1097 | } |
| 1098 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1099 | vchan_get_all_descriptors(&c->vc, &head); |
| 1100 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 1101 | vchan_dma_desc_free_list(&c->vc, &head); |
| 1102 | |
| 1103 | return 0; |
| 1104 | } |
| 1105 | |
Peter Ujfalusi | 9bef6d8 | 2016-02-11 11:08:34 +0200 | [diff] [blame] | 1106 | static void omap_dma_synchronize(struct dma_chan *chan) |
| 1107 | { |
| 1108 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1109 | |
| 1110 | vchan_synchronize(&c->vc); |
| 1111 | } |
| 1112 | |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1113 | static int omap_dma_pause(struct dma_chan *chan) |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1114 | { |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1115 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1116 | |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1117 | /* Pause/Resume only allowed with cyclic mode */ |
| 1118 | if (!c->cyclic) |
| 1119 | return -EINVAL; |
| 1120 | |
| 1121 | if (!c->paused) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1122 | omap_dma_stop(c); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1123 | c->paused = true; |
| 1124 | } |
| 1125 | |
| 1126 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1127 | } |
| 1128 | |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1129 | static int omap_dma_resume(struct dma_chan *chan) |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1130 | { |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1131 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1132 | |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1133 | /* Pause/Resume only allowed with cyclic mode */ |
| 1134 | if (!c->cyclic) |
| 1135 | return -EINVAL; |
| 1136 | |
| 1137 | if (c->paused) { |
Peter Ujfalusi | b3d09da | 2014-09-16 22:45:56 +0300 | [diff] [blame] | 1138 | mb(); |
| 1139 | |
Peter Ujfalusi | bfb6074 | 2014-09-16 22:45:57 +0300 | [diff] [blame] | 1140 | /* Restore channel link register */ |
| 1141 | omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl); |
| 1142 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1143 | omap_dma_start(c, c->desc); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1144 | c->paused = false; |
| 1145 | } |
| 1146 | |
| 1147 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1148 | } |
| 1149 | |
Peter Ujfalusi | eea531e | 2015-04-09 12:35:52 +0300 | [diff] [blame] | 1150 | static int omap_dma_chan_init(struct omap_dmadev *od) |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1151 | { |
| 1152 | struct omap_chan *c; |
| 1153 | |
| 1154 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
| 1155 | if (!c) |
| 1156 | return -ENOMEM; |
| 1157 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1158 | c->reg_map = od->reg_map; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1159 | c->vc.desc_free = omap_dma_desc_free; |
| 1160 | vchan_init(&c->vc, &od->ddev); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1161 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1162 | return 0; |
| 1163 | } |
| 1164 | |
| 1165 | static void omap_dma_free(struct omap_dmadev *od) |
| 1166 | { |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1167 | while (!list_empty(&od->ddev.channels)) { |
| 1168 | struct omap_chan *c = list_first_entry(&od->ddev.channels, |
| 1169 | struct omap_chan, vc.chan.device_node); |
| 1170 | |
| 1171 | list_del(&c->vc.chan.device_node); |
| 1172 | tasklet_kill(&c->vc.task); |
| 1173 | kfree(c); |
| 1174 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1175 | } |
| 1176 | |
Peter Ujfalusi | 80b0e0a | 2014-03-29 19:03:30 +0530 | [diff] [blame] | 1177 | #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
| 1178 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
| 1179 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) |
| 1180 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1181 | static int omap_dma_probe(struct platform_device *pdev) |
| 1182 | { |
| 1183 | struct omap_dmadev *od; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1184 | struct resource *res; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 1185 | int rc, i, irq; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1186 | |
Russell King | 104fce7 | 2013-11-02 12:58:29 +0000 | [diff] [blame] | 1187 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1188 | if (!od) |
| 1189 | return -ENOMEM; |
| 1190 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1191 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1192 | od->base = devm_ioremap_resource(&pdev->dev, res); |
| 1193 | if (IS_ERR(od->base)) |
| 1194 | return PTR_ERR(od->base); |
| 1195 | |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 1196 | od->plat = omap_get_plat_info(); |
| 1197 | if (!od->plat) |
| 1198 | return -EPROBE_DEFER; |
| 1199 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1200 | od->reg_map = od->plat->reg_map; |
| 1201 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1202 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1203 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 1204 | dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 1205 | dma_cap_set(DMA_INTERLEAVE, od->ddev.cap_mask); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1206 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
| 1207 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; |
| 1208 | od->ddev.device_tx_status = omap_dma_tx_status; |
| 1209 | od->ddev.device_issue_pending = omap_dma_issue_pending; |
| 1210 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1211 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
Peter Ujfalusi | 4ce98c0 | 2015-04-22 10:34:29 +0300 | [diff] [blame] | 1212 | od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy; |
Peter Ujfalusi | ad52465 | 2016-07-12 14:21:14 +0300 | [diff] [blame] | 1213 | od->ddev.device_prep_interleaved_dma = omap_dma_prep_dma_interleaved; |
Vinod Koul | 6c04cd4 | 2014-12-07 23:12:31 +0530 | [diff] [blame] | 1214 | od->ddev.device_config = omap_dma_slave_config; |
Maxime Ripard | 78ea4fe | 2014-11-17 14:42:28 +0100 | [diff] [blame] | 1215 | od->ddev.device_pause = omap_dma_pause; |
| 1216 | od->ddev.device_resume = omap_dma_resume; |
| 1217 | od->ddev.device_terminate_all = omap_dma_terminate_all; |
Peter Ujfalusi | 9bef6d8 | 2016-02-11 11:08:34 +0200 | [diff] [blame] | 1218 | od->ddev.device_synchronize = omap_dma_synchronize; |
Maxime Ripard | 7d15b87 | 2014-11-17 14:42:49 +0100 | [diff] [blame] | 1219 | od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS; |
| 1220 | od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS; |
| 1221 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); |
| 1222 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1223 | od->ddev.dev = &pdev->dev; |
| 1224 | INIT_LIST_HEAD(&od->ddev.channels); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1225 | spin_lock_init(&od->lock); |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 1226 | spin_lock_init(&od->irq_lock); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1227 | |
Peter Ujfalusi | de50608 | 2015-04-09 12:35:51 +0300 | [diff] [blame] | 1228 | od->dma_requests = OMAP_SDMA_REQUESTS; |
| 1229 | if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, |
| 1230 | "dma-requests", |
| 1231 | &od->dma_requests)) { |
| 1232 | dev_info(&pdev->dev, |
| 1233 | "Missing dma-requests property, using %u.\n", |
| 1234 | OMAP_SDMA_REQUESTS); |
| 1235 | } |
| 1236 | |
Peter Ujfalusi | 8a32222 | 2015-04-09 12:35:53 +0300 | [diff] [blame] | 1237 | for (i = 0; i < OMAP_SDMA_CHANNELS; i++) { |
Peter Ujfalusi | eea531e | 2015-04-09 12:35:52 +0300 | [diff] [blame] | 1238 | rc = omap_dma_chan_init(od); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1239 | if (rc) { |
| 1240 | omap_dma_free(od); |
| 1241 | return rc; |
| 1242 | } |
| 1243 | } |
| 1244 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 1245 | irq = platform_get_irq(pdev, 1); |
| 1246 | if (irq <= 0) { |
| 1247 | dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq); |
| 1248 | od->legacy = true; |
| 1249 | } else { |
| 1250 | /* Disable all interrupts */ |
| 1251 | od->irq_enable_mask = 0; |
| 1252 | omap_dma_glbl_write(od, IRQENABLE_L1, 0); |
| 1253 | |
| 1254 | rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq, |
| 1255 | IRQF_SHARED, "omap-dma-engine", od); |
| 1256 | if (rc) |
| 1257 | return rc; |
| 1258 | } |
| 1259 | |
Peter Ujfalusi | 020c62a | 2015-12-14 22:47:42 +0200 | [diff] [blame] | 1260 | od->ddev.filter.map = od->plat->slave_map; |
| 1261 | od->ddev.filter.mapcnt = od->plat->slavecnt; |
| 1262 | od->ddev.filter.fn = omap_dma_filter_fn; |
| 1263 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1264 | rc = dma_async_device_register(&od->ddev); |
| 1265 | if (rc) { |
| 1266 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", |
| 1267 | rc); |
| 1268 | omap_dma_free(od); |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1269 | return rc; |
| 1270 | } |
| 1271 | |
| 1272 | platform_set_drvdata(pdev, od); |
| 1273 | |
| 1274 | if (pdev->dev.of_node) { |
| 1275 | omap_dma_info.dma_cap = od->ddev.cap_mask; |
| 1276 | |
| 1277 | /* Device-tree DMA controller registration */ |
| 1278 | rc = of_dma_controller_register(pdev->dev.of_node, |
| 1279 | of_dma_simple_xlate, &omap_dma_info); |
| 1280 | if (rc) { |
| 1281 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); |
| 1282 | dma_async_device_unregister(&od->ddev); |
| 1283 | omap_dma_free(od); |
| 1284 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1285 | } |
| 1286 | |
| 1287 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); |
| 1288 | |
| 1289 | return rc; |
| 1290 | } |
| 1291 | |
| 1292 | static int omap_dma_remove(struct platform_device *pdev) |
| 1293 | { |
| 1294 | struct omap_dmadev *od = platform_get_drvdata(pdev); |
Vinod Koul | 898dbbf | 2016-07-05 09:58:33 +0530 | [diff] [blame] | 1295 | int irq; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1296 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1297 | if (pdev->dev.of_node) |
| 1298 | of_dma_controller_free(pdev->dev.of_node); |
| 1299 | |
Vinod Koul | 898dbbf | 2016-07-05 09:58:33 +0530 | [diff] [blame] | 1300 | irq = platform_get_irq(pdev, 1); |
| 1301 | devm_free_irq(&pdev->dev, irq, od); |
| 1302 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1303 | dma_async_device_unregister(&od->ddev); |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame] | 1304 | |
| 1305 | if (!od->legacy) { |
| 1306 | /* Disable all interrupts */ |
| 1307 | omap_dma_glbl_write(od, IRQENABLE_L0, 0); |
| 1308 | } |
| 1309 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1310 | omap_dma_free(od); |
| 1311 | |
| 1312 | return 0; |
| 1313 | } |
| 1314 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1315 | static const struct of_device_id omap_dma_match[] = { |
| 1316 | { .compatible = "ti,omap2420-sdma", }, |
| 1317 | { .compatible = "ti,omap2430-sdma", }, |
| 1318 | { .compatible = "ti,omap3430-sdma", }, |
| 1319 | { .compatible = "ti,omap3630-sdma", }, |
| 1320 | { .compatible = "ti,omap4430-sdma", }, |
| 1321 | {}, |
| 1322 | }; |
| 1323 | MODULE_DEVICE_TABLE(of, omap_dma_match); |
| 1324 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1325 | static struct platform_driver omap_dma_driver = { |
| 1326 | .probe = omap_dma_probe, |
| 1327 | .remove = omap_dma_remove, |
| 1328 | .driver = { |
| 1329 | .name = "omap-dma-engine", |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1330 | .of_match_table = of_match_ptr(omap_dma_match), |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1331 | }, |
| 1332 | }; |
| 1333 | |
| 1334 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) |
| 1335 | { |
| 1336 | if (chan->device->dev->driver == &omap_dma_driver.driver) { |
Peter Ujfalusi | eea531e | 2015-04-09 12:35:52 +0300 | [diff] [blame] | 1337 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1338 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1339 | unsigned req = *(unsigned *)param; |
| 1340 | |
Peter Ujfalusi | eea531e | 2015-04-09 12:35:52 +0300 | [diff] [blame] | 1341 | if (req <= od->dma_requests) { |
| 1342 | c->dma_sig = req; |
| 1343 | return true; |
| 1344 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1345 | } |
| 1346 | return false; |
| 1347 | } |
| 1348 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); |
| 1349 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1350 | static int omap_dma_init(void) |
| 1351 | { |
Tony Lindgren | be1f948 | 2013-01-11 11:24:19 -0800 | [diff] [blame] | 1352 | return platform_driver_register(&omap_dma_driver); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1353 | } |
| 1354 | subsys_initcall(omap_dma_init); |
| 1355 | |
| 1356 | static void __exit omap_dma_exit(void) |
| 1357 | { |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1358 | platform_driver_unregister(&omap_dma_driver); |
| 1359 | } |
| 1360 | module_exit(omap_dma_exit); |
| 1361 | |
| 1362 | MODULE_AUTHOR("Russell King"); |
| 1363 | MODULE_LICENSE("GPL"); |