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Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Clarence Ip4ce59322016-06-26 22:27:51 -040012#include <linux/debugfs.h>
Clarence Ip5e2a9222016-06-26 22:38:24 -040013#include <uapi/drm/sde_drm.h>
Clarence Ipaa0faf42016-05-30 12:07:48 -040014
15#include "msm_prop.h"
16
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017#include "sde_kms.h"
Clarence Ipae4e60c2016-06-26 22:44:04 -040018#include "sde_fence.h"
Clarence Ipc475b082016-06-26 09:27:23 -040019#include "sde_formats.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040020#include "sde_hw_sspp.h"
21
22#define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
23#define PHASE_STEP_SHIFT 21
24#define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
25#define PHASE_RESIDUAL 15
26
Clarence Ipe78efb72016-06-24 18:35:21 -040027#define SHARP_STRENGTH_DEFAULT 32
28#define SHARP_EDGE_THR_DEFAULT 112
29#define SHARP_SMOOTH_THR_DEFAULT 8
30#define SHARP_NOISE_THR_DEFAULT 2
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040031
Clarence Ip5e2a9222016-06-26 22:38:24 -040032#define SDE_NAME_SIZE 12
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070033
34struct sde_plane {
35 struct drm_plane base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040036
37 int mmu_id;
38
Clarence Ip730e7192016-06-26 22:45:09 -040039 struct mutex lock;
40
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040041 enum sde_sspp pipe;
42 uint32_t features; /* capabilities from catalog */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070043 uint32_t nformats;
44 uint32_t formats[32];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040045
46 struct sde_hw_pipe *pipe_hw;
47 struct sde_hw_pipe_cfg pipe_cfg;
48 struct sde_hw_pixel_ext pixel_ext;
Clarence Ipe78efb72016-06-24 18:35:21 -040049 struct sde_hw_sharp_cfg sharp_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -040050 struct sde_hw_scaler3_cfg scaler3_cfg;
Clarence Ip4ce59322016-06-26 22:27:51 -040051
Clarence Ip373f8592016-05-26 00:58:42 -040052 struct sde_csc_cfg csc_cfg;
53 struct sde_csc_cfg *csc_ptr;
54
Clarence Ip4c1d9772016-06-26 09:35:38 -040055 const struct sde_sspp_sub_blks *pipe_sblk;
56
Clarence Ip5e2a9222016-06-26 22:38:24 -040057 char pipe_name[SDE_NAME_SIZE];
Clarence Ip4ce59322016-06-26 22:27:51 -040058
Clarence Ipaa0faf42016-05-30 12:07:48 -040059 struct msm_property_info property_info;
60 struct msm_property_data property_data[PLANE_PROP_COUNT];
Clarence Ip730e7192016-06-26 22:45:09 -040061
Clarence Ip4ce59322016-06-26 22:27:51 -040062 /* debugfs related stuff */
63 struct dentry *debugfs_root;
64 struct sde_debugfs_regset32 debugfs_src;
65 struct sde_debugfs_regset32 debugfs_scaler;
66 struct sde_debugfs_regset32 debugfs_csc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070067};
68#define to_sde_plane(x) container_of(x, struct sde_plane, base)
69
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040070static bool sde_plane_enabled(struct drm_plane_state *state)
71{
Clarence Ipdbde9832016-06-26 09:48:36 -040072 return state && state->fb && state->crtc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040073}
74
Clarence Ipae4e60c2016-06-26 22:44:04 -040075/* helper to update a state's sync fence pointer from the property */
76static void _sde_plane_update_sync_fence(struct drm_plane *plane,
77 struct sde_plane_state *pstate, uint64_t fd)
78{
79 if (!plane || !pstate)
80 return;
81
82 /* clear previous reference */
83 if (pstate->sync_fence)
84 sde_sync_put(pstate->sync_fence);
85
86 /* get fence pointer for later */
87 pstate->sync_fence = sde_sync_get(fd);
88
89 DBG("0x%llX", fd);
90}
91
Clarence Ipcb410d42016-06-26 22:52:33 -040092int sde_plane_wait_sync_fence(struct drm_plane *plane)
Clarence Ipae4e60c2016-06-26 22:44:04 -040093{
94 struct sde_plane_state *pstate;
Clarence Ipcb410d42016-06-26 22:52:33 -040095 void *sync_fence;
96 long wait_ms;
97 int ret = -EINVAL;
Clarence Ipae4e60c2016-06-26 22:44:04 -040098
99 if (!plane) {
100 DRM_ERROR("Invalid plane\n");
101 } else if (!plane->state) {
102 DRM_ERROR("Invalid plane state\n");
103 } else {
104 pstate = to_sde_plane_state(plane->state);
Clarence Ipcb410d42016-06-26 22:52:33 -0400105 sync_fence = pstate->sync_fence;
Clarence Ipae4e60c2016-06-26 22:44:04 -0400106
Clarence Ipcb410d42016-06-26 22:52:33 -0400107 if (sync_fence) {
108 wait_ms = (long)sde_plane_get_property(pstate,
109 PLANE_PROP_SYNC_FENCE_TIMEOUT);
110
111 DBG("%s", to_sde_plane(plane)->pipe_name);
112 ret = sde_sync_wait(sync_fence, wait_ms);
113 if (!ret)
114 DBG("signaled");
115 else if (ret == -ETIME)
116 DRM_ERROR("timeout\n");
117 else
118 DRM_ERROR("error %d\n", ret);
119 } else {
120 ret = 0;
121 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400122 }
Clarence Ipae4e60c2016-06-26 22:44:04 -0400123 return ret;
124}
125
Clarence Ipe78efb72016-06-24 18:35:21 -0400126static void _sde_plane_set_scanout(struct drm_plane *plane,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400127 struct sde_plane_state *pstate,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400128 struct sde_hw_pipe_cfg *pipe_cfg, struct drm_framebuffer *fb)
129{
Clarence Ipae4e60c2016-06-26 22:44:04 -0400130 struct sde_plane *psde;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400131 unsigned int shift;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400132 int i;
133
Clarence Ipae4e60c2016-06-26 22:44:04 -0400134 if (!plane || !pstate || !pipe_cfg || !fb)
135 return;
136
137 psde = to_sde_plane(plane);
138
139 if (psde->pipe_hw && psde->pipe_hw->ops.setup_sourceaddress) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400140 /* stride */
Clarence Ip4c1d9772016-06-26 09:35:38 -0400141 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
Clarence Ip5e2a9222016-06-26 22:38:24 -0400142 BIT(SDE_DRM_DEINTERLACE))
143 shift = 1;
144 else
145 shift = 0;
146
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400147 i = min_t(int, ARRAY_SIZE(fb->pitches), SDE_MAX_PLANES);
148 while (i) {
149 --i;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400150 pipe_cfg->src.ystride[i] = fb->pitches[i] << shift;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400151 }
152
153 /* address */
154 for (i = 0; i < ARRAY_SIZE(pipe_cfg->addr.plane); ++i)
155 pipe_cfg->addr.plane[i] = msm_framebuffer_iova(fb,
156 psde->mmu_id, i);
157
158 /* hw driver */
159 psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg);
160 }
161}
162
Clarence Ipcb410d42016-06-26 22:52:33 -0400163static void _sde_plane_setup_scaler3(struct sde_plane *psde,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400164 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
165 struct sde_hw_scaler3_cfg *scale_cfg,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400166 const struct sde_format *fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400167 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
168{
169}
170
Clarence Ipcb410d42016-06-26 22:52:33 -0400171/**
172 * _sde_plane_setup_scaler2(): Determine default scaler phase steps/filter type
173 * @psde: Pointer to SDE plane object
174 * @src: Source size
175 * @dst: Destination size
176 * @phase_steps: Pointer to output array for phase steps
177 * @filter: Pointer to output array for filter type
178 * @fmt: Pointer to format definition
179 * @chroma_subsampling: Subsampling amount for chroma channel
180 *
181 * Returns: 0 on success
182 */
183static int _sde_plane_setup_scaler2(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400184 uint32_t src, uint32_t dst, uint32_t *phase_steps,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400185 enum sde_hw_filter *filter, const struct sde_format *fmt,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400186 uint32_t chroma_subsampling)
187{
Clarence Ipcb410d42016-06-26 22:52:33 -0400188 if (!psde || !phase_steps || !filter || !fmt) {
189 DRM_ERROR("Invalid arguments\n");
190 return -EINVAL;
191 }
192
Clarence Ip4c1d9772016-06-26 09:35:38 -0400193 /* calculate phase steps, leave init phase as zero */
Clarence Ipe78efb72016-06-24 18:35:21 -0400194 phase_steps[SDE_SSPP_COMP_0] =
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400195 mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
Clarence Ipe78efb72016-06-24 18:35:21 -0400196 phase_steps[SDE_SSPP_COMP_1_2] =
197 phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
198 phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
199 phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400200
201 /* calculate scaler config, if necessary */
Clarence Ipdbde9832016-06-26 09:48:36 -0400202 if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
Clarence Ipe78efb72016-06-24 18:35:21 -0400203 filter[SDE_SSPP_COMP_3] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400204 (src <= dst) ? SDE_SCALE_FILTER_BIL :
205 SDE_SCALE_FILTER_PCMN;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400206
Clarence Ipdbde9832016-06-26 09:48:36 -0400207 if (SDE_FORMAT_IS_YUV(fmt)) {
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400208 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
Clarence Ipe78efb72016-06-24 18:35:21 -0400209 filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
210 } else {
211 filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
212 filter[SDE_SSPP_COMP_1_2] =
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400213 SDE_SCALE_FILTER_NEAREST;
Clarence Ipe78efb72016-06-24 18:35:21 -0400214 }
215 } else {
216 /* disable scaler */
Clarence Ipcb410d42016-06-26 22:52:33 -0400217 DBG("Disable scaler");
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400218 filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
219 filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
220 filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400221 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400222 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400223}
224
Clarence Ipcb410d42016-06-26 22:52:33 -0400225/**
226 * _sde_plane_setup_pixel_ext - determine default pixel extension values
227 * @psde: Pointer to SDE plane object
228 * @src: Source size
229 * @dst: Destination size
230 * @decimated_src: Source size after decimation, if any
231 * @phase_steps: Pointer to output array for phase steps
232 * @out_src: Output array for pixel extension values
233 * @out_edge1: Output array for pixel extension first edge
234 * @out_edge2: Output array for pixel extension second edge
235 * @filter: Pointer to array for filter type
236 * @fmt: Pointer to format definition
237 * @chroma_subsampling: Subsampling amount for chroma channel
238 * @post_compare: Whether to chroma subsampled source size for comparisions
239 */
240static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400241 uint32_t src, uint32_t dst, uint32_t decimated_src,
242 uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
Clarence Ipe78efb72016-06-24 18:35:21 -0400243 int *out_edge2, enum sde_hw_filter *filter,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400244 const struct sde_format *fmt, uint32_t chroma_subsampling,
Clarence Ipe78efb72016-06-24 18:35:21 -0400245 bool post_compare)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400246{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400247 int64_t edge1, edge2, caf;
248 uint32_t src_work;
249 int i, tmp;
250
Clarence Ipcb410d42016-06-26 22:52:33 -0400251 if (psde && phase_steps && out_src && out_edge1 &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400252 out_edge2 && filter && fmt) {
253 /* handle CAF for YUV formats */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400254 if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400255 caf = PHASE_STEP_UNIT_SCALE;
256 else
257 caf = 0;
258
259 for (i = 0; i < SDE_MAX_PLANES; i++) {
260 src_work = decimated_src;
Clarence Ipe78efb72016-06-24 18:35:21 -0400261 if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400262 src_work /= chroma_subsampling;
263 if (post_compare)
264 src = src_work;
Clarence Ipdbde9832016-06-26 09:48:36 -0400265 if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400266 /* unity */
267 edge1 = 0;
268 edge2 = 0;
269 } else if (dst >= src) {
270 /* upscale */
271 edge1 = (1 << PHASE_RESIDUAL);
272 edge1 -= caf;
273 edge2 = (1 << PHASE_RESIDUAL);
274 edge2 += (dst - 1) * *(phase_steps + i);
275 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
276 edge2 += caf;
277 edge2 = -(edge2);
278 } else {
279 /* downscale */
280 edge1 = 0;
281 edge2 = (dst - 1) * *(phase_steps + i);
282 edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
283 edge2 += *(phase_steps + i);
284 edge2 = -(edge2);
285 }
286
287 /* only enable CAF for luma plane */
288 caf = 0;
289
290 /* populate output arrays */
291 *(out_src + i) = src_work;
292
293 /* edge updates taken from __pxl_extn_helper */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400294 if (edge1 >= 0) {
295 tmp = (uint32_t)edge1;
296 tmp >>= PHASE_STEP_SHIFT;
297 *(out_edge1 + i) = -tmp;
298 } else {
299 tmp = (uint32_t)(-edge1);
Clarence Ipe78efb72016-06-24 18:35:21 -0400300 *(out_edge1 + i) =
301 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
302 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400303 }
304 if (edge2 >= 0) {
305 tmp = (uint32_t)edge2;
306 tmp >>= PHASE_STEP_SHIFT;
307 *(out_edge2 + i) = -tmp;
308 } else {
309 tmp = (uint32_t)(-edge2);
Clarence Ipe78efb72016-06-24 18:35:21 -0400310 *(out_edge2 + i) =
311 (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
312 PHASE_STEP_SHIFT;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400313 }
314 }
315 }
316}
317
Clarence Ip5e2a9222016-06-26 22:38:24 -0400318/**
319 * _sde_plane_verify_blob - verify incoming blob is big enough to contain
320 * sub-structure
321 * @blob_ptr: Pointer to start of incoming blob data
322 * @blob_size: Size of incoming blob data, in bytes
323 * @sub_ptr: Pointer to start of desired sub-structure
324 * @sub_size: Required size of sub-structure, in bytes
325 */
326static int _sde_plane_verify_blob(void *blob_ptr,
327 size_t blob_size,
328 void *sub_ptr,
329 size_t sub_size)
330{
331 /*
332 * Use the blob size provided by drm to check if there are enough
333 * bytes from the start of versioned sub-structures to the end of
334 * blob data:
335 *
336 * e.g.,
337 * blob_ptr --> struct blob_data {
338 * uint32_t version;
339 * sub_ptr --> struct blob_data_v1 v1;
340 * sub_ptr + sub_size --> struct blob_stuff more_stuff;
341 * blob_ptr + blob_size --> };
342 *
343 * It's important to check the actual number of bytes from the start
344 * of the sub-structure to the end of the blob data, and not just rely
345 * on something like,
346 *
347 * sizeof(blob) - sizeof(blob->version) >= sizeof(sub-struct)
348 *
349 * This is because the start of the sub-structure can vary based on
350 * how the compiler pads the overall structure.
351 */
352 if (blob_ptr && sub_ptr)
353 /* return zero if end of blob >= end of sub-struct */
354 return ((unsigned char *)blob_ptr + blob_size) <
355 ((unsigned char *)sub_ptr + sub_size);
356 return -EINVAL;
357}
358
Clarence Ipe78efb72016-06-24 18:35:21 -0400359static void _sde_plane_setup_csc(struct sde_plane *psde,
360 struct sde_plane_state *pstate,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400361 const struct sde_format *fmt)
Clarence Ipe78efb72016-06-24 18:35:21 -0400362{
363 static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
364 {
Clarence Ip373f8592016-05-26 00:58:42 -0400365 /* S15.16 format */
366 0x00012A00, 0x00000000, 0x00019880,
367 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
368 0x00012A00, 0x00020480, 0x00000000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400369 },
Clarence Ip373f8592016-05-26 00:58:42 -0400370 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400371 { 0xfff0, 0xff80, 0xff80,},
372 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400373 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400374 { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400375 { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
Clarence Ipe78efb72016-06-24 18:35:21 -0400376 };
Clarence Ipe78efb72016-06-24 18:35:21 -0400377 static const struct sde_csc_cfg sde_csc_NOP = {
378 {
Clarence Ip373f8592016-05-26 00:58:42 -0400379 /* identity matrix, S15.16 format */
380 0x10000, 0x00000, 0x00000,
381 0x00000, 0x10000, 0x00000,
382 0x00000, 0x00000, 0x10000,
Clarence Ipe78efb72016-06-24 18:35:21 -0400383 },
Clarence Ip373f8592016-05-26 00:58:42 -0400384 /* signed bias */
Clarence Ipe78efb72016-06-24 18:35:21 -0400385 { 0x0, 0x0, 0x0,},
386 { 0x0, 0x0, 0x0,},
Clarence Ip373f8592016-05-26 00:58:42 -0400387 /* unsigned clamp */
Clarence Ipe78efb72016-06-24 18:35:21 -0400388 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,},
389 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff,},
390 };
Clarence Ip5e2a9222016-06-26 22:38:24 -0400391 struct sde_drm_csc *csc = NULL;
392 size_t csc_size = 0;
393 bool user_blob = false;
Clarence Ipe78efb72016-06-24 18:35:21 -0400394
Clarence Ipaa0faf42016-05-30 12:07:48 -0400395 if (!psde || !pstate || !fmt) {
396 DRM_ERROR("Invalid arguments\n");
397 return;
398 }
399 if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_csc)
Clarence Ipe78efb72016-06-24 18:35:21 -0400400 return;
401
Clarence Ip5e2a9222016-06-26 22:38:24 -0400402 /* check for user space override */
Clarence Ipaa0faf42016-05-30 12:07:48 -0400403 csc = msm_property_get_blob(&psde->property_info,
404 pstate->property_blobs,
405 &csc_size,
406 PLANE_PROP_CSC);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400407 if (csc) {
408 struct sde_csc_cfg cfg;
409 int i;
410
411 /* user space override */
412 memcpy(&cfg, &sde_csc_NOP, sizeof(struct sde_csc_cfg));
413 switch (csc->version) {
414 case SDE_DRM_CSC_V1:
415 if (!_sde_plane_verify_blob(csc,
416 csc_size,
417 &csc->v1,
418 sizeof(struct sde_drm_csc_v1))) {
419 for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
420 cfg.csc_mv[i] =
Clarence Ip373f8592016-05-26 00:58:42 -0400421 csc->v1.ctm_coeff[i] >> 16;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400422 for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
423 cfg.csc_pre_bv[i] =
424 csc->v1.pre_bias[i];
425 cfg.csc_post_bv[i] =
426 csc->v1.post_bias[i];
427 }
428 for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
429 cfg.csc_pre_lv[i] =
430 csc->v1.pre_clamp[i];
431 cfg.csc_post_lv[i] =
432 csc->v1.post_clamp[i];
433 }
434 user_blob = true;
435 }
436 break;
437 default:
438 break;
439 }
440
441 if (!user_blob)
442 DRM_ERROR("Invalid csc blob, v%lld\n", csc->version);
443 else
444 psde->pipe_hw->ops.setup_csc(psde->pipe_hw,
445 (struct sde_csc_cfg *)&cfg);
446 }
447
448 if (user_blob) {
449 DBG("User blobs override for CSC");
Clarence Ip373f8592016-05-26 00:58:42 -0400450 psde->csc_ptr = &psde->csc_cfg;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400451 /* revert to kernel default */
Clarence Ipdbde9832016-06-26 09:48:36 -0400452 } else if (SDE_FORMAT_IS_YUV(fmt)) {
Clarence Ip373f8592016-05-26 00:58:42 -0400453 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400454 } else {
Clarence Ip373f8592016-05-26 00:58:42 -0400455 psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_NOP;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400456 }
Clarence Ip373f8592016-05-26 00:58:42 -0400457
458 psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
Clarence Ipe78efb72016-06-24 18:35:21 -0400459}
460
Clarence Ipcb410d42016-06-26 22:52:33 -0400461static void _sde_plane_setup_scaler(struct sde_plane *psde,
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400462 const struct sde_format *fmt,
Clarence Ipcb410d42016-06-26 22:52:33 -0400463 struct sde_plane_state *pstate)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700464{
Clarence Ipcb410d42016-06-26 22:52:33 -0400465 struct sde_hw_pixel_ext *pe = NULL;
Clarence Ip5e2a9222016-06-26 22:38:24 -0400466 struct sde_drm_scaler *sc_u = NULL;
467 struct sde_drm_scaler_v1 *sc_u1 = NULL;
Clarence Ipcb410d42016-06-26 22:52:33 -0400468 size_t sc_u_size = 0;
469 uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
470 uint32_t tmp;
471 int i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400472
Clarence Ipcb410d42016-06-26 22:52:33 -0400473 if (!psde || !fmt)
474 return;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400475
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400476 pe = &(psde->pixel_ext);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400477 memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400478
Clarence Ip5e2a9222016-06-26 22:38:24 -0400479 /* get scaler config from user space */
Clarence Ipc3ffec12016-07-18 19:07:24 -0400480 if (pstate)
481 sc_u = msm_property_get_blob(&psde->property_info,
482 pstate->property_blobs,
483 &sc_u_size,
484 PLANE_PROP_SCALER);
Clarence Ip5e2a9222016-06-26 22:38:24 -0400485 if (sc_u) {
486 switch (sc_u->version) {
487 case SDE_DRM_SCALER_V1:
488 if (!_sde_plane_verify_blob(sc_u,
489 sc_u_size,
490 &sc_u->v1,
491 sizeof(*sc_u1)))
492 sc_u1 = &sc_u->v1;
493 break;
494 default:
495 DBG("Unrecognized scaler blob v%lld", sc_u->version);
496 break;
497 }
498 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400499
Clarence Ip04ec67d2016-05-26 01:16:15 -0400500 /* decimation */
501 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_DECIMATE)) {
502 psde->pipe_cfg.horz_decimation = sc_u1->horz_decimate;
503 psde->pipe_cfg.vert_decimation = sc_u1->vert_decimate;
Clarence Ipcb410d42016-06-26 22:52:33 -0400504 } else {
505 psde->pipe_cfg.horz_decimation = 0;
506 psde->pipe_cfg.vert_decimation = 0;
Clarence Ip04ec67d2016-05-26 01:16:15 -0400507 }
508
509 /* don't chroma subsample if decimating */
510 chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400511 drm_format_horz_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400512 chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 :
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400513 drm_format_vert_chroma_subsampling(fmt->base.pixel_format);
Clarence Ip04ec67d2016-05-26 01:16:15 -0400514
Clarence Ip5e2a9222016-06-26 22:38:24 -0400515 /* update scaler */
516 if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
517 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_3))
Clarence Ipcb410d42016-06-26 22:52:33 -0400518 DBG("SCALER3 blob detected");
Clarence Ip5e2a9222016-06-26 22:38:24 -0400519 else
Clarence Ipcb410d42016-06-26 22:52:33 -0400520 _sde_plane_setup_scaler3(psde,
521 psde->pipe_cfg.src_rect.w,
522 psde->pipe_cfg.src_rect.h,
523 psde->pipe_cfg.dst_rect.w,
524 psde->pipe_cfg.dst_rect.h,
525 &psde->scaler3_cfg, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400526 chroma_subsmpl_h, chroma_subsmpl_v);
527 } else {
528 /* always calculate basic scaler config */
529 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_SCALER_2)) {
530 /* populate from user space */
531 for (i = 0; i < SDE_MAX_PLANES; i++) {
532 pe->init_phase_x[i] = sc_u1->init_phase_x[i];
533 pe->phase_step_x[i] = sc_u1->phase_step_x[i];
534 pe->init_phase_y[i] = sc_u1->init_phase_y[i];
535 pe->phase_step_y[i] = sc_u1->phase_step_y[i];
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400536
Clarence Ip5e2a9222016-06-26 22:38:24 -0400537 pe->horz_filter[i] = sc_u1->horz_filter[i];
538 pe->vert_filter[i] = sc_u1->vert_filter[i];
539 }
540 } else {
541 /* calculate phase steps */
Clarence Ipcb410d42016-06-26 22:52:33 -0400542 _sde_plane_setup_scaler2(psde,
543 psde->pipe_cfg.src_rect.w,
544 psde->pipe_cfg.dst_rect.w,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400545 pe->phase_step_x,
546 pe->horz_filter, fmt, chroma_subsmpl_h);
Clarence Ipcb410d42016-06-26 22:52:33 -0400547 _sde_plane_setup_scaler2(psde,
548 psde->pipe_cfg.src_rect.h,
549 psde->pipe_cfg.dst_rect.h,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400550 pe->phase_step_y,
551 pe->vert_filter, fmt, chroma_subsmpl_v);
552 }
553 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400554
Clarence Ip5e2a9222016-06-26 22:38:24 -0400555 /* update pixel extensions */
556 if (sc_u1 && (sc_u1->enable & SDE_DRM_SCALER_PIX_EXT)) {
557 /* populate from user space */
Clarence Ipcb410d42016-06-26 22:52:33 -0400558 DBG("PIXEXT blob detected");
Clarence Ip5e2a9222016-06-26 22:38:24 -0400559 for (i = 0; i < SDE_MAX_PLANES; i++) {
560 pe->num_ext_pxls_left[i] = sc_u1->lr.num_pxls_start[i];
561 pe->num_ext_pxls_right[i] = sc_u1->lr.num_pxls_end[i];
562 pe->left_ftch[i] = sc_u1->lr.ftch_start[i];
563 pe->right_ftch[i] = sc_u1->lr.ftch_end[i];
564 pe->left_rpt[i] = sc_u1->lr.rpt_start[i];
565 pe->right_rpt[i] = sc_u1->lr.rpt_end[i];
566 pe->roi_w[i] = sc_u1->lr.roi[i];
567
568 pe->num_ext_pxls_top[i] = sc_u1->tb.num_pxls_start[i];
569 pe->num_ext_pxls_btm[i] = sc_u1->tb.num_pxls_end[i];
570 pe->top_ftch[i] = sc_u1->tb.ftch_start[i];
571 pe->btm_ftch[i] = sc_u1->tb.ftch_end[i];
572 pe->top_rpt[i] = sc_u1->tb.rpt_start[i];
573 pe->btm_rpt[i] = sc_u1->tb.rpt_end[i];
574 pe->roi_h[i] = sc_u1->tb.roi[i];
575 }
576 } else {
577 /* calculate left/right/top/bottom pixel extensions */
Clarence Ipcb410d42016-06-26 22:52:33 -0400578 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400579 psde->pipe_cfg.horz_decimation);
Clarence Ipdbde9832016-06-26 09:48:36 -0400580 if (SDE_FORMAT_IS_YUV(fmt))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400581 tmp &= ~0x1;
Clarence Ipcb410d42016-06-26 22:52:33 -0400582 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
583 psde->pipe_cfg.dst_rect.w, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400584 pe->phase_step_x,
585 pe->roi_w,
586 pe->num_ext_pxls_left,
Clarence Ipe78efb72016-06-24 18:35:21 -0400587 pe->num_ext_pxls_right, pe->horz_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400588 chroma_subsmpl_h, 0);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400589
Clarence Ipcb410d42016-06-26 22:52:33 -0400590 tmp = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400591 psde->pipe_cfg.vert_decimation);
Clarence Ipcb410d42016-06-26 22:52:33 -0400592 _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
593 psde->pipe_cfg.dst_rect.h, tmp,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400594 pe->phase_step_y,
595 pe->roi_h,
596 pe->num_ext_pxls_top,
Clarence Ipe78efb72016-06-24 18:35:21 -0400597 pe->num_ext_pxls_btm, pe->vert_filter, fmt,
Clarence Ip5e2a9222016-06-26 22:38:24 -0400598 chroma_subsmpl_v, 1);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400599
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400600 for (i = 0; i < SDE_MAX_PLANES; i++) {
601 if (pe->num_ext_pxls_left[i] >= 0)
602 pe->left_rpt[i] =
603 pe->num_ext_pxls_left[i];
604 else
605 pe->left_ftch[i] =
606 pe->num_ext_pxls_left[i];
607
608 if (pe->num_ext_pxls_right[i] >= 0)
609 pe->right_rpt[i] =
610 pe->num_ext_pxls_right[i];
611 else
612 pe->right_ftch[i] =
613 pe->num_ext_pxls_right[i];
614
615 if (pe->num_ext_pxls_top[i] >= 0)
616 pe->top_rpt[i] =
617 pe->num_ext_pxls_top[i];
618 else
619 pe->top_ftch[i] =
620 pe->num_ext_pxls_top[i];
621
622 if (pe->num_ext_pxls_btm[i] >= 0)
623 pe->btm_rpt[i] =
624 pe->num_ext_pxls_btm[i];
625 else
626 pe->btm_ftch[i] =
627 pe->num_ext_pxls_btm[i];
628 }
629 }
Clarence Ipcb410d42016-06-26 22:52:33 -0400630}
631
632int sde_plane_color_fill(struct drm_plane *plane,
633 uint32_t color, uint32_t alpha)
634{
635 struct sde_plane *psde;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400636 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400637
638 if (!plane) {
639 DRM_ERROR("Invalid plane\n");
640 return -EINVAL;
641 }
642
643 psde = to_sde_plane(plane);
644 if (!psde->pipe_hw) {
645 DRM_ERROR("Invalid plane h/w pointer\n");
646 return -EINVAL;
647 }
648
649 /*
650 * select fill format to match user property expectation,
651 * h/w only supports RGB variants
652 */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400653 fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
Clarence Ipcb410d42016-06-26 22:52:33 -0400654
655 /* update sspp */
656 if (fmt && psde->pipe_hw->ops.setup_solidfill) {
657 psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
658 (color & 0xFFFFFF) | ((alpha & 0xFF) << 24));
659
660 /* override scaler/decimation if solid fill */
661 psde->pipe_cfg.src_rect.x = 0;
662 psde->pipe_cfg.src_rect.y = 0;
663 psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
664 psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
665
666 _sde_plane_setup_scaler(psde, fmt, 0);
667
668 if (psde->pipe_hw->ops.setup_format)
669 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
670 fmt, SDE_SSPP_SOLID_FILL);
671
672 if (psde->pipe_hw->ops.setup_rects)
673 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
674 &psde->pipe_cfg, &psde->pixel_ext);
675 }
676
677 return 0;
678}
679
680static int _sde_plane_mode_set(struct drm_plane *plane,
681 struct drm_crtc *crtc, struct drm_framebuffer *fb,
682 int crtc_x, int crtc_y,
683 unsigned int crtc_w, unsigned int crtc_h,
684 uint32_t src_x, uint32_t src_y,
685 uint32_t src_w, uint32_t src_h)
686{
687 struct sde_plane *psde;
688 struct sde_plane_state *pstate;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400689 uint32_t nplanes, color_fill;
Clarence Ipcb410d42016-06-26 22:52:33 -0400690 uint32_t src_flags;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400691 const struct sde_format *fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400692
693 DBG("");
694
695 if (!plane || !plane->state) {
696 DRM_ERROR("Invalid plane/state\n");
697 return -EINVAL;
698 }
699 if (!crtc || !fb) {
700 DRM_ERROR("Invalid crtc/fb\n");
701 return -EINVAL;
702 }
703
704 psde = to_sde_plane(plane);
705 pstate = to_sde_plane_state(plane->state);
706 nplanes = drm_format_num_planes(fb->pixel_format);
707
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400708 fmt = to_sde_format(msm_framebuffer_format(fb));
Clarence Ipcb410d42016-06-26 22:52:33 -0400709
710 /* src values are in Q16 fixed point, convert to integer */
711 src_x = src_x >> 16;
712 src_y = src_y >> 16;
713 src_w = src_w >> 16;
714 src_h = src_h >> 16;
715
716 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", psde->pipe_name,
717 fb->base.id, src_x, src_y, src_w, src_h,
718 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
719
720 /* update format configuration */
721 memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
722 src_flags = 0;
723
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400724 psde->pipe_cfg.src.format = fmt;
Clarence Ipcb410d42016-06-26 22:52:33 -0400725 psde->pipe_cfg.src.width = fb->width;
726 psde->pipe_cfg.src.height = fb->height;
727 psde->pipe_cfg.src.num_planes = nplanes;
728
729 /* flags */
730 DBG("Flags 0x%llX, rotation 0x%llX",
731 sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG),
732 sde_plane_get_property(pstate, PLANE_PROP_ROTATION));
733 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
734 BIT(DRM_REFLECT_X))
735 src_flags |= SDE_SSPP_FLIP_LR;
736 if (sde_plane_get_property(pstate, PLANE_PROP_ROTATION) &
737 BIT(DRM_REFLECT_Y))
738 src_flags |= SDE_SSPP_FLIP_UD;
739 if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
740 BIT(SDE_DRM_DEINTERLACE)) {
741 src_h /= 2;
742 src_y = DIV_ROUND_UP(src_y, 2);
743 src_y &= ~0x1;
744 }
745
746 psde->pipe_cfg.src_rect.x = src_x;
747 psde->pipe_cfg.src_rect.y = src_y;
748 psde->pipe_cfg.src_rect.w = src_w;
749 psde->pipe_cfg.src_rect.h = src_h;
750
751 psde->pipe_cfg.dst_rect.x = crtc_x;
752 psde->pipe_cfg.dst_rect.y = crtc_y;
753 psde->pipe_cfg.dst_rect.w = crtc_w;
754 psde->pipe_cfg.dst_rect.h = crtc_h;
755
756 /* get sde pixel format definition */
757 fmt = psde->pipe_cfg.src.format;
758
759 /* check for color fill */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400760 color_fill = (uint32_t)sde_plane_get_property(pstate,
761 PLANE_PROP_COLOR_FILL);
762 if (color_fill & BIT(31)) {
Clarence Ipcb410d42016-06-26 22:52:33 -0400763 /* force 100% alpha, stop other processing */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400764 return sde_plane_color_fill(plane, color_fill, 0xFF);
Clarence Ipcb410d42016-06-26 22:52:33 -0400765 }
766
767 _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
768
769 _sde_plane_setup_scaler(psde, fmt, pstate);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400770
Clarence Ip4c1d9772016-06-26 09:35:38 -0400771 if (psde->pipe_hw->ops.setup_format)
772 psde->pipe_hw->ops.setup_format(psde->pipe_hw,
Clarence Ipcb410d42016-06-26 22:52:33 -0400773 fmt, src_flags);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400774 if (psde->pipe_hw->ops.setup_rects)
775 psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
776 &psde->pipe_cfg, &psde->pixel_ext);
777
Clarence Ipe78efb72016-06-24 18:35:21 -0400778 /* update sharpening */
779 psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
780 psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
781 psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
782 psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
783
784 if (psde->pipe_hw->ops.setup_sharpening)
785 psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
786 &psde->sharp_cfg);
787
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400788 /* update csc */
Clarence Ipdbde9832016-06-26 09:48:36 -0400789 if (SDE_FORMAT_IS_YUV(fmt))
Clarence Ipe78efb72016-06-24 18:35:21 -0400790 _sde_plane_setup_csc(psde, pstate, fmt);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400791
Clarence Ip5e2a9222016-06-26 22:38:24 -0400792 return 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400793}
794
795static int sde_plane_prepare_fb(struct drm_plane *plane,
796 const struct drm_plane_state *new_state)
797{
798 struct drm_framebuffer *fb = new_state->fb;
799 struct sde_plane *psde = to_sde_plane(plane);
800
801 if (!new_state->fb)
802 return 0;
803
Clarence Ipae4e60c2016-06-26 22:44:04 -0400804 DBG("%s: FB[%u]", psde->pipe_name, fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400805 return msm_framebuffer_prepare(fb, psde->mmu_id);
806}
807
808static void sde_plane_cleanup_fb(struct drm_plane *plane,
809 const struct drm_plane_state *old_state)
810{
811 struct drm_framebuffer *fb = old_state->fb;
812 struct sde_plane *psde = to_sde_plane(plane);
813
814 if (!fb)
815 return;
816
Clarence Ipae4e60c2016-06-26 22:44:04 -0400817 DBG("%s: FB[%u]", psde->pipe_name, fb->base.id);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400818 msm_framebuffer_cleanup(fb, psde->mmu_id);
819}
820
Clarence Ipdbde9832016-06-26 09:48:36 -0400821static int _sde_plane_atomic_check_fb(struct sde_plane *psde,
822 struct sde_plane_state *pstate,
823 struct drm_framebuffer *fb)
824{
825 return 0;
826}
827
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400828static int sde_plane_atomic_check(struct drm_plane *plane,
829 struct drm_plane_state *state)
830{
Clarence Ipdbde9832016-06-26 09:48:36 -0400831 struct sde_plane *psde;
832 struct sde_plane_state *pstate;
833 struct drm_plane_state *old_state;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400834 const struct sde_format *fmt;
Clarence Ipdbde9832016-06-26 09:48:36 -0400835 size_t sc_u_size = 0;
836 struct sde_drm_scaler *sc_u = NULL;
837 int ret = 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400838
Clarence Ipdbde9832016-06-26 09:48:36 -0400839 uint32_t src_x, src_y;
840 uint32_t src_w, src_h;
841 uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
842 uint32_t src_max_x, src_max_y, src_max_w, src_max_h;
843 uint32_t upscale_max, downscale_max;
844
845 DBG();
846
847 if (!plane || !state) {
848 DRM_ERROR("Invalid plane/state\n");
849 ret = -EINVAL;
850 goto exit;
851 }
852
853 psde = to_sde_plane(plane);
854 pstate = to_sde_plane_state(state);
855 old_state = plane->state;
856
857 if (!psde->pipe_sblk) {
858 DRM_ERROR("Invalid plane catalog\n");
859 ret = -EINVAL;
860 goto exit;
861 }
862
863 /* get decimation config from user space */
864 deci_w = 0;
865 deci_h = 0;
Clarence Ipaa0faf42016-05-30 12:07:48 -0400866 sc_u = msm_property_get_blob(&psde->property_info,
867 pstate->property_blobs,
868 &sc_u_size,
869 PLANE_PROP_SCALER);
Clarence Ipdbde9832016-06-26 09:48:36 -0400870 if (sc_u) {
871 switch (sc_u->version) {
872 case SDE_DRM_SCALER_V1:
873 if (!_sde_plane_verify_blob(sc_u,
874 sc_u_size,
875 &sc_u->v1,
876 sizeof(struct sde_drm_scaler_v1))) {
877 deci_w = sc_u->v1.horz_decimate;
878 deci_h = sc_u->v1.vert_decimate;
879 }
880 break;
881 default:
882 DBG("Unrecognized scaler blob v%lld", sc_u->version);
883 break;
884 }
885 }
886
887 /* src values are in Q16 fixed point, convert to integer */
888 src_x = state->src_x >> 16;
889 src_y = state->src_y >> 16;
890 src_w = state->src_w >> 16;
891 src_h = state->src_h >> 16;
892
893 src_deci_w = DECIMATED_DIMENSION(src_w, deci_w);
894 src_deci_h = DECIMATED_DIMENSION(src_h, deci_h);
895
896 src_max_x = 0xFFFF;
897 src_max_y = 0xFFFF;
898 src_max_w = 0x3FFF;
899 src_max_h = 0x3FFF;
900 upscale_max = psde->pipe_sblk->maxupscale;
901 downscale_max = psde->pipe_sblk->maxdwnscale;
902
903 /*
904 * Including checks from mdss
905 * - mdss_mdp_overlay_req_check()
906 */
Clarence Ip4ce59322016-06-26 22:27:51 -0400907 DBG("%s: check (%d -> %d)", psde->pipe_name,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400908 sde_plane_enabled(old_state), sde_plane_enabled(state));
909
910 if (sde_plane_enabled(state)) {
Clarence Ipdbde9832016-06-26 09:48:36 -0400911 /* determine SDE format definition. State's fb is valid here. */
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400912 fmt = to_sde_format(msm_framebuffer_format(state->fb));
Clarence Ipdbde9832016-06-26 09:48:36 -0400913
914 /* don't check for other errors after first failure */
915 if (SDE_FORMAT_IS_YUV(fmt) &&
Clarence Ipe78efb72016-06-24 18:35:21 -0400916 (!(psde->features & SDE_SSPP_SCALER) ||
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400917 !(psde->features & BIT(SDE_SSPP_CSC)))) {
Lloyd Atkinsond49de562016-05-30 13:23:48 -0400918 DRM_ERROR("Pipe doesn't support YUV\n");
Clarence Ipdbde9832016-06-26 09:48:36 -0400919 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400920
Clarence Ipdbde9832016-06-26 09:48:36 -0400921 /* verify source size/region */
922 } else if (!src_w || !src_h ||
923 (src_w > src_max_w) || (src_h > src_max_h) ||
924 (src_x > src_max_x) || (src_y > src_max_y) ||
925 (src_x + src_w > src_max_x) ||
926 (src_y + src_h > src_max_y)) {
927 DRM_ERROR("Invalid source (%u, %u) -> (%u, %u)\n",
928 src_x, src_y, src_x + src_w,
929 src_y + src_h);
930 ret = -EINVAL;
931
932 /* require even source for YUV */
933 } else if (SDE_FORMAT_IS_YUV(fmt) &&
934 ((src_x & 0x1) || (src_y & 0x1) ||
935 (src_w & 0x1) || (src_h & 0x1))) {
936 DRM_ERROR("Invalid odd src res/pos for YUV\n");
937 ret = -EINVAL;
938
939 /* verify scaler requirements */
940 } else if (!(psde->features & SDE_SSPP_SCALER) &&
941 ((src_w != state->crtc_w) ||
942 (src_h != state->crtc_h))) {
943 DRM_ERROR("Pipe doesn't support scaling %ux%u->%ux%u\n",
944 src_w, src_h, state->crtc_w,
945 state->crtc_h);
946 ret = -EINVAL;
947
948 /* check decimated source width */
949 } else if (src_deci_w > psde->pipe_sblk->maxlinewidth) {
950 DRM_ERROR("Invalid source [W:%u, Wd:%u] > %u\n",
951 src_w, src_deci_w,
952 psde->pipe_sblk->maxlinewidth);
953 ret = -EINVAL;
954
955 /* check max scaler capability */
956 } else if (((src_deci_w * upscale_max) < state->crtc_w) ||
957 ((src_deci_h * upscale_max) < state->crtc_h) ||
958 ((state->crtc_w * downscale_max) < src_deci_w) ||
959 ((state->crtc_h * downscale_max) < src_deci_h)) {
960 DRM_ERROR("Too much scaling requested %ux%u -> %ux%u\n",
961 src_deci_w, src_deci_h,
962 state->crtc_w, state->crtc_h);
963 ret = -EINVAL;
964
965 /* check frame buffer */
966 } else if (_sde_plane_atomic_check_fb(
967 psde, pstate, state->fb)) {
968 ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400969 }
970
Clarence Ipdbde9832016-06-26 09:48:36 -0400971 /* check decimation (and bwc/fetch mode) */
972 if (!ret && (deci_w || deci_h)) {
973 if (SDE_FORMAT_IS_UBWC(fmt)) {
974 DRM_ERROR("No decimation with BWC\n");
975 ret = -EINVAL;
976 } else if ((deci_w > psde->pipe_sblk->maxhdeciexp) ||
977 (deci_h > psde->pipe_sblk->maxvdeciexp)) {
978 DRM_ERROR("Too much decimation requested\n");
979 ret = -EINVAL;
Lloyd Atkinson9a673492016-07-05 11:41:57 -0400980 } else if (fmt->fetch_mode != SDE_FETCH_LINEAR) {
Clarence Ipdbde9832016-06-26 09:48:36 -0400981 DRM_ERROR("Decimation requires linear fetch\n");
982 ret = -EINVAL;
983 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400984 }
985 }
986
Clarence Ipdbde9832016-06-26 09:48:36 -0400987 if (!ret) {
988 if (sde_plane_enabled(state) &&
989 sde_plane_enabled(old_state)) {
990 bool full_modeset = false;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400991
Clarence Ipdbde9832016-06-26 09:48:36 -0400992 if (state->fb->pixel_format !=
993 old_state->fb->pixel_format) {
994 DBG("%s: format change!", psde->pipe_name);
995 full_modeset = true;
996 }
997 if (state->src_w != old_state->src_w ||
998 state->src_h != old_state->src_h) {
999 DBG("%s: src_w change!", psde->pipe_name);
1000 full_modeset = true;
1001 }
1002 if (to_sde_plane_state(old_state)->pending) {
1003 DBG("%s: still pending!", psde->pipe_name);
1004 full_modeset = true;
1005 }
Lloyd Atkinson66358902016-03-23 11:58:23 -04001006 if (full_modeset)
Clarence Ipdbde9832016-06-26 09:48:36 -04001007 to_sde_plane_state(state)->mode_changed = true;
Lloyd Atkinson66358902016-03-23 11:58:23 -04001008
Clarence Ipdbde9832016-06-26 09:48:36 -04001009 } else {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001010 to_sde_plane_state(state)->mode_changed = true;
1011 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001012 }
1013
Clarence Ipdbde9832016-06-26 09:48:36 -04001014exit:
1015 return ret;
1016}
1017
1018void sde_plane_complete_flip(struct drm_plane *plane)
1019{
1020 if (plane && plane->state)
1021 to_sde_plane_state(plane->state)->pending = false;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001022}
1023
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001024static void sde_plane_atomic_update(struct drm_plane *plane,
Clarence Ipe78efb72016-06-24 18:35:21 -04001025 struct drm_plane_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001026{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001027 struct sde_plane *sde_plane;
1028 struct drm_plane_state *state;
1029 struct sde_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001030
Clarence Ip5e2a9222016-06-26 22:38:24 -04001031 if (!plane || !plane->state) {
1032 DRM_ERROR("Invalid plane/state\n");
1033 return;
1034 }
1035
1036 sde_plane = to_sde_plane(plane);
1037 state = plane->state;
1038 pstate = to_sde_plane_state(state);
1039
Clarence Ipae4e60c2016-06-26 22:44:04 -04001040 DBG("%s: update", sde_plane->pipe_name);
1041
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001042 if (!sde_plane_enabled(state)) {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001043 pstate->pending = true;
1044 } else if (pstate->mode_changed) {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001045 int ret;
1046
Clarence Ip5e2a9222016-06-26 22:38:24 -04001047 pstate->pending = true;
Clarence Ipe78efb72016-06-24 18:35:21 -04001048 ret = _sde_plane_mode_set(plane,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001049 state->crtc, state->fb,
1050 state->crtc_x, state->crtc_y,
1051 state->crtc_w, state->crtc_h,
1052 state->src_x, state->src_y,
1053 state->src_w, state->src_h);
1054 /* atomic_check should have ensured that this doesn't fail */
1055 WARN_ON(ret < 0);
1056 } else {
Clarence Ip5e2a9222016-06-26 22:38:24 -04001057 _sde_plane_set_scanout(plane, pstate,
1058 &sde_plane->pipe_cfg, state->fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001059 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001060}
1061
1062/* helper to install properties which are common to planes and crtcs */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001063static void _sde_plane_install_properties(struct drm_plane *plane)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001064{
Clarence Ip5e2a9222016-06-26 22:38:24 -04001065 static const struct drm_prop_enum_list e_blend_op[] = {
1066 {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
1067 {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
1068 {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
1069 {SDE_DRM_BLEND_OP_COVERAGE, "coverage"}
1070 };
1071 static const struct drm_prop_enum_list e_src_config[] = {
1072 {SDE_DRM_DEINTERLACE, "deinterlace"}
1073 };
1074 struct sde_plane *psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001075
Clarence Ip4ce59322016-06-26 22:27:51 -04001076 DBG("");
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001077
Clarence Ipaa0faf42016-05-30 12:07:48 -04001078 if (!plane || !psde || !psde->pipe_hw || !psde->pipe_sblk) {
1079 DRM_ERROR("Invalid argument(s)\n");
Clarence Ip5e2a9222016-06-26 22:38:24 -04001080 return;
1081 }
1082
1083 /* range properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001084 msm_property_install_range(&psde->property_info, "zpos", 0, 255,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001085 plane->type == DRM_PLANE_TYPE_PRIMARY ?
1086 STAGE_BASE : STAGE0 + drm_plane_index(plane),
1087 PLANE_PROP_ZPOS);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001088
Clarence Ipaa0faf42016-05-30 12:07:48 -04001089 msm_property_install_range(&psde->property_info, "alpha", 0, 255, 255,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001090 PLANE_PROP_ALPHA);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001091
Clarence Ipcb410d42016-06-26 22:52:33 -04001092 if (psde->pipe_hw->ops.setup_solidfill)
Clarence Ipaa0faf42016-05-30 12:07:48 -04001093 msm_property_install_range(&psde->property_info, "color_fill",
Clarence Ipcb410d42016-06-26 22:52:33 -04001094 0, 0xFFFFFFFF, 0,
1095 PLANE_PROP_COLOR_FILL);
1096
Clarence Ipaa0faf42016-05-30 12:07:48 -04001097 msm_property_install_range(&psde->property_info, "sync_fence",
1098 0, ~0, ~0, PLANE_PROP_SYNC_FENCE);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001099
Clarence Ipaa0faf42016-05-30 12:07:48 -04001100 msm_property_install_range(&psde->property_info, "sync_fence_timeout",
Clarence Ipcb410d42016-06-26 22:52:33 -04001101 0, ~0, 10000,
1102 PLANE_PROP_SYNC_FENCE_TIMEOUT);
1103
Clarence Ip5e2a9222016-06-26 22:38:24 -04001104 /* standard properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001105 msm_property_install_rotation(&psde->property_info,
1106 BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y),
1107 PLANE_PROP_ROTATION);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001108
Clarence Ip04ec67d2016-05-26 01:16:15 -04001109 /* enum/bitmask properties */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001110 msm_property_install_enum(&psde->property_info, "blend_op", 0,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001111 e_blend_op, ARRAY_SIZE(e_blend_op),
Clarence Ipae4e60c2016-06-26 22:44:04 -04001112 PLANE_PROP_BLEND_OP);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001113 msm_property_install_enum(&psde->property_info, "src_config", 1,
Clarence Ip5e2a9222016-06-26 22:38:24 -04001114 e_src_config, ARRAY_SIZE(e_src_config),
Clarence Ipae4e60c2016-06-26 22:44:04 -04001115 PLANE_PROP_SRC_CONFIG);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001116
Clarence Ipe78efb72016-06-24 18:35:21 -04001117 /* blob properties */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001118 if (psde->features & SDE_SSPP_SCALER)
Clarence Ipaa0faf42016-05-30 12:07:48 -04001119 msm_property_install_blob(&psde->property_info, "scaler", 0,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001120 PLANE_PROP_SCALER);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001121 if (psde->features & BIT(SDE_SSPP_CSC)) {
1122 msm_property_install_blob(&psde->property_info, "csc", 0,
Clarence Ipae4e60c2016-06-26 22:44:04 -04001123 PLANE_PROP_CSC);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001124 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001125}
1126
1127static int sde_plane_atomic_set_property(struct drm_plane *plane,
1128 struct drm_plane_state *state, struct drm_property *property,
1129 uint64_t val)
1130{
Clarence Ip730e7192016-06-26 22:45:09 -04001131 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001132 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001133 int idx, ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001134
Clarence Ipaa0faf42016-05-30 12:07:48 -04001135 DBG("");
1136
1137 if (!plane) {
1138 DRM_ERROR("Invalid plane\n");
1139 } else if (!state) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001140 DRM_ERROR("Invalid state\n");
Clarence Ip730e7192016-06-26 22:45:09 -04001141 } else {
1142 psde = to_sde_plane(plane);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001143 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001144 ret = msm_property_atomic_set(&psde->property_info,
1145 pstate->property_values, pstate->property_blobs,
1146 property, val);
1147 if (!ret) {
1148 idx = msm_property_index(&psde->property_info,
1149 property);
1150 if (idx == PLANE_PROP_SYNC_FENCE)
1151 _sde_plane_update_sync_fence(plane,
1152 pstate, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001153 }
1154 }
1155
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001156 return ret;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001157}
1158
1159static int sde_plane_set_property(struct drm_plane *plane,
1160 struct drm_property *property, uint64_t val)
1161{
Clarence Ip4ce59322016-06-26 22:27:51 -04001162 DBG("");
Clarence Ip4c1d9772016-06-26 09:35:38 -04001163
Clarence Ipae4e60c2016-06-26 22:44:04 -04001164 return sde_plane_atomic_set_property(plane,
1165 plane->state, property, val);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001166}
1167
1168static int sde_plane_atomic_get_property(struct drm_plane *plane,
1169 const struct drm_plane_state *state,
1170 struct drm_property *property, uint64_t *val)
1171{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001172 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001173 struct sde_plane_state *pstate;
Clarence Ipaa0faf42016-05-30 12:07:48 -04001174 int ret = -EINVAL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001175
Clarence Ipaa0faf42016-05-30 12:07:48 -04001176 DBG("");
1177
1178 if (!plane) {
1179 DRM_ERROR("Invalid plane\n");
1180 } else if (!state) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001181 DRM_ERROR("Invalid state\n");
Clarence Ipaa0faf42016-05-30 12:07:48 -04001182 } else {
1183 psde = to_sde_plane(plane);
Clarence Ip4c1d9772016-06-26 09:35:38 -04001184 pstate = to_sde_plane_state(state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001185 ret = msm_property_atomic_get(&psde->property_info,
1186 pstate->property_values, pstate->property_blobs,
1187 property, val);
Clarence Ipe78efb72016-06-24 18:35:21 -04001188 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001189
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001190 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001191}
1192
1193static void sde_plane_destroy(struct drm_plane *plane)
1194{
Clarence Ip4ce59322016-06-26 22:27:51 -04001195 struct sde_plane *psde;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001196
Clarence Ip4ce59322016-06-26 22:27:51 -04001197 DBG("");
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001198
Clarence Ip4ce59322016-06-26 22:27:51 -04001199 if (plane) {
1200 psde = to_sde_plane(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001201
Clarence Ip4ce59322016-06-26 22:27:51 -04001202 debugfs_remove_recursive(psde->debugfs_root);
Clarence Ipe78efb72016-06-24 18:35:21 -04001203
Clarence Ipaa0faf42016-05-30 12:07:48 -04001204 msm_property_destroy(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001205 mutex_destroy(&psde->lock);
1206
Clarence Ip4ce59322016-06-26 22:27:51 -04001207 drm_plane_helper_disable(plane);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001208
Clarence Ip4ce59322016-06-26 22:27:51 -04001209 /* this will destroy the states as well */
1210 drm_plane_cleanup(plane);
1211
Clarence Ip4c1d9772016-06-26 09:35:38 -04001212 if (psde->pipe_hw)
1213 sde_hw_sspp_destroy(psde->pipe_hw);
1214
Clarence Ip4ce59322016-06-26 22:27:51 -04001215 kfree(psde);
1216 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001217}
1218
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001219static void sde_plane_destroy_state(struct drm_plane *plane,
1220 struct drm_plane_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001221{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001222 struct sde_plane *psde;
Clarence Ipe78efb72016-06-24 18:35:21 -04001223 struct sde_plane_state *pstate;
Clarence Ipe78efb72016-06-24 18:35:21 -04001224
Clarence Ipae4e60c2016-06-26 22:44:04 -04001225 if (!plane || !state) {
1226 DRM_ERROR("Invalid plane/state\n");
1227 return;
1228 }
1229
Clarence Ipaa0faf42016-05-30 12:07:48 -04001230 psde = to_sde_plane(plane);
Clarence Ip730e7192016-06-26 22:45:09 -04001231 pstate = to_sde_plane_state(state);
1232
1233 DBG("");
1234
Clarence Ipe78efb72016-06-24 18:35:21 -04001235 /* remove ref count for frame buffers */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001236 if (state->fb)
1237 drm_framebuffer_unreference(state->fb);
1238
Clarence Ipae4e60c2016-06-26 22:44:04 -04001239 /* remove ref count for fence */
1240 if (pstate->sync_fence)
1241 sde_sync_put(pstate->sync_fence);
1242
Clarence Ipaa0faf42016-05-30 12:07:48 -04001243 /* destroy value helper */
1244 msm_property_destroy_state(&psde->property_info, pstate,
1245 pstate->property_values, pstate->property_blobs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001246}
1247
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001248static struct drm_plane_state *
1249sde_plane_duplicate_state(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001250{
Clarence Ipaa0faf42016-05-30 12:07:48 -04001251 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001252 struct sde_plane_state *pstate;
Clarence Ip730e7192016-06-26 22:45:09 -04001253 struct sde_plane_state *old_state;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001254
Clarence Ip730e7192016-06-26 22:45:09 -04001255 if (!plane || !plane->state)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001256 return NULL;
1257
Clarence Ip730e7192016-06-26 22:45:09 -04001258 old_state = to_sde_plane_state(plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001259 psde = to_sde_plane(plane);
1260 pstate = msm_property_alloc_state(&psde->property_info);
Clarence Ip730e7192016-06-26 22:45:09 -04001261 if (!pstate)
1262 return NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001263
Clarence Ipaa0faf42016-05-30 12:07:48 -04001264 DBG("");
1265
1266 /* duplicate value helper */
1267 msm_property_duplicate_state(&psde->property_info, old_state, pstate,
1268 pstate->property_values, pstate->property_blobs);
Clarence Ipae4e60c2016-06-26 22:44:04 -04001269
Clarence Ip730e7192016-06-26 22:45:09 -04001270 /* add ref count for frame buffer */
1271 if (pstate->base.fb)
1272 drm_framebuffer_reference(pstate->base.fb);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001273
Clarence Ip730e7192016-06-26 22:45:09 -04001274 /* add ref count for fence */
1275 if (pstate->sync_fence) {
1276 pstate->sync_fence = 0;
1277 _sde_plane_update_sync_fence(plane, pstate, pstate->
1278 property_values[PLANE_PROP_SYNC_FENCE]);
Clarence Ipe78efb72016-06-24 18:35:21 -04001279 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001280
Clarence Ip730e7192016-06-26 22:45:09 -04001281 pstate->mode_changed = false;
1282 pstate->pending = false;
1283
1284 return &pstate->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001285}
1286
1287static void sde_plane_reset(struct drm_plane *plane)
1288{
Clarence Ipae4e60c2016-06-26 22:44:04 -04001289 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001290 struct sde_plane_state *pstate;
1291
Clarence Ipae4e60c2016-06-26 22:44:04 -04001292 if (!plane) {
1293 DRM_ERROR("Invalid plane\n");
1294 return;
1295 }
1296
Clarence Ip730e7192016-06-26 22:45:09 -04001297 psde = to_sde_plane(plane);
1298 DBG("%s", psde->pipe_name);
1299
Clarence Ipae4e60c2016-06-26 22:44:04 -04001300 /* remove previous state, if present */
Clarence Ipaa0faf42016-05-30 12:07:48 -04001301 if (plane->state) {
Clarence Ipae4e60c2016-06-26 22:44:04 -04001302 sde_plane_destroy_state(plane, plane->state);
Clarence Ipaa0faf42016-05-30 12:07:48 -04001303 plane->state = 0;
Clarence Ipae4e60c2016-06-26 22:44:04 -04001304 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001305
Clarence Ipaa0faf42016-05-30 12:07:48 -04001306 pstate = msm_property_alloc_state(&psde->property_info);
1307 if (!pstate)
1308 return;
Clarence Ip730e7192016-06-26 22:45:09 -04001309
Clarence Ipaa0faf42016-05-30 12:07:48 -04001310 /* reset value helper */
1311 msm_property_reset_state(&psde->property_info, pstate,
1312 pstate->property_values, pstate->property_blobs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001313
1314 pstate->base.plane = plane;
1315
1316 plane->state = &pstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001317}
1318
1319static const struct drm_plane_funcs sde_plane_funcs = {
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001320 .update_plane = drm_atomic_helper_update_plane,
1321 .disable_plane = drm_atomic_helper_disable_plane,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001322 .destroy = sde_plane_destroy,
1323 .set_property = sde_plane_set_property,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001324 .atomic_set_property = sde_plane_atomic_set_property,
1325 .atomic_get_property = sde_plane_atomic_get_property,
1326 .reset = sde_plane_reset,
1327 .atomic_duplicate_state = sde_plane_duplicate_state,
1328 .atomic_destroy_state = sde_plane_destroy_state,
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001329};
1330
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001331static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
1332 .prepare_fb = sde_plane_prepare_fb,
1333 .cleanup_fb = sde_plane_cleanup_fb,
1334 .atomic_check = sde_plane_atomic_check,
1335 .atomic_update = sde_plane_atomic_update,
1336};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001337
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001338enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001339{
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001340 struct sde_plane *sde_plane = to_sde_plane(plane);
1341
1342 return sde_plane->pipe;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001343}
1344
Clarence Ip4ce59322016-06-26 22:27:51 -04001345static void _sde_plane_init_debugfs(struct sde_plane *psde, struct sde_kms *kms)
1346{
1347 const struct sde_sspp_sub_blks *sblk = 0;
1348 const struct sde_sspp_cfg *cfg = 0;
1349
1350 if (psde && psde->pipe_hw)
1351 cfg = psde->pipe_hw->cap;
1352 if (cfg)
1353 sblk = cfg->sblk;
1354
1355 if (kms && sblk) {
1356 /* create overall sub-directory for the pipe */
1357 psde->debugfs_root =
1358 debugfs_create_dir(psde->pipe_name,
1359 sde_debugfs_get_root(kms));
1360 if (psde->debugfs_root) {
1361 /* don't error check these */
Clarence Ip4c1d9772016-06-26 09:35:38 -04001362 debugfs_create_x32("features", 0644,
Clarence Ip4ce59322016-06-26 22:27:51 -04001363 psde->debugfs_root, &psde->features);
1364
1365 /* add register dump support */
1366 sde_debugfs_setup_regset32(&psde->debugfs_src,
1367 sblk->src_blk.base + cfg->base,
1368 sblk->src_blk.len,
1369 kms->mmio);
1370 sde_debugfs_create_regset32("src_blk", 0444,
1371 psde->debugfs_root, &psde->debugfs_src);
1372
1373 sde_debugfs_setup_regset32(&psde->debugfs_scaler,
1374 sblk->scaler_blk.base + cfg->base,
1375 sblk->scaler_blk.len,
1376 kms->mmio);
1377 sde_debugfs_create_regset32("scaler_blk", 0444,
1378 psde->debugfs_root,
1379 &psde->debugfs_scaler);
1380
1381 sde_debugfs_setup_regset32(&psde->debugfs_csc,
1382 sblk->csc_blk.base + cfg->base,
1383 sblk->csc_blk.len,
1384 kms->mmio);
1385 sde_debugfs_create_regset32("csc_blk", 0444,
1386 psde->debugfs_root, &psde->debugfs_csc);
1387 }
1388 }
1389}
1390
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001391/* initialize plane */
Clarence Ipe78efb72016-06-24 18:35:21 -04001392struct drm_plane *sde_plane_init(struct drm_device *dev,
Clarence Ip4c1d9772016-06-26 09:35:38 -04001393 uint32_t pipe, bool primary_plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001394{
1395 struct drm_plane *plane = NULL;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001396 struct sde_plane *psde;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001397 struct msm_drm_private *priv;
1398 struct sde_kms *kms;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001399 enum drm_plane_type type;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001400 int ret = -EINVAL;
1401
1402 if (!dev) {
1403 DRM_ERROR("[%u]Device is NULL\n", pipe);
1404 goto exit;
1405 }
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001406
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001407 priv = dev->dev_private;
Ben Chan78647cd2016-06-26 22:02:47 -04001408 if (!priv) {
1409 DRM_ERROR("[%u]Private data is NULL\n", pipe);
1410 goto exit;
1411 }
1412
1413 if (!priv->kms) {
1414 DRM_ERROR("[%u]Invalid KMS reference\n", pipe);
1415 goto exit;
1416 }
1417 kms = to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001418
Clarence Ip4c1d9772016-06-26 09:35:38 -04001419 if (!kms->catalog) {
1420 DRM_ERROR("[%u]Invalid catalog reference\n", pipe);
1421 goto exit;
1422 }
1423
Clarence Ip4ce59322016-06-26 22:27:51 -04001424 /* create and zero local structure */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001425 psde = kzalloc(sizeof(*psde), GFP_KERNEL);
1426 if (!psde) {
Clarence Ip4c1d9772016-06-26 09:35:38 -04001427 DRM_ERROR("[%u]Failed to allocate local plane struct\n", pipe);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001428 ret = -ENOMEM;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001429 goto exit;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001430 }
1431
Clarence Ip4c1d9772016-06-26 09:35:38 -04001432 /* cache local stuff for later */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001433 plane = &psde->base;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001434 psde->pipe = pipe;
Clarence Ip4c1d9772016-06-26 09:35:38 -04001435 psde->mmu_id = kms->mmu_id;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001436
Clarence Ip4c1d9772016-06-26 09:35:38 -04001437 /* initialize underlying h/w driver */
1438 psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog);
1439 if (IS_ERR(psde->pipe_hw)) {
1440 DRM_ERROR("[%u]SSPP init failed\n", pipe);
1441 ret = PTR_ERR(psde->pipe_hw);
1442 goto clean_plane;
1443 } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
1444 DRM_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
1445 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001446 }
Clarence Ip4c1d9772016-06-26 09:35:38 -04001447
1448 /* cache features mask for later */
1449 psde->features = psde->pipe_hw->cap->features;
1450 psde->pipe_sblk = psde->pipe_hw->cap->sblk;
1451
1452 /* add plane to DRM framework */
Lloyd Atkinson9a673492016-07-05 11:41:57 -04001453 psde->nformats = sde_populate_formats(psde->formats,
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001454 ARRAY_SIZE(psde->formats),
1455 !(psde->features & BIT(SDE_SSPP_CSC)) ||
Clarence Ipe78efb72016-06-24 18:35:21 -04001456 !(psde->features & SDE_SSPP_SCALER));
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001457
Clarence Ip4c1d9772016-06-26 09:35:38 -04001458 if (!psde->nformats) {
1459 DRM_ERROR("[%u]No valid formats for plane\n", pipe);
1460 goto clean_sspp;
1461 }
1462
1463 if (psde->features & BIT(SDE_SSPP_CURSOR))
1464 type = DRM_PLANE_TYPE_CURSOR;
1465 else if (primary_plane)
1466 type = DRM_PLANE_TYPE_PRIMARY;
1467 else
1468 type = DRM_PLANE_TYPE_OVERLAY;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001469 ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
1470 psde->formats, psde->nformats,
1471 type);
1472 if (ret)
Clarence Ip4c1d9772016-06-26 09:35:38 -04001473 goto clean_sspp;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001474
Clarence Ip4c1d9772016-06-26 09:35:38 -04001475 /* success! finalize initialization */
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001476 drm_plane_helper_add(plane, &sde_plane_helper_funcs);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001477
Clarence Ipaa0faf42016-05-30 12:07:48 -04001478 msm_property_init(&psde->property_info, &plane->base, dev,
1479 priv->plane_property, psde->property_data,
1480 PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
1481 sizeof(struct sde_plane_state));
1482
1483 _sde_plane_install_properties(plane);
Clarence Ip5e2a9222016-06-26 22:38:24 -04001484
Clarence Ip4ce59322016-06-26 22:27:51 -04001485 /* save user friendly pipe name for later */
Clarence Ip5e2a9222016-06-26 22:38:24 -04001486 snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
Clarence Ip4ce59322016-06-26 22:27:51 -04001487
Clarence Ip730e7192016-06-26 22:45:09 -04001488 mutex_init(&psde->lock);
1489
Clarence Ip4ce59322016-06-26 22:27:51 -04001490 _sde_plane_init_debugfs(psde, kms);
1491
Clarence Ip4c1d9772016-06-26 09:35:38 -04001492 DRM_INFO("[%u]Successfully created %s\n", pipe, psde->pipe_name);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001493 return plane;
1494
Clarence Ip4c1d9772016-06-26 09:35:38 -04001495clean_sspp:
1496 if (psde && psde->pipe_hw)
1497 sde_hw_sspp_destroy(psde->pipe_hw);
1498clean_plane:
1499 kfree(psde);
Ben Chan78647cd2016-06-26 22:02:47 -04001500exit:
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001501 return ERR_PTR(ret);
1502}