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gerrit-public.fairphone.software / kernel / msm-4.9 / c5fcafa528463b207108cd606e0d41741fb7dc50 / . / drivers / gpu / drm / nouveau / nvkm / engine / device / gf100.c
blob: df9e3fbca3df098eac8f49865b7f87d6eb069cbd [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
Ben Skeggs97190472015-01-14 15:35:00 +1000[diff] [blame]24#include "priv.h"
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]25
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]26int
Ben Skeggs97190472015-01-14 15:35:00 +1000[diff] [blame]27gf100_identify(struct nvkm_device *device)
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]28{
29 switch (device->chipset) {
30 case 0xc0:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]31 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]32 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]33 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]34 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]35 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]36 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]37 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]38 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]39 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]40 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]41 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]42 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]43 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]44 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]45 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]46 device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]47 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]48 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]49 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]50 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
51 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]52 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]53 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]54 break;
55 case 0xc4:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]56 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]57 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]58 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]59 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]60 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]62 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]66 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]67 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]68 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]69 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]70 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]71 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]72 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]73 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]74 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]75 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
76 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]77 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]78 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]79 break;
80 case 0xc3:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]81 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]82 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]83 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]84 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]85 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]86 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]87 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]88 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]89 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]90 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]93 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]94 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]95 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]96 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]97 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]98 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]99 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]100 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]101 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]102 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]103 break;
104 case 0xce:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]105 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]106 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]107 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]108 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]109 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]110 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]111 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]112 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]113 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]114 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]115 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]117 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]118 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]119 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]120 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]121 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]122 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]123 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]124 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
125 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]126 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]127 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]128 break;
129 case 0xcf:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]130 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]134 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]136 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]137 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]138 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]139 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]140 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]141 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]142 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]143 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]144 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]145 device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]146 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]147 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]148 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]149 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]150 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]151 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]152 break;
153 case 0xc1:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]154 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]155 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]156 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]157 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]158 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]159 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]161 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]162 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]163 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]165 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]166 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]167 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]168 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]169 device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]170 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]171 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]172 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]173 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]174 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset94a2ef62015-06-14 13:33:55 +0200[diff] [blame]175 device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]176 break;
177 case 0xc8:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]178 device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]179 device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]180 device->oclass[NVDEV_SUBDEV_THERM ] = &gt215_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]181 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]182 device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]183 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]184 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]185 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]186 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]187 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]188 device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]189 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]190 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]191 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]192 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]193 device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]194 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]195 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]196 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]197 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
198 device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]199 device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
Samuel Pitoiset060f50e2015-06-14 13:33:54 +0200[diff] [blame]200 device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]201 break;
202 case 0xd9:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]203 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
Ben Skeggsb9ec1422015-01-14 15:04:16 +1000[diff] [blame]204 device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]207 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]208 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]209 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]210 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]211 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]212 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs21b13792015-01-14 15:10:40 +1000[diff] [blame]213 device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]214 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]215 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]216 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]217 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]218 device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]219 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]220 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]221 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]222 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]223 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
Samuel Pitoiset94a2ef62015-06-14 13:33:55 +0200[diff] [blame]224 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]225 break;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]226 case 0xd7:
Ben Skeggs4e7659f2015-01-14 15:02:59 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
Ben Skeggs82c2b5e2014-06-18 15:46:22 +1000[diff] [blame]228 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
Ben Skeggse1404612015-01-14 15:11:48 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]230 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggsd7e5fcd2015-01-14 15:08:21 +1000[diff] [blame]231 device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs95484b52014-08-10 04:10:28 +1000[diff] [blame]233 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
Ben Skeggs5ecfade2015-01-14 15:04:31 +1000[diff] [blame]234 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]235 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs42594602015-01-14 15:09:19 +1000[diff] [blame]236 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
Ben Skeggs5b850572015-01-14 15:27:54 +1000[diff] [blame]237 device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
Ben Skeggs05c71452015-01-14 15:28:47 +1000[diff] [blame]238 device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
Ben Skeggsf84aff42015-01-14 15:32:15 +1000[diff] [blame]239 device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
Ben Skeggse3c71eb2015-01-14 15:29:43 +1000[diff] [blame]240 device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
Ben Skeggse3332c22015-01-14 15:30:09 +1000[diff] [blame]241 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
Ben Skeggs87c33f42015-01-14 15:30:40 +1000[diff] [blame]242 device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
Ben Skeggs87a87652015-01-14 15:30:22 +1000[diff] [blame]243 device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
Ben Skeggsbd6c5ca2015-01-14 15:22:32 +1000[diff] [blame]244 device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
Ben Skeggs878da152015-01-14 15:24:57 +1000[diff] [blame]245 device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
Samuel Pitoiset94a2ef62015-06-14 13:33:55 +0200[diff] [blame]246 device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]247 break;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]248 default:
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]249 return -EINVAL;
250 }
251
252 return 0;
Ben Skeggs97190472015-01-14 15:35:00 +1000[diff] [blame]253}