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gerrit-public.fairphone.software / kernel / msm-4.9 / 82c2b5ed6f2760caaa7871f018166fadd849d2d2 / . / drivers / gpu / drm / nouveau / core / engine / device / nvc0.c
blob: 8d55ed633b19dd059d18eff54d02deabf7b83ecf [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]25#include <subdev/bios.h>
Martin Peresa10220b2012-11-04 01:01:53 +0100[diff] [blame]26#include <subdev/bus.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame]30#include <subdev/therm.h>
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]31#include <subdev/mxm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]32#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]33#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]34#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]35#include <subdev/fb.h>
36#include <subdev/ltcg.h>
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]37#include <subdev/ibus.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]38#include <subdev/instmem.h>
39#include <subdev/vm.h>
40#include <subdev/bar.h>
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]41#include <subdev/pwr.h>
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]42#include <subdev/volt.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]43
Ben Skeggsdded35d2013-04-25 17:23:43 +1000[diff] [blame]44#include <engine/device.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]45#include <engine/dmaobj.h>
46#include <engine/fifo.h>
47#include <engine/software.h>
48#include <engine/graph.h>
49#include <engine/vp.h>
50#include <engine/bsp.h>
51#include <engine/ppp.h>
52#include <engine/copy.h>
53#include <engine/disp.h>
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]54#include <engine/perfmon.h>
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]55
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]56int
57nvc0_identify(struct nouveau_device *device)
58{
59 switch (device->chipset) {
60 case 0xc0:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]61 device->cname = "GF100";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]62 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]63 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]64 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]65 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]66 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]67 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]68 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]69 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]70 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]72 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]75 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
77 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]78 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]79 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]80 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]81 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]82 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]83 device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]84 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]85 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]86 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]87 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
88 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]89 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]90 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]91 break;
92 case 0xc4:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]93 device->cname = "GF104";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]95 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]99 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]100 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs08f6fbd2013-10-11 15:34:08 +1000[diff] [blame]101 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]102 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]103 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]104 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]105 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]106 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]107 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]108 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
109 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]110 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]111 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]112 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]113 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]114 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggseeb05582014-03-03 16:18:55 +1000[diff] [blame]115 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]116 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]117 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]118 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]119 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
120 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]121 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]122 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]123 break;
124 case 0xc3:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]125 device->cname = "GF106";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]126 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]127 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]128 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]129 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]130 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]134 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]135 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]136 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]137 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]138 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]139 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]140 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
141 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]142 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]143 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]144 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]145 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]146 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggseeb05582014-03-03 16:18:55 +1000[diff] [blame]147 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]148 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]149 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]150 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]151 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]152 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]153 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]154 break;
155 case 0xce:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]156 device->cname = "GF114";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]157 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]158 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]159 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]161 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]162 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]163 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Sid Boyce6e9cbb42014-01-06 09:12:05 +1000[diff] [blame]164 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]165 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]166 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]167 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]168 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]169 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]170 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
172 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]173 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]174 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]175 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]176 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]177 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggseeb05582014-03-03 16:18:55 +1000[diff] [blame]178 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]179 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]180 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]181 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]182 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
183 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]184 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]185 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]186 break;
187 case 0xcf:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]188 device->cname = "GF116";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]189 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]190 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]191 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]192 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]193 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]194 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]195 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]196 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]197 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]199 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]200 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]201 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]203 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
204 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]205 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]207 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]208 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]209 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggseeb05582014-03-03 16:18:55 +1000[diff] [blame]210 device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]211 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]212 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]213 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]214 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
215 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]216 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]217 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]218 break;
219 case 0xc1:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]220 device->cname = "GF108";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]221 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]222 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]223 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]224 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]225 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]226 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]227 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]228 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]229 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]230 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]231 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]233 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]234 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]235 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
236 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]237 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]238 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]239 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]240 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]241 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]242 device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]243 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]244 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]245 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]246 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]247 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]248 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]249 break;
250 case 0xc8:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]251 device->cname = "GF110";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]252 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggs73568592014-05-12 15:22:42 +1000[diff] [blame]253 device->oclass[NVDEV_SUBDEV_GPIO ] = nv92_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]254 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]255 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]256 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]257 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]258 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs0bae1d62013-11-11 12:40:27 +1000[diff] [blame]259 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]260 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]261 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]262 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]263 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]264 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]265 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]266 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
267 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]268 device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]269 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]270 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]271 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]272 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]273 device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]274 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]275 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]276 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]277 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
278 device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]279 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]280 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]281 break;
282 case 0xd9:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]283 device->cname = "GF119";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]284 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +1000[diff] [blame]285 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +1000[diff] [blame]286 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]287 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
Ben Skeggsbc792022012-12-04 09:50:33 +1000[diff] [blame]288 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
Ben Skeggsd38ac522012-07-22 16:41:26 +1000[diff] [blame]289 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]290 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]291 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]292 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]293 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]294 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]295 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggsc0abf5c2012-09-26 13:05:01 +1000[diff] [blame]296 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]297 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]298 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
299 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
Ben Skeggsff4b42c2013-10-15 09:38:12 +1000[diff] [blame]300 device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
Ben Skeggsc9c0cca2013-02-08 09:34:56 +1000[diff] [blame]301 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
Ben Skeggs344e1072012-10-08 14:11:35 +1000[diff] [blame]302 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]303 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]304 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs30f4e082013-06-09 16:08:22 +1000[diff] [blame]305 device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
Maarten Lankhorst7d8bd912012-11-23 11:10:45 +1000[diff] [blame]306 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
Maarten Lankhorst23c14ed2012-11-23 11:08:23 +1000[diff] [blame]307 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
Maarten Lankhorst4a795012012-11-23 11:13:36 +1000[diff] [blame]308 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]309 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]310 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]311 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]312 break;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]313 case 0xd7:
314 device->cname = "GF117";
315 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +1000[diff] [blame]316 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
Ben Skeggs82c2b5e2014-06-18 15:46:22 +1000[diff] [blame^]317 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]318 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
319 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
320 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
Ben Skeggscf336012014-01-14 15:55:38 +1000[diff] [blame]321 device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
Ben Skeggs1b4fea02013-10-11 15:38:15 +1000[diff] [blame]322 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
Ben Skeggs48ae0b32013-10-24 09:39:05 +1000[diff] [blame]323 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]324 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs1e9fc302013-10-18 14:18:04 +1000[diff] [blame]325 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
Ben Skeggsf6bad8a2014-02-24 14:17:49 +1000[diff] [blame]326 device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]327 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
Ben Skeggs24a4ae82013-12-23 00:39:47 +1000[diff] [blame]328 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]329 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
330 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
331 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
Ben Skeggs16c4f222013-11-05 14:26:58 +1000[diff] [blame]332 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
Ben Skeggsc46c3dd2013-10-03 07:30:11 +1000[diff] [blame]333 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Maarten Lankhorst26410c62013-07-04 10:04:30 +1000[diff] [blame]334 device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]335 device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
336 device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
337 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
338 device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
Ben Skeggsa8f8b482014-02-20 21:33:34 +1000[diff] [blame]339 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
Ben Skeggsaa4d7a42013-02-13 15:29:11 +1000[diff] [blame]340 device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
Ben Skeggs3f196a02013-03-30 21:56:26 +1000[diff] [blame]341 break;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]342 default:
343 nv_fatal(device, "unknown Fermi chipset\n");
344 return -EINVAL;
345 }
346
347 return 0;
Ben Skeggs7b49bd62012-12-04 12:18:59 +1000[diff] [blame]348 }