Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1 | /* |
Huang Shijie | 8eabdd1 | 2014-04-10 16:27:28 +0800 | [diff] [blame] | 2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
| 3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c |
| 4 | * |
| 5 | * Copyright (C) 2005, Intec Automation Inc. |
| 6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 7 | * |
| 8 | * This code is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/err.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/device.h> |
| 17 | #include <linux/mutex.h> |
| 18 | #include <linux/math64.h> |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 19 | #include <linux/sizes.h> |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 20 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 21 | #include <linux/mtd/mtd.h> |
| 22 | #include <linux/of_platform.h> |
| 23 | #include <linux/spi/flash.h> |
| 24 | #include <linux/mtd/spi-nor.h> |
| 25 | |
| 26 | /* Define max times to check status register before we give up. */ |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 27 | |
| 28 | /* |
| 29 | * For everything but full-chip erase; probably could be much smaller, but kept |
| 30 | * around for safety for now |
| 31 | */ |
| 32 | #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) |
| 33 | |
| 34 | /* |
| 35 | * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up |
| 36 | * for larger flash |
| 37 | */ |
| 38 | #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 39 | |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 40 | #define SPI_NOR_MAX_ID_LEN 6 |
Brian Norris | c67cbb8 | 2015-11-10 12:15:27 -0800 | [diff] [blame^] | 41 | #define SPI_NOR_MAX_ADDR_WIDTH 4 |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 42 | |
| 43 | struct flash_info { |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 44 | char *name; |
| 45 | |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 46 | /* |
| 47 | * This array stores the ID bytes. |
| 48 | * The first three bytes are the JEDIC ID. |
| 49 | * JEDEC ID zero means "no ID" (mostly older chips). |
| 50 | */ |
| 51 | u8 id[SPI_NOR_MAX_ID_LEN]; |
| 52 | u8 id_len; |
| 53 | |
| 54 | /* The size listed here is what works with SPINOR_OP_SE, which isn't |
| 55 | * necessarily called a "sector" by the vendor. |
| 56 | */ |
| 57 | unsigned sector_size; |
| 58 | u16 n_sectors; |
| 59 | |
| 60 | u16 page_size; |
| 61 | u16 addr_width; |
| 62 | |
| 63 | u16 flags; |
| 64 | #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ |
| 65 | #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ |
| 66 | #define SST_WRITE 0x04 /* use SST byte programming */ |
| 67 | #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ |
| 68 | #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ |
| 69 | #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ |
| 70 | #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ |
| 71 | #define USE_FSR 0x80 /* use flag status register */ |
| 72 | }; |
| 73 | |
| 74 | #define JEDEC_MFR(info) ((info)->id[0]) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 75 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 76 | static const struct flash_info *spi_nor_match_id(const char *name); |
Ben Hutchings | 70f3ce0 | 2014-09-29 11:47:54 +0200 | [diff] [blame] | 77 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 78 | /* |
| 79 | * Read the status register, returning its value in the location |
| 80 | * Return the status register value. |
| 81 | * Returns negative if error occurred. |
| 82 | */ |
| 83 | static int read_sr(struct spi_nor *nor) |
| 84 | { |
| 85 | int ret; |
| 86 | u8 val; |
| 87 | |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 88 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 89 | if (ret < 0) { |
| 90 | pr_err("error %d reading SR\n", (int) ret); |
| 91 | return ret; |
| 92 | } |
| 93 | |
| 94 | return val; |
| 95 | } |
| 96 | |
| 97 | /* |
grmoore@altera.com | c14dedd | 2014-04-29 10:29:51 -0500 | [diff] [blame] | 98 | * Read the flag status register, returning its value in the location |
| 99 | * Return the status register value. |
| 100 | * Returns negative if error occurred. |
| 101 | */ |
| 102 | static int read_fsr(struct spi_nor *nor) |
| 103 | { |
| 104 | int ret; |
| 105 | u8 val; |
| 106 | |
| 107 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); |
| 108 | if (ret < 0) { |
| 109 | pr_err("error %d reading FSR\n", ret); |
| 110 | return ret; |
| 111 | } |
| 112 | |
| 113 | return val; |
| 114 | } |
| 115 | |
| 116 | /* |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 117 | * Read configuration register, returning its value in the |
| 118 | * location. Return the configuration register value. |
| 119 | * Returns negative if error occured. |
| 120 | */ |
| 121 | static int read_cr(struct spi_nor *nor) |
| 122 | { |
| 123 | int ret; |
| 124 | u8 val; |
| 125 | |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 126 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 127 | if (ret < 0) { |
| 128 | dev_err(nor->dev, "error %d reading CR\n", ret); |
| 129 | return ret; |
| 130 | } |
| 131 | |
| 132 | return val; |
| 133 | } |
| 134 | |
| 135 | /* |
| 136 | * Dummy Cycle calculation for different type of read. |
| 137 | * It can be used to support more commands with |
| 138 | * different dummy cycle requirements. |
| 139 | */ |
| 140 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) |
| 141 | { |
| 142 | switch (nor->flash_read) { |
| 143 | case SPI_NOR_FAST: |
| 144 | case SPI_NOR_DUAL: |
| 145 | case SPI_NOR_QUAD: |
Huang Shijie | 0b78a2c | 2014-04-28 11:53:38 +0800 | [diff] [blame] | 146 | return 8; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 147 | case SPI_NOR_NORMAL: |
| 148 | return 0; |
| 149 | } |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | /* |
| 154 | * Write status register 1 byte |
| 155 | * Returns negative if error occurred. |
| 156 | */ |
| 157 | static inline int write_sr(struct spi_nor *nor, u8 val) |
| 158 | { |
| 159 | nor->cmd_buf[0] = val; |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 160 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* |
| 164 | * Set write enable latch with Write Enable command. |
| 165 | * Returns negative if error occurred. |
| 166 | */ |
| 167 | static inline int write_enable(struct spi_nor *nor) |
| 168 | { |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 169 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | /* |
| 173 | * Send write disble instruction to the chip. |
| 174 | */ |
| 175 | static inline int write_disable(struct spi_nor *nor) |
| 176 | { |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 177 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) |
| 181 | { |
| 182 | return mtd->priv; |
| 183 | } |
| 184 | |
| 185 | /* Enable/disable 4-byte addressing mode. */ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 186 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 187 | int enable) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 188 | { |
| 189 | int status; |
| 190 | bool need_wren = false; |
| 191 | u8 cmd; |
| 192 | |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 193 | switch (JEDEC_MFR(info)) { |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 194 | case SNOR_MFR_MICRON: |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 195 | /* Some Micron need WREN command; all will accept it */ |
| 196 | need_wren = true; |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 197 | case SNOR_MFR_MACRONIX: |
| 198 | case SNOR_MFR_WINBOND: |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 199 | if (need_wren) |
| 200 | write_enable(nor); |
| 201 | |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 202 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 203 | status = nor->write_reg(nor, cmd, NULL, 0); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 204 | if (need_wren) |
| 205 | write_disable(nor); |
| 206 | |
| 207 | return status; |
| 208 | default: |
| 209 | /* Spansion style */ |
| 210 | nor->cmd_buf[0] = enable << 7; |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 211 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 212 | } |
| 213 | } |
Brian Norris | 51983b7 | 2014-09-10 00:26:16 -0700 | [diff] [blame] | 214 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
| 215 | { |
| 216 | int sr = read_sr(nor); |
| 217 | if (sr < 0) |
| 218 | return sr; |
| 219 | else |
| 220 | return !(sr & SR_WIP); |
| 221 | } |
| 222 | |
| 223 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
| 224 | { |
| 225 | int fsr = read_fsr(nor); |
| 226 | if (fsr < 0) |
| 227 | return fsr; |
| 228 | else |
| 229 | return fsr & FSR_READY; |
| 230 | } |
| 231 | |
| 232 | static int spi_nor_ready(struct spi_nor *nor) |
| 233 | { |
| 234 | int sr, fsr; |
| 235 | sr = spi_nor_sr_ready(nor); |
| 236 | if (sr < 0) |
| 237 | return sr; |
| 238 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; |
| 239 | if (fsr < 0) |
| 240 | return fsr; |
| 241 | return sr && fsr; |
| 242 | } |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 243 | |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 244 | /* |
| 245 | * Service routine to read status register until ready, or timeout occurs. |
| 246 | * Returns non-zero if error. |
| 247 | */ |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 248 | static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, |
| 249 | unsigned long timeout_jiffies) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 250 | { |
| 251 | unsigned long deadline; |
Brian Norris | a95ce92 | 2014-11-05 02:32:03 -0800 | [diff] [blame] | 252 | int timeout = 0, ret; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 253 | |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 254 | deadline = jiffies + timeout_jiffies; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 255 | |
Brian Norris | a95ce92 | 2014-11-05 02:32:03 -0800 | [diff] [blame] | 256 | while (!timeout) { |
| 257 | if (time_after_eq(jiffies, deadline)) |
| 258 | timeout = 1; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 259 | |
Brian Norris | 51983b7 | 2014-09-10 00:26:16 -0700 | [diff] [blame] | 260 | ret = spi_nor_ready(nor); |
| 261 | if (ret < 0) |
| 262 | return ret; |
| 263 | if (ret) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 264 | return 0; |
Brian Norris | a95ce92 | 2014-11-05 02:32:03 -0800 | [diff] [blame] | 265 | |
| 266 | cond_resched(); |
| 267 | } |
| 268 | |
| 269 | dev_err(nor->dev, "flash operation timed out\n"); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 270 | |
| 271 | return -ETIMEDOUT; |
| 272 | } |
| 273 | |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 274 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
| 275 | { |
| 276 | return spi_nor_wait_till_ready_with_timeout(nor, |
| 277 | DEFAULT_READY_WAIT_JIFFIES); |
| 278 | } |
| 279 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 280 | /* |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 281 | * Erase the whole flash memory |
| 282 | * |
| 283 | * Returns 0 if successful, non-zero otherwise. |
| 284 | */ |
| 285 | static int erase_chip(struct spi_nor *nor) |
| 286 | { |
Brian Norris | 1976367 | 2015-08-13 15:46:05 -0700 | [diff] [blame] | 287 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 288 | |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 289 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) |
| 293 | { |
| 294 | int ret = 0; |
| 295 | |
| 296 | mutex_lock(&nor->lock); |
| 297 | |
| 298 | if (nor->prepare) { |
| 299 | ret = nor->prepare(nor, ops); |
| 300 | if (ret) { |
| 301 | dev_err(nor->dev, "failed in the preparation.\n"); |
| 302 | mutex_unlock(&nor->lock); |
| 303 | return ret; |
| 304 | } |
| 305 | } |
| 306 | return ret; |
| 307 | } |
| 308 | |
| 309 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) |
| 310 | { |
| 311 | if (nor->unprepare) |
| 312 | nor->unprepare(nor, ops); |
| 313 | mutex_unlock(&nor->lock); |
| 314 | } |
| 315 | |
| 316 | /* |
Brian Norris | c67cbb8 | 2015-11-10 12:15:27 -0800 | [diff] [blame^] | 317 | * Initiate the erasure of a single sector |
| 318 | */ |
| 319 | static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) |
| 320 | { |
| 321 | u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; |
| 322 | int i; |
| 323 | |
| 324 | if (nor->erase) |
| 325 | return nor->erase(nor, addr); |
| 326 | |
| 327 | /* |
| 328 | * Default implementation, if driver doesn't have a specialized HW |
| 329 | * control |
| 330 | */ |
| 331 | for (i = nor->addr_width - 1; i >= 0; i--) { |
| 332 | buf[i] = addr & 0xff; |
| 333 | addr >>= 8; |
| 334 | } |
| 335 | |
| 336 | return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); |
| 337 | } |
| 338 | |
| 339 | /* |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 340 | * Erase an address range on the nor chip. The address range may extend |
| 341 | * one or more erase sectors. Return an error is there is a problem erasing. |
| 342 | */ |
| 343 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) |
| 344 | { |
| 345 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 346 | u32 addr, len; |
| 347 | uint32_t rem; |
| 348 | int ret; |
| 349 | |
| 350 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, |
| 351 | (long long)instr->len); |
| 352 | |
| 353 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
| 354 | if (rem) |
| 355 | return -EINVAL; |
| 356 | |
| 357 | addr = instr->addr; |
| 358 | len = instr->len; |
| 359 | |
| 360 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); |
| 361 | if (ret) |
| 362 | return ret; |
| 363 | |
| 364 | /* whole-chip erase? */ |
| 365 | if (len == mtd->size) { |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 366 | unsigned long timeout; |
| 367 | |
Brian Norris | 05241ae | 2014-11-05 02:29:03 -0800 | [diff] [blame] | 368 | write_enable(nor); |
| 369 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 370 | if (erase_chip(nor)) { |
| 371 | ret = -EIO; |
| 372 | goto erase_err; |
| 373 | } |
| 374 | |
Furquan Shaikh | 09b6a37 | 2015-09-18 14:59:17 -0700 | [diff] [blame] | 375 | /* |
| 376 | * Scale the timeout linearly with the size of the flash, with |
| 377 | * a minimum calibrated to an old 2MB flash. We could try to |
| 378 | * pull these from CFI/SFDP, but these values should be good |
| 379 | * enough for now. |
| 380 | */ |
| 381 | timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, |
| 382 | CHIP_ERASE_2MB_READY_WAIT_JIFFIES * |
| 383 | (unsigned long)(mtd->size / SZ_2M)); |
| 384 | ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); |
Brian Norris | dfa9c0c | 2014-08-06 18:16:57 -0700 | [diff] [blame] | 385 | if (ret) |
| 386 | goto erase_err; |
| 387 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 388 | /* REVISIT in some cases we could speed up erasing large regions |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 389 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 390 | * to use "small sector erase", but that's not always optimal. |
| 391 | */ |
| 392 | |
| 393 | /* "sector"-at-a-time erase */ |
| 394 | } else { |
| 395 | while (len) { |
Brian Norris | 05241ae | 2014-11-05 02:29:03 -0800 | [diff] [blame] | 396 | write_enable(nor); |
| 397 | |
Brian Norris | c67cbb8 | 2015-11-10 12:15:27 -0800 | [diff] [blame^] | 398 | ret = spi_nor_erase_sector(nor, addr); |
| 399 | if (ret) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 400 | goto erase_err; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 401 | |
| 402 | addr += mtd->erasesize; |
| 403 | len -= mtd->erasesize; |
Brian Norris | dfa9c0c | 2014-08-06 18:16:57 -0700 | [diff] [blame] | 404 | |
| 405 | ret = spi_nor_wait_till_ready(nor); |
| 406 | if (ret) |
| 407 | goto erase_err; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 408 | } |
| 409 | } |
| 410 | |
Brian Norris | 05241ae | 2014-11-05 02:29:03 -0800 | [diff] [blame] | 411 | write_disable(nor); |
| 412 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 413 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
| 414 | |
| 415 | instr->state = MTD_ERASE_DONE; |
| 416 | mtd_erase_callback(instr); |
| 417 | |
| 418 | return ret; |
| 419 | |
| 420 | erase_err: |
| 421 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
| 422 | instr->state = MTD_ERASE_FAILED; |
| 423 | return ret; |
| 424 | } |
| 425 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 426 | static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, |
| 427 | uint64_t *len) |
| 428 | { |
| 429 | struct mtd_info *mtd = &nor->mtd; |
| 430 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
| 431 | int shift = ffs(mask) - 1; |
| 432 | int pow; |
| 433 | |
| 434 | if (!(sr & mask)) { |
| 435 | /* No protection */ |
| 436 | *ofs = 0; |
| 437 | *len = 0; |
| 438 | } else { |
| 439 | pow = ((sr & mask) ^ mask) >> shift; |
| 440 | *len = mtd->size >> pow; |
| 441 | *ofs = mtd->size - *len; |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | /* |
| 446 | * Return 1 if the entire region is locked, 0 otherwise |
| 447 | */ |
| 448 | static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, |
| 449 | u8 sr) |
| 450 | { |
| 451 | loff_t lock_offs; |
| 452 | uint64_t lock_len; |
| 453 | |
| 454 | stm_get_locked_range(nor, sr, &lock_offs, &lock_len); |
| 455 | |
| 456 | return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); |
| 457 | } |
| 458 | |
| 459 | /* |
| 460 | * Lock a region of the flash. Compatible with ST Micro and similar flash. |
| 461 | * Supports only the block protection bits BP{0,1,2} in the status register |
| 462 | * (SR). Does not support these features found in newer SR bitfields: |
| 463 | * - TB: top/bottom protect - only handle TB=0 (top protect) |
| 464 | * - SEC: sector/block protect - only handle SEC=0 (block protect) |
| 465 | * - CMP: complement protect - only support CMP=0 (range is not complemented) |
| 466 | * |
| 467 | * Sample table portion for 8MB flash (Winbond w25q64fw): |
| 468 | * |
| 469 | * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion |
| 470 | * -------------------------------------------------------------------------- |
| 471 | * X | X | 0 | 0 | 0 | NONE | NONE |
| 472 | * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 |
| 473 | * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 |
| 474 | * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 |
| 475 | * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 |
| 476 | * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 |
| 477 | * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 |
| 478 | * X | X | 1 | 1 | 1 | 8 MB | ALL |
| 479 | * |
| 480 | * Returns negative on errors, 0 on success. |
| 481 | */ |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 482 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 483 | { |
Brian Norris | 1976367 | 2015-08-13 15:46:05 -0700 | [diff] [blame] | 484 | struct mtd_info *mtd = &nor->mtd; |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 485 | u8 status_old, status_new; |
| 486 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
| 487 | u8 shift = ffs(mask) - 1, pow, val; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 488 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 489 | status_old = read_sr(nor); |
| 490 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 491 | /* SPI NOR always locks to the end */ |
| 492 | if (ofs + len != mtd->size) { |
| 493 | /* Does combined region extend to end? */ |
| 494 | if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len, |
| 495 | status_old)) |
| 496 | return -EINVAL; |
| 497 | len = mtd->size - ofs; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 498 | } |
| 499 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 500 | /* |
| 501 | * Need smallest pow such that: |
| 502 | * |
| 503 | * 1 / (2^pow) <= (len / size) |
| 504 | * |
| 505 | * so (assuming power-of-2 size) we do: |
| 506 | * |
| 507 | * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) |
| 508 | */ |
| 509 | pow = ilog2(mtd->size) - ilog2(len); |
| 510 | val = mask - (pow << shift); |
| 511 | if (val & ~mask) |
| 512 | return -EINVAL; |
| 513 | /* Don't "lock" with no region! */ |
| 514 | if (!(val & mask)) |
| 515 | return -EINVAL; |
| 516 | |
| 517 | status_new = (status_old & ~mask) | val; |
| 518 | |
| 519 | /* Only modify protection if it will not unlock other areas */ |
| 520 | if ((status_new & mask) <= (status_old & mask)) |
| 521 | return -EINVAL; |
| 522 | |
| 523 | write_enable(nor); |
| 524 | return write_sr(nor, status_new); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 525 | } |
| 526 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 527 | /* |
| 528 | * Unlock a region of the flash. See stm_lock() for more info |
| 529 | * |
| 530 | * Returns negative on errors, 0 on success. |
| 531 | */ |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 532 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 533 | { |
Brian Norris | 1976367 | 2015-08-13 15:46:05 -0700 | [diff] [blame] | 534 | struct mtd_info *mtd = &nor->mtd; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 535 | uint8_t status_old, status_new; |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 536 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
| 537 | u8 shift = ffs(mask) - 1, pow, val; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 538 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 539 | status_old = read_sr(nor); |
| 540 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 541 | /* Cannot unlock; would unlock larger region than requested */ |
| 542 | if (stm_is_locked_sr(nor, status_old, ofs - mtd->erasesize, |
| 543 | mtd->erasesize)) |
| 544 | return -EINVAL; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 545 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 546 | /* |
| 547 | * Need largest pow such that: |
| 548 | * |
| 549 | * 1 / (2^pow) >= (len / size) |
| 550 | * |
| 551 | * so (assuming power-of-2 size) we do: |
| 552 | * |
| 553 | * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) |
| 554 | */ |
| 555 | pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len)); |
| 556 | if (ofs + len == mtd->size) { |
| 557 | val = 0; /* fully unlocked */ |
| 558 | } else { |
| 559 | val = mask - (pow << shift); |
| 560 | /* Some power-of-two sizes are not supported */ |
| 561 | if (val & ~mask) |
| 562 | return -EINVAL; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 563 | } |
| 564 | |
Brian Norris | 62593cf | 2015-09-01 12:57:11 -0700 | [diff] [blame] | 565 | status_new = (status_old & ~mask) | val; |
| 566 | |
| 567 | /* Only modify protection if it will not lock other areas */ |
| 568 | if ((status_new & mask) >= (status_old & mask)) |
| 569 | return -EINVAL; |
| 570 | |
| 571 | write_enable(nor); |
| 572 | return write_sr(nor, status_new); |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 573 | } |
| 574 | |
Brian Norris | 5bf0e69 | 2015-09-01 12:57:12 -0700 | [diff] [blame] | 575 | /* |
| 576 | * Check if a region of the flash is (completely) locked. See stm_lock() for |
| 577 | * more info. |
| 578 | * |
| 579 | * Returns 1 if entire region is locked, 0 if any portion is unlocked, and |
| 580 | * negative on errors. |
| 581 | */ |
| 582 | static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) |
| 583 | { |
| 584 | int status; |
| 585 | |
| 586 | status = read_sr(nor); |
| 587 | if (status < 0) |
| 588 | return status; |
| 589 | |
| 590 | return stm_is_locked_sr(nor, ofs, len, status); |
| 591 | } |
| 592 | |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 593 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
| 594 | { |
| 595 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 596 | int ret; |
| 597 | |
| 598 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); |
| 599 | if (ret) |
| 600 | return ret; |
| 601 | |
| 602 | ret = nor->flash_lock(nor, ofs, len); |
| 603 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 604 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
| 605 | return ret; |
| 606 | } |
| 607 | |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 608 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
| 609 | { |
| 610 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 611 | int ret; |
| 612 | |
| 613 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); |
| 614 | if (ret) |
| 615 | return ret; |
| 616 | |
| 617 | ret = nor->flash_unlock(nor, ofs, len); |
| 618 | |
| 619 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); |
| 620 | return ret; |
| 621 | } |
| 622 | |
Brian Norris | 5bf0e69 | 2015-09-01 12:57:12 -0700 | [diff] [blame] | 623 | static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
| 624 | { |
| 625 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 626 | int ret; |
| 627 | |
| 628 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); |
| 629 | if (ret) |
| 630 | return ret; |
| 631 | |
| 632 | ret = nor->flash_is_locked(nor, ofs, len); |
| 633 | |
| 634 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); |
| 635 | return ret; |
| 636 | } |
| 637 | |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 638 | /* Used when the "_ext_id" is two bytes at most */ |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 639 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 640 | .id = { \ |
| 641 | ((_jedec_id) >> 16) & 0xff, \ |
| 642 | ((_jedec_id) >> 8) & 0xff, \ |
| 643 | (_jedec_id) & 0xff, \ |
| 644 | ((_ext_id) >> 8) & 0xff, \ |
| 645 | (_ext_id) & 0xff, \ |
| 646 | }, \ |
| 647 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 648 | .sector_size = (_sector_size), \ |
| 649 | .n_sectors = (_n_sectors), \ |
| 650 | .page_size = 256, \ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 651 | .flags = (_flags), |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 652 | |
Huang Shijie | 6d7604e | 2014-08-12 08:54:56 +0800 | [diff] [blame] | 653 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
Huang Shijie | 6d7604e | 2014-08-12 08:54:56 +0800 | [diff] [blame] | 654 | .id = { \ |
| 655 | ((_jedec_id) >> 16) & 0xff, \ |
| 656 | ((_jedec_id) >> 8) & 0xff, \ |
| 657 | (_jedec_id) & 0xff, \ |
| 658 | ((_ext_id) >> 16) & 0xff, \ |
| 659 | ((_ext_id) >> 8) & 0xff, \ |
| 660 | (_ext_id) & 0xff, \ |
| 661 | }, \ |
| 662 | .id_len = 6, \ |
| 663 | .sector_size = (_sector_size), \ |
| 664 | .n_sectors = (_n_sectors), \ |
| 665 | .page_size = 256, \ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 666 | .flags = (_flags), |
Huang Shijie | 6d7604e | 2014-08-12 08:54:56 +0800 | [diff] [blame] | 667 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 668 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 669 | .sector_size = (_sector_size), \ |
| 670 | .n_sectors = (_n_sectors), \ |
| 671 | .page_size = (_page_size), \ |
| 672 | .addr_width = (_addr_width), \ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 673 | .flags = (_flags), |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 674 | |
| 675 | /* NOTE: double check command sets and memory organization when you add |
| 676 | * more nor chips. This current list focusses on newer chips, which |
| 677 | * have been converging on command sets which including JEDEC ID. |
Rafał Miłecki | c19900e | 2015-04-25 12:41:30 +0200 | [diff] [blame] | 678 | * |
| 679 | * All newly added entries should describe *hardware* and should use SECT_4K |
| 680 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage |
| 681 | * scenarios excluding small sectors there is config option that can be |
| 682 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. |
| 683 | * For historical (and compatibility) reasons (before we got above config) some |
| 684 | * old entries may be missing 4K flag. |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 685 | */ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 686 | static const struct flash_info spi_nor_ids[] = { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 687 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
| 688 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
| 689 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, |
| 690 | |
| 691 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
| 692 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
| 693 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, |
| 694 | |
| 695 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
| 696 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, |
| 697 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, |
| 698 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
| 699 | |
| 700 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, |
| 701 | |
| 702 | /* EON -- en25xxx */ |
| 703 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, |
| 704 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, |
| 705 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, |
| 706 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, |
| 707 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, |
Sergey Ryazanov | a41595b | 2014-06-12 18:16:46 +0400 | [diff] [blame] | 708 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 709 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
Rafał Miłecki | c19900e | 2015-04-25 12:41:30 +0200 | [diff] [blame] | 710 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 711 | |
| 712 | /* ESMT */ |
| 713 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, |
| 714 | |
| 715 | /* Everspin */ |
| 716 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 717 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 718 | |
Rostislav Lisovy | ce56ce7 | 2014-10-29 10:10:47 +0100 | [diff] [blame] | 719 | /* Fujitsu */ |
| 720 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, |
| 721 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 722 | /* GigaDevice */ |
| 723 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, |
| 724 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, |
Rafał Miłecki | fcc87a9 | 2014-12-16 22:46:56 +0100 | [diff] [blame] | 725 | { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 726 | |
| 727 | /* Intel/Numonyx -- xxxs33b */ |
| 728 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, |
| 729 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, |
| 730 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, |
| 731 | |
Gabor Juhos | b79c332 | 2015-04-07 19:35:02 +0200 | [diff] [blame] | 732 | /* ISSI */ |
| 733 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, |
| 734 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 735 | /* Macronix */ |
Gabor Juhos | 660b5b0 | 2015-04-07 19:35:01 +0200 | [diff] [blame] | 736 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 737 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
| 738 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
| 739 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
| 740 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, |
| 741 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
| 742 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, |
| 743 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, |
Mika Westerberg | 81a1209 | 2015-02-05 18:39:03 +0200 | [diff] [blame] | 744 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 745 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
| 746 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, |
| 747 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, |
| 748 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
| 749 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, |
| 750 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, |
| 751 | |
| 752 | /* Micron */ |
Bean Huo 霍斌斌 (beanhuo) | 548cd3ab | 2014-12-17 07:35:45 +0000 | [diff] [blame] | 753 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
Aurelien Chanot | f9bcb6d | 2015-10-07 12:10:08 -0700 | [diff] [blame] | 754 | { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
Alexey Firago | 0db7fae | 2015-06-30 12:53:46 +0300 | [diff] [blame] | 755 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
Mika Westerberg | 2a06c7b | 2015-08-27 12:52:19 +0300 | [diff] [blame] | 756 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
Bean Huo 霍斌斌 (beanhuo) | 548cd3ab | 2014-12-17 07:35:45 +0000 | [diff] [blame] | 757 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, |
| 758 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, |
| 759 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
| 760 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
| 761 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
| 762 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 763 | |
| 764 | /* PMC */ |
| 765 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, |
| 766 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, |
| 767 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, |
| 768 | |
| 769 | /* Spansion -- single (large) sector size only, at least |
| 770 | * for the chips listed here (without boot sectors). |
| 771 | */ |
Geert Uytterhoeven | 9ab8699 | 2014-04-22 14:45:32 +0200 | [diff] [blame] | 772 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Joachim Eastwood | 0f12a27 | 2015-08-14 18:42:32 +0200 | [diff] [blame] | 773 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 774 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
| 775 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 776 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 777 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, |
| 778 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, |
| 779 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, |
Rafał Miłecki | c19900e | 2015-04-25 12:41:30 +0200 | [diff] [blame] | 780 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
Jonas Gorski | c175208 | 2015-08-26 14:56:53 +0200 | [diff] [blame] | 781 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 782 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 783 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
| 784 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, |
| 785 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, |
| 786 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, |
| 787 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, |
Sean Nyekjaer | 7c748f5 | 2015-10-13 08:50:30 +0200 | [diff] [blame] | 788 | { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Joachim Eastwood | adf508c | 2015-07-09 22:30:57 +0200 | [diff] [blame] | 789 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
| 790 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 791 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
Rafał Miłecki | c19900e | 2015-04-25 12:41:30 +0200 | [diff] [blame] | 792 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
Rafał Miłecki | 413780d | 2015-04-25 12:01:35 +0200 | [diff] [blame] | 793 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
Sean Nyekjaer | aada20c | 2015-10-13 08:51:14 +0200 | [diff] [blame] | 794 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 795 | |
| 796 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ |
| 797 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
| 798 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
| 799 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, |
| 800 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, |
| 801 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, |
| 802 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, |
| 803 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, |
| 804 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, |
Alexis Ballier | a1d97ef | 2015-08-14 19:35:39 +0200 | [diff] [blame] | 805 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
Yao Yuan | c887be7 | 2015-09-16 17:59:45 +0800 | [diff] [blame] | 806 | { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 807 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
Harini Katakam | f02985b | 2014-10-21 13:37:59 +0200 | [diff] [blame] | 808 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 809 | |
| 810 | /* ST Microelectronics -- newer production may have feature updates */ |
| 811 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
| 812 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, |
| 813 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, |
| 814 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, |
| 815 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, |
| 816 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, |
| 817 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, |
| 818 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, |
| 819 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 820 | |
| 821 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
| 822 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, |
| 823 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, |
| 824 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, |
| 825 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, |
| 826 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, |
| 827 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, |
| 828 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, |
| 829 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, |
| 830 | |
| 831 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
| 832 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, |
| 833 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, |
| 834 | |
| 835 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, |
| 836 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, |
| 837 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, |
| 838 | |
| 839 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, |
| 840 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, |
| 841 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, |
| 842 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, |
| 843 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, |
Thomas Petazzoni | f2fabe1 | 2014-07-27 23:56:08 +0200 | [diff] [blame] | 844 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 845 | |
| 846 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
Gabor Juhos | 40d19ab | 2015-03-26 23:58:02 +0100 | [diff] [blame] | 847 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 848 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
| 849 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, |
| 850 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, |
| 851 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, |
| 852 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, |
| 853 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, |
| 854 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
Brian Norris | a23eb34 | 2015-09-01 12:57:13 -0700 | [diff] [blame] | 855 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 856 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
| 857 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
Brian Norris | a23eb34 | 2015-09-01 12:57:13 -0700 | [diff] [blame] | 858 | { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Brian Norris | 4404bd7 | 2015-09-18 15:08:14 -0700 | [diff] [blame] | 859 | { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 860 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
| 861 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, |
| 862 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, |
| 863 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, |
| 864 | |
| 865 | /* Catalyst / On Semiconductor -- non-JEDEC */ |
| 866 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 867 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 868 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 869 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 870 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
| 871 | { }, |
| 872 | }; |
| 873 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 874 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 875 | { |
| 876 | int tmp; |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 877 | u8 id[SPI_NOR_MAX_ID_LEN]; |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 878 | const struct flash_info *info; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 879 | |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 880 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 881 | if (tmp < 0) { |
Brian Norris | 20625df | 2015-10-30 12:56:22 -0700 | [diff] [blame] | 882 | dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 883 | return ERR_PTR(tmp); |
| 884 | } |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 885 | |
| 886 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 887 | info = &spi_nor_ids[tmp]; |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 888 | if (info->id_len) { |
| 889 | if (!memcmp(info->id, id, info->id_len)) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 890 | return &spi_nor_ids[tmp]; |
| 891 | } |
| 892 | } |
Huang Shijie | 09ffafb | 2014-11-06 07:34:01 +0100 | [diff] [blame] | 893 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", |
| 894 | id[0], id[1], id[2]); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 895 | return ERR_PTR(-ENODEV); |
| 896 | } |
| 897 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 898 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
| 899 | size_t *retlen, u_char *buf) |
| 900 | { |
| 901 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 902 | int ret; |
| 903 | |
| 904 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); |
| 905 | |
| 906 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); |
| 907 | if (ret) |
| 908 | return ret; |
| 909 | |
| 910 | ret = nor->read(nor, from, len, retlen, buf); |
| 911 | |
| 912 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); |
| 913 | return ret; |
| 914 | } |
| 915 | |
| 916 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
| 917 | size_t *retlen, const u_char *buf) |
| 918 | { |
| 919 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 920 | size_t actual; |
| 921 | int ret; |
| 922 | |
| 923 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); |
| 924 | |
| 925 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); |
| 926 | if (ret) |
| 927 | return ret; |
| 928 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 929 | write_enable(nor); |
| 930 | |
| 931 | nor->sst_write_second = false; |
| 932 | |
| 933 | actual = to % 2; |
| 934 | /* Start write from odd address. */ |
| 935 | if (actual) { |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 936 | nor->program_opcode = SPINOR_OP_BP; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 937 | |
| 938 | /* write one byte. */ |
| 939 | nor->write(nor, to, 1, retlen, buf); |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 940 | ret = spi_nor_wait_till_ready(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 941 | if (ret) |
| 942 | goto time_out; |
| 943 | } |
| 944 | to += actual; |
| 945 | |
| 946 | /* Write out most of the data here. */ |
| 947 | for (; actual < len - 1; actual += 2) { |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 948 | nor->program_opcode = SPINOR_OP_AAI_WP; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 949 | |
| 950 | /* write two bytes. */ |
| 951 | nor->write(nor, to, 2, retlen, buf + actual); |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 952 | ret = spi_nor_wait_till_ready(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 953 | if (ret) |
| 954 | goto time_out; |
| 955 | to += 2; |
| 956 | nor->sst_write_second = true; |
| 957 | } |
| 958 | nor->sst_write_second = false; |
| 959 | |
| 960 | write_disable(nor); |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 961 | ret = spi_nor_wait_till_ready(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 962 | if (ret) |
| 963 | goto time_out; |
| 964 | |
| 965 | /* Write out trailing byte if it exists. */ |
| 966 | if (actual != len) { |
| 967 | write_enable(nor); |
| 968 | |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 969 | nor->program_opcode = SPINOR_OP_BP; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 970 | nor->write(nor, to, 1, retlen, buf + actual); |
| 971 | |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 972 | ret = spi_nor_wait_till_ready(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 973 | if (ret) |
| 974 | goto time_out; |
| 975 | write_disable(nor); |
| 976 | } |
| 977 | time_out: |
| 978 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); |
| 979 | return ret; |
| 980 | } |
| 981 | |
| 982 | /* |
| 983 | * Write an address range to the nor chip. Data must be written in |
| 984 | * FLASH_PAGESIZE chunks. The address range may be any size provided |
| 985 | * it is within the physical boundaries. |
| 986 | */ |
| 987 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, |
| 988 | size_t *retlen, const u_char *buf) |
| 989 | { |
| 990 | struct spi_nor *nor = mtd_to_spi_nor(mtd); |
| 991 | u32 page_offset, page_size, i; |
| 992 | int ret; |
| 993 | |
| 994 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); |
| 995 | |
| 996 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); |
| 997 | if (ret) |
| 998 | return ret; |
| 999 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1000 | write_enable(nor); |
| 1001 | |
| 1002 | page_offset = to & (nor->page_size - 1); |
| 1003 | |
| 1004 | /* do all the bytes fit onto one page? */ |
| 1005 | if (page_offset + len <= nor->page_size) { |
| 1006 | nor->write(nor, to, len, retlen, buf); |
| 1007 | } else { |
| 1008 | /* the size of data remaining on the first page */ |
| 1009 | page_size = nor->page_size - page_offset; |
| 1010 | nor->write(nor, to, page_size, retlen, buf); |
| 1011 | |
| 1012 | /* write everything in nor->page_size chunks */ |
| 1013 | for (i = page_size; i < len; i += page_size) { |
| 1014 | page_size = len - i; |
| 1015 | if (page_size > nor->page_size) |
| 1016 | page_size = nor->page_size; |
| 1017 | |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 1018 | ret = spi_nor_wait_till_ready(nor); |
Brian Norris | 1d61dcb | 2014-08-06 18:16:56 -0700 | [diff] [blame] | 1019 | if (ret) |
| 1020 | goto write_err; |
| 1021 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1022 | write_enable(nor); |
| 1023 | |
| 1024 | nor->write(nor, to + i, page_size, retlen, buf + i); |
| 1025 | } |
| 1026 | } |
| 1027 | |
Brian Norris | dfa9c0c | 2014-08-06 18:16:57 -0700 | [diff] [blame] | 1028 | ret = spi_nor_wait_till_ready(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1029 | write_err: |
| 1030 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); |
Brian Norris | 1d61dcb | 2014-08-06 18:16:56 -0700 | [diff] [blame] | 1031 | return ret; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1032 | } |
| 1033 | |
| 1034 | static int macronix_quad_enable(struct spi_nor *nor) |
| 1035 | { |
| 1036 | int ret, val; |
| 1037 | |
| 1038 | val = read_sr(nor); |
| 1039 | write_enable(nor); |
| 1040 | |
Jagan Teki | fd72523 | 2015-08-19 15:26:43 +0530 | [diff] [blame] | 1041 | write_sr(nor, val | SR_QUAD_EN_MX); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1042 | |
Brian Norris | b94ed08 | 2014-08-06 18:17:00 -0700 | [diff] [blame] | 1043 | if (spi_nor_wait_till_ready(nor)) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1044 | return 1; |
| 1045 | |
| 1046 | ret = read_sr(nor); |
| 1047 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { |
| 1048 | dev_err(nor->dev, "Macronix Quad bit not set\n"); |
| 1049 | return -EINVAL; |
| 1050 | } |
| 1051 | |
| 1052 | return 0; |
| 1053 | } |
| 1054 | |
| 1055 | /* |
| 1056 | * Write status Register and configuration register with 2 bytes |
| 1057 | * The first byte will be written to the status register, while the |
| 1058 | * second byte will be written to the configuration register. |
| 1059 | * Return negative if error occured. |
| 1060 | */ |
| 1061 | static int write_sr_cr(struct spi_nor *nor, u16 val) |
| 1062 | { |
| 1063 | nor->cmd_buf[0] = val & 0xff; |
| 1064 | nor->cmd_buf[1] = (val >> 8); |
| 1065 | |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 1066 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1067 | } |
| 1068 | |
| 1069 | static int spansion_quad_enable(struct spi_nor *nor) |
| 1070 | { |
| 1071 | int ret; |
| 1072 | int quad_en = CR_QUAD_EN_SPAN << 8; |
| 1073 | |
| 1074 | write_enable(nor); |
| 1075 | |
| 1076 | ret = write_sr_cr(nor, quad_en); |
| 1077 | if (ret < 0) { |
| 1078 | dev_err(nor->dev, |
| 1079 | "error while writing configuration register\n"); |
| 1080 | return -EINVAL; |
| 1081 | } |
| 1082 | |
| 1083 | /* read back and check it */ |
| 1084 | ret = read_cr(nor); |
| 1085 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { |
| 1086 | dev_err(nor->dev, "Spansion Quad bit not set\n"); |
| 1087 | return -EINVAL; |
| 1088 | } |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
Bean Huo 霍斌斌 (beanhuo) | 548cd3ab | 2014-12-17 07:35:45 +0000 | [diff] [blame] | 1093 | static int micron_quad_enable(struct spi_nor *nor) |
| 1094 | { |
| 1095 | int ret; |
| 1096 | u8 val; |
| 1097 | |
| 1098 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); |
| 1099 | if (ret < 0) { |
| 1100 | dev_err(nor->dev, "error %d reading EVCR\n", ret); |
| 1101 | return ret; |
| 1102 | } |
| 1103 | |
| 1104 | write_enable(nor); |
| 1105 | |
| 1106 | /* set EVCR, enable quad I/O */ |
| 1107 | nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON; |
Jagan Teki | f9f3ce8 | 2015-08-19 15:26:44 +0530 | [diff] [blame] | 1108 | ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1); |
Bean Huo 霍斌斌 (beanhuo) | 548cd3ab | 2014-12-17 07:35:45 +0000 | [diff] [blame] | 1109 | if (ret < 0) { |
| 1110 | dev_err(nor->dev, "error while writing EVCR register\n"); |
| 1111 | return ret; |
| 1112 | } |
| 1113 | |
| 1114 | ret = spi_nor_wait_till_ready(nor); |
| 1115 | if (ret) |
| 1116 | return ret; |
| 1117 | |
| 1118 | /* read EVCR and check it */ |
| 1119 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); |
| 1120 | if (ret < 0) { |
| 1121 | dev_err(nor->dev, "error %d reading EVCR\n", ret); |
| 1122 | return ret; |
| 1123 | } |
| 1124 | if (val & EVCR_QUAD_EN_MICRON) { |
| 1125 | dev_err(nor->dev, "Micron EVCR Quad bit not clear\n"); |
| 1126 | return -EINVAL; |
| 1127 | } |
| 1128 | |
| 1129 | return 0; |
| 1130 | } |
| 1131 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1132 | static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1133 | { |
| 1134 | int status; |
| 1135 | |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 1136 | switch (JEDEC_MFR(info)) { |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 1137 | case SNOR_MFR_MACRONIX: |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1138 | status = macronix_quad_enable(nor); |
| 1139 | if (status) { |
| 1140 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); |
| 1141 | return -EINVAL; |
| 1142 | } |
| 1143 | return status; |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 1144 | case SNOR_MFR_MICRON: |
Bean Huo 霍斌斌 (beanhuo) | 548cd3ab | 2014-12-17 07:35:45 +0000 | [diff] [blame] | 1145 | status = micron_quad_enable(nor); |
| 1146 | if (status) { |
| 1147 | dev_err(nor->dev, "Micron quad-read not enabled\n"); |
| 1148 | return -EINVAL; |
| 1149 | } |
| 1150 | return status; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1151 | default: |
| 1152 | status = spansion_quad_enable(nor); |
| 1153 | if (status) { |
| 1154 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); |
| 1155 | return -EINVAL; |
| 1156 | } |
| 1157 | return status; |
| 1158 | } |
| 1159 | } |
| 1160 | |
| 1161 | static int spi_nor_check(struct spi_nor *nor) |
| 1162 | { |
| 1163 | if (!nor->dev || !nor->read || !nor->write || |
Brian Norris | c67cbb8 | 2015-11-10 12:15:27 -0800 | [diff] [blame^] | 1164 | !nor->read_reg || !nor->write_reg) { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1165 | pr_err("spi-nor: please fill all the necessary fields!\n"); |
| 1166 | return -EINVAL; |
| 1167 | } |
| 1168 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1169 | return 0; |
| 1170 | } |
| 1171 | |
Ben Hutchings | 70f3ce0 | 2014-09-29 11:47:54 +0200 | [diff] [blame] | 1172 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1173 | { |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1174 | const struct flash_info *info = NULL; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1175 | struct device *dev = nor->dev; |
Brian Norris | 1976367 | 2015-08-13 15:46:05 -0700 | [diff] [blame] | 1176 | struct mtd_info *mtd = &nor->mtd; |
Brian Norris | 9c7d787 | 2015-10-30 20:33:24 -0700 | [diff] [blame] | 1177 | struct device_node *np = spi_nor_get_flash_node(nor); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1178 | int ret; |
| 1179 | int i; |
| 1180 | |
| 1181 | ret = spi_nor_check(nor); |
| 1182 | if (ret) |
| 1183 | return ret; |
| 1184 | |
Brian Norris | 4316302 | 2015-05-19 14:38:22 -0700 | [diff] [blame] | 1185 | if (name) |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1186 | info = spi_nor_match_id(name); |
Brian Norris | 4316302 | 2015-05-19 14:38:22 -0700 | [diff] [blame] | 1187 | /* Try to auto-detect if chip name wasn't specified or not found */ |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1188 | if (!info) |
| 1189 | info = spi_nor_read_id(nor); |
| 1190 | if (IS_ERR_OR_NULL(info)) |
Ben Hutchings | 70f3ce0 | 2014-09-29 11:47:54 +0200 | [diff] [blame] | 1191 | return -ENOENT; |
| 1192 | |
Rafał Miłecki | 58c8195 | 2014-12-01 09:42:16 +0100 | [diff] [blame] | 1193 | /* |
| 1194 | * If caller has specified name of flash model that can normally be |
| 1195 | * detected using JEDEC, let's verify it. |
| 1196 | */ |
| 1197 | if (name && info->id_len) { |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1198 | const struct flash_info *jinfo; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1199 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1200 | jinfo = spi_nor_read_id(nor); |
| 1201 | if (IS_ERR(jinfo)) { |
| 1202 | return PTR_ERR(jinfo); |
| 1203 | } else if (jinfo != info) { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1204 | /* |
| 1205 | * JEDEC knows better, so overwrite platform ID. We |
| 1206 | * can't trust partitions any longer, but we'll let |
| 1207 | * mtd apply them anyway, since some partitions may be |
| 1208 | * marked read-only, and we don't want to lose that |
| 1209 | * information, even if it's not 100% accurate. |
| 1210 | */ |
| 1211 | dev_warn(dev, "found %s, expected %s\n", |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1212 | jinfo->name, info->name); |
| 1213 | info = jinfo; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1214 | } |
| 1215 | } |
| 1216 | |
| 1217 | mutex_init(&nor->lock); |
| 1218 | |
| 1219 | /* |
Brian Norris | c6fc217 | 2015-09-01 12:57:15 -0700 | [diff] [blame] | 1220 | * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up |
| 1221 | * with the software protection bits set |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1222 | */ |
| 1223 | |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 1224 | if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || |
| 1225 | JEDEC_MFR(info) == SNOR_MFR_INTEL || |
Brian Norris | c6fc217 | 2015-09-01 12:57:15 -0700 | [diff] [blame] | 1226 | JEDEC_MFR(info) == SNOR_MFR_SST || |
| 1227 | JEDEC_MFR(info) == SNOR_MFR_WINBOND) { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1228 | write_enable(nor); |
| 1229 | write_sr(nor, 0); |
| 1230 | } |
| 1231 | |
Rafał Miłecki | 32f1b7c | 2014-09-28 22:36:54 +0200 | [diff] [blame] | 1232 | if (!mtd->name) |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1233 | mtd->name = dev_name(dev); |
Brian Norris | c9ec390 | 2015-08-13 15:46:03 -0700 | [diff] [blame] | 1234 | mtd->priv = nor; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1235 | mtd->type = MTD_NORFLASH; |
| 1236 | mtd->writesize = 1; |
| 1237 | mtd->flags = MTD_CAP_NORFLASH; |
| 1238 | mtd->size = info->sector_size * info->n_sectors; |
| 1239 | mtd->_erase = spi_nor_erase; |
| 1240 | mtd->_read = spi_nor_read; |
| 1241 | |
Brian Norris | 357ca38 | 2015-09-01 12:57:14 -0700 | [diff] [blame] | 1242 | /* NOR protection support for STmicro/Micron chips and similar */ |
| 1243 | if (JEDEC_MFR(info) == SNOR_MFR_MICRON || |
| 1244 | JEDEC_MFR(info) == SNOR_MFR_WINBOND) { |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 1245 | nor->flash_lock = stm_lock; |
| 1246 | nor->flash_unlock = stm_unlock; |
Brian Norris | 5bf0e69 | 2015-09-01 12:57:12 -0700 | [diff] [blame] | 1247 | nor->flash_is_locked = stm_is_locked; |
Brian Norris | 8cc7f33 | 2015-03-13 00:38:39 -0700 | [diff] [blame] | 1248 | } |
| 1249 | |
Brian Norris | 5bf0e69 | 2015-09-01 12:57:12 -0700 | [diff] [blame] | 1250 | if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1251 | mtd->_lock = spi_nor_lock; |
| 1252 | mtd->_unlock = spi_nor_unlock; |
Brian Norris | 5bf0e69 | 2015-09-01 12:57:12 -0700 | [diff] [blame] | 1253 | mtd->_is_locked = spi_nor_is_locked; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | /* sst nor chips use AAI word program */ |
| 1257 | if (info->flags & SST_WRITE) |
| 1258 | mtd->_write = sst_write; |
| 1259 | else |
| 1260 | mtd->_write = spi_nor_write; |
| 1261 | |
Brian Norris | 51983b7 | 2014-09-10 00:26:16 -0700 | [diff] [blame] | 1262 | if (info->flags & USE_FSR) |
| 1263 | nor->flags |= SNOR_F_USE_FSR; |
grmoore@altera.com | c14dedd | 2014-04-29 10:29:51 -0500 | [diff] [blame] | 1264 | |
Rafał Miłecki | 57cf26c | 2014-08-17 11:27:26 +0200 | [diff] [blame] | 1265 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1266 | /* prefer "small sector" erase if possible */ |
| 1267 | if (info->flags & SECT_4K) { |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1268 | nor->erase_opcode = SPINOR_OP_BE_4K; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1269 | mtd->erasesize = 4096; |
| 1270 | } else if (info->flags & SECT_4K_PMC) { |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1271 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1272 | mtd->erasesize = 4096; |
Rafał Miłecki | 57cf26c | 2014-08-17 11:27:26 +0200 | [diff] [blame] | 1273 | } else |
| 1274 | #endif |
| 1275 | { |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1276 | nor->erase_opcode = SPINOR_OP_SE; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1277 | mtd->erasesize = info->sector_size; |
| 1278 | } |
| 1279 | |
| 1280 | if (info->flags & SPI_NOR_NO_ERASE) |
| 1281 | mtd->flags |= MTD_NO_ERASE; |
| 1282 | |
| 1283 | mtd->dev.parent = dev; |
| 1284 | nor->page_size = info->page_size; |
| 1285 | mtd->writebufsize = nor->page_size; |
| 1286 | |
| 1287 | if (np) { |
| 1288 | /* If we were instantiated by DT, use it */ |
| 1289 | if (of_property_read_bool(np, "m25p,fast-read")) |
| 1290 | nor->flash_read = SPI_NOR_FAST; |
| 1291 | else |
| 1292 | nor->flash_read = SPI_NOR_NORMAL; |
| 1293 | } else { |
| 1294 | /* If we weren't instantiated by DT, default to fast-read */ |
| 1295 | nor->flash_read = SPI_NOR_FAST; |
| 1296 | } |
| 1297 | |
| 1298 | /* Some devices cannot do fast-read, no matter what DT tells us */ |
| 1299 | if (info->flags & SPI_NOR_NO_FR) |
| 1300 | nor->flash_read = SPI_NOR_NORMAL; |
| 1301 | |
| 1302 | /* Quad/Dual-read mode takes precedence over fast/normal */ |
| 1303 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 1304 | ret = set_quad_mode(nor, info); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1305 | if (ret) { |
| 1306 | dev_err(dev, "quad mode not supported\n"); |
| 1307 | return ret; |
| 1308 | } |
| 1309 | nor->flash_read = SPI_NOR_QUAD; |
| 1310 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { |
| 1311 | nor->flash_read = SPI_NOR_DUAL; |
| 1312 | } |
| 1313 | |
| 1314 | /* Default commands */ |
| 1315 | switch (nor->flash_read) { |
| 1316 | case SPI_NOR_QUAD: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1317 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1318 | break; |
| 1319 | case SPI_NOR_DUAL: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1320 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1321 | break; |
| 1322 | case SPI_NOR_FAST: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1323 | nor->read_opcode = SPINOR_OP_READ_FAST; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1324 | break; |
| 1325 | case SPI_NOR_NORMAL: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1326 | nor->read_opcode = SPINOR_OP_READ; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1327 | break; |
| 1328 | default: |
| 1329 | dev_err(dev, "No Read opcode defined\n"); |
| 1330 | return -EINVAL; |
| 1331 | } |
| 1332 | |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1333 | nor->program_opcode = SPINOR_OP_PP; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1334 | |
| 1335 | if (info->addr_width) |
| 1336 | nor->addr_width = info->addr_width; |
| 1337 | else if (mtd->size > 0x1000000) { |
| 1338 | /* enable 4-byte addressing if the device exceeds 16MiB */ |
| 1339 | nor->addr_width = 4; |
Brian Norris | f0d2448 | 2015-09-01 12:57:09 -0700 | [diff] [blame] | 1340 | if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1341 | /* Dedicated 4-byte command set */ |
| 1342 | switch (nor->flash_read) { |
| 1343 | case SPI_NOR_QUAD: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1344 | nor->read_opcode = SPINOR_OP_READ4_1_1_4; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1345 | break; |
| 1346 | case SPI_NOR_DUAL: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1347 | nor->read_opcode = SPINOR_OP_READ4_1_1_2; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1348 | break; |
| 1349 | case SPI_NOR_FAST: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1350 | nor->read_opcode = SPINOR_OP_READ4_FAST; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1351 | break; |
| 1352 | case SPI_NOR_NORMAL: |
Brian Norris | 58b89a1 | 2014-04-08 19:16:49 -0700 | [diff] [blame] | 1353 | nor->read_opcode = SPINOR_OP_READ4; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1354 | break; |
| 1355 | } |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1356 | nor->program_opcode = SPINOR_OP_PP_4B; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1357 | /* No small sector erase for 4-byte command set */ |
Brian Norris | b02e7f3 | 2014-04-08 18:15:31 -0700 | [diff] [blame] | 1358 | nor->erase_opcode = SPINOR_OP_SE_4B; |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1359 | mtd->erasesize = info->sector_size; |
| 1360 | } else |
Huang Shijie | d928a25 | 2014-11-06 11:24:33 +0800 | [diff] [blame] | 1361 | set_4byte(nor, info, 1); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1362 | } else { |
| 1363 | nor->addr_width = 3; |
| 1364 | } |
| 1365 | |
Brian Norris | c67cbb8 | 2015-11-10 12:15:27 -0800 | [diff] [blame^] | 1366 | if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |
| 1367 | dev_err(dev, "address width is too large: %u\n", |
| 1368 | nor->addr_width); |
| 1369 | return -EINVAL; |
| 1370 | } |
| 1371 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1372 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); |
| 1373 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1374 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1375 | (long long)mtd->size >> 10); |
| 1376 | |
| 1377 | dev_dbg(dev, |
| 1378 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " |
| 1379 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
| 1380 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), |
| 1381 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); |
| 1382 | |
| 1383 | if (mtd->numeraseregions) |
| 1384 | for (i = 0; i < mtd->numeraseregions; i++) |
| 1385 | dev_dbg(dev, |
| 1386 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " |
| 1387 | ".erasesize = 0x%.8x (%uKiB), " |
| 1388 | ".numblocks = %d }\n", |
| 1389 | i, (long long)mtd->eraseregions[i].offset, |
| 1390 | mtd->eraseregions[i].erasesize, |
| 1391 | mtd->eraseregions[i].erasesize / 1024, |
| 1392 | mtd->eraseregions[i].numblocks); |
| 1393 | return 0; |
| 1394 | } |
Brian Norris | b61834b | 2014-04-08 18:22:57 -0700 | [diff] [blame] | 1395 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1396 | |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1397 | static const struct flash_info *spi_nor_match_id(const char *name) |
Huang Shijie | 0d8c11c | 2014-02-24 18:37:40 +0800 | [diff] [blame] | 1398 | { |
Rafał Miłecki | 06bb6f5 | 2015-08-10 21:39:03 +0200 | [diff] [blame] | 1399 | const struct flash_info *id = spi_nor_ids; |
Huang Shijie | 0d8c11c | 2014-02-24 18:37:40 +0800 | [diff] [blame] | 1400 | |
Brian Norris | 2ff46e6 | 2015-09-02 16:34:35 -0700 | [diff] [blame] | 1401 | while (id->name) { |
Huang Shijie | 0d8c11c | 2014-02-24 18:37:40 +0800 | [diff] [blame] | 1402 | if (!strcmp(name, id->name)) |
| 1403 | return id; |
| 1404 | id++; |
| 1405 | } |
| 1406 | return NULL; |
| 1407 | } |
| 1408 | |
Huang Shijie | b199489 | 2014-02-24 18:37:37 +0800 | [diff] [blame] | 1409 | MODULE_LICENSE("GPL"); |
| 1410 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); |
| 1411 | MODULE_AUTHOR("Mike Lavender"); |
| 1412 | MODULE_DESCRIPTION("framework for SPI NOR"); |