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gerrit-public.fairphone.software / kernel / msm-4.9 / c7ff9e471a59f5b70fec03b5ab19c8b3581b5eb7 / . / arch / arm64 / boot / dts / qcom / sdm845-sde.dtsi
blob: 6132722a562b02704082ae10ed04caf67db36c90 [file] [log] [blame]
Xu Yang8eb0dbe2018-02-06 15:54:01 +0800[diff] [blame]1/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]12#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]13
14&soc {
15 mdss_mdp: qcom,mdss_mdp@ae00000 {
16 compatible = "qcom,sde-kms";
Lloyd Atkinson8f2bd8c2017-04-06 11:55:49 -0700[diff] [blame]17 reg = <0x0ae00000 0x81d40>,
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]18 <0x0aeb0000 0x2008>,
19 <0x0aeac000 0xf0>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]20 reg-names = "mdp_phys",
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]21 "vbif_phys",
22 "regdma_phys";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]23
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]24 clocks =
25 <&clock_gcc GCC_DISP_AHB_CLK>,
26 <&clock_gcc GCC_DISP_AXI_CLK>,
27 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]28 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]29 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
30 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
Dhaval Patel2cd94b12017-04-21 19:39:53 -0700[diff] [blame]31 clock-names = "gcc_iface", "gcc_bus", "iface_clk",
32 "bus_clk", "core_clk", "vsync_clk";
33 clock-rate = <0 0 0 0 300000000 19200000 0>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]34 clock-max-rate = <0 0 0 0 412500000 19200000 0>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]35
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]36 sde-vdd-supply = <&mdss_core_gdsc>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]37
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]38 /* interrupt config */
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -0700[diff] [blame]39 interrupt-parent = <&pdc>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]40 interrupts = <0 83 0>;
41 interrupt-controller;
42 #interrupt-cells = <1>;
Patrick Dalycaf09c92017-04-18 16:30:52 -0700[diff] [blame]43 iommus = <&apps_smmu 0x880 0x8>,
44 <&apps_smmu 0xc80 0x8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]45
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]46 #address-cells = <1>;
47 #size-cells = <0>;
48
Alan Kwong78dbffd2017-09-19 17:07:11 -0400[diff] [blame]49 #power-domain-cells = <0>;
50
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]51 /* hw blocks */
52 qcom,sde-off = <0x1000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]53 qcom,sde-len = <0x45C>;
54
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]55 qcom,sde-ctl-off = <0x2000 0x2200 0x2400
56 0x2600 0x2800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]57 qcom,sde-ctl-size = <0xE4>;
Jeykumar Sankaran3ed2ec32017-09-13 15:02:40 -0700[diff] [blame]58 qcom,sde-ctl-display-pref = "primary", "primary", "none",
59 "none", "none";
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]60
Jeykumar Sankaran32c5f602017-09-13 14:03:10 -0700[diff] [blame]61 qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0 0 0x4a000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]62 qcom,sde-mixer-size = <0x320>;
Jeykumar Sankaran3ed2ec32017-09-13 15:02:40 -0700[diff] [blame]63 qcom,sde-mixer-display-pref = "primary", "primary", "none",
64 "none", "none", "none";
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]65
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]66 qcom,sde-dspp-top-off = <0x1300>;
67 qcom,sde-dspp-top-size = <0xc>;
68
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]69 qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
Ping Li2d6c5f92017-05-04 14:17:03 -0700[diff] [blame]70 qcom,sde-dspp-size = <0x17e0>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]71
Sravanthi Kollukudurua45d8e72017-07-19 20:41:27 +0530[diff] [blame]72 qcom,sde-dest-scaler-top-off = <0x00061000>;
73 qcom,sde-dest-scaler-top-size = <0xc>;
74 qcom,sde-dest-scaler-off = <0x800 0x1000>;
75 qcom,sde-dest-scaler-size = <0x800>;
76
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]77 qcom,sde-wb-off = <0x66000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]78 qcom,sde-wb-size = <0x2c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]79 qcom,sde-wb-xin-id = <6>;
80 qcom,sde-wb-id = <2>;
Steve Cohen76bc0982017-06-20 13:19:04 -0400[diff] [blame]81 qcom,sde-wb-clk-ctrl = <0x3b8 24>;
82
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]83 qcom,sde-intf-off = <0x6b000 0x6b800
84 0x6c000 0x6c800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]85 qcom,sde-intf-size = <0x280>;
86
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]87 qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
88 qcom,sde-pp-off = <0x71000 0x71800
89 0x72000 0x72800 0x73000>;
90 qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]91 qcom,sde-pp-size = <0xd4>;
92
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]93 qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>;
94 qcom,sde-cdm-off = <0x7a200>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]95 qcom,sde-cdm-size = <0x224>;
96
97 qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
98 qcom,sde-dsc-size = <0x140>;
99
Narendra Muppallaa0826c62017-06-12 11:55:33 -0700[diff] [blame]100 qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x0>;
Ping Lic7dd65f2017-03-08 12:11:01 -0800[diff] [blame]101 qcom,sde-dither-version = <0x00010000>;
102 qcom,sde-dither-size = <0x20>;
103
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]104 qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
105 "dma", "dma", "dma", "dma";
106
107 qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
108 0x25000 0x27000 0x29000 0x2b000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]109 qcom,sde-sspp-src-size = <0x1c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]110
111 qcom,sde-sspp-xin-id = <0 4 8 12
112 1 5 9 13>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]113 qcom,sde-sspp-excl-rect = <1 1 1 1
114 1 1 1 1>;
Jeykumar Sankaran07515162017-05-16 13:02:33 -0700[diff] [blame]115 qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
116 qcom,sde-smart-dma-rev = "smart_dma_v2";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]117
Veera Sundaram Sankaran370b9912017-01-10 18:03:42 -0800[diff] [blame]118 qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
119
120 qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
121 0xb0 0xc8 0xe0 0xf8 0x110>;
122
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]123 /* offsets are relative to "mdp_phys + qcom,sde-off */
124 qcom,sde-sspp-clk-ctrl =
125 <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
126 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
127 qcom,sde-sspp-csc-off = <0x1a00>;
128 qcom,sde-csc-type = "csc-10bit";
129 qcom,sde-qseed-type = "qseedv3";
130 qcom,sde-sspp-qseed-off = <0xa00>;
131 qcom,sde-mixer-linewidth = <2560>;
132 qcom,sde-sspp-linewidth = <2560>;
Alan Kwongd939be42017-03-08 19:37:38 -0800[diff] [blame]133 qcom,sde-wb-linewidth = <4096>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]134 qcom,sde-mixer-blendstages = <0xb>;
135 qcom,sde-highest-bank-bit = <0x2>;
Clarence Ip03f2ffe2017-04-28 16:12:17 -0700[diff] [blame]136 qcom,sde-ubwc-version = <0x200>;
Sravanthi Kollukudurufa72e492017-10-26 12:23:41 +0530[diff] [blame]137 qcom,sde-smart-panel-align-mode = <0xc>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]138 qcom,sde-panic-per-pipe;
139 qcom,sde-has-cdp;
140 qcom,sde-has-src-split;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]141 qcom,sde-has-dim-layer;
Veera Sundaram Sankarana92444a2017-04-07 15:48:07 -0700[diff] [blame]142 qcom,sde-has-idle-pc;
Sravanthi Kollukudurua45d8e72017-07-19 20:41:27 +0530[diff] [blame]143 qcom,sde-has-dest-scaler;
144 qcom,sde-max-dest-scaler-input-linewidth = <2048>;
145 qcom,sde-max-dest-scaler-output-linewidth = <2560>;
Narendra Muppallaf1f7ecc2017-08-07 14:23:56 -0700[diff] [blame]146 qcom,sde-max-bw-low-kbps = <6800000>;
147 qcom,sde-max-bw-high-kbps = <6800000>;
Narendra Muppalla86a46a02017-08-17 11:14:37 -0700[diff] [blame]148 qcom,sde-min-core-ib-kbps = <2400000>;
149 qcom,sde-min-llcc-ib-kbps = <800000>;
150 qcom,sde-min-dram-ib-kbps = <800000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]151 qcom,sde-dram-channels = <2>;
152 qcom,sde-num-nrt-paths = <0>;
Gopikrishnaiah Anandanaaf6dcd2017-02-08 14:10:18 -0800[diff] [blame]153 qcom,sde-dspp-ad-version = <0x00040000>;
154 qcom,sde-dspp-ad-off = <0x28000 0x27000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]155
156 qcom,sde-vbif-off = <0>;
157 qcom,sde-vbif-size = <0x1040>;
158 qcom,sde-vbif-id = <0>;
Clarence Ip0b5f4412017-05-17 11:29:24 -0400[diff] [blame]159 qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
160 qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]161
Alan Kwong1641b0b2017-04-19 09:01:13 -0700[diff] [blame]162 qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
163 qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
164
Alan Kwonge67b3792017-04-27 15:57:50 -0700[diff] [blame]165 qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
166 0x00000000>;
Ingrid Gallardoaf41bba2017-10-06 17:31:35 -0700[diff] [blame]167 qcom,sde-safe-lut-linear =
168 <4 0xfff8>,
169 <0 0xfff0>;
170 qcom,sde-safe-lut-macrotile =
171 <10 0xfe00>,
172 <11 0xfc00>,
173 <12 0xf800>,
174 <0 0xf000>;
175 qcom,sde-safe-lut-nrt =
176 <0 0xffff>;
177 qcom,sde-safe-lut-cwb =
178 <0 0xffff>;
Alan Kwonge67b3792017-04-27 15:57:50 -0700[diff] [blame]179 qcom,sde-qos-lut-linear =
180 <4 0x00000000 0x00000357>,
181 <5 0x00000000 0x00003357>,
182 <6 0x00000000 0x00023357>,
183 <7 0x00000000 0x00223357>,
184 <8 0x00000000 0x02223357>,
185 <9 0x00000000 0x22223357>,
186 <10 0x00000002 0x22223357>,
187 <11 0x00000022 0x22223357>,
188 <12 0x00000222 0x22223357>,
189 <13 0x00002222 0x22223357>,
190 <14 0x00012222 0x22223357>,
191 <0 0x00112222 0x22223357>;
192 qcom,sde-qos-lut-macrotile =
193 <10 0x00000003 0x44556677>,
194 <11 0x00000033 0x44556677>,
195 <12 0x00000233 0x44556677>,
196 <13 0x00002233 0x44556677>,
197 <14 0x00012233 0x44556677>,
198 <0 0x00112233 0x44556677>;
199 qcom,sde-qos-lut-nrt =
200 <0 0x00000000 0x00000000>;
201 qcom,sde-qos-lut-cwb =
202 <0 0x75300000 0x00000000>;
203
Alan Kwong23ef3f392017-04-28 11:09:06 -0700[diff] [blame]204 qcom,sde-cdp-setting = <1 1>, <1 0>;
205
Lloyd Atkinson2b4973a2017-10-11 11:40:22 -0400[diff] [blame]206 qcom,sde-qos-cpu-mask = <0x3>;
207 qcom,sde-qos-cpu-dma-latency = <300>;
208
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]209 qcom,sde-inline-rotator = <&mdss_rotator 0>;
Veera Sundaram Sankaran5f9ef0d2017-05-24 18:49:53 -0700[diff] [blame]210 qcom,sde-inline-rot-xin = <10 11>;
211 qcom,sde-inline-rot-xin-type = "sspp", "wb";
212
213 /* offsets are relative to "mdp_phys + qcom,sde-off */
214 qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]215
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]216 qcom,sde-reg-dma-off = <0>;
217 qcom,sde-reg-dma-version = <0x1>;
218 qcom,sde-reg-dma-trigger-off = <0x119c>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]219
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]220 qcom,sde-sspp-vig-blocks {
221 qcom,sde-vig-csc-off = <0x1a00>;
222 qcom,sde-vig-qseed-off = <0xa00>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]223 qcom,sde-vig-qseed-size = <0xa0>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]224 };
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]225
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]226 qcom,sde-dspp-blocks {
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]227 qcom,sde-dspp-igc = <0x0 0x00030001>;
Rajesh Yadav284947c2017-07-21 20:32:13 +0530[diff] [blame]228 qcom,sde-dspp-hsic = <0x800 0x00010007>;
Rajesh Yadav7b8fbae2017-08-28 14:48:14 +0530[diff] [blame]229 qcom,sde-dspp-memcolor = <0x880 0x00010007>;
Rajesh Yadav0a92eea2017-07-18 18:18:55 +0530[diff] [blame]230 qcom,sde-dspp-sixzone= <0x900 0x00010007>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]231 qcom,sde-dspp-vlut = <0xa00 0x00010008>;
232 qcom,sde-dspp-gamut = <0x1000 0x00040000>;
Rajesh Yadavd490cb62017-07-04 13:20:42 +0530[diff] [blame]233 qcom,sde-dspp-pcc = <0x1700 0x00040000>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]234 qcom,sde-dspp-gc = <0x17c0 0x00010008>;
Xu Yang056d39b2017-07-11 16:34:13 +0800[diff] [blame]235 qcom,sde-dspp-hist = <0x800 0x00010007>;
Xu Yang8eb0dbe2018-02-06 15:54:01 +0800[diff] [blame]236 qcom,sde-dspp-dither = <0x82c 0x00010007>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]237 };
238
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]239 qcom,platform-supply-entries {
240 #address-cells = <1>;
241 #size-cells = <0>;
242
243 qcom,platform-supply-entry@0 {
244 reg = <0>;
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]245 qcom,supply-name = "sde-vdd";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]246 qcom,supply-min-voltage = <0>;
247 qcom,supply-max-voltage = <0>;
248 qcom,supply-enable-load = <0>;
249 qcom,supply-disable-load = <0>;
250 };
251 };
252
Abhijit Kulkarni1774dac2017-05-01 10:51:02 -0700[diff] [blame]253 smmu_sde_sec: qcom,smmu_sde_sec_cb {
254 compatible = "qcom,smmu_sde_sec";
255 iommus = <&apps_smmu 0x881 0x8>,
256 <&apps_smmu 0xc81 0x8>;
257 };
258
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]259 /* data and reg bus scale settings */
260 qcom,sde-data-bus {
Dhaval Patelf28be312018-05-22 23:21:53 -0700[diff] [blame]261 qcom,msm-bus,name = "mdss_sde";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]262 qcom,msm-bus,num-cases = <3>;
263 qcom,msm-bus,num-paths = <2>;
264 qcom,msm-bus,vectors-KBps =
Dhaval Patelf28be312018-05-22 23:21:53 -0700[diff] [blame]265 <22 512 0 0>, <23 512 0 0>,
266 <22 512 0 6400000>, <23 512 0 6400000>,
267 <22 512 0 6400000>, <23 512 0 6400000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]268 };
269
270 qcom,sde-reg-bus {
271 qcom,msm-bus,name = "mdss_reg";
272 qcom,msm-bus,num-cases = <4>;
273 qcom,msm-bus,num-paths = <1>;
274 qcom,msm-bus,active-only;
275 qcom,msm-bus,vectors-KBps =
276 <1 590 0 0>,
277 <1 590 0 76800>,
278 <1 590 0 150000>,
279 <1 590 0 300000>;
280 };
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]281 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]282
283 sde_rscc: qcom,sde_rscc@af20000 {
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]284 cell-index = <0>;
285 compatible = "qcom,sde-rsc";
286 reg = <0xaf20000 0x1c44>,
287 <0xaf30000 0x3fd4>;
288 reg-names = "drv", "wrapper";
289 qcom,sde-rsc-version = <1>;
290
291 vdd-supply = <&mdss_core_gdsc>;
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]292 clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
293 <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
294 clock-names = "vsync_clk", "iface_clk";
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]295 clock-rate = <0 0>;
296
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]297 qcom,sde-dram-channels = <2>;
298
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]299 mboxes = <&disp_rsc 0>;
300 mbox-names = "disp_rsc";
301
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]302 /* data and reg bus scale settings */
303 qcom,sde-data-bus {
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]304 qcom,msm-bus,name = "disp_rsc_mnoc";
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]305 qcom,msm-bus,active-only;
306 qcom,msm-bus,num-cases = <3>;
307 qcom,msm-bus,num-paths = <2>;
308 qcom,msm-bus,vectors-KBps =
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]309 <20003 20515 0 0>, <20004 20515 0 0>,
310 <20003 20515 0 6400000>, <20004 20515 0 6400000>,
311 <20003 20515 0 6400000>, <20004 20515 0 6400000>;
312 };
313
314 qcom,sde-llcc-bus {
315 qcom,msm-bus,name = "disp_rsc_llcc";
316 qcom,msm-bus,active-only;
317 qcom,msm-bus,num-cases = <3>;
318 qcom,msm-bus,num-paths = <1>;
319 qcom,msm-bus,vectors-KBps =
320 <20001 20513 0 0>,
321 <20001 20513 0 6400000>,
322 <20001 20513 0 6400000>;
323 };
324
325 qcom,sde-ebi-bus {
326 qcom,msm-bus,name = "disp_rsc_ebi";
327 qcom,msm-bus,active-only;
328 qcom,msm-bus,num-cases = <3>;
329 qcom,msm-bus,num-paths = <1>;
330 qcom,msm-bus,vectors-KBps =
331 <20000 20512 0 0>,
332 <20000 20512 0 6400000>,
333 <20000 20512 0 6400000>;
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]334 };
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]335 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]336
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]337 mdss_rotator: qcom,mdss_rotator@ae00000 {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]338 compatible = "qcom,sde_rotator";
339 reg = <0x0ae00000 0xac000>,
340 <0x0aeb8000 0x3000>;
341 reg-names = "mdp_phys",
342 "rot_vbif_phys";
343
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]344 #list-cells = <1>;
345
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]346 qcom,mdss-rot-mode = <1>;
347 qcom,mdss-highest-bank-bit = <0x2>;
348
349 /* Bus Scale Settings */
350 qcom,msm-bus,name = "mdss_rotator";
351 qcom,msm-bus,num-cases = <3>;
352 qcom,msm-bus,num-paths = <1>;
353 qcom,msm-bus,vectors-KBps =
354 <25 512 0 0>,
355 <25 512 0 6400000>,
356 <25 512 0 6400000>;
357
358 rot-vdd-supply = <&mdss_core_gdsc>;
359 qcom,supply-names = "rot-vdd";
360
361 clocks =
362 <&clock_gcc GCC_DISP_AHB_CLK>,
363 <&clock_gcc GCC_DISP_AXI_CLK>,
364 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]365 <&clock_dispcc DISP_CC_MDSS_ROT_CLK>,
366 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
367 clock-names = "gcc_iface", "gcc_bus",
Clarence Ip015924e2017-05-01 13:28:03 -0700[diff] [blame]368 "iface_clk", "rot_clk", "axi_clk";
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]369
370 interrupt-parent = <&mdss_mdp>;
371 interrupts = <2 0>;
372
Alan Kwong78dbffd2017-09-19 17:07:11 -0400[diff] [blame]373 power-domains = <&mdss_mdp>;
374
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]375 /* Offline rotator QoS setting */
Veera Sundaram Sankaranf28be032017-04-20 08:16:41 -0700[diff] [blame]376 qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
Alan Kwong8efe4a82017-06-30 16:05:50 -0400[diff] [blame]377 qcom,mdss-rot-vbif-memtype = <3 3>;
Veera Sundaram Sankaranfd4b37d2017-05-11 12:44:38 -0700[diff] [blame]378 qcom,mdss-rot-cdp-setting = <1 1>;
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]379 qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
380 qcom,mdss-rot-danger-lut = <0x0 0x0>;
381 qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
382
383 /* Inline rotator QoS Setting */
384 /* setting default register values for RD - qos/danger/safe */
385 qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
386 0x44556677 0x00112233>;
387 qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
388 qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]389
390 qcom,mdss-default-ot-rd-limit = <32>;
391 qcom,mdss-default-ot-wr-limit = <32>;
392
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]393 qcom,mdss-sbuf-headroom = <20>;
394
395 cache-slice-names = "rotator";
396 cache-slices = <&llcc 4>;
397
Veera Sundaram Sankaran06418032017-06-30 14:12:58 -0700[diff] [blame]398 /* reg bus scale settings */
399 rot_reg: qcom,rot-reg-bus {
400 qcom,msm-bus,name = "mdss_rot_reg";
401 qcom,msm-bus,num-cases = <2>;
402 qcom,msm-bus,num-paths = <1>;
403 qcom,msm-bus,active-only;
404 qcom,msm-bus,vectors-KBps =
405 <1 590 0 0>,
406 <1 590 0 76800>;
407 };
408
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]409 smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
410 compatible = "qcom,smmu_sde_rot_unsec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]411 iommus = <&apps_smmu 0x1090 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]412 };
413
414 smmu_rot_sec: qcom,smmu_rot_sec_cb {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]415 compatible = "qcom,smmu_sde_rot_sec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]416 iommus = <&apps_smmu 0x1091 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]417 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]418 };
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]419
420 mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]421 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]422 label = "dsi-ctrl-0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]423 cell-index = <0>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]424 reg = <0xae94000 0x400>,
425 <0xaf08000 0x4>;
426 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]427 interrupt-parent = <&mdss_mdp>;
428 interrupts = <4 0>;
429 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]430 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
431 <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
432 <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
433 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]434 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
435 <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]436 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]437 "pixel_clk", "pixel_clk_rcg",
438 "esc_clk";
Sravanthi Kollukudurud2a4f872017-10-26 15:37:06 +0530[diff] [blame]439 qcom,null-insertion-enabled;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]440 qcom,ctrl-supply-entries {
441 #address-cells = <1>;
442 #size-cells = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]443
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]444 qcom,ctrl-supply-entry@0 {
445 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]446 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]447 qcom,supply-min-voltage = <1200000>;
448 qcom,supply-max-voltage = <1200000>;
449 qcom,supply-enable-load = <21800>;
450 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]451 };
452 };
453 };
454
455 mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]456 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]457 label = "dsi-ctrl-1";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]458 cell-index = <1>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]459 reg = <0xae96000 0x400>,
460 <0xaf08000 0x4>;
461 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]462 interrupt-parent = <&mdss_mdp>;
463 interrupts = <5 0>;
464 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]465 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
466 <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
467 <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
468 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
469 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
470 <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]471 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]472 "pixel_clk", "pixel_clk_rcg", "esc_clk";
Sravanthi Kollukudurud2a4f872017-10-26 15:37:06 +0530[diff] [blame]473 qcom,null-insertion-enabled;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]474 qcom,ctrl-supply-entries {
475 #address-cells = <1>;
476 #size-cells = <0>;
477
478 qcom,ctrl-supply-entry@0 {
479 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]480 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]481 qcom,supply-min-voltage = <1200000>;
482 qcom,supply-max-voltage = <1200000>;
483 qcom,supply-enable-load = <21800>;
484 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]485 };
486 };
487 };
488
489 mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
490 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]491 label = "dsi-phy-0";
492 cell-index = <0>;
493 reg = <0xae94400 0x7c0>;
494 reg-names = "dsi_phy";
495 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]496 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]497 qcom,platform-strength-ctrl = [55 03
498 55 03
499 55 03
500 55 03
501 55 00];
502 qcom,platform-lane-config = [00 00 00 00
503 00 00 00 00
504 00 00 00 00
505 00 00 00 00
506 00 00 00 80];
507 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]508 qcom,phy-supply-entries {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 qcom,phy-supply-entry@0 {
512 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]513 qcom,supply-name = "vdda-0p9";
514 qcom,supply-min-voltage = <880000>;
515 qcom,supply-max-voltage = <880000>;
516 qcom,supply-enable-load = <36000>;
517 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]518 };
519 };
520 };
521
522 mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 {
523 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]524 label = "dsi-phy-1";
525 cell-index = <1>;
526 reg = <0xae96400 0x7c0>;
527 reg-names = "dsi_phy";
528 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]529 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]530 qcom,platform-strength-ctrl = [55 03
531 55 03
532 55 03
533 55 03
534 55 00];
535 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
536 qcom,platform-lane-config = [00 00 00 00
537 00 00 00 00
538 00 00 00 00
539 00 00 00 00
540 00 00 00 80];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]541 qcom,phy-supply-entries {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 qcom,phy-supply-entry@0 {
545 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]546 qcom,supply-name = "vdda-0p9";
547 qcom,supply-min-voltage = <880000>;
548 qcom,supply-max-voltage = <880000>;
549 qcom,supply-enable-load = <36000>;
550 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]551 };
552 };
553 };
554
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]555 sde_dp: qcom,dp_display@0{
556 cell-index = <0>;
557 compatible = "qcom,dp-display";
558
559 gdsc-supply = <&mdss_core_gdsc>;
560 vdda-1p2-supply = <&pm8998_l26>;
561 vdda-0p9-supply = <&pm8998_l1>;
562
Samantha Tran45c3e5c2017-10-19 12:51:09 -0700[diff] [blame]563 reg = <0xae90000 0x0dc>,
564 <0xae90200 0x0c0>,
565 <0xae90400 0x508>,
566 <0xae90a00 0x094>,
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]567 <0x88eaa00 0x200>,
568 <0x88ea200 0x200>,
569 <0x88ea600 0x200>,
570 <0xaf02000 0x1a0>,
571 <0x780000 0x621c>,
572 <0x88ea030 0x10>,
573 <0x88e8000 0x20>,
574 <0x0aee1000 0x034>;
Samantha Tran45c3e5c2017-10-19 12:51:09 -0700[diff] [blame]575 /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
576 reg-names = "dp_ahb", "dp_aux", "dp_link",
577 "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]578 "dp_mmss_cc", "qfprom_physical", "dp_pll",
579 "usb3_dp_com", "hdcp_physical";
580
581 interrupt-parent = <&mdss_mdp>;
582 interrupts = <12 0>;
583
584 clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
585 <&clock_rpmh RPMH_CXO_CLK>,
586 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
587 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
588 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
589 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
590 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
591 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
592 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
593 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
594 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
595 clock-names = "core_aux_clk", "core_usb_ref_clk_src",
596 "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
597 "core_usb_pipe_clk", "ctrl_link_clk",
598 "ctrl_link_iface_clk", "ctrl_pixel_clk",
599 "crypto_clk", "pixel_clk_rcg", "pixel_parent";
600
601 qcom,aux-cfg0-settings = [20 00];
602 qcom,aux-cfg1-settings = [24 13 23 1d];
603 qcom,aux-cfg2-settings = [28 24];
604 qcom,aux-cfg3-settings = [2c 00];
605 qcom,aux-cfg4-settings = [30 0a];
606 qcom,aux-cfg5-settings = [34 26];
607 qcom,aux-cfg6-settings = [38 0a];
608 qcom,aux-cfg7-settings = [3c 03];
609 qcom,aux-cfg8-settings = [40 bb];
610 qcom,aux-cfg9-settings = [44 03];
611
612 qcom,max-pclk-frequency-khz = <675000>;
613
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]614 qcom,ctrl-supply-entries {
615 #address-cells = <1>;
616 #size-cells = <0>;
617
618 qcom,ctrl-supply-entry@0 {
619 reg = <0>;
620 qcom,supply-name = "vdda-1p2";
621 qcom,supply-min-voltage = <1200000>;
622 qcom,supply-max-voltage = <1200000>;
623 qcom,supply-enable-load = <21800>;
624 qcom,supply-disable-load = <4>;
625 };
626 };
627
628 qcom,phy-supply-entries {
629 #address-cells = <1>;
630 #size-cells = <0>;
631
632 qcom,phy-supply-entry@0 {
633 reg = <0>;
634 qcom,supply-name = "vdda-0p9";
635 qcom,supply-min-voltage = <880000>;
636 qcom,supply-max-voltage = <880000>;
637 qcom,supply-enable-load = <36000>;
638 qcom,supply-disable-load = <32>;
639 };
640 };
641 };
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]642};