blob: 98ec614c56901a53b43d17aeef91a7350a767c8c [file] [log] [blame]
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
Stephen Hemminger747802a2005-06-27 11:33:16 -070010 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040011 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
Stephen Hemminger798b6b12006-10-22 20:16:57 -070014 * the Free Software Foundation; either version 2 of the License.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040015 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Joe Perchesf15063c2010-02-17 15:01:57 +000026#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020028#include <linux/in.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040029#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
Al Viro40754002005-04-03 09:15:52 +010040#include <linux/dma-mapping.h>
Stephen Hemminger678aa1f2007-10-16 12:15:54 -070041#include <linux/debugfs.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040042#include <linux/sched.h>
Stephen Hemminger678aa1f2007-10-16 12:15:54 -070043#include <linux/seq_file.h>
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080044#include <linux/mii.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/slab.h>
Stanislaw Gruszka392bd0c2010-10-05 15:11:40 -070046#include <linux/dmi.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040047#include <linux/prefetch.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040048#include <asm/irq.h>
49
50#include "skge.h"
51
52#define DRV_NAME "skge"
stephen hemminger5a9d6912011-07-06 19:00:08 +000053#define DRV_VERSION "1.14"
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040054
55#define DEFAULT_TX_RING_SIZE 128
56#define DEFAULT_RX_RING_SIZE 512
57#define MAX_TX_RING_SIZE 1024
Stephen Hemminger9db96472006-06-06 10:11:12 -070058#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040059#define MAX_RX_RING_SIZE 4096
Stephen Hemminger19a33d42005-06-27 11:33:15 -070060#define RX_COPY_THRESHOLD 128
61#define RX_BUF_SIZE 1536
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040062#define PHY_RETRIES 1000
63#define ETH_JUMBO_MTU 9000
64#define TX_WATCHDOG (5 * HZ)
65#define NAPI_WEIGHT 64
Stephen Hemminger6abebb52005-07-22 16:26:10 -070066#define BLINK_MS 250
Stephen Hemminger501fb722007-10-16 12:15:51 -070067#define LINK_HZ HZ
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040068
Stephen Hemmingerafa151b2007-10-16 12:15:53 -070069#define SKGE_EEPROM_MAGIC 0x9933aabb
70
71
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040072MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
Stephen Hemminger65ebe6342007-01-23 11:38:57 -080073MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040074MODULE_LICENSE("GPL");
75MODULE_VERSION(DRV_VERSION);
76
Joe Perches67777f92010-02-17 15:01:58 +000077static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
79 NETIF_MSG_IFDOWN);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040080
81static int debug = -1; /* defaults above */
82module_param(debug, int, 0);
83MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
Alexey Dobriyana3aa1882010-01-07 11:58:11 +000085static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
stephen hemminger6f7d32f2011-07-06 19:00:05 +000086 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
stephen hemminger57d6fa32011-07-06 19:00:07 +000088#ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90#endif
stephen hemminger6f7d32f2011-07-06 19:00:05 +000091 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
stephen hemmingerc0743042011-07-06 19:00:06 +000094 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
stephen hemminger6f7d32f2011-07-06 19:00:05 +000095 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400100 { 0 }
101};
102MODULE_DEVICE_TABLE(pci, skge_id_table);
103
104static int skge_up(struct net_device *dev);
105static int skge_down(struct net_device *dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800106static void skge_phy_reset(struct skge_port *skge);
Stephen Hemminger513f5332006-09-01 15:53:49 -0700107static void skge_tx_clean(struct net_device *dev);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800108static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400110static void genesis_get_stats(struct skge_port *skge, u64 *data);
111static void yukon_get_stats(struct skge_port *skge, u64 *data);
112static void yukon_init(struct skge_hw *hw, int port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400113static void genesis_mac_init(struct skge_hw *hw, int port);
Stephen Hemminger45bada62005-06-27 11:33:12 -0700114static void genesis_link_up(struct skge_port *skge);
Stephen Hemmingerf80d0322008-11-19 22:01:26 -0800115static void skge_set_multicast(struct net_device *dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400116
Stephen Hemminger7e676d92005-06-27 11:33:13 -0700117/* Avoid conditionals by using array */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400118static const int txqaddr[] = { Q_XA1, Q_XA2 };
119static const int rxqaddr[] = { Q_R1, Q_R2 };
120static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
121static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -0700122static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
123static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400124
stephen hemminger57d6fa32011-07-06 19:00:07 +0000125static inline bool is_genesis(const struct skge_hw *hw)
126{
127#ifdef CONFIG_SKGE_GENESIS
128 return hw->chip_id == CHIP_ID_GENESIS;
129#else
130 return false;
131#endif
132}
133
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400134static int skge_get_regs_len(struct net_device *dev)
135{
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700136 return 0x4000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400137}
138
139/*
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700140 * Returns copy of whole control register region
141 * Note: skip RAM address register because accessing it will
142 * cause bus hangs!
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400143 */
144static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
145 void *p)
146{
147 const struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400148 const void __iomem *io = skge->hw->regs;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400149
150 regs->version = 1;
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700151 memset(p, 0, regs->len);
152 memcpy_fromio(p, io, B3_RAM_ADDR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400153
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700154 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
155 regs->len - B3_RI_WTO_R1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400156}
157
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800158/* Wake on Lan only supported on Yukon chips with rev 1 or above */
Stephen Hemmingera504e642007-02-02 08:22:53 -0800159static u32 wol_supported(const struct skge_hw *hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400160{
stephen hemminger57d6fa32011-07-06 19:00:07 +0000161 if (is_genesis(hw))
Stephen Hemmingera504e642007-02-02 08:22:53 -0800162 return 0;
Stephen Hemmingerd17ecb22007-05-07 11:01:55 -0700163
164 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
165 return 0;
166
167 return WAKE_MAGIC | WAKE_PHY;
Stephen Hemmingera504e642007-02-02 08:22:53 -0800168}
169
Stephen Hemmingera504e642007-02-02 08:22:53 -0800170static void skge_wol_init(struct skge_port *skge)
171{
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
Stephen Hemminger692412b2007-04-09 15:32:45 -0700174 u16 ctrl;
Stephen Hemmingera504e642007-02-02 08:22:53 -0800175
Stephen Hemmingera504e642007-02-02 08:22:53 -0800176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
Stephen Hemminger692412b2007-04-09 15:32:45 -0700179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
182
183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
196
197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
Stephen Hemmingera504e642007-02-02 08:22:53 -0800203
204 /* Force to 10/100 skge_reset will re-enable on resume */
Stephen Hemminger692412b2007-04-09 15:32:45 -0700205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
Joe Perches67777f92010-02-17 15:01:58 +0000206 (PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
Stephen Hemminger692412b2007-04-09 15:32:45 -0700208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
Stephen Hemmingera504e642007-02-02 08:22:53 -0800213
Stephen Hemmingera504e642007-02-02 08:22:53 -0800214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
Joe Perchesa419aef2009-08-18 11:18:35 -0700235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
Stephen Hemmingera504e642007-02-02 08:22:53 -0800236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400242}
243
244static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245{
246 struct skge_port *skge = netdev_priv(dev);
247
Stephen Hemmingera504e642007-02-02 08:22:53 -0800248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400250}
251
252static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253{
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
Joe Perches8e95a202009-12-03 07:58:21 +0000257 if ((wol->wolopts & ~wol_supported(hw)) ||
258 !device_can_wakeup(&hw->pdev->dev))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400259 return -EOPNOTSUPP;
260
Stephen Hemmingera504e642007-02-02 08:22:53 -0800261 skge->wol = wol->wolopts;
Rafael J. Wysocki5177b322008-10-29 14:22:14 -0700262
263 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
264
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400265 return 0;
266}
267
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800268/* Determine supported/advertised modes based on hardware.
269 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700270 */
271static u32 skge_supported_modes(const struct skge_hw *hw)
272{
273 u32 supported;
274
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700275 if (hw->copper) {
Joe Perches67777f92010-02-17 15:01:58 +0000276 supported = (SUPPORTED_10baseT_Half |
277 SUPPORTED_10baseT_Full |
278 SUPPORTED_100baseT_Half |
279 SUPPORTED_100baseT_Full |
280 SUPPORTED_1000baseT_Half |
281 SUPPORTED_1000baseT_Full |
282 SUPPORTED_Autoneg |
283 SUPPORTED_TP);
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700284
stephen hemminger57d6fa32011-07-06 19:00:07 +0000285 if (is_genesis(hw))
Joe Perches67777f92010-02-17 15:01:58 +0000286 supported &= ~(SUPPORTED_10baseT_Half |
287 SUPPORTED_10baseT_Full |
288 SUPPORTED_100baseT_Half |
289 SUPPORTED_100baseT_Full);
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700290
291 else if (hw->chip_id == CHIP_ID_YUKON)
292 supported &= ~SUPPORTED_1000baseT_Half;
293 } else
Joe Perches67777f92010-02-17 15:01:58 +0000294 supported = (SUPPORTED_1000baseT_Full |
295 SUPPORTED_1000baseT_Half |
296 SUPPORTED_FIBRE |
297 SUPPORTED_Autoneg);
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700298
299 return supported;
300}
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400301
302static int skge_get_settings(struct net_device *dev,
303 struct ethtool_cmd *ecmd)
304{
305 struct skge_port *skge = netdev_priv(dev);
306 struct skge_hw *hw = skge->hw;
307
308 ecmd->transceiver = XCVR_INTERNAL;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700309 ecmd->supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400310
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700311 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400312 ecmd->port = PORT_TP;
313 ecmd->phy_address = hw->phy_addr;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700314 } else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400315 ecmd->port = PORT_FIBRE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400316
317 ecmd->advertising = skge->advertising;
318 ecmd->autoneg = skge->autoneg;
David Decotigny70739492011-04-27 18:32:40 +0000319 ethtool_cmd_speed_set(ecmd, skge->speed);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400320 ecmd->duplex = skge->duplex;
321 return 0;
322}
323
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400324static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
325{
326 struct skge_port *skge = netdev_priv(dev);
327 const struct skge_hw *hw = skge->hw;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700328 u32 supported = skge_supported_modes(hw);
Xiaoming.Zhang9ac13532008-09-25 20:28:05 +0000329 int err = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400330
331 if (ecmd->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700332 ecmd->advertising = supported;
333 skge->duplex = -1;
334 skge->speed = -1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400335 } else {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700336 u32 setting;
David Decotigny25db0332011-04-27 18:32:39 +0000337 u32 speed = ethtool_cmd_speed(ecmd);
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700338
David Decotigny25db0332011-04-27 18:32:39 +0000339 switch (speed) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400340 case SPEED_1000:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700341 if (ecmd->duplex == DUPLEX_FULL)
342 setting = SUPPORTED_1000baseT_Full;
343 else if (ecmd->duplex == DUPLEX_HALF)
344 setting = SUPPORTED_1000baseT_Half;
345 else
346 return -EINVAL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400347 break;
348 case SPEED_100:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_100baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_100baseT_Half;
353 else
354 return -EINVAL;
355 break;
356
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400357 case SPEED_10:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700358 if (ecmd->duplex == DUPLEX_FULL)
359 setting = SUPPORTED_10baseT_Full;
360 else if (ecmd->duplex == DUPLEX_HALF)
361 setting = SUPPORTED_10baseT_Half;
362 else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400363 return -EINVAL;
364 break;
365 default:
366 return -EINVAL;
367 }
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700368
369 if ((setting & supported) == 0)
370 return -EINVAL;
371
David Decotigny25db0332011-04-27 18:32:39 +0000372 skge->speed = speed;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700373 skge->duplex = ecmd->duplex;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400374 }
375
376 skge->autoneg = ecmd->autoneg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400377 skge->advertising = ecmd->advertising;
378
Xiaoming.Zhang9ac13532008-09-25 20:28:05 +0000379 if (netif_running(dev)) {
380 skge_down(dev);
381 err = skge_up(dev);
382 if (err) {
383 dev_close(dev);
384 return err;
385 }
386 }
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800387
Joe Perches67777f92010-02-17 15:01:58 +0000388 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400389}
390
391static void skge_get_drvinfo(struct net_device *dev,
392 struct ethtool_drvinfo *info)
393{
394 struct skge_port *skge = netdev_priv(dev);
395
396 strcpy(info->driver, DRV_NAME);
397 strcpy(info->version, DRV_VERSION);
398 strcpy(info->fw_version, "N/A");
399 strcpy(info->bus_info, pci_name(skge->hw->pdev));
400}
401
402static const struct skge_stat {
403 char name[ETH_GSTRING_LEN];
404 u16 xmac_offset;
405 u16 gma_offset;
406} skge_stats[] = {
407 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
408 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
409
410 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
411 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
412 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
413 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
414 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
415 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
416 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
417 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
418
419 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
420 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
421 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
422 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
423 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
424 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
425
426 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
427 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
428 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
429 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
430 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
431};
432
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700433static int skge_get_sset_count(struct net_device *dev, int sset)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400434{
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700435 switch (sset) {
436 case ETH_SS_STATS:
437 return ARRAY_SIZE(skge_stats);
438 default:
439 return -EOPNOTSUPP;
440 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400441}
442
443static void skge_get_ethtool_stats(struct net_device *dev,
444 struct ethtool_stats *stats, u64 *data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447
stephen hemminger57d6fa32011-07-06 19:00:07 +0000448 if (is_genesis(skge->hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452}
453
454/* Use hardware MIB variables for critical path statistics and
455 * transmit feedback not reported at interrupt.
456 * Other errors are accounted for in interrupt handler.
457 */
458static struct net_device_stats *skge_get_stats(struct net_device *dev)
459{
460 struct skge_port *skge = netdev_priv(dev);
461 u64 data[ARRAY_SIZE(skge_stats)];
462
stephen hemminger57d6fa32011-07-06 19:00:07 +0000463 if (is_genesis(skge->hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400464 genesis_get_stats(skge, data);
465 else
466 yukon_get_stats(skge, data);
467
Stephen Hemmingerda007722007-10-16 12:15:52 -0700468 dev->stats.tx_bytes = data[0];
469 dev->stats.rx_bytes = data[1];
470 dev->stats.tx_packets = data[2] + data[4] + data[6];
471 dev->stats.rx_packets = data[3] + data[5] + data[7];
472 dev->stats.multicast = data[3] + data[5];
473 dev->stats.collisions = data[10];
474 dev->stats.tx_aborted_errors = data[12];
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400475
Stephen Hemmingerda007722007-10-16 12:15:52 -0700476 return &dev->stats;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400477}
478
479static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
480{
481 int i;
482
Stephen Hemminger95566062005-06-27 11:33:02 -0700483 switch (stringset) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400484 case ETH_SS_STATS:
485 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
486 memcpy(data + i * ETH_GSTRING_LEN,
487 skge_stats[i].name, ETH_GSTRING_LEN);
488 break;
489 }
490}
491
492static void skge_get_ring_param(struct net_device *dev,
493 struct ethtool_ringparam *p)
494{
495 struct skge_port *skge = netdev_priv(dev);
496
497 p->rx_max_pending = MAX_RX_RING_SIZE;
498 p->tx_max_pending = MAX_TX_RING_SIZE;
499 p->rx_mini_max_pending = 0;
500 p->rx_jumbo_max_pending = 0;
501
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
504 p->rx_mini_pending = 0;
505 p->rx_jumbo_pending = 0;
506}
507
508static int skge_set_ring_param(struct net_device *dev,
509 struct ethtool_ringparam *p)
510{
511 struct skge_port *skge = netdev_priv(dev);
Wang Chene824b3e2008-09-26 16:20:32 +0800512 int err = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400513
514 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
Stephen Hemminger9db96472006-06-06 10:11:12 -0700515 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400516 return -EINVAL;
517
518 skge->rx_ring.count = p->rx_pending;
519 skge->tx_ring.count = p->tx_pending;
520
521 if (netif_running(dev)) {
522 skge_down(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800523 err = skge_up(dev);
524 if (err)
525 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400526 }
527
Wang Chene824b3e2008-09-26 16:20:32 +0800528 return err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400529}
530
531static u32 skge_get_msglevel(struct net_device *netdev)
532{
533 struct skge_port *skge = netdev_priv(netdev);
534 return skge->msg_enable;
535}
536
537static void skge_set_msglevel(struct net_device *netdev, u32 value)
538{
539 struct skge_port *skge = netdev_priv(netdev);
540 skge->msg_enable = value;
541}
542
543static int skge_nway_reset(struct net_device *dev)
544{
545 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400546
547 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
548 return -EINVAL;
549
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800550 skge_phy_reset(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400551 return 0;
552}
553
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400554static void skge_get_pauseparam(struct net_device *dev,
555 struct ethtool_pauseparam *ecmd)
556{
557 struct skge_port *skge = netdev_priv(dev);
558
Joe Perches8e95a202009-12-03 07:58:21 +0000559 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
560 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
561 ecmd->tx_pause = (ecmd->rx_pause ||
562 (skge->flow_control == FLOW_MODE_LOC_SEND));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400563
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700564 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400565}
566
567static int skge_set_pauseparam(struct net_device *dev,
568 struct ethtool_pauseparam *ecmd)
569{
570 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700571 struct ethtool_pauseparam old;
Xiaoming.Zhang9ac13532008-09-25 20:28:05 +0000572 int err = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400573
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700574 skge_get_pauseparam(dev, &old);
575
576 if (ecmd->autoneg != old.autoneg)
577 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
578 else {
579 if (ecmd->rx_pause && ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYMMETRIC;
581 else if (ecmd->rx_pause && !ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_SYM_OR_REM;
583 else if (!ecmd->rx_pause && ecmd->tx_pause)
584 skge->flow_control = FLOW_MODE_LOC_SEND;
585 else
586 skge->flow_control = FLOW_MODE_NONE;
587 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400588
Xiaoming.Zhang9ac13532008-09-25 20:28:05 +0000589 if (netif_running(dev)) {
590 skge_down(dev);
591 err = skge_up(dev);
592 if (err) {
593 dev_close(dev);
594 return err;
595 }
596 }
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700597
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400598 return 0;
599}
600
601/* Chip internal frequency for clock calculations */
602static inline u32 hwkhz(const struct skge_hw *hw)
603{
stephen hemminger57d6fa32011-07-06 19:00:07 +0000604 return is_genesis(hw) ? 53125 : 78125;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400605}
606
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800607/* Chip HZ to microseconds */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400608static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
609{
610 return (ticks * 1000) / hwkhz(hw);
611}
612
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800613/* Microseconds to chip HZ */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400614static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
615{
616 return hwkhz(hw) * usec / 1000;
617}
618
619static int skge_get_coalesce(struct net_device *dev,
620 struct ethtool_coalesce *ecmd)
621{
622 struct skge_port *skge = netdev_priv(dev);
623 struct skge_hw *hw = skge->hw;
624 int port = skge->port;
625
626 ecmd->rx_coalesce_usecs = 0;
627 ecmd->tx_coalesce_usecs = 0;
628
629 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
630 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
631 u32 msk = skge_read32(hw, B2_IRQM_MSK);
632
633 if (msk & rxirqmask[port])
634 ecmd->rx_coalesce_usecs = delay;
635 if (msk & txirqmask[port])
636 ecmd->tx_coalesce_usecs = delay;
637 }
638
639 return 0;
640}
641
642/* Note: interrupt timer is per board, but can turn on/off per port */
643static int skge_set_coalesce(struct net_device *dev,
644 struct ethtool_coalesce *ecmd)
645{
646 struct skge_port *skge = netdev_priv(dev);
647 struct skge_hw *hw = skge->hw;
648 int port = skge->port;
649 u32 msk = skge_read32(hw, B2_IRQM_MSK);
650 u32 delay = 25;
651
652 if (ecmd->rx_coalesce_usecs == 0)
653 msk &= ~rxirqmask[port];
654 else if (ecmd->rx_coalesce_usecs < 25 ||
655 ecmd->rx_coalesce_usecs > 33333)
656 return -EINVAL;
657 else {
658 msk |= rxirqmask[port];
659 delay = ecmd->rx_coalesce_usecs;
660 }
661
662 if (ecmd->tx_coalesce_usecs == 0)
663 msk &= ~txirqmask[port];
664 else if (ecmd->tx_coalesce_usecs < 25 ||
665 ecmd->tx_coalesce_usecs > 33333)
666 return -EINVAL;
667 else {
668 msk |= txirqmask[port];
669 delay = min(delay, ecmd->rx_coalesce_usecs);
670 }
671
672 skge_write32(hw, B2_IRQM_MSK, msk);
673 if (msk == 0)
674 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
675 else {
676 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
677 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
678 }
679 return 0;
680}
681
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700682enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
683static void skge_led(struct skge_port *skge, enum led_mode mode)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400684{
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400685 struct skge_hw *hw = skge->hw;
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700686 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400687
Stephen Hemminger9cbe3302007-03-16 14:01:28 -0700688 spin_lock_bh(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +0000689 if (is_genesis(hw)) {
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700690 switch (mode) {
691 case LED_MODE_OFF:
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700692 if (hw->phy_type == SK_PHY_BCOM)
693 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
694 else {
695 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
696 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
697 }
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700698 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
699 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
700 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
701 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400702
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700703 case LED_MODE_ON:
704 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
706
707 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
709
710 break;
711
712 case LED_MODE_TST:
713 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
714 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
715 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
716
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700717 if (hw->phy_type == SK_PHY_BCOM)
718 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
719 else {
720 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
721 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
722 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
723 }
724
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700725 }
726 } else {
727 switch (mode) {
728 case LED_MODE_OFF:
729 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
731 PHY_M_LED_MO_DUP(MO_LED_OFF) |
732 PHY_M_LED_MO_10(MO_LED_OFF) |
733 PHY_M_LED_MO_100(MO_LED_OFF) |
734 PHY_M_LED_MO_1000(MO_LED_OFF) |
735 PHY_M_LED_MO_RX(MO_LED_OFF));
736 break;
737 case LED_MODE_ON:
738 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
739 PHY_M_LED_PULS_DUR(PULS_170MS) |
740 PHY_M_LED_BLINK_RT(BLINK_84MS) |
741 PHY_M_LEDC_TX_CTRL |
742 PHY_M_LEDC_DP_CTRL);
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700743
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700744 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
745 PHY_M_LED_MO_RX(MO_LED_OFF) |
746 (skge->speed == SPEED_100 ?
747 PHY_M_LED_MO_100(MO_LED_ON) : 0));
748 break;
749 case LED_MODE_TST:
750 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_DUP(MO_LED_ON) |
753 PHY_M_LED_MO_10(MO_LED_ON) |
754 PHY_M_LED_MO_100(MO_LED_ON) |
755 PHY_M_LED_MO_1000(MO_LED_ON) |
756 PHY_M_LED_MO_RX(MO_LED_ON));
757 }
758 }
Stephen Hemminger9cbe3302007-03-16 14:01:28 -0700759 spin_unlock_bh(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400760}
761
762/* blink LED's for finding board */
stephen hemmingera5b9f412011-04-04 08:43:42 +0000763static int skge_set_phys_id(struct net_device *dev,
764 enum ethtool_phys_id_state state)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400765{
766 struct skge_port *skge = netdev_priv(dev);
767
stephen hemmingera5b9f412011-04-04 08:43:42 +0000768 switch (state) {
769 case ETHTOOL_ID_ACTIVE:
Allan, Bruce Wfce55922011-04-13 13:09:10 +0000770 return 2; /* cycle on/off twice per second */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400771
stephen hemmingera5b9f412011-04-04 08:43:42 +0000772 case ETHTOOL_ID_ON:
773 skge_led(skge, LED_MODE_TST);
774 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400775
stephen hemmingera5b9f412011-04-04 08:43:42 +0000776 case ETHTOOL_ID_OFF:
777 skge_led(skge, LED_MODE_OFF);
778 break;
779
780 case ETHTOOL_ID_INACTIVE:
781 /* back to regular LED state */
782 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700783 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400784
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400785 return 0;
786}
787
Stephen Hemmingerafa151b2007-10-16 12:15:53 -0700788static int skge_get_eeprom_len(struct net_device *dev)
789{
790 struct skge_port *skge = netdev_priv(dev);
791 u32 reg2;
792
793 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
Joe Perches67777f92010-02-17 15:01:58 +0000794 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
Stephen Hemmingerafa151b2007-10-16 12:15:53 -0700795}
796
797static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
798{
799 u32 val;
800
801 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
802
803 do {
804 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
805 } while (!(offset & PCI_VPD_ADDR_F));
806
807 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
808 return val;
809}
810
811static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
812{
813 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
814 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
815 offset | PCI_VPD_ADDR_F);
816
817 do {
818 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
819 } while (offset & PCI_VPD_ADDR_F);
820}
821
822static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
823 u8 *data)
824{
825 struct skge_port *skge = netdev_priv(dev);
826 struct pci_dev *pdev = skge->hw->pdev;
827 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
828 int length = eeprom->len;
829 u16 offset = eeprom->offset;
830
831 if (!cap)
832 return -EINVAL;
833
834 eeprom->magic = SKGE_EEPROM_MAGIC;
835
836 while (length > 0) {
837 u32 val = skge_vpd_read(pdev, cap, offset);
838 int n = min_t(int, length, sizeof(val));
839
840 memcpy(data, &val, n);
841 length -= n;
842 data += n;
843 offset += n;
844 }
845 return 0;
846}
847
848static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
849 u8 *data)
850{
851 struct skge_port *skge = netdev_priv(dev);
852 struct pci_dev *pdev = skge->hw->pdev;
853 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
854 int length = eeprom->len;
855 u16 offset = eeprom->offset;
856
857 if (!cap)
858 return -EINVAL;
859
860 if (eeprom->magic != SKGE_EEPROM_MAGIC)
861 return -EINVAL;
862
863 while (length > 0) {
864 u32 val;
865 int n = min_t(int, length, sizeof(val));
866
867 if (n < sizeof(val))
868 val = skge_vpd_read(pdev, cap, offset);
869 memcpy(&val, data, n);
870
871 skge_vpd_write(pdev, cap, offset, val);
872
873 length -= n;
874 data += n;
875 offset += n;
876 }
877 return 0;
878}
879
Jeff Garzik7282d492006-09-13 14:30:00 -0400880static const struct ethtool_ops skge_ethtool_ops = {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400881 .get_settings = skge_get_settings,
882 .set_settings = skge_set_settings,
883 .get_drvinfo = skge_get_drvinfo,
884 .get_regs_len = skge_get_regs_len,
885 .get_regs = skge_get_regs,
886 .get_wol = skge_get_wol,
887 .set_wol = skge_set_wol,
888 .get_msglevel = skge_get_msglevel,
889 .set_msglevel = skge_set_msglevel,
890 .nway_reset = skge_nway_reset,
891 .get_link = ethtool_op_get_link,
Stephen Hemmingerafa151b2007-10-16 12:15:53 -0700892 .get_eeprom_len = skge_get_eeprom_len,
893 .get_eeprom = skge_get_eeprom,
894 .set_eeprom = skge_set_eeprom,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400895 .get_ringparam = skge_get_ring_param,
896 .set_ringparam = skge_set_ring_param,
897 .get_pauseparam = skge_get_pauseparam,
898 .set_pauseparam = skge_set_pauseparam,
899 .get_coalesce = skge_get_coalesce,
900 .set_coalesce = skge_set_coalesce,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400901 .get_strings = skge_get_strings,
stephen hemmingera5b9f412011-04-04 08:43:42 +0000902 .set_phys_id = skge_set_phys_id,
Jeff Garzikb9f2c042007-10-03 18:07:32 -0700903 .get_sset_count = skge_get_sset_count,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400904 .get_ethtool_stats = skge_get_ethtool_stats,
905};
906
907/*
908 * Allocate ring elements and chain them together
909 * One-to-one association of board descriptors with ring elements
910 */
Stephen Hemmingerc3da1442006-03-21 10:57:01 -0800911static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400912{
913 struct skge_tx_desc *d;
914 struct skge_element *e;
915 int i;
916
Robert P. J. Daycd861282006-12-13 00:34:52 -0800917 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400918 if (!ring->start)
919 return -ENOMEM;
920
921 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
922 e->desc = d;
923 if (i == ring->count - 1) {
924 e->next = ring->start;
925 d->next_offset = base;
926 } else {
927 e->next = e + 1;
928 d->next_offset = base + (i+1) * sizeof(*d);
929 }
930 }
931 ring->to_use = ring->to_clean = ring->start;
932
933 return 0;
934}
935
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700936/* Allocate and setup a new buffer for receiving */
937static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
938 struct sk_buff *skb, unsigned int bufsize)
939{
940 struct skge_rx_desc *rd = e->desc;
941 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400942
943 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
944 PCI_DMA_FROMDEVICE);
945
946 rd->dma_lo = map;
947 rd->dma_hi = map >> 32;
948 e->skb = skb;
949 rd->csum1_start = ETH_HLEN;
950 rd->csum2_start = ETH_HLEN;
951 rd->csum1 = 0;
952 rd->csum2 = 0;
953
954 wmb();
955
956 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +0000957 dma_unmap_addr_set(e, mapaddr, map);
958 dma_unmap_len_set(e, maplen, bufsize);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400959}
960
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700961/* Resume receiving using existing skb,
962 * Note: DMA address is not changed by chip.
963 * MTU not changed while receiver active.
964 */
Stephen Hemminger5a011442006-03-23 11:07:25 -0800965static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700966{
967 struct skge_rx_desc *rd = e->desc;
968
969 rd->csum2 = 0;
970 rd->csum2_start = ETH_HLEN;
971
972 wmb();
973
974 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
975}
976
977
978/* Free all buffers in receive ring, assumes receiver stopped */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400979static void skge_rx_clean(struct skge_port *skge)
980{
981 struct skge_hw *hw = skge->hw;
982 struct skge_ring *ring = &skge->rx_ring;
983 struct skge_element *e;
984
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700985 e = ring->start;
986 do {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400987 struct skge_rx_desc *rd = e->desc;
988 rd->control = 0;
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700989 if (e->skb) {
990 pci_unmap_single(hw->pdev,
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +0000991 dma_unmap_addr(e, mapaddr),
992 dma_unmap_len(e, maplen),
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700993 PCI_DMA_FROMDEVICE);
994 dev_kfree_skb(e->skb);
995 e->skb = NULL;
996 }
997 } while ((e = e->next) != ring->start);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400998}
999
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001000
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001001/* Allocate buffers for receive ring
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001002 * For receive: to_clean is next received frame.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001003 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001004static int skge_rx_fill(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001005{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001006 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001007 struct skge_ring *ring = &skge->rx_ring;
1008 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001009
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001010 e = ring->start;
1011 do {
Stephen Hemminger383181a2005-09-19 15:37:16 -07001012 struct sk_buff *skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001013
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07001014 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1015 GFP_KERNEL);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001016 if (!skb)
1017 return -ENOMEM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001018
Stephen Hemminger383181a2005-09-19 15:37:16 -07001019 skb_reserve(skb, NET_IP_ALIGN);
1020 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
Joe Perches67777f92010-02-17 15:01:58 +00001021 } while ((e = e->next) != ring->start);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07001022
1023 ring->to_clean = ring->start;
1024 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001025}
1026
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001027static const char *skge_pause(enum pause_status status)
1028{
Joe Perches67777f92010-02-17 15:01:58 +00001029 switch (status) {
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001030 case FLOW_STAT_NONE:
1031 return "none";
1032 case FLOW_STAT_REM_SEND:
1033 return "rx only";
1034 case FLOW_STAT_LOC_SEND:
1035 return "tx_only";
1036 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1037 return "both";
1038 default:
1039 return "indeterminated";
1040 }
1041}
1042
1043
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001044static void skge_link_up(struct skge_port *skge)
1045{
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001046 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -07001047 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1048
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001049 netif_carrier_on(skge->netdev);
Stephen Hemminger29b4e882006-03-23 11:07:28 -08001050 netif_wake_queue(skge->netdev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001051
Joe Perchesd7072042010-02-09 11:49:53 +00001052 netif_info(skge, link, skge->netdev,
1053 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1054 skge->speed,
1055 skge->duplex == DUPLEX_FULL ? "full" : "half",
1056 skge_pause(skge->flow_status));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001057}
1058
1059static void skge_link_down(struct skge_port *skge)
1060{
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -07001061 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001062 netif_carrier_off(skge->netdev);
1063 netif_stop_queue(skge->netdev);
1064
Joe Perchesd7072042010-02-09 11:49:53 +00001065 netif_info(skge, link, skge->netdev, "Link is down\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001066}
1067
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001068static void xm_link_down(struct skge_hw *hw, int port)
1069{
1070 struct net_device *dev = hw->dev[port];
1071 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001072
Stephen Hemminger501fb722007-10-16 12:15:51 -07001073 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001074
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001075 if (netif_carrier_ok(dev))
1076 skge_link_down(skge);
1077}
1078
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001079static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001080{
1081 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001082
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001083 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemminger07811912006-02-22 10:28:34 -08001084 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001085
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001086 if (hw->phy_type == SK_PHY_XMAC)
1087 goto ready;
1088
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001089 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001090 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001091 goto ready;
Stephen Hemminger07811912006-02-22 10:28:34 -08001092 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001093 }
1094
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001095 return -ETIMEDOUT;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001096 ready:
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001097 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001098
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001099 return 0;
1100}
1101
1102static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1103{
1104 u16 v = 0;
1105 if (__xm_phy_read(hw, port, reg, &v))
Joe Perchesf15063c2010-02-17 15:01:57 +00001106 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001107 return v;
1108}
1109
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001110static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001111{
1112 int i;
1113
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001114 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001115 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001116 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001117 goto ready;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001118 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001119 }
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001120 return -EIO;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001121
1122 ready:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001123 xm_write16(hw, port, XM_PHY_DATA, val);
Stephen Hemminger07811912006-02-22 10:28:34 -08001124 for (i = 0; i < PHY_RETRIES; i++) {
1125 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1126 return 0;
1127 udelay(1);
1128 }
1129 return -ETIMEDOUT;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001130}
1131
1132static void genesis_init(struct skge_hw *hw)
1133{
1134 /* set blink source counter */
1135 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1136 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1137
1138 /* configure mac arbiter */
1139 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1140
1141 /* configure mac arbiter timeout values */
1142 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1143 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1144 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1145 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1146
1147 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1148 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1149 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1150 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1151
1152 /* configure packet arbiter timeout */
1153 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1154 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1155 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1156 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1157 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1158}
1159
1160static void genesis_reset(struct skge_hw *hw, int port)
1161{
Joe Perchesb6bc7652010-12-21 02:16:08 -08001162 static const u8 zero[8] = { 0 };
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001163 u32 reg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001164
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001165 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1166
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001167 /* reset the statistics module */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001168 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001169 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001170 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1171 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1172 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001173
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001174 /* disable Broadcom PHY IRQ */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001175 if (hw->phy_type == SK_PHY_BCOM)
1176 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001177
Stephen Hemminger45bada62005-06-27 11:33:12 -07001178 xm_outhash(hw, port, XM_HSM, zero);
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001179
1180 /* Flush TX and RX fifo */
1181 reg = xm_read32(hw, port, XM_MODE);
1182 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1183 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001184}
1185
Stephen Hemminger45bada62005-06-27 11:33:12 -07001186/* Convert mode to MII values */
1187static const u16 phy_pause_map[] = {
1188 [FLOW_MODE_NONE] = 0,
1189 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1190 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001191 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001192};
1193
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001194/* special defines for FIBER (88E1011S only) */
1195static const u16 fiber_pause_map[] = {
1196 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1197 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1198 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001199 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001200};
1201
Stephen Hemminger45bada62005-06-27 11:33:12 -07001202
1203/* Check status of Broadcom phy link */
1204static void bcom_check_link(struct skge_hw *hw, int port)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001205{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001206 struct net_device *dev = hw->dev[port];
1207 struct skge_port *skge = netdev_priv(dev);
1208 u16 status;
1209
1210 /* read twice because of latch */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001211 xm_phy_read(hw, port, PHY_BCOM_STAT);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001212 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1213
Stephen Hemminger45bada62005-06-27 11:33:12 -07001214 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001215 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001216 return;
1217 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001218
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001219 if (skge->autoneg == AUTONEG_ENABLE) {
1220 u16 lpa, aux;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001221
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001222 if (!(status & PHY_ST_AN_OVER))
1223 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001224
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001225 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1226 if (lpa & PHY_B_AN_RF) {
Joe Perchesf15063c2010-02-17 15:01:57 +00001227 netdev_notice(dev, "remote fault\n");
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001228 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001229 }
1230
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001231 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1232
1233 /* Check Duplex mismatch */
1234 switch (aux & PHY_B_AS_AN_RES_MSK) {
1235 case PHY_B_RES_1000FD:
1236 skge->duplex = DUPLEX_FULL;
1237 break;
1238 case PHY_B_RES_1000HD:
1239 skge->duplex = DUPLEX_HALF;
1240 break;
1241 default:
Joe Perchesf15063c2010-02-17 15:01:57 +00001242 netdev_notice(dev, "duplex mismatch\n");
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001243 return;
1244 }
1245
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001246 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1247 switch (aux & PHY_B_AS_PAUSE_MSK) {
1248 case PHY_B_AS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001249 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001250 break;
1251 case PHY_B_AS_PRR:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001252 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001253 break;
1254 case PHY_B_AS_PRT:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001255 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001256 break;
1257 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001258 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001259 }
1260 skge->speed = SPEED_1000;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001261 }
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001262
1263 if (!netif_carrier_ok(dev))
1264 genesis_link_up(skge);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001265}
1266
1267/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1268 * Phy on for 100 or 10Mbit operation
1269 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001270static void bcom_phy_init(struct skge_port *skge)
Stephen Hemminger45bada62005-06-27 11:33:12 -07001271{
1272 struct skge_hw *hw = skge->hw;
1273 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001274 int i;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001275 u16 id1, r, ext, ctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001276
1277 /* magic workaround patterns for Broadcom */
1278 static const struct {
1279 u16 reg;
1280 u16 val;
1281 } A1hack[] = {
1282 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1283 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1284 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1285 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1286 }, C0hack[] = {
1287 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1288 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1289 };
1290
Stephen Hemminger45bada62005-06-27 11:33:12 -07001291 /* read Id from external PHY (all have the same address) */
1292 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1293
1294 /* Optimize MDIO transfer by suppressing preamble. */
1295 r = xm_read16(hw, port, XM_MMU_CMD);
1296 r |= XM_MMU_NO_PRE;
Joe Perches67777f92010-02-17 15:01:58 +00001297 xm_write16(hw, port, XM_MMU_CMD, r);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001298
Stephen Hemminger2c668512005-07-22 16:26:07 -07001299 switch (id1) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001300 case PHY_BCOM_ID1_C0:
1301 /*
1302 * Workaround BCOM Errata for the C0 type.
1303 * Write magic patterns to reserved registers.
1304 */
1305 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1306 xm_phy_write(hw, port,
1307 C0hack[i].reg, C0hack[i].val);
1308
1309 break;
1310 case PHY_BCOM_ID1_A1:
1311 /*
1312 * Workaround BCOM Errata for the A1 type.
1313 * Write magic patterns to reserved registers.
1314 */
1315 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1316 xm_phy_write(hw, port,
1317 A1hack[i].reg, A1hack[i].val);
1318 break;
1319 }
1320
1321 /*
1322 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1323 * Disable Power Management after reset.
1324 */
1325 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1326 r |= PHY_B_AC_DIS_PM;
1327 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1328
1329 /* Dummy read */
1330 xm_read16(hw, port, XM_ISRC);
1331
1332 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1333 ctl = PHY_CT_SP1000; /* always 1000mbit */
1334
1335 if (skge->autoneg == AUTONEG_ENABLE) {
1336 /*
1337 * Workaround BCOM Errata #1 for the C5 type.
1338 * 1000Base-T Link Acquisition Failure in Slave Mode
1339 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1340 */
1341 u16 adv = PHY_B_1000C_RD;
1342 if (skge->advertising & ADVERTISED_1000baseT_Half)
1343 adv |= PHY_B_1000C_AHD;
1344 if (skge->advertising & ADVERTISED_1000baseT_Full)
1345 adv |= PHY_B_1000C_AFD;
1346 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1347
1348 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1349 } else {
1350 if (skge->duplex == DUPLEX_FULL)
1351 ctl |= PHY_CT_DUP_MD;
1352 /* Force to slave */
1353 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1354 }
1355
1356 /* Set autonegotiation pause parameters */
1357 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1358 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1359
1360 /* Handle Jumbo frames */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001361 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001362 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1363 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1364
1365 ext |= PHY_B_PEC_HIGH_LA;
1366
1367 }
1368
1369 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1370 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1371
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001372 /* Use link status change interrupt */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001373 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001374}
Stephen Hemminger45bada62005-06-27 11:33:12 -07001375
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001376static void xm_phy_init(struct skge_port *skge)
1377{
1378 struct skge_hw *hw = skge->hw;
1379 int port = skge->port;
1380 u16 ctrl = 0;
1381
1382 if (skge->autoneg == AUTONEG_ENABLE) {
1383 if (skge->advertising & ADVERTISED_1000baseT_Half)
1384 ctrl |= PHY_X_AN_HD;
1385 if (skge->advertising & ADVERTISED_1000baseT_Full)
1386 ctrl |= PHY_X_AN_FD;
1387
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001388 ctrl |= fiber_pause_map[skge->flow_control];
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001389
1390 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1391
1392 /* Restart Auto-negotiation */
1393 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1394 } else {
1395 /* Set DuplexMode in Config register */
1396 if (skge->duplex == DUPLEX_FULL)
1397 ctrl |= PHY_CT_DUP_MD;
1398 /*
1399 * Do NOT enable Auto-negotiation here. This would hold
1400 * the link down because no IDLEs are transmitted
1401 */
1402 }
1403
1404 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1405
1406 /* Poll PHY for status changes */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001407 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001408}
1409
Stephen Hemminger501fb722007-10-16 12:15:51 -07001410static int xm_check_link(struct net_device *dev)
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001411{
1412 struct skge_port *skge = netdev_priv(dev);
1413 struct skge_hw *hw = skge->hw;
1414 int port = skge->port;
1415 u16 status;
1416
1417 /* read twice because of latch */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001418 xm_phy_read(hw, port, PHY_XMAC_STAT);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001419 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1420
1421 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001422 xm_link_down(hw, port);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001423 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001424 }
1425
1426 if (skge->autoneg == AUTONEG_ENABLE) {
1427 u16 lpa, res;
1428
1429 if (!(status & PHY_ST_AN_OVER))
Stephen Hemminger501fb722007-10-16 12:15:51 -07001430 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001431
1432 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1433 if (lpa & PHY_B_AN_RF) {
Joe Perchesf15063c2010-02-17 15:01:57 +00001434 netdev_notice(dev, "remote fault\n");
Stephen Hemminger501fb722007-10-16 12:15:51 -07001435 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001436 }
1437
1438 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1439
1440 /* Check Duplex mismatch */
1441 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1442 case PHY_X_RS_FD:
1443 skge->duplex = DUPLEX_FULL;
1444 break;
1445 case PHY_X_RS_HD:
1446 skge->duplex = DUPLEX_HALF;
1447 break;
1448 default:
Joe Perchesf15063c2010-02-17 15:01:57 +00001449 netdev_notice(dev, "duplex mismatch\n");
Stephen Hemminger501fb722007-10-16 12:15:51 -07001450 return 0;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001451 }
1452
1453 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001454 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1455 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1456 (lpa & PHY_X_P_SYM_MD))
1457 skge->flow_status = FLOW_STAT_SYMMETRIC;
1458 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1459 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1460 /* Enable PAUSE receive, disable PAUSE transmit */
1461 skge->flow_status = FLOW_STAT_REM_SEND;
1462 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1463 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1464 /* Disable PAUSE receive, enable PAUSE transmit */
1465 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001466 else
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001467 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001468
1469 skge->speed = SPEED_1000;
1470 }
1471
1472 if (!netif_carrier_ok(dev))
1473 genesis_link_up(skge);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001474 return 1;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001475}
1476
1477/* Poll to check for link coming up.
Stephen Hemminger501fb722007-10-16 12:15:51 -07001478 *
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001479 * Since internal PHY is wired to a level triggered pin, can't
Stephen Hemminger501fb722007-10-16 12:15:51 -07001480 * get an interrupt when carrier is detected, need to poll for
1481 * link coming up.
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001482 */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001483static void xm_link_timer(unsigned long arg)
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001484{
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07001485 struct skge_port *skge = (struct skge_port *) arg;
David Howellsc4028952006-11-22 14:57:56 +00001486 struct net_device *dev = skge->netdev;
Joe Perches67777f92010-02-17 15:01:58 +00001487 struct skge_hw *hw = skge->hw;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001488 int port = skge->port;
Stephen Hemminger501fb722007-10-16 12:15:51 -07001489 int i;
1490 unsigned long flags;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001491
1492 if (!netif_running(dev))
1493 return;
1494
Stephen Hemminger501fb722007-10-16 12:15:51 -07001495 spin_lock_irqsave(&hw->phy_lock, flags);
1496
1497 /*
1498 * Verify that the link by checking GPIO register three times.
1499 * This pin has the signal from the link_sync pin connected to it.
1500 */
1501 for (i = 0; i < 3; i++) {
1502 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1503 goto link_down;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001504 }
1505
Joe Perches67777f92010-02-17 15:01:58 +00001506 /* Re-enable interrupt to detect link down */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001507 if (xm_check_link(dev)) {
1508 u16 msk = xm_read16(hw, port, XM_IMSK);
1509 msk &= ~XM_IS_INP_ASS;
1510 xm_write16(hw, port, XM_IMSK, msk);
1511 xm_read16(hw, port, XM_ISRC);
1512 } else {
1513link_down:
1514 mod_timer(&skge->link_timer,
1515 round_jiffies(jiffies + LINK_HZ));
1516 }
1517 spin_unlock_irqrestore(&hw->phy_lock, flags);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001518}
1519
1520static void genesis_mac_init(struct skge_hw *hw, int port)
1521{
1522 struct net_device *dev = hw->dev[port];
1523 struct skge_port *skge = netdev_priv(dev);
1524 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1525 int i;
1526 u32 r;
Joe Perchesb6bc7652010-12-21 02:16:08 -08001527 static const u8 zero[6] = { 0 };
Stephen Hemminger45bada62005-06-27 11:33:12 -07001528
Stephen Hemminger07811912006-02-22 10:28:34 -08001529 for (i = 0; i < 10; i++) {
1530 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1531 MFF_SET_MAC_RST);
1532 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1533 goto reset_ok;
1534 udelay(1);
1535 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001536
Joe Perchesf15063c2010-02-17 15:01:57 +00001537 netdev_warn(dev, "genesis reset failed\n");
Stephen Hemminger07811912006-02-22 10:28:34 -08001538
1539 reset_ok:
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001540 /* Unreset the XMAC. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001541 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001542
1543 /*
1544 * Perform additional initialization for external PHYs,
1545 * namely for the 1000baseTX cards that use the XMAC's
1546 * GMII mode.
1547 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001548 if (hw->phy_type != SK_PHY_XMAC) {
1549 /* Take external Phy out of reset */
1550 r = skge_read32(hw, B2_GP_IO);
1551 if (port == 0)
1552 r |= GP_DIR_0|GP_IO_0;
1553 else
1554 r |= GP_DIR_2|GP_IO_2;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001555
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001556 skge_write32(hw, B2_GP_IO, r);
1557
1558 /* Enable GMII interface */
1559 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1560 }
Stephen Hemminger07811912006-02-22 10:28:34 -08001561
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001562
Joe Perches67777f92010-02-17 15:01:58 +00001563 switch (hw->phy_type) {
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001564 case SK_PHY_XMAC:
1565 xm_phy_init(skge);
1566 break;
1567 case SK_PHY_BCOM:
1568 bcom_phy_init(skge);
1569 bcom_check_link(hw, port);
1570 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001571
Stephen Hemminger45bada62005-06-27 11:33:12 -07001572 /* Set Station Address */
1573 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001574
Stephen Hemminger45bada62005-06-27 11:33:12 -07001575 /* We don't use match addresses so clear */
1576 for (i = 1; i < 16; i++)
1577 xm_outaddr(hw, port, XM_EXM(i), zero);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001578
Stephen Hemminger07811912006-02-22 10:28:34 -08001579 /* Clear MIB counters */
1580 xm_write16(hw, port, XM_STAT_CMD,
1581 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1582 /* Clear two times according to Errata #3 */
1583 xm_write16(hw, port, XM_STAT_CMD,
1584 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1585
Stephen Hemminger45bada62005-06-27 11:33:12 -07001586 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1587 xm_write16(hw, port, XM_RX_HI_WM, 1450);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001588
1589 /* We don't need the FCS appended to the packet. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001590 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1591 if (jumbo)
1592 r |= XM_RX_BIG_PK_OK;
1593
1594 if (skge->duplex == DUPLEX_HALF) {
1595 /*
1596 * If in manual half duplex mode the other side might be in
1597 * full duplex mode, so ignore if a carrier extension is not seen
1598 * on frames received
1599 */
1600 r |= XM_RX_DIS_CEXT;
1601 }
1602 xm_write16(hw, port, XM_RX_CMD, r);
1603
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001604 /* We want short frames padded to 60 bytes. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001605 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1606
Stephen Hemminger485982a2007-11-26 11:54:52 -08001607 /* Increase threshold for jumbo frames on dual port */
1608 if (hw->ports > 1 && jumbo)
1609 xm_write16(hw, port, XM_TX_THR, 1020);
1610 else
1611 xm_write16(hw, port, XM_TX_THR, 512);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001612
1613 /*
1614 * Enable the reception of all error frames. This is is
1615 * a necessary evil due to the design of the XMAC. The
1616 * XMAC's receive FIFO is only 8K in size, however jumbo
1617 * frames can be up to 9000 bytes in length. When bad
1618 * frame filtering is enabled, the XMAC's RX FIFO operates
1619 * in 'store and forward' mode. For this to work, the
1620 * entire frame has to fit into the FIFO, but that means
1621 * that jumbo frames larger than 8192 bytes will be
1622 * truncated. Disabling all bad frame filtering causes
1623 * the RX FIFO to operate in streaming mode, in which
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001624 * case the XMAC will start transferring frames out of the
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001625 * RX FIFO as soon as the FIFO threshold is reached.
1626 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001627 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001628
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001629
1630 /*
Stephen Hemminger45bada62005-06-27 11:33:12 -07001631 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1632 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1633 * and 'Octets Rx OK Hi Cnt Ov'.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001634 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001635 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1636
1637 /*
1638 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1639 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1640 * and 'Octets Tx OK Hi Cnt Ov'.
1641 */
1642 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001643
1644 /* Configure MAC arbiter */
1645 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1646
1647 /* configure timeout values */
1648 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1649 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1650 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1651 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1652
1653 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1654 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1655 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1656 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1657
1658 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001659 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1660 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1661 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001662
1663 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001664 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1665 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1666 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001667
Stephen Hemminger45bada62005-06-27 11:33:12 -07001668 if (jumbo) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001669 /* Enable frame flushing if jumbo frames used */
Joe Perches67777f92010-02-17 15:01:58 +00001670 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001671 } else {
1672 /* enable timeout timers if normal frames */
1673 skge_write16(hw, B3_PA_CTRL,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001674 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001675 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001676}
1677
1678static void genesis_stop(struct skge_port *skge)
1679{
1680 struct skge_hw *hw = skge->hw;
1681 int port = skge->port;
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001682 unsigned retries = 1000;
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001683 u16 cmd;
1684
Joe Perches67777f92010-02-17 15:01:58 +00001685 /* Disable Tx and Rx */
Stephen Hemminger21d7f672007-11-26 11:54:51 -08001686 cmd = xm_read16(hw, port, XM_MMU_CMD);
1687 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1688 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001689
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001690 genesis_reset(hw, port);
1691
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001692 /* Clear Tx packet arbiter timeout IRQ */
1693 skge_write16(hw, B3_PA_CTRL,
1694 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1695
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001696 /* Reset the MAC */
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001697 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1698 do {
1699 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1700 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1701 break;
1702 } while (--retries > 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001703
1704 /* For external PHYs there must be special handling */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001705 if (hw->phy_type != SK_PHY_XMAC) {
Stephen Hemminger799b21d2007-11-26 11:54:50 -08001706 u32 reg = skge_read32(hw, B2_GP_IO);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001707 if (port == 0) {
1708 reg |= GP_DIR_0;
1709 reg &= ~GP_IO_0;
1710 } else {
1711 reg |= GP_DIR_2;
1712 reg &= ~GP_IO_2;
1713 }
1714 skge_write32(hw, B2_GP_IO, reg);
1715 skge_read32(hw, B2_GP_IO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001716 }
1717
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001718 xm_write16(hw, port, XM_MMU_CMD,
1719 xm_read16(hw, port, XM_MMU_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001720 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1721
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001722 xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001723}
1724
1725
1726static void genesis_get_stats(struct skge_port *skge, u64 *data)
1727{
1728 struct skge_hw *hw = skge->hw;
1729 int port = skge->port;
1730 int i;
1731 unsigned long timeout = jiffies + HZ;
1732
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001733 xm_write16(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001734 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1735
1736 /* wait for update to complete */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001737 while (xm_read16(hw, port, XM_STAT_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001738 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1739 if (time_after(jiffies, timeout))
1740 break;
1741 udelay(10);
1742 }
1743
1744 /* special case for 64 bit octet counter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001745 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1746 | xm_read32(hw, port, XM_TXO_OK_LO);
1747 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1748 | xm_read32(hw, port, XM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001749
1750 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001751 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001752}
1753
1754static void genesis_mac_intr(struct skge_hw *hw, int port)
1755{
Stephen Hemmingerda007722007-10-16 12:15:52 -07001756 struct net_device *dev = hw->dev[port];
1757 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001758 u16 status = xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001759
Joe Perchesd7072042010-02-09 11:49:53 +00001760 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1761 "mac interrupt status 0x%x\n", status);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001762
Stephen Hemminger501fb722007-10-16 12:15:51 -07001763 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
Joe Perches67777f92010-02-17 15:01:58 +00001764 xm_link_down(hw, port);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001765 mod_timer(&skge->link_timer, jiffies + 1);
1766 }
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001767
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001768 if (status & XM_IS_TXF_UR) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001769 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
Stephen Hemmingerda007722007-10-16 12:15:52 -07001770 ++dev->stats.tx_fifo_errors;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001771 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001772}
1773
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001774static void genesis_link_up(struct skge_port *skge)
1775{
1776 struct skge_hw *hw = skge->hw;
1777 int port = skge->port;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001778 u16 cmd, msk;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001779 u32 mode;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001780
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001781 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001782
1783 /*
1784 * enabling pause frame reception is required for 1000BT
1785 * because the XMAC is not reset if the link is going down
1786 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001787 if (skge->flow_status == FLOW_STAT_NONE ||
1788 skge->flow_status == FLOW_STAT_LOC_SEND)
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001789 /* Disable Pause Frame Reception */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001790 cmd |= XM_MMU_IGN_PF;
1791 else
1792 /* Enable Pause Frame Reception */
1793 cmd &= ~XM_MMU_IGN_PF;
1794
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001795 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001796
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001797 mode = xm_read32(hw, port, XM_MODE);
Joe Perches67777f92010-02-17 15:01:58 +00001798 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001799 skge->flow_status == FLOW_STAT_LOC_SEND) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001800 /*
1801 * Configure Pause Frame Generation
1802 * Use internal and external Pause Frame Generation.
1803 * Sending pause frames is edge triggered.
1804 * Send a Pause frame with the maximum pause time if
1805 * internal oder external FIFO full condition occurs.
1806 * Send a zero pause time frame to re-start transmission.
1807 */
1808 /* XM_PAUSE_DA = '010000C28001' (default) */
1809 /* XM_MAC_PTIME = 0xffff (maximum) */
1810 /* remember this value is defined in big endian (!) */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001811 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001812
1813 mode |= XM_PAUSE_MODE;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001814 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001815 } else {
1816 /*
1817 * disable pause frame generation is required for 1000BT
1818 * because the XMAC is not reset if the link is going down
1819 */
1820 /* Disable Pause Mode in Mode Register */
1821 mode &= ~XM_PAUSE_MODE;
1822
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001823 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001824 }
1825
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001826 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001827
Stephen Hemmingerd08b9bd2007-11-26 11:54:49 -08001828 /* Turn on detection of Tx underrun */
Stephen Hemminger501fb722007-10-16 12:15:51 -07001829 msk = xm_read16(hw, port, XM_IMSK);
Stephen Hemmingerd08b9bd2007-11-26 11:54:49 -08001830 msk &= ~XM_IS_TXF_UR;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001831 xm_write16(hw, port, XM_IMSK, msk);
Stephen Hemminger501fb722007-10-16 12:15:51 -07001832
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001833 xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001834
1835 /* get MMU Command Reg. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001836 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001837 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001838 cmd |= XM_MMU_GMII_FD;
1839
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001840 /*
1841 * Workaround BCOM Errata (#10523) for all BCom Phys
1842 * Enable Power Management after link up
1843 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001844 if (hw->phy_type == SK_PHY_BCOM) {
1845 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1846 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1847 & ~PHY_B_AC_DIS_PM);
1848 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1849 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001850
1851 /* enable Rx/Tx */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001852 xm_write16(hw, port, XM_MMU_CMD,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001853 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1854 skge_link_up(skge);
1855}
1856
1857
Stephen Hemminger45bada62005-06-27 11:33:12 -07001858static inline void bcom_phy_intr(struct skge_port *skge)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001859{
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001862 u16 isrc;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001863
Stephen Hemminger45bada62005-06-27 11:33:12 -07001864 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
Joe Perchesd7072042010-02-09 11:49:53 +00001865 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1866 "phy interrupt status 0x%x\n", isrc);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001867
1868 if (isrc & PHY_B_IS_PSE)
Joe Perchesf15063c2010-02-17 15:01:57 +00001869 pr_err("%s: uncorrectable pair swap error\n",
Stephen Hemminger45bada62005-06-27 11:33:12 -07001870 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001871
1872 /* Workaround BCom Errata:
1873 * enable and disable loopback mode if "NO HCD" occurs.
1874 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001875 if (isrc & PHY_B_IS_NO_HDCL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001876 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1877 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001878 ctrl | PHY_CT_LOOP);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001879 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001880 ctrl & ~PHY_CT_LOOP);
1881 }
1882
Stephen Hemminger45bada62005-06-27 11:33:12 -07001883 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1884 bcom_check_link(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001885
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001886}
1887
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001888static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1889{
1890 int i;
1891
1892 gma_write16(hw, port, GM_SMI_DATA, val);
1893 gma_write16(hw, port, GM_SMI_CTRL,
1894 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1895 for (i = 0; i < PHY_RETRIES; i++) {
1896 udelay(1);
1897
1898 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1899 return 0;
1900 }
1901
Joe Perchesf15063c2010-02-17 15:01:57 +00001902 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001903 return -EIO;
1904}
1905
1906static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1907{
1908 int i;
1909
1910 gma_write16(hw, port, GM_SMI_CTRL,
1911 GM_SMI_CT_PHY_AD(hw->phy_addr)
1912 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1913
1914 for (i = 0; i < PHY_RETRIES; i++) {
1915 udelay(1);
1916 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1917 goto ready;
1918 }
1919
1920 return -ETIMEDOUT;
1921 ready:
1922 *val = gma_read16(hw, port, GM_SMI_DATA);
1923 return 0;
1924}
1925
1926static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1927{
1928 u16 v = 0;
1929 if (__gm_phy_read(hw, port, reg, &v))
Joe Perchesf15063c2010-02-17 15:01:57 +00001930 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001931 return v;
1932}
1933
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001934/* Marvell Phy Initialization */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001935static void yukon_init(struct skge_hw *hw, int port)
1936{
1937 struct skge_port *skge = netdev_priv(hw->dev[port]);
1938 u16 ctrl, ct1000, adv;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001939
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001940 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001941 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001942
1943 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1944 PHY_M_EC_MAC_S_MSK);
1945 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1946
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001947 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001948
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001949 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001950 }
1951
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001952 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001953 if (skge->autoneg == AUTONEG_DISABLE)
1954 ctrl &= ~PHY_CT_ANE;
1955
1956 ctrl |= PHY_CT_RESET;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001957 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001958
1959 ctrl = 0;
1960 ct1000 = 0;
Stephen Hemmingerb18f2092005-06-27 11:33:08 -07001961 adv = PHY_AN_CSMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001962
1963 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07001964 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001965 if (skge->advertising & ADVERTISED_1000baseT_Full)
1966 ct1000 |= PHY_M_1000C_AFD;
1967 if (skge->advertising & ADVERTISED_1000baseT_Half)
1968 ct1000 |= PHY_M_1000C_AHD;
1969 if (skge->advertising & ADVERTISED_100baseT_Full)
1970 adv |= PHY_M_AN_100_FD;
1971 if (skge->advertising & ADVERTISED_100baseT_Half)
1972 adv |= PHY_M_AN_100_HD;
1973 if (skge->advertising & ADVERTISED_10baseT_Full)
1974 adv |= PHY_M_AN_10_FD;
1975 if (skge->advertising & ADVERTISED_10baseT_Half)
1976 adv |= PHY_M_AN_10_HD;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001977
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001978 /* Set Flow-control capabilities */
1979 adv |= phy_pause_map[skge->flow_control];
1980 } else {
1981 if (skge->advertising & ADVERTISED_1000baseT_Full)
1982 adv |= PHY_M_AN_1000X_AFD;
1983 if (skge->advertising & ADVERTISED_1000baseT_Half)
1984 adv |= PHY_M_AN_1000X_AHD;
1985
1986 adv |= fiber_pause_map[skge->flow_control];
1987 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001988
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001989 /* Restart Auto-negotiation */
1990 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1991 } else {
1992 /* forced speed/duplex settings */
1993 ct1000 = PHY_M_1000C_MSE;
1994
1995 if (skge->duplex == DUPLEX_FULL)
1996 ctrl |= PHY_CT_DUP_MD;
1997
1998 switch (skge->speed) {
1999 case SPEED_1000:
2000 ctrl |= PHY_CT_SP1000;
2001 break;
2002 case SPEED_100:
2003 ctrl |= PHY_CT_SP100;
2004 break;
2005 }
2006
2007 ctrl |= PHY_CT_RESET;
2008 }
2009
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002010 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002011
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002012 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2013 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002014
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002015 /* Enable phy interrupt on autonegotiation complete (or link up) */
2016 if (skge->autoneg == AUTONEG_ENABLE)
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002017 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002018 else
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002019 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002020}
2021
2022static void yukon_reset(struct skge_hw *hw, int port)
2023{
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002024 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2025 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2026 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2027 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2028 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002029
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002030 gma_write16(hw, port, GM_RX_CTRL,
2031 gma_read16(hw, port, GM_RX_CTRL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002032 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2033}
2034
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002035/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2036static int is_yukon_lite_a0(struct skge_hw *hw)
2037{
2038 u32 reg;
2039 int ret;
2040
2041 if (hw->chip_id != CHIP_ID_YUKON)
2042 return 0;
2043
2044 reg = skge_read32(hw, B2_FAR);
2045 skge_write8(hw, B2_FAR + 3, 0xff);
2046 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2047 skge_write32(hw, B2_FAR, reg);
2048 return ret;
2049}
2050
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002051static void yukon_mac_init(struct skge_hw *hw, int port)
2052{
2053 struct skge_port *skge = netdev_priv(hw->dev[port]);
2054 int i;
2055 u32 reg;
2056 const u8 *addr = hw->dev[port]->dev_addr;
2057
2058 /* WA code for COMA mode -- set PHY reset */
2059 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002060 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2061 reg = skge_read32(hw, B2_GP_IO);
2062 reg |= GP_DIR_9 | GP_IO_9;
2063 skge_write32(hw, B2_GP_IO, reg);
2064 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002065
2066 /* hard reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002067 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2068 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002069
2070 /* WA code for COMA mode -- clear PHY reset */
2071 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002072 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2073 reg = skge_read32(hw, B2_GP_IO);
2074 reg |= GP_DIR_9;
2075 reg &= ~GP_IO_9;
2076 skge_write32(hw, B2_GP_IO, reg);
2077 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002078
2079 /* Set hardware config mode */
2080 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2081 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07002082 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002083
2084 /* Clear GMC reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002085 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2086 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2087 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002088
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002089 if (skge->autoneg == AUTONEG_DISABLE) {
2090 reg = GM_GPCR_AU_ALL_DIS;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002091 gma_write16(hw, port, GM_GP_CTRL,
2092 gma_read16(hw, port, GM_GP_CTRL) | reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002093
2094 switch (skge->speed) {
2095 case SPEED_1000:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002096 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002097 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002098 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002099 case SPEED_100:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002100 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002101 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002102 break;
2103 case SPEED_10:
2104 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2105 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002106 }
2107
2108 if (skge->duplex == DUPLEX_FULL)
2109 reg |= GM_GPCR_DUP_FULL;
2110 } else
2111 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002112
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002113 switch (skge->flow_control) {
2114 case FLOW_MODE_NONE:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002115 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002116 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2117 break;
2118 case FLOW_MODE_LOC_SEND:
2119 /* disable Rx flow-control */
2120 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002121 break;
2122 case FLOW_MODE_SYMMETRIC:
2123 case FLOW_MODE_SYM_OR_REM:
2124 /* enable Tx & Rx flow-control */
2125 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002126 }
2127
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002128 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002129 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002130
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002131 yukon_init(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002132
2133 /* MIB clear */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002134 reg = gma_read16(hw, port, GM_PHY_ADDR);
2135 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002136
2137 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002138 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2139 gma_write16(hw, port, GM_PHY_ADDR, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002140
2141 /* transmit control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002142 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002143
2144 /* receive control reg: unicast + multicast + no FCS */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002145 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002146 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2147
2148 /* transmit flow control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002149 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002150
2151 /* transmit parameter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002152 gma_write16(hw, port, GM_TX_PARAM,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002153 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2154 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2155 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2156
Stephen Hemminger44c7fcc2007-11-28 14:23:01 -08002157 /* configure the Serial Mode Register */
2158 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2159 | GM_SMOD_VLAN_ENA
2160 | IPG_DATA_VAL(IPG_DATA_DEF);
2161
2162 if (hw->dev[port]->mtu > ETH_DATA_LEN)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002163 reg |= GM_SMOD_JUMBO_ENA;
2164
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002165 gma_write16(hw, port, GM_SERIAL_MODE, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002166
2167 /* physical address: used for pause frames */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002168 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002169 /* virtual address for data */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002170 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002171
2172 /* enable interrupt mask for counter overflows */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002173 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2174 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2175 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002176
2177 /* Initialize Mac Fifo */
2178
2179 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002180 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002181 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002182
2183 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2184 if (is_yukon_lite_a0(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002185 reg &= ~GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002186
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002187 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2188 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
Stephen Hemmingerc5923082005-08-16 14:01:02 -07002189 /*
2190 * because Pause Packet Truncation in GMAC is not working
2191 * we have to increase the Flush Threshold to 64 bytes
2192 * in order to flush pause packets in Rx FIFO on Yukon-1
2193 */
2194 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002195
2196 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002197 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2198 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002199}
2200
Stephen Hemminger355ec572005-11-08 10:33:43 -08002201/* Go into power down mode */
2202static void yukon_suspend(struct skge_hw *hw, int port)
2203{
2204 u16 ctrl;
2205
2206 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2207 ctrl |= PHY_M_PC_POL_R_DIS;
2208 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2209
2210 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2211 ctrl |= PHY_CT_RESET;
2212 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2213
2214 /* switch IEEE compatible power down mode on */
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2216 ctrl |= PHY_CT_PDOWN;
2217 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2218}
2219
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002220static void yukon_stop(struct skge_port *skge)
2221{
2222 struct skge_hw *hw = skge->hw;
2223 int port = skge->port;
2224
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002225 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2226 yukon_reset(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002227
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002228 gma_write16(hw, port, GM_GP_CTRL,
2229 gma_read16(hw, port, GM_GP_CTRL)
Stephen Hemminger0eedf4a2005-07-22 16:26:04 -07002230 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002231 gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002232
Stephen Hemminger355ec572005-11-08 10:33:43 -08002233 yukon_suspend(hw, port);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002234
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002235 /* set GPHY Control reset */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002236 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2237 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002238}
2239
2240static void yukon_get_stats(struct skge_port *skge, u64 *data)
2241{
2242 struct skge_hw *hw = skge->hw;
2243 int port = skge->port;
2244 int i;
2245
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002246 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2247 | gma_read32(hw, port, GM_TXO_OK_LO);
2248 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2249 | gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002250
2251 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002252 data[i] = gma_read32(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002253 skge_stats[i].gma_offset);
2254}
2255
2256static void yukon_mac_intr(struct skge_hw *hw, int port)
2257{
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002258 struct net_device *dev = hw->dev[port];
2259 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002260 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002261
Joe Perchesd7072042010-02-09 11:49:53 +00002262 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2263 "mac interrupt status 0x%x\n", status);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002264
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002265 if (status & GM_IS_RX_FF_OR) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07002266 ++dev->stats.rx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002267 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002268 }
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002269
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002270 if (status & GM_IS_TX_FF_UR) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07002271 ++dev->stats.tx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002272 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002273 }
2274
2275}
2276
2277static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2278{
Stephen Hemminger95566062005-06-27 11:33:02 -07002279 switch (aux & PHY_M_PS_SPEED_MSK) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002280 case PHY_M_PS_SPEED_1000:
2281 return SPEED_1000;
2282 case PHY_M_PS_SPEED_100:
2283 return SPEED_100;
2284 default:
2285 return SPEED_10;
2286 }
2287}
2288
2289static void yukon_link_up(struct skge_port *skge)
2290{
2291 struct skge_hw *hw = skge->hw;
2292 int port = skge->port;
2293 u16 reg;
2294
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002295 /* Enable Transmit FIFO Underrun */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002296 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002297
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002298 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002299 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2300 reg |= GM_GPCR_DUP_FULL;
2301
2302 /* enable Rx/Tx */
2303 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002304 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002305
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002306 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002307 skge_link_up(skge);
2308}
2309
2310static void yukon_link_down(struct skge_port *skge)
2311{
2312 struct skge_hw *hw = skge->hw;
2313 int port = skge->port;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002314 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002315
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002316 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2317 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2318 gma_write16(hw, port, GM_GP_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002319
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002320 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2321 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2322 ctrl |= PHY_M_AN_ASP;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002323 /* restore Asymmetric Pause bit */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002324 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002325 }
2326
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002327 skge_link_down(skge);
2328
2329 yukon_init(hw, port);
2330}
2331
2332static void yukon_phy_intr(struct skge_port *skge)
2333{
2334 struct skge_hw *hw = skge->hw;
2335 int port = skge->port;
2336 const char *reason = NULL;
2337 u16 istatus, phystat;
2338
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002339 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2340 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002341
Joe Perchesd7072042010-02-09 11:49:53 +00002342 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2343 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002344
2345 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002346 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002347 & PHY_M_AN_RF) {
2348 reason = "remote fault";
2349 goto failed;
2350 }
2351
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002352 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002353 reason = "master/slave fault";
2354 goto failed;
2355 }
2356
2357 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2358 reason = "speed/duplex";
2359 goto failed;
2360 }
2361
2362 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2363 ? DUPLEX_FULL : DUPLEX_HALF;
2364 skge->speed = yukon_speed(hw, phystat);
2365
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002366 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2367 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2368 case PHY_M_PS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002369 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002370 break;
2371 case PHY_M_PS_RX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002372 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002373 break;
2374 case PHY_M_PS_TX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002375 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002376 break;
2377 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002378 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002379 }
2380
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002381 if (skge->flow_status == FLOW_STAT_NONE ||
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002382 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002383 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002384 else
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002385 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002386 yukon_link_up(skge);
2387 return;
2388 }
2389
2390 if (istatus & PHY_M_IS_LSP_CHANGE)
2391 skge->speed = yukon_speed(hw, phystat);
2392
2393 if (istatus & PHY_M_IS_DUP_CHANGE)
2394 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2395 if (istatus & PHY_M_IS_LST_CHANGE) {
2396 if (phystat & PHY_M_PS_LINK_UP)
2397 yukon_link_up(skge);
2398 else
2399 yukon_link_down(skge);
2400 }
2401 return;
2402 failed:
Joe Perchesf15063c2010-02-17 15:01:57 +00002403 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002404
2405 /* XXX restart autonegotiation? */
2406}
2407
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002408static void skge_phy_reset(struct skge_port *skge)
2409{
2410 struct skge_hw *hw = skge->hw;
2411 int port = skge->port;
Jeff Garzikaae343d2006-12-02 07:14:39 -05002412 struct net_device *dev = hw->dev[port];
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002413
2414 netif_stop_queue(skge->netdev);
2415 netif_carrier_off(skge->netdev);
2416
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002417 spin_lock_bh(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +00002418 if (is_genesis(hw)) {
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002419 genesis_reset(hw, port);
2420 genesis_mac_init(hw, port);
2421 } else {
2422 yukon_reset(hw, port);
2423 yukon_init(hw, port);
2424 }
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002425 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger75814092006-12-01 11:41:08 -08002426
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08002427 skge_set_multicast(dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002428}
2429
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002430/* Basic MII support */
2431static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2432{
2433 struct mii_ioctl_data *data = if_mii(ifr);
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int err = -EOPNOTSUPP;
2437
2438 if (!netif_running(dev))
2439 return -ENODEV; /* Phy still in reset */
2440
Joe Perches67777f92010-02-17 15:01:58 +00002441 switch (cmd) {
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002442 case SIOCGMIIPHY:
2443 data->phy_id = hw->phy_addr;
2444
2445 /* fallthru */
2446 case SIOCGMIIREG: {
2447 u16 val = 0;
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002448 spin_lock_bh(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +00002449
2450 if (is_genesis(hw))
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002451 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2452 else
2453 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002454 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002455 data->val_out = val;
2456 break;
2457 }
2458
2459 case SIOCSMIIREG:
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002460 spin_lock_bh(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +00002461 if (is_genesis(hw))
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002462 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2463 data->val_in);
2464 else
2465 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2466 data->val_in);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002467 spin_unlock_bh(&hw->phy_lock);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002468 break;
2469 }
2470 return err;
2471}
2472
Linus Torvalds279e1da2007-11-15 08:44:36 -08002473static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002474{
2475 u32 end;
2476
Linus Torvalds279e1da2007-11-15 08:44:36 -08002477 start /= 8;
2478 len /= 8;
2479 end = start + len - 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002480
2481 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2482 skge_write32(hw, RB_ADDR(q, RB_START), start);
2483 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2484 skge_write32(hw, RB_ADDR(q, RB_RP), start);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002485 skge_write32(hw, RB_ADDR(q, RB_END), end);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002486
2487 if (q == Q_R1 || q == Q_R2) {
2488 /* Set thresholds on receive queue's */
Linus Torvalds279e1da2007-11-15 08:44:36 -08002489 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2490 start + (2*len)/3);
2491 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2492 start + (len/3));
2493 } else {
2494 /* Enable store & forward on Tx queue's because
2495 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2496 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002497 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002498 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002499
2500 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2501}
2502
2503/* Setup Bus Memory Interface */
2504static void skge_qset(struct skge_port *skge, u16 q,
2505 const struct skge_element *e)
2506{
2507 struct skge_hw *hw = skge->hw;
2508 u32 watermark = 0x600;
2509 u64 base = skge->dma + (e->desc - skge->mem);
2510
2511 /* optimization to reduce window on 32bit/33mhz */
2512 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2513 watermark /= 2;
2514
2515 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2516 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2517 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2518 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2519}
2520
2521static int skge_up(struct net_device *dev)
2522{
2523 struct skge_port *skge = netdev_priv(dev);
2524 struct skge_hw *hw = skge->hw;
2525 int port = skge->port;
Linus Torvalds279e1da2007-11-15 08:44:36 -08002526 u32 chunk, ram_addr;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002527 size_t rx_size, tx_size;
2528 int err;
2529
Stephen Hemmingerfae87592007-02-02 08:22:51 -08002530 if (!is_valid_ether_addr(dev->dev_addr))
2531 return -EINVAL;
2532
Joe Perchesd7072042010-02-09 11:49:53 +00002533 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002534
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002535 if (dev->mtu > RX_BUF_SIZE)
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002536 skge->rx_buf_size = dev->mtu + ETH_HLEN;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002537 else
2538 skge->rx_buf_size = RX_BUF_SIZE;
2539
2540
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002541 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2542 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2543 skge->mem_size = tx_size + rx_size;
2544 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2545 if (!skge->mem)
2546 return -ENOMEM;
2547
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002548 BUG_ON(skge->dma & 7);
2549
2550 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08002551 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002552 err = -EINVAL;
2553 goto free_pci_mem;
2554 }
2555
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002556 memset(skge->mem, 0, skge->mem_size);
2557
Stephen Hemminger203babb2006-03-21 10:57:05 -08002558 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2559 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002560 goto free_pci_mem;
2561
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002562 err = skge_rx_fill(dev);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002563 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002564 goto free_rx_ring;
2565
Stephen Hemminger203babb2006-03-21 10:57:05 -08002566 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2567 skge->dma + rx_size);
2568 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002569 goto free_rx_ring;
2570
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002571 /* Initialize MAC */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002572 spin_lock_bh(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +00002573 if (is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002574 genesis_mac_init(hw, port);
2575 else
2576 yukon_mac_init(hw, port);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002577 spin_unlock_bh(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002578
Stephen Hemminger29816d92007-11-26 11:54:48 -08002579 /* Configure RAMbuffers - equally between ports and tx/rx */
2580 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002581 ram_addr = hw->ram_offset + 2 * chunk * port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002582
Linus Torvalds279e1da2007-11-15 08:44:36 -08002583 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002584 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002585
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002586 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
Linus Torvalds279e1da2007-11-15 08:44:36 -08002587 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002588 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2589
2590 /* Start receiver BMU */
2591 wmb();
2592 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002593 skge_led(skge, LED_MODE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002594
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07002595 spin_lock_irq(&hw->hw_lock);
2596 hw->intr_mask |= portmask[port];
2597 skge_write32(hw, B0_IMSK, hw->intr_mask);
2598 spin_unlock_irq(&hw->hw_lock);
2599
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002600 napi_enable(&skge->napi);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002601 return 0;
2602
2603 free_rx_ring:
2604 skge_rx_clean(skge);
2605 kfree(skge->rx_ring.start);
2606 free_pci_mem:
2607 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002608 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002609
2610 return err;
2611}
2612
Stephen Hemminger60b24b52007-10-16 12:15:50 -07002613/* stop receiver */
2614static void skge_rx_stop(struct skge_hw *hw, int port)
2615{
2616 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2617 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2618 RB_RST_SET|RB_DIS_OP_MD);
2619 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2620}
2621
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002622static int skge_down(struct net_device *dev)
2623{
2624 struct skge_port *skge = netdev_priv(dev);
2625 struct skge_hw *hw = skge->hw;
2626 int port = skge->port;
2627
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002628 if (skge->mem == NULL)
2629 return 0;
2630
Joe Perchesd7072042010-02-09 11:49:53 +00002631 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002632
Michal Schmidtd119b392009-04-14 15:16:55 -07002633 netif_tx_disable(dev);
Stephen Hemminger692412b2007-04-09 15:32:45 -07002634
stephen hemminger57d6fa32011-07-06 19:00:07 +00002635 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07002636 del_timer_sync(&skge->link_timer);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002637
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002638 napi_disable(&skge->napi);
Stephen Hemminger692412b2007-04-09 15:32:45 -07002639 netif_carrier_off(dev);
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07002640
2641 spin_lock_irq(&hw->hw_lock);
2642 hw->intr_mask &= ~portmask[port];
2643 skge_write32(hw, B0_IMSK, hw->intr_mask);
2644 spin_unlock_irq(&hw->hw_lock);
2645
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002646 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
stephen hemminger57d6fa32011-07-06 19:00:07 +00002647 if (is_genesis(hw))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002648 genesis_stop(skge);
2649 else
2650 yukon_stop(skge);
2651
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002652 /* Stop transmitter */
2653 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2654 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2655 RB_RST_SET|RB_DIS_OP_MD);
2656
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002657
2658 /* Disable Force Sync bit and Enable Alloc bit */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002659 skge_write8(hw, SK_REG(port, TXA_CTRL),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002660 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2661
2662 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002663 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2664 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002665
2666 /* Reset PCI FIFO */
2667 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2668 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2669
2670 /* Reset the RAM Buffer async Tx queue */
2671 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
Stephen Hemminger60b24b52007-10-16 12:15:50 -07002672
2673 skge_rx_stop(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002674
stephen hemminger57d6fa32011-07-06 19:00:07 +00002675 if (is_genesis(hw)) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2677 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002678 } else {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002679 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2680 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002681 }
2682
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002683 skge_led(skge, LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002684
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002685 netif_tx_lock_bh(dev);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002686 skge_tx_clean(dev);
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002687 netif_tx_unlock_bh(dev);
2688
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002689 skge_rx_clean(skge);
2690
2691 kfree(skge->rx_ring.start);
2692 kfree(skge->tx_ring.start);
2693 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002694 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002695 return 0;
2696}
2697
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002698static inline int skge_avail(const struct skge_ring *ring)
2699{
Stephen Hemminger992c9622007-03-16 14:01:30 -07002700 smp_mb();
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002701 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2702 + (ring->to_clean - ring->to_use) - 1;
2703}
2704
Stephen Hemminger613573252009-08-31 19:50:58 +00002705static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2706 struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002707{
2708 struct skge_port *skge = netdev_priv(dev);
2709 struct skge_hw *hw = skge->hw;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002710 struct skge_element *e;
2711 struct skge_tx_desc *td;
2712 int i;
2713 u32 control, len;
2714 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002715
Herbert Xu5b057c62006-06-23 02:06:41 -07002716 if (skb_padto(skb, ETH_ZLEN))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002717 return NETDEV_TX_OK;
2718
Stephen Hemminger513f5332006-09-01 15:53:49 -07002719 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002720 return NETDEV_TX_BUSY;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002721
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002722 e = skge->tx_ring.to_use;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002723 td = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002724 BUG_ON(td->control & BMU_OWN);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002725 e->skb = skb;
2726 len = skb_headlen(skb);
2727 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00002728 dma_unmap_addr_set(e, mapaddr, map);
2729 dma_unmap_len_set(e, maplen, len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002730
2731 td->dma_lo = map;
2732 td->dma_hi = map >> 32;
2733
Patrick McHardy84fa7932006-08-29 16:44:56 -07002734 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michał Mirosław0d0b1672010-12-14 15:24:08 +00002735 const int offset = skb_checksum_start_offset(skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002736
2737 /* This seems backwards, but it is what the sk98lin
2738 * does. Looks like hardware is wrong?
2739 */
Joe Perches8e95a202009-12-03 07:58:21 +00002740 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
Joe Perches67777f92010-02-17 15:01:58 +00002741 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002742 control = BMU_TCP_CHECK;
2743 else
2744 control = BMU_UDP_CHECK;
2745
2746 td->csum_offs = 0;
2747 td->csum_start = offset;
Al Viroff1dcad2006-11-20 18:07:29 -08002748 td->csum_write = offset + skb->csum_offset;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002749 } else
2750 control = BMU_CHECK;
2751
2752 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
Joe Perches67777f92010-02-17 15:01:58 +00002753 control |= BMU_EOF | BMU_IRQ_EOF;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002754 else {
2755 struct skge_tx_desc *tf = td;
2756
2757 control |= BMU_STFWD;
2758 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2759 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2760
2761 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2762 frag->size, PCI_DMA_TODEVICE);
2763
2764 e = e->next;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002765 e->skb = skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002766 tf = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002767 BUG_ON(tf->control & BMU_OWN);
2768
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002769 tf->dma_lo = map;
2770 tf->dma_hi = (u64) map >> 32;
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00002771 dma_unmap_addr_set(e, mapaddr, map);
2772 dma_unmap_len_set(e, maplen, frag->size);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002773
2774 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2775 }
2776 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2777 }
2778 /* Make sure all the descriptors written */
2779 wmb();
2780 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2781 wmb();
2782
2783 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2784
Joe Perchesd7072042010-02-09 11:49:53 +00002785 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2786 "tx queued, slot %td, len %d\n",
2787 e - skge->tx_ring.start, skb->len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002788
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002789 skge->tx_ring.to_use = e->next;
Stephen Hemminger992c9622007-03-16 14:01:30 -07002790 smp_wmb();
2791
Stephen Hemminger9db96472006-06-06 10:11:12 -07002792 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
Joe Perchesf15063c2010-02-17 15:01:57 +00002793 netdev_dbg(dev, "transmit queue full\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002794 netif_stop_queue(dev);
2795 }
2796
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002797 return NETDEV_TX_OK;
2798}
2799
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002800
2801/* Free resources associated with this reing element */
2802static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2803 u32 control)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002804{
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002805 struct pci_dev *pdev = skge->hw->pdev;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002806
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002807 /* skb header vs. fragment */
2808 if (control & BMU_STF)
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00002809 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2810 dma_unmap_len(e, maplen),
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002811 PCI_DMA_TODEVICE);
2812 else
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00002813 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2814 dma_unmap_len(e, maplen),
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002815 PCI_DMA_TODEVICE);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002816
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002817 if (control & BMU_EOF) {
Joe Perchesd7072042010-02-09 11:49:53 +00002818 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2819 "tx done slot %td\n", e - skge->tx_ring.start);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002820
Stephen Hemminger513f5332006-09-01 15:53:49 -07002821 dev_kfree_skb(e->skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002822 }
2823}
2824
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002825/* Free all buffers in transmit ring */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002826static void skge_tx_clean(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002827{
Stephen Hemminger513f5332006-09-01 15:53:49 -07002828 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002829 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002830
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002831 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2832 struct skge_tx_desc *td = e->desc;
2833 skge_tx_free(skge, e, td->control);
2834 td->control = 0;
2835 }
2836
2837 skge->tx_ring.to_clean = e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002838}
2839
2840static void skge_tx_timeout(struct net_device *dev)
2841{
2842 struct skge_port *skge = netdev_priv(dev);
2843
Joe Perchesd7072042010-02-09 11:49:53 +00002844 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002845
2846 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002847 skge_tx_clean(dev);
Michal Schmidtd119b392009-04-14 15:16:55 -07002848 netif_wake_queue(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002849}
2850
2851static int skge_change_mtu(struct net_device *dev, int new_mtu)
2852{
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002853 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002854
Stephen Hemminger95566062005-06-27 11:33:02 -07002855 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002856 return -EINVAL;
2857
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002858 if (!netif_running(dev)) {
2859 dev->mtu = new_mtu;
2860 return 0;
2861 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002862
Stephen Hemminger1a8098b2007-11-28 14:25:05 -08002863 skge_down(dev);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002864
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002865 dev->mtu = new_mtu;
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002866
Stephen Hemminger1a8098b2007-11-28 14:25:05 -08002867 err = skge_up(dev);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002868 if (err)
2869 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002870
2871 return err;
2872}
2873
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002874static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2875
2876static void genesis_add_filter(u8 filter[8], const u8 *addr)
2877{
2878 u32 crc, bit;
2879
2880 crc = ether_crc_le(ETH_ALEN, addr);
2881 bit = ~crc & 0x3f;
2882 filter[bit/8] |= 1 << (bit%8);
2883}
2884
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002885static void genesis_set_multicast(struct net_device *dev)
2886{
2887 struct skge_port *skge = netdev_priv(dev);
2888 struct skge_hw *hw = skge->hw;
2889 int port = skge->port;
Jiri Pirko22bedad32010-04-01 21:22:57 +00002890 struct netdev_hw_addr *ha;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002891 u32 mode;
2892 u8 filter[8];
2893
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002894 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002895 mode |= XM_MD_ENA_HASH;
2896 if (dev->flags & IFF_PROMISC)
2897 mode |= XM_MD_ENA_PROM;
2898 else
2899 mode &= ~XM_MD_ENA_PROM;
2900
2901 if (dev->flags & IFF_ALLMULTI)
2902 memset(filter, 0xff, sizeof(filter));
2903 else {
2904 memset(filter, 0, sizeof(filter));
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002905
Joe Perches8e95a202009-12-03 07:58:21 +00002906 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2907 skge->flow_status == FLOW_STAT_SYMMETRIC)
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002908 genesis_add_filter(filter, pause_mc_addr);
2909
Jiri Pirko22bedad32010-04-01 21:22:57 +00002910 netdev_for_each_mc_addr(ha, dev)
2911 genesis_add_filter(filter, ha->addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002912 }
2913
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002914 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemminger45bada62005-06-27 11:33:12 -07002915 xm_outhash(hw, port, XM_HSM, filter);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002916}
2917
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002918static void yukon_add_filter(u8 filter[8], const u8 *addr)
2919{
2920 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2921 filter[bit/8] |= 1 << (bit%8);
2922}
2923
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002924static void yukon_set_multicast(struct net_device *dev)
2925{
2926 struct skge_port *skge = netdev_priv(dev);
2927 struct skge_hw *hw = skge->hw;
2928 int port = skge->port;
Jiri Pirko22bedad32010-04-01 21:22:57 +00002929 struct netdev_hw_addr *ha;
Joe Perches8e95a202009-12-03 07:58:21 +00002930 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2931 skge->flow_status == FLOW_STAT_SYMMETRIC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002932 u16 reg;
2933 u8 filter[8];
2934
2935 memset(filter, 0, sizeof(filter));
2936
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002937 reg = gma_read16(hw, port, GM_RX_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002938 reg |= GM_RXCR_UCF_ENA;
2939
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002940 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002941 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2942 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2943 memset(filter, 0xff, sizeof(filter));
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00002944 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002945 reg &= ~GM_RXCR_MCF_ENA;
2946 else {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002947 reg |= GM_RXCR_MCF_ENA;
2948
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002949 if (rx_pause)
2950 yukon_add_filter(filter, pause_mc_addr);
2951
Jiri Pirko22bedad32010-04-01 21:22:57 +00002952 netdev_for_each_mc_addr(ha, dev)
2953 yukon_add_filter(filter, ha->addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002954 }
2955
2956
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002957 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002958 (u16)filter[0] | ((u16)filter[1] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002959 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002960 (u16)filter[2] | ((u16)filter[3] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002961 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002962 (u16)filter[4] | ((u16)filter[5] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002963 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002964 (u16)filter[6] | ((u16)filter[7] << 8));
2965
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002966 gma_write16(hw, port, GM_RX_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002967}
2968
Stephen Hemminger383181a2005-09-19 15:37:16 -07002969static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2970{
stephen hemminger57d6fa32011-07-06 19:00:07 +00002971 if (is_genesis(hw))
Stephen Hemminger383181a2005-09-19 15:37:16 -07002972 return status >> XMR_FS_LEN_SHIFT;
2973 else
2974 return status >> GMR_FS_LEN_SHIFT;
2975}
2976
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002977static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2978{
stephen hemminger57d6fa32011-07-06 19:00:07 +00002979 if (is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002980 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2981 else
2982 return (status & GMR_FS_ANY_ERR) ||
2983 (status & GMR_FS_RX_OK) == 0;
2984}
2985
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08002986static void skge_set_multicast(struct net_device *dev)
2987{
2988 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08002989
stephen hemminger57d6fa32011-07-06 19:00:07 +00002990 if (is_genesis(skge->hw))
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08002991 genesis_set_multicast(dev);
2992 else
2993 yukon_set_multicast(dev);
2994
2995}
2996
Stephen Hemminger383181a2005-09-19 15:37:16 -07002997
2998/* Get receive buffer from descriptor.
2999 * Handles copy of small buffers and reallocation failures
3000 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003001static struct sk_buff *skge_rx_get(struct net_device *dev,
3002 struct skge_element *e,
3003 u32 control, u32 status, u16 csum)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003004{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003005 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003006 struct sk_buff *skb;
3007 u16 len = control & BMU_BBC;
3008
Joe Perchesd7072042010-02-09 11:49:53 +00003009 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3010 "rx slot %td status 0x%x len %d\n",
3011 e - skge->rx_ring.start, status, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003012
3013 if (len > skge->rx_buf_size)
3014 goto error;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003015
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003016 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
Stephen Hemminger383181a2005-09-19 15:37:16 -07003017 goto error;
3018
3019 if (bad_phy_status(skge->hw, status))
3020 goto error;
3021
3022 if (phy_length(skge->hw, status) != len)
3023 goto error;
3024
3025 if (len < RX_COPY_THRESHOLD) {
Eric Dumazet89d71a62009-10-13 05:34:20 +00003026 skb = netdev_alloc_skb_ip_align(dev, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003027 if (!skb)
3028 goto resubmit;
3029
Stephen Hemminger383181a2005-09-19 15:37:16 -07003030 pci_dma_sync_single_for_cpu(skge->hw->pdev,
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00003031 dma_unmap_addr(e, mapaddr),
Stephen Hemminger383181a2005-09-19 15:37:16 -07003032 len, PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03003033 skb_copy_from_linear_data(e->skb, skb->data, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003034 pci_dma_sync_single_for_device(skge->hw->pdev,
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00003035 dma_unmap_addr(e, mapaddr),
Stephen Hemminger383181a2005-09-19 15:37:16 -07003036 len, PCI_DMA_FROMDEVICE);
3037 skge_rx_reuse(e, skge->rx_buf_size);
3038 } else {
3039 struct sk_buff *nskb;
Eric Dumazet89d71a62009-10-13 05:34:20 +00003040
3041 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003042 if (!nskb)
3043 goto resubmit;
3044
3045 pci_unmap_single(skge->hw->pdev,
FUJITA Tomonori10fc51b2010-04-27 14:57:04 +00003046 dma_unmap_addr(e, mapaddr),
3047 dma_unmap_len(e, maplen),
Stephen Hemminger383181a2005-09-19 15:37:16 -07003048 PCI_DMA_FROMDEVICE);
3049 skb = e->skb;
Joe Perches67777f92010-02-17 15:01:58 +00003050 prefetch(skb->data);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003051 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3052 }
3053
3054 skb_put(skb, len);
Michał Mirosławe92702b2011-03-31 01:01:35 +00003055
3056 if (dev->features & NETIF_F_RXCSUM) {
Stephen Hemminger383181a2005-09-19 15:37:16 -07003057 skb->csum = csum;
Patrick McHardy84fa7932006-08-29 16:44:56 -07003058 skb->ip_summed = CHECKSUM_COMPLETE;
Stephen Hemminger383181a2005-09-19 15:37:16 -07003059 }
3060
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003061 skb->protocol = eth_type_trans(skb, dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003062
3063 return skb;
3064error:
3065
Joe Perchesd7072042010-02-09 11:49:53 +00003066 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3067 "rx err, slot %td control 0x%x status 0x%x\n",
3068 e - skge->rx_ring.start, control, status);
Stephen Hemminger383181a2005-09-19 15:37:16 -07003069
stephen hemminger57d6fa32011-07-06 19:00:07 +00003070 if (is_genesis(skge->hw)) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003071 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
Stephen Hemmingerda007722007-10-16 12:15:52 -07003072 dev->stats.rx_length_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003073 if (status & XMR_FS_FRA_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003074 dev->stats.rx_frame_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003075 if (status & XMR_FS_FCS_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003076 dev->stats.rx_crc_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003077 } else {
3078 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
Stephen Hemmingerda007722007-10-16 12:15:52 -07003079 dev->stats.rx_length_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003080 if (status & GMR_FS_FRAGMENT)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003081 dev->stats.rx_frame_errors++;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003082 if (status & GMR_FS_CRC_ERR)
Stephen Hemmingerda007722007-10-16 12:15:52 -07003083 dev->stats.rx_crc_errors++;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003084 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003085
Stephen Hemminger383181a2005-09-19 15:37:16 -07003086resubmit:
3087 skge_rx_reuse(e, skge->rx_buf_size);
3088 return NULL;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003089}
3090
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003091/* Free all buffers in Tx ring which are no longer owned by device */
Stephen Hemminger513f5332006-09-01 15:53:49 -07003092static void skge_tx_done(struct net_device *dev)
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003093{
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003094 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003095 struct skge_ring *ring = &skge->tx_ring;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003096 struct skge_element *e;
3097
Stephen Hemminger513f5332006-09-01 15:53:49 -07003098 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003099
Stephen Hemminger866b4f32006-03-23 11:07:27 -08003100 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
Stephen Hemminger992c9622007-03-16 14:01:30 -07003101 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003102
Stephen Hemminger992c9622007-03-16 14:01:30 -07003103 if (control & BMU_OWN)
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003104 break;
3105
Stephen Hemminger992c9622007-03-16 14:01:30 -07003106 skge_tx_free(skge, e, control);
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003107 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003108 skge->tx_ring.to_clean = e;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08003109
Stephen Hemminger992c9622007-03-16 14:01:30 -07003110 /* Can run lockless until we need to synchronize to restart queue. */
3111 smp_mb();
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003112
Stephen Hemminger992c9622007-03-16 14:01:30 -07003113 if (unlikely(netif_queue_stopped(dev) &&
3114 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3115 netif_tx_lock(dev);
3116 if (unlikely(netif_queue_stopped(dev) &&
3117 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3118 netif_wake_queue(dev);
3119
3120 }
3121 netif_tx_unlock(dev);
3122 }
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003123}
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003124
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003125static int skge_poll(struct napi_struct *napi, int to_do)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003126{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003127 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3128 struct net_device *dev = skge->netdev;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003129 struct skge_hw *hw = skge->hw;
3130 struct skge_ring *ring = &skge->rx_ring;
3131 struct skge_element *e;
Stephen Hemminger00a6cae22006-03-21 10:56:59 -08003132 int work_done = 0;
3133
Stephen Hemminger513f5332006-09-01 15:53:49 -07003134 skge_tx_done(dev);
3135
3136 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3137
Stephen Hemminger1631aef2005-11-08 10:33:44 -08003138 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003139 struct skge_rx_desc *rd = e->desc;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003140 struct sk_buff *skb;
Stephen Hemminger383181a2005-09-19 15:37:16 -07003141 u32 control;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003142
3143 rmb();
3144 control = rd->control;
3145 if (control & BMU_OWN)
3146 break;
3147
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003148 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003149 if (likely(skb)) {
Eric Dumazet86cac582010-08-31 18:25:32 +00003150 napi_gro_receive(napi, skb);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003151 ++work_done;
Stephen Hemminger5a011442006-03-23 11:07:25 -08003152 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003153 }
3154 ring->to_clean = e;
3155
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003156 /* restart receiver */
3157 wmb();
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08003158 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003159
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003160 if (work_done < to_do) {
Marin Mitov6ef29772008-03-23 10:20:09 +02003161 unsigned long flags;
Jeff Garzikf0c88f92008-03-25 23:53:24 -04003162
Eric Dumazet86cac582010-08-31 18:25:32 +00003163 napi_gro_flush(napi);
Marin Mitov6ef29772008-03-23 10:20:09 +02003164 spin_lock_irqsave(&hw->hw_lock, flags);
Ben Hutchings288379f2009-01-19 16:43:59 -08003165 __napi_complete(napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003166 hw->intr_mask |= napimask[skge->port];
3167 skge_write32(hw, B0_IMSK, hw->intr_mask);
3168 skge_read32(hw, B0_IMSK);
Marin Mitov6ef29772008-03-23 10:20:09 +02003169 spin_unlock_irqrestore(&hw->hw_lock, flags);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003170 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003171
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003172 return work_done;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003173}
3174
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003175/* Parity errors seem to happen when Genesis is connected to a switch
3176 * with no other ports present. Heartbeat error??
3177 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003178static void skge_mac_parity(struct skge_hw *hw, int port)
3179{
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003180 struct net_device *dev = hw->dev[port];
3181
Stephen Hemmingerda007722007-10-16 12:15:52 -07003182 ++dev->stats.tx_heartbeat_errors;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003183
stephen hemminger57d6fa32011-07-06 19:00:07 +00003184 if (is_genesis(hw))
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003186 MFF_CLR_PERR);
3187 else
3188 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003189 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
Stephen Hemminger981d0372005-06-27 11:33:06 -07003190 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003191 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3192}
3193
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003194static void skge_mac_intr(struct skge_hw *hw, int port)
3195{
stephen hemminger57d6fa32011-07-06 19:00:07 +00003196 if (is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003197 genesis_mac_intr(hw, port);
3198 else
3199 yukon_mac_intr(hw, port);
3200}
3201
3202/* Handle device specific framing and timeout interrupts */
3203static void skge_error_irq(struct skge_hw *hw)
3204{
Stephen Hemminger1479d132007-02-02 08:22:52 -08003205 struct pci_dev *pdev = hw->pdev;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003206 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3207
stephen hemminger57d6fa32011-07-06 19:00:07 +00003208 if (is_genesis(hw)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003209 /* clear xmac errors */
3210 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003211 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003212 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003213 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003214 } else {
3215 /* Timestamp (unused) overflow */
3216 if (hwstatus & IS_IRQ_TIST_OV)
3217 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003218 }
3219
3220 if (hwstatus & IS_RAM_RD_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003221 dev_err(&pdev->dev, "Ram read data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003222 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3223 }
3224
3225 if (hwstatus & IS_RAM_WR_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003226 dev_err(&pdev->dev, "Ram write data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003227 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3228 }
3229
3230 if (hwstatus & IS_M1_PAR_ERR)
3231 skge_mac_parity(hw, 0);
3232
3233 if (hwstatus & IS_M2_PAR_ERR)
3234 skge_mac_parity(hw, 1);
3235
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003236 if (hwstatus & IS_R1_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003237 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3238 hw->dev[0]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003239 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003240 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003241
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003242 if (hwstatus & IS_R2_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003243 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3244 hw->dev[1]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003245 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003246 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003247
3248 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003249 u16 pci_status, pci_cmd;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003250
Stephen Hemminger1479d132007-02-02 08:22:52 -08003251 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3252 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003253
Stephen Hemminger1479d132007-02-02 08:22:52 -08003254 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3255 pci_cmd, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003256
3257 /* Write the error bits back to clear them. */
3258 pci_status &= PCI_STATUS_ERROR_BITS;
3259 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003260 pci_write_config_word(pdev, PCI_COMMAND,
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003261 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003262 pci_write_config_word(pdev, PCI_STATUS, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003263 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003264
Stephen Hemminger050ec182005-08-16 14:00:54 -07003265 /* if error still set then just ignore it */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003266 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3267 if (hwstatus & IS_IRQ_STAT) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003268 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003269 hw->intr_mask &= ~IS_HW_ERR;
3270 }
3271 }
3272}
3273
3274/*
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003275 * Interrupt from PHY are handled in tasklet (softirq)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003276 * because accessing phy registers requires spin wait which might
3277 * cause excess interrupt latency.
3278 */
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003279static void skge_extirq(unsigned long arg)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003280{
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003281 struct skge_hw *hw = (struct skge_hw *) arg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003282 int port;
3283
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003284 for (port = 0; port < hw->ports; port++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003285 struct net_device *dev = hw->dev[port];
3286
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003287 if (netif_running(dev)) {
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003288 struct skge_port *skge = netdev_priv(dev);
3289
3290 spin_lock(&hw->phy_lock);
stephen hemminger57d6fa32011-07-06 19:00:07 +00003291 if (!is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003292 yukon_phy_intr(skge);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003293 else if (hw->phy_type == SK_PHY_BCOM)
Stephen Hemminger45bada62005-06-27 11:33:12 -07003294 bcom_phy_intr(skge);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003295 spin_unlock(&hw->phy_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003296 }
3297 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003298
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003299 spin_lock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003300 hw->intr_mask |= IS_EXT_REG;
3301 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003302 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003303 spin_unlock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003304}
3305
David Howells7d12e782006-10-05 14:55:46 +01003306static irqreturn_t skge_intr(int irq, void *dev_id)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003307{
3308 struct skge_hw *hw = dev_id;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003309 u32 status;
Stephen Hemminger29365c92006-09-01 15:53:48 -07003310 int handled = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003311
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003312 spin_lock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003313 /* Reading this register masks IRQ */
3314 status = skge_read32(hw, B0_SP_ISRC);
Stephen Hemminger0486a8c2006-09-06 11:06:10 -07003315 if (status == 0 || status == ~0)
Stephen Hemminger29365c92006-09-01 15:53:48 -07003316 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003317
Stephen Hemminger29365c92006-09-01 15:53:48 -07003318 handled = 1;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003319 status &= hw->intr_mask;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003320 if (status & IS_EXT_REG) {
3321 hw->intr_mask &= ~IS_EXT_REG;
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003322 tasklet_schedule(&hw->phy_task);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003323 }
3324
Stephen Hemminger513f5332006-09-01 15:53:49 -07003325 if (status & (IS_XA1_F|IS_R1_F)) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003326 struct skge_port *skge = netdev_priv(hw->dev[0]);
Stephen Hemminger513f5332006-09-01 15:53:49 -07003327 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
Ben Hutchings288379f2009-01-19 16:43:59 -08003328 napi_schedule(&skge->napi);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003329 }
3330
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003331 if (status & IS_PA_TO_TX1)
3332 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3333
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003334 if (status & IS_PA_TO_RX1) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07003335 ++hw->dev[0]->stats.rx_over_errors;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003336 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3337 }
3338
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003339
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003340 if (status & IS_MAC1)
3341 skge_mac_intr(hw, 0);
Stephen Hemminger95566062005-06-27 11:33:02 -07003342
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003343 if (hw->dev[1]) {
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003344 struct skge_port *skge = netdev_priv(hw->dev[1]);
3345
Stephen Hemminger513f5332006-09-01 15:53:49 -07003346 if (status & (IS_XA2_F|IS_R2_F)) {
3347 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
Ben Hutchings288379f2009-01-19 16:43:59 -08003348 napi_schedule(&skge->napi);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003349 }
3350
3351 if (status & IS_PA_TO_RX2) {
Stephen Hemmingerda007722007-10-16 12:15:52 -07003352 ++hw->dev[1]->stats.rx_over_errors;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003353 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3354 }
3355
3356 if (status & IS_PA_TO_TX2)
3357 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3358
3359 if (status & IS_MAC2)
3360 skge_mac_intr(hw, 1);
3361 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003362
3363 if (status & IS_HW_ERR)
3364 skge_error_irq(hw);
3365
Stephen Hemminger7e676d92005-06-27 11:33:13 -07003366 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003367 skge_read32(hw, B0_IMSK);
Stephen Hemminger29365c92006-09-01 15:53:48 -07003368out:
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003369 spin_unlock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003370
Stephen Hemminger29365c92006-09-01 15:53:48 -07003371 return IRQ_RETVAL(handled);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003372}
3373
3374#ifdef CONFIG_NET_POLL_CONTROLLER
3375static void skge_netpoll(struct net_device *dev)
3376{
3377 struct skge_port *skge = netdev_priv(dev);
3378
3379 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +01003380 skge_intr(dev->irq, skge->hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003381 enable_irq(dev->irq);
3382}
3383#endif
3384
3385static int skge_set_mac_address(struct net_device *dev, void *p)
3386{
3387 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003388 struct skge_hw *hw = skge->hw;
3389 unsigned port = skge->port;
3390 const struct sockaddr *addr = p;
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003391 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003392
3393 if (!is_valid_ether_addr(addr->sa_data))
3394 return -EADDRNOTAVAIL;
3395
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003396 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003397
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003398 if (!netif_running(dev)) {
3399 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3400 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3401 } else {
3402 /* disable Rx */
3403 spin_lock_bh(&hw->phy_lock);
3404 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3405 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003406
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003407 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3408 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003409
stephen hemminger57d6fa32011-07-06 19:00:07 +00003410 if (is_genesis(hw))
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003411 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3412 else {
3413 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3414 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3415 }
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003416
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003417 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3418 spin_unlock_bh(&hw->phy_lock);
3419 }
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003420
3421 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003422}
3423
3424static const struct {
3425 u8 id;
3426 const char *name;
3427} skge_chips[] = {
3428 { CHIP_ID_GENESIS, "Genesis" },
3429 { CHIP_ID_YUKON, "Yukon" },
3430 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3431 { CHIP_ID_YUKON_LP, "Yukon-LP"},
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003432};
3433
3434static const char *skge_board_name(const struct skge_hw *hw)
3435{
3436 int i;
3437 static char buf[16];
3438
3439 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3440 if (skge_chips[i].id == hw->chip_id)
3441 return skge_chips[i].name;
3442
3443 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3444 return buf;
3445}
3446
3447
3448/*
3449 * Setup the board data structure, but don't bring up
3450 * the port(s)
3451 */
3452static int skge_reset(struct skge_hw *hw)
3453{
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003454 u32 reg;
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003455 u16 ctst, pci_status;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003456 u8 t8, mac_cfg, pmd_type;
Stephen Hemminger981d0372005-06-27 11:33:06 -07003457 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003458
3459 ctst = skge_read16(hw, B0_CTST);
3460
3461 /* do a SW reset */
3462 skge_write8(hw, B0_CTST, CS_RST_SET);
3463 skge_write8(hw, B0_CTST, CS_RST_CLR);
3464
3465 /* clear PCI errors, if any */
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003466 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3467 skge_write8(hw, B2_TST_CTRL2, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003468
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003469 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3470 pci_write_config_word(hw->pdev, PCI_STATUS,
3471 pci_status | PCI_STATUS_ERROR_BITS);
3472 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003473 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3474
3475 /* restore CLK_RUN bits (for Yukon-Lite) */
3476 skge_write16(hw, B0_CTST,
3477 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3478
3479 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003480 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003481 pmd_type = skge_read8(hw, B2_PMD_TYP);
3482 hw->copper = (pmd_type == 'T' || pmd_type == '1');
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003483
Stephen Hemminger95566062005-06-27 11:33:02 -07003484 switch (hw->chip_id) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003485 case CHIP_ID_GENESIS:
stephen hemminger57d6fa32011-07-06 19:00:07 +00003486#ifdef CONFIG_SKGE_GENESIS
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003487 switch (hw->phy_type) {
3488 case SK_PHY_XMAC:
3489 hw->phy_addr = PHY_ADDR_XMAC;
3490 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003491 case SK_PHY_BCOM:
3492 hw->phy_addr = PHY_ADDR_BCOM;
3493 break;
3494 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003495 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3496 hw->phy_type);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003497 return -EOPNOTSUPP;
3498 }
3499 break;
stephen hemminger57d6fa32011-07-06 19:00:07 +00003500#else
3501 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3502 return -EOPNOTSUPP;
3503#endif
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003504
3505 case CHIP_ID_YUKON:
3506 case CHIP_ID_YUKON_LITE:
3507 case CHIP_ID_YUKON_LP:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003508 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003509 hw->copper = 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003510
3511 hw->phy_addr = PHY_ADDR_MARV;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003512 break;
3513
3514 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003515 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3516 hw->chip_id);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003517 return -EOPNOTSUPP;
3518 }
3519
Stephen Hemminger981d0372005-06-27 11:33:06 -07003520 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3521 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3522 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003523
3524 /* read the adapters RAM size */
3525 t8 = skge_read8(hw, B2_E_0);
stephen hemminger57d6fa32011-07-06 19:00:07 +00003526 if (is_genesis(hw)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003527 if (t8 == 3) {
3528 /* special case: 4 x 64k x 36, offset = 0x80000 */
Linus Torvalds279e1da2007-11-15 08:44:36 -08003529 hw->ram_size = 0x100000;
3530 hw->ram_offset = 0x80000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003531 } else
3532 hw->ram_size = t8 * 512;
Joe Perches67777f92010-02-17 15:01:58 +00003533 } else if (t8 == 0)
Linus Torvalds279e1da2007-11-15 08:44:36 -08003534 hw->ram_size = 0x20000;
3535 else
3536 hw->ram_size = t8 * 4096;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003537
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07003538 hw->intr_mask = IS_HW_ERR;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003539
Stephen Hemminger4ebabfc2007-03-16 14:01:27 -07003540 /* Use PHY IRQ for all but fiber based Genesis board */
stephen hemminger57d6fa32011-07-06 19:00:07 +00003541 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003542 hw->intr_mask |= IS_EXT_REG;
3543
stephen hemminger57d6fa32011-07-06 19:00:07 +00003544 if (is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003545 genesis_init(hw);
3546 else {
3547 /* switch power to VCC (WA for VAUX problem) */
3548 skge_write8(hw, B0_POWER_CTRL,
3549 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003550
Stephen Hemminger050ec182005-08-16 14:00:54 -07003551 /* avoid boards with stuck Hardware error bits */
3552 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3553 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003554 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
Stephen Hemminger050ec182005-08-16 14:00:54 -07003555 hw->intr_mask &= ~IS_HW_ERR;
3556 }
3557
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003558 /* Clear PHY COMA */
3559 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3560 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3561 reg &= ~PCI_PHY_COMA;
3562 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3563 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3564
3565
Stephen Hemminger981d0372005-06-27 11:33:06 -07003566 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003567 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3568 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003569 }
3570 }
3571
3572 /* turn off hardware timer (unused) */
3573 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3574 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3575 skge_write8(hw, B0_LED, LED_STAT_ON);
3576
3577 /* enable the Tx Arbiters */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003578 for (i = 0; i < hw->ports; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003579 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003580
3581 /* Initialize ram interface */
3582 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3583
3584 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3585 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3586 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3587 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3588 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3589 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3590 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3591 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3592 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3593 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3594 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3595 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3596
3597 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3598
3599 /* Set interrupt moderation for Transmit only
3600 * Receive interrupts avoided by NAPI
3601 */
3602 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3603 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3604 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3605
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003606 skge_write32(hw, B0_IMSK, hw->intr_mask);
3607
Stephen Hemminger981d0372005-06-27 11:33:06 -07003608 for (i = 0; i < hw->ports; i++) {
stephen hemminger57d6fa32011-07-06 19:00:07 +00003609 if (is_genesis(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003610 genesis_reset(hw, i);
3611 else
3612 yukon_reset(hw, i);
3613 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003614
3615 return 0;
3616}
3617
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003618
3619#ifdef CONFIG_SKGE_DEBUG
3620
3621static struct dentry *skge_debug;
3622
3623static int skge_debug_show(struct seq_file *seq, void *v)
3624{
3625 struct net_device *dev = seq->private;
3626 const struct skge_port *skge = netdev_priv(dev);
3627 const struct skge_hw *hw = skge->hw;
3628 const struct skge_element *e;
3629
3630 if (!netif_running(dev))
3631 return -ENETDOWN;
3632
3633 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3634 skge_read32(hw, B0_IMSK));
3635
3636 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3637 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3638 const struct skge_tx_desc *t = e->desc;
3639 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3640 t->control, t->dma_hi, t->dma_lo, t->status,
3641 t->csum_offs, t->csum_write, t->csum_start);
3642 }
3643
Frans Pop2381a552010-03-24 07:57:36 +00003644 seq_printf(seq, "\nRx Ring:\n");
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003645 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3646 const struct skge_rx_desc *r = e->desc;
3647
3648 if (r->control & BMU_OWN)
3649 break;
3650
3651 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3652 r->control, r->dma_hi, r->dma_lo, r->status,
3653 r->timestamp, r->csum1, r->csum1_start);
3654 }
3655
3656 return 0;
3657}
3658
3659static int skge_debug_open(struct inode *inode, struct file *file)
3660{
3661 return single_open(file, skge_debug_show, inode->i_private);
3662}
3663
3664static const struct file_operations skge_debug_fops = {
3665 .owner = THIS_MODULE,
3666 .open = skge_debug_open,
3667 .read = seq_read,
3668 .llseek = seq_lseek,
3669 .release = single_release,
3670};
3671
3672/*
3673 * Use network device events to create/remove/rename
3674 * debugfs file entries
3675 */
3676static int skge_device_event(struct notifier_block *unused,
3677 unsigned long event, void *ptr)
3678{
3679 struct net_device *dev = ptr;
3680 struct skge_port *skge;
3681 struct dentry *d;
3682
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08003683 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003684 goto done;
3685
3686 skge = netdev_priv(dev);
Joe Perches67777f92010-02-17 15:01:58 +00003687 switch (event) {
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003688 case NETDEV_CHANGENAME:
3689 if (skge->debugfs) {
3690 d = debugfs_rename(skge_debug, skge->debugfs,
3691 skge_debug, dev->name);
3692 if (d)
3693 skge->debugfs = d;
3694 else {
Joe Perchesf15063c2010-02-17 15:01:57 +00003695 netdev_info(dev, "rename failed\n");
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003696 debugfs_remove(skge->debugfs);
3697 }
3698 }
3699 break;
3700
3701 case NETDEV_GOING_DOWN:
3702 if (skge->debugfs) {
3703 debugfs_remove(skge->debugfs);
3704 skge->debugfs = NULL;
3705 }
3706 break;
3707
3708 case NETDEV_UP:
3709 d = debugfs_create_file(dev->name, S_IRUGO,
3710 skge_debug, dev,
3711 &skge_debug_fops);
3712 if (!d || IS_ERR(d))
Joe Perchesf15063c2010-02-17 15:01:57 +00003713 netdev_info(dev, "debugfs create failed\n");
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003714 else
3715 skge->debugfs = d;
3716 break;
3717 }
3718
3719done:
3720 return NOTIFY_DONE;
3721}
3722
3723static struct notifier_block skge_notifier = {
3724 .notifier_call = skge_device_event,
3725};
3726
3727
3728static __init void skge_debug_init(void)
3729{
3730 struct dentry *ent;
3731
3732 ent = debugfs_create_dir("skge", NULL);
3733 if (!ent || IS_ERR(ent)) {
Joe Perchesf15063c2010-02-17 15:01:57 +00003734 pr_info("debugfs create directory failed\n");
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07003735 return;
3736 }
3737
3738 skge_debug = ent;
3739 register_netdevice_notifier(&skge_notifier);
3740}
3741
3742static __exit void skge_debug_cleanup(void)
3743{
3744 if (skge_debug) {
3745 unregister_netdevice_notifier(&skge_notifier);
3746 debugfs_remove(skge_debug);
3747 skge_debug = NULL;
3748 }
3749}
3750
3751#else
3752#define skge_debug_init()
3753#define skge_debug_cleanup()
3754#endif
3755
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08003756static const struct net_device_ops skge_netdev_ops = {
3757 .ndo_open = skge_up,
3758 .ndo_stop = skge_down,
Stephen Hemminger00829822008-11-20 20:14:53 -08003759 .ndo_start_xmit = skge_xmit_frame,
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08003760 .ndo_do_ioctl = skge_ioctl,
3761 .ndo_get_stats = skge_get_stats,
3762 .ndo_tx_timeout = skge_tx_timeout,
3763 .ndo_change_mtu = skge_change_mtu,
3764 .ndo_validate_addr = eth_validate_addr,
3765 .ndo_set_multicast_list = skge_set_multicast,
3766 .ndo_set_mac_address = skge_set_mac_address,
3767#ifdef CONFIG_NET_POLL_CONTROLLER
3768 .ndo_poll_controller = skge_netpoll,
3769#endif
3770};
3771
3772
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003773/* Initialize network device */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003774static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3775 int highmem)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003776{
3777 struct skge_port *skge;
3778 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3779
3780 if (!dev) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003781 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003782 return NULL;
3783 }
3784
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003785 SET_NETDEV_DEV(dev, &hw->pdev->dev);
Stephen Hemmingerf80d0322008-11-19 22:01:26 -08003786 dev->netdev_ops = &skge_netdev_ops;
3787 dev->ethtool_ops = &skge_ethtool_ops;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003788 dev->watchdog_timeo = TX_WATCHDOG;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003789 dev->irq = hw->pdev->irq;
Stephen Hemminger513f5332006-09-01 15:53:49 -07003790
Stephen Hemminger981d0372005-06-27 11:33:06 -07003791 if (highmem)
3792 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003793
3794 skge = netdev_priv(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003795 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003796 skge->netdev = dev;
3797 skge->hw = hw;
3798 skge->msg_enable = netif_msg_init(debug, default_msg);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003799
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003800 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3801 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3802
3803 /* Auto speed and flow control */
3804 skge->autoneg = AUTONEG_ENABLE;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07003805 skge->flow_control = FLOW_MODE_SYM_OR_REM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003806 skge->duplex = -1;
3807 skge->speed = -1;
Stephen Hemminger31b619c2005-06-27 11:33:11 -07003808 skge->advertising = skge_supported_modes(hw);
Stephen Hemminger5b982c52007-05-08 13:36:20 -07003809
Rafael J. Wysocki7b55a4a2009-07-22 02:58:55 +00003810 if (device_can_wakeup(&hw->pdev->dev)) {
Stephen Hemminger5b982c52007-05-08 13:36:20 -07003811 skge->wol = wol_supported(hw) & WAKE_MAGIC;
Rafael J. Wysocki7b55a4a2009-07-22 02:58:55 +00003812 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3813 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003814
3815 hw->dev[port] = dev;
3816
3817 skge->port = port;
3818
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003819 /* Only used for Genesis XMAC */
stephen hemminger57d6fa32011-07-06 19:00:07 +00003820 if (is_genesis(hw))
3821 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3822 else {
Michał Mirosławe92702b2011-03-31 01:01:35 +00003823 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3824 NETIF_F_RXCSUM;
3825 dev->features |= dev->hw_features;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003826 }
3827
3828 /* read the mac address */
3829 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
John W. Linville56230d52005-09-12 10:48:57 -04003830 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003831
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003832 return dev;
3833}
3834
3835static void __devinit skge_show_addr(struct net_device *dev)
3836{
3837 const struct skge_port *skge = netdev_priv(dev);
3838
Joe Perchesd7072042010-02-09 11:49:53 +00003839 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003840}
3841
Stanislaw Gruszka392bd0c2010-10-05 15:11:40 -07003842static int only_32bit_dma;
3843
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003844static int __devinit skge_probe(struct pci_dev *pdev,
3845 const struct pci_device_id *ent)
3846{
3847 struct net_device *dev, *dev1;
3848 struct skge_hw *hw;
3849 int err, using_dac = 0;
3850
Stephen Hemminger203babb2006-03-21 10:57:05 -08003851 err = pci_enable_device(pdev);
3852 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003853 dev_err(&pdev->dev, "cannot enable PCI device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003854 goto err_out;
3855 }
3856
Stephen Hemminger203babb2006-03-21 10:57:05 -08003857 err = pci_request_regions(pdev, DRV_NAME);
3858 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003859 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003860 goto err_out_disable_pdev;
3861 }
3862
3863 pci_set_master(pdev);
3864
Stanislaw Gruszka392bd0c2010-10-05 15:11:40 -07003865 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003866 using_dac = 1;
Yang Hongyang6a355282009-04-06 19:01:13 -07003867 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Yang Hongyang284901a2009-04-06 19:01:15 -07003868 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
Stephen Hemminger93aea712006-03-21 10:57:02 -08003869 using_dac = 0;
Yang Hongyang284901a2009-04-06 19:01:15 -07003870 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Stephen Hemminger93aea712006-03-21 10:57:02 -08003871 }
3872
3873 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003874 dev_err(&pdev->dev, "no usable DMA configuration\n");
Stephen Hemminger93aea712006-03-21 10:57:02 -08003875 goto err_out_free_regions;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003876 }
3877
3878#ifdef __BIG_ENDIAN
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08003879 /* byte swap descriptors in hardware */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003880 {
3881 u32 reg;
3882
3883 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3884 reg |= PCI_REV_DESC;
3885 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3886 }
3887#endif
3888
3889 err = -ENOMEM;
Michal Schmidt415e69e2009-10-01 08:13:23 +00003890 /* space for skge@pci:0000:04:00.0 */
Joe Perches67777f92010-02-17 15:01:58 +00003891 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
Michal Schmidt415e69e2009-10-01 08:13:23 +00003892 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003893 if (!hw) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003894 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003895 goto err_out_free_regions;
3896 }
Michal Schmidt415e69e2009-10-01 08:13:23 +00003897 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003898
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003899 hw->pdev = pdev;
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003900 spin_lock_init(&hw->hw_lock);
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003901 spin_lock_init(&hw->phy_lock);
Joe Perches164165d2009-11-19 09:30:10 +00003902 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003903
3904 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3905 if (!hw->regs) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003906 dev_err(&pdev->dev, "cannot map device registers\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003907 goto err_out_free_hw;
3908 }
3909
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003910 err = skge_reset(hw);
3911 if (err)
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003912 goto err_out_iounmap;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003913
Joe Perchesf15063c2010-02-17 15:01:57 +00003914 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3915 DRV_VERSION,
3916 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3917 skge_board_name(hw), hw->chip_rev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003918
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003919 dev = skge_devinit(hw, 0, using_dac);
3920 if (!dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003921 goto err_out_led_off;
3922
Stephen Hemmingerfae87592007-02-02 08:22:51 -08003923 /* Some motherboards are broken and has zero in ROM. */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003924 if (!is_valid_ether_addr(dev->dev_addr))
3925 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
Stephen Hemminger631ae322006-06-06 10:11:14 -07003926
Stephen Hemminger203babb2006-03-21 10:57:05 -08003927 err = register_netdev(dev);
3928 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003929 dev_err(&pdev->dev, "cannot register net device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003930 goto err_out_free_netdev;
3931 }
3932
Michal Schmidt415e69e2009-10-01 08:13:23 +00003933 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003934 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003935 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003936 dev->name, pdev->irq);
3937 goto err_out_unregister;
3938 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003939 skge_show_addr(dev);
3940
Mike McCormackf1914222009-09-23 03:50:36 +00003941 if (hw->ports > 1) {
3942 dev1 = skge_devinit(hw, 1, using_dac);
3943 if (dev1 && register_netdev(dev1) == 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003944 skge_show_addr(dev1);
3945 else {
3946 /* Failure to register second port need not be fatal */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003947 dev_warn(&pdev->dev, "register of second port failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003948 hw->dev[1] = NULL;
Mike McCormackf1914222009-09-23 03:50:36 +00003949 hw->ports = 1;
3950 if (dev1)
3951 free_netdev(dev1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003952 }
3953 }
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003954 pci_set_drvdata(pdev, hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003955
3956 return 0;
3957
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003958err_out_unregister:
3959 unregister_netdev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003960err_out_free_netdev:
3961 free_netdev(dev);
3962err_out_led_off:
3963 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003964err_out_iounmap:
3965 iounmap(hw->regs);
3966err_out_free_hw:
3967 kfree(hw);
3968err_out_free_regions:
3969 pci_release_regions(pdev);
3970err_out_disable_pdev:
3971 pci_disable_device(pdev);
3972 pci_set_drvdata(pdev, NULL);
3973err_out:
3974 return err;
3975}
3976
3977static void __devexit skge_remove(struct pci_dev *pdev)
3978{
3979 struct skge_hw *hw = pci_get_drvdata(pdev);
3980 struct net_device *dev0, *dev1;
3981
Stephen Hemminger95566062005-06-27 11:33:02 -07003982 if (!hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003983 return;
3984
Joe Perches67777f92010-02-17 15:01:58 +00003985 dev1 = hw->dev[1];
3986 if (dev1)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003987 unregister_netdev(dev1);
3988 dev0 = hw->dev[0];
3989 unregister_netdev(dev0);
3990
Stephen Hemminger9cbe3302007-03-16 14:01:28 -07003991 tasklet_disable(&hw->phy_task);
3992
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003993 spin_lock_irq(&hw->hw_lock);
3994 hw->intr_mask = 0;
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003995 skge_write32(hw, B0_IMSK, 0);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003996 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003997 spin_unlock_irq(&hw->hw_lock);
3998
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003999 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004000 skge_write8(hw, B0_CTST, CS_RST_SET);
4001
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004002 free_irq(pdev->irq, hw);
4003 pci_release_regions(pdev);
4004 pci_disable_device(pdev);
4005 if (dev1)
4006 free_netdev(dev1);
4007 free_netdev(dev0);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07004008
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004009 iounmap(hw->regs);
4010 kfree(hw);
4011 pci_set_drvdata(pdev, NULL);
4012}
4013
4014#ifdef CONFIG_PM
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004015static int skge_suspend(struct device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004016{
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004017 struct pci_dev *pdev = to_pci_dev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004018 struct skge_hw *hw = pci_get_drvdata(pdev);
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004019 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004020
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004021 if (!hw)
4022 return 0;
4023
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004024 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004025 struct net_device *dev = hw->dev[i];
Stephen Hemmingera504e642007-02-02 08:22:53 -08004026 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004027
Stephen Hemmingera504e642007-02-02 08:22:53 -08004028 if (netif_running(dev))
4029 skge_down(dev);
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004030
Stephen Hemmingera504e642007-02-02 08:22:53 -08004031 if (skge->wol)
4032 skge_wol_init(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004033 }
4034
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004035 skge_write32(hw, B0_IMSK, 0);
Rafael J. Wysocki5177b322008-10-29 14:22:14 -07004036
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004037 return 0;
4038}
4039
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004040static int skge_resume(struct device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004041{
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004042 struct pci_dev *pdev = to_pci_dev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004043 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004044 int i, err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004045
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004046 if (!hw)
4047 return 0;
4048
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004049 err = skge_reset(hw);
4050 if (err)
4051 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004052
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004053 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004054 struct net_device *dev = hw->dev[i];
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004055
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004056 if (netif_running(dev)) {
4057 err = skge_up(dev);
4058
4059 if (err) {
Joe Perchesf15063c2010-02-17 15:01:57 +00004060 netdev_err(dev, "could not up: %d\n", err);
Stephen Hemmingeredd702e2005-12-15 12:18:00 -08004061 dev_close(dev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004062 goto out;
4063 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004064 }
4065 }
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07004066out:
4067 return err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004068}
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004069
4070static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4071#define SKGE_PM_OPS (&skge_pm_ops)
4072
4073#else
4074
4075#define SKGE_PM_OPS NULL
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004076#endif
4077
Stephen Hemminger692412b2007-04-09 15:32:45 -07004078static void skge_shutdown(struct pci_dev *pdev)
4079{
4080 struct skge_hw *hw = pci_get_drvdata(pdev);
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004081 int i;
Stephen Hemminger692412b2007-04-09 15:32:45 -07004082
Stephen Hemmingere3b7df12007-05-11 11:21:45 -07004083 if (!hw)
4084 return;
4085
Stephen Hemminger692412b2007-04-09 15:32:45 -07004086 for (i = 0; i < hw->ports; i++) {
4087 struct net_device *dev = hw->dev[i];
4088 struct skge_port *skge = netdev_priv(dev);
4089
4090 if (skge->wol)
4091 skge_wol_init(skge);
Stephen Hemminger692412b2007-04-09 15:32:45 -07004092 }
4093
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004094 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
Stephen Hemminger692412b2007-04-09 15:32:45 -07004095 pci_set_power_state(pdev, PCI_D3hot);
Stephen Hemminger692412b2007-04-09 15:32:45 -07004096}
4097
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004098static struct pci_driver skge_driver = {
4099 .name = DRV_NAME,
4100 .id_table = skge_id_table,
4101 .probe = skge_probe,
4102 .remove = __devexit_p(skge_remove),
Stephen Hemminger692412b2007-04-09 15:32:45 -07004103 .shutdown = skge_shutdown,
stephen hemminger7dbf6ac2010-12-30 08:52:29 +00004104 .driver.pm = SKGE_PM_OPS,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004105};
4106
Stanislaw Gruszka392bd0c2010-10-05 15:11:40 -07004107static struct dmi_system_id skge_32bit_dma_boards[] = {
4108 {
4109 .ident = "Gigabyte nForce boards",
4110 .matches = {
4111 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4112 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4113 },
4114 },
4115 {}
4116};
4117
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004118static int __init skge_init_module(void)
4119{
Stanislaw Gruszka392bd0c2010-10-05 15:11:40 -07004120 if (dmi_check_system(skge_32bit_dma_boards))
4121 only_32bit_dma = 1;
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07004122 skge_debug_init();
Jeff Garzik29917622006-08-19 17:48:59 -04004123 return pci_register_driver(&skge_driver);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004124}
4125
4126static void __exit skge_cleanup_module(void)
4127{
4128 pci_unregister_driver(&skge_driver);
Stephen Hemminger678aa1f2007-10-16 12:15:54 -07004129 skge_debug_cleanup();
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04004130}
4131
4132module_init(skge_init_module);
4133module_exit(skge_cleanup_module);