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Catalin Marinas382266a2007-02-05 14:48:19 +01001/*
2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/init.h>
Catalin Marinas07620972007-07-20 11:42:40 +010020#include <linux/spinlock.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010022
23#include <asm/cacheflush.h>
Catalin Marinas382266a2007-02-05 14:48:19 +010024#include <asm/hardware/cache-l2x0.h>
25
26#define CACHE_LINE_SIZE 32
27
28static void __iomem *l2x0_base;
Catalin Marinas07620972007-07-20 11:42:40 +010029static DEFINE_SPINLOCK(l2x0_lock);
Catalin Marinas382266a2007-02-05 14:48:19 +010030
Russell King3d107432009-11-19 11:41:09 +000031static inline void cache_wait(void __iomem *reg, unsigned long mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010032{
Catalin Marinas382266a2007-02-05 14:48:19 +010033 /* wait for the operation to complete */
Russell King3d107432009-11-19 11:41:09 +000034 while (readl(reg) & mask)
Catalin Marinas382266a2007-02-05 14:48:19 +010035 ;
Catalin Marinas382266a2007-02-05 14:48:19 +010036}
37
38static inline void cache_sync(void)
39{
Russell King3d107432009-11-19 11:41:09 +000040 void __iomem *base = l2x0_base;
41 writel(0, base + L2X0_CACHE_SYNC);
42 cache_wait(base + L2X0_CACHE_SYNC, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +010043}
44
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010045static inline void l2x0_clean_line(unsigned long addr)
46{
47 void __iomem *base = l2x0_base;
48 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
49 writel(addr, base + L2X0_CLEAN_LINE_PA);
50}
51
52static inline void l2x0_inv_line(unsigned long addr)
53{
54 void __iomem *base = l2x0_base;
55 cache_wait(base + L2X0_INV_LINE_PA, 1);
56 writel(addr, base + L2X0_INV_LINE_PA);
57}
58
Santosh Shilimkar9e655822010-02-04 19:42:42 +010059#ifdef CONFIG_PL310_ERRATA_588369
60static void debug_writel(unsigned long val)
61{
62 extern void omap_smc1(u32 fn, u32 arg);
63
64 /*
65 * Texas Instrument secure monitor api to modify the
66 * PL310 Debug Control Register.
67 */
68 omap_smc1(0x100, val);
69}
70
71static inline void l2x0_flush_line(unsigned long addr)
72{
73 void __iomem *base = l2x0_base;
74
75 /* Clean by PA followed by Invalidate by PA */
76 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
77 writel(addr, base + L2X0_CLEAN_LINE_PA);
78 cache_wait(base + L2X0_INV_LINE_PA, 1);
79 writel(addr, base + L2X0_INV_LINE_PA);
80}
81#else
82
83/* Optimised out for non-errata case */
84static inline void debug_writel(unsigned long val)
85{
86}
87
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010088static inline void l2x0_flush_line(unsigned long addr)
89{
90 void __iomem *base = l2x0_base;
91 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
92 writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
93}
Santosh Shilimkar9e655822010-02-04 19:42:42 +010094#endif
Santosh Shilimkar424d6b12010-02-04 19:35:06 +010095
Catalin Marinas23107c52010-03-24 16:48:53 +010096static void l2x0_cache_sync(void)
97{
98 unsigned long flags;
99
100 spin_lock_irqsave(&l2x0_lock, flags);
101 cache_sync();
102 spin_unlock_irqrestore(&l2x0_lock, flags);
103}
104
Catalin Marinas382266a2007-02-05 14:48:19 +0100105static inline void l2x0_inv_all(void)
106{
Russell King0eb948d2009-11-19 11:12:15 +0000107 unsigned long flags;
108
Catalin Marinas382266a2007-02-05 14:48:19 +0100109 /* invalidate all ways */
Russell King0eb948d2009-11-19 11:12:15 +0000110 spin_lock_irqsave(&l2x0_lock, flags);
Russell King3d107432009-11-19 11:41:09 +0000111 writel(0xff, l2x0_base + L2X0_INV_WAY);
112 cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
Catalin Marinas382266a2007-02-05 14:48:19 +0100113 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000114 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100115}
116
117static void l2x0_inv_range(unsigned long start, unsigned long end)
118{
Russell King3d107432009-11-19 11:41:09 +0000119 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000120 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100121
Russell King0eb948d2009-11-19 11:12:15 +0000122 spin_lock_irqsave(&l2x0_lock, flags);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100123 if (start & (CACHE_LINE_SIZE - 1)) {
124 start &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100125 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100126 l2x0_flush_line(start);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100127 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100128 start += CACHE_LINE_SIZE;
129 }
130
131 if (end & (CACHE_LINE_SIZE - 1)) {
132 end &= ~(CACHE_LINE_SIZE - 1);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100133 debug_writel(0x03);
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100134 l2x0_flush_line(end);
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100135 debug_writel(0x00);
Rui Sousa4f6627a2007-09-15 00:56:19 +0100136 }
137
Russell King0eb948d2009-11-19 11:12:15 +0000138 while (start < end) {
139 unsigned long blk_end = start + min(end - start, 4096UL);
140
141 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100142 l2x0_inv_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000143 start += CACHE_LINE_SIZE;
144 }
145
146 if (blk_end < end) {
147 spin_unlock_irqrestore(&l2x0_lock, flags);
148 spin_lock_irqsave(&l2x0_lock, flags);
149 }
150 }
Russell King3d107432009-11-19 11:41:09 +0000151 cache_wait(base + L2X0_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100152 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000153 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100154}
155
156static void l2x0_clean_range(unsigned long start, unsigned long end)
157{
Russell King3d107432009-11-19 11:41:09 +0000158 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000159 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100160
Russell King0eb948d2009-11-19 11:12:15 +0000161 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100162 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000163 while (start < end) {
164 unsigned long blk_end = start + min(end - start, 4096UL);
165
166 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100167 l2x0_clean_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000168 start += CACHE_LINE_SIZE;
169 }
170
171 if (blk_end < end) {
172 spin_unlock_irqrestore(&l2x0_lock, flags);
173 spin_lock_irqsave(&l2x0_lock, flags);
174 }
175 }
Russell King3d107432009-11-19 11:41:09 +0000176 cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100177 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000178 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100179}
180
181static void l2x0_flush_range(unsigned long start, unsigned long end)
182{
Russell King3d107432009-11-19 11:41:09 +0000183 void __iomem *base = l2x0_base;
Russell King0eb948d2009-11-19 11:12:15 +0000184 unsigned long flags;
Catalin Marinas382266a2007-02-05 14:48:19 +0100185
Russell King0eb948d2009-11-19 11:12:15 +0000186 spin_lock_irqsave(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100187 start &= ~(CACHE_LINE_SIZE - 1);
Russell King0eb948d2009-11-19 11:12:15 +0000188 while (start < end) {
189 unsigned long blk_end = start + min(end - start, 4096UL);
190
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100191 debug_writel(0x03);
Russell King0eb948d2009-11-19 11:12:15 +0000192 while (start < blk_end) {
Santosh Shilimkar424d6b12010-02-04 19:35:06 +0100193 l2x0_flush_line(start);
Russell King0eb948d2009-11-19 11:12:15 +0000194 start += CACHE_LINE_SIZE;
195 }
Santosh Shilimkar9e655822010-02-04 19:42:42 +0100196 debug_writel(0x00);
Russell King0eb948d2009-11-19 11:12:15 +0000197
198 if (blk_end < end) {
199 spin_unlock_irqrestore(&l2x0_lock, flags);
200 spin_lock_irqsave(&l2x0_lock, flags);
201 }
202 }
Russell King3d107432009-11-19 11:41:09 +0000203 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
Catalin Marinas382266a2007-02-05 14:48:19 +0100204 cache_sync();
Russell King0eb948d2009-11-19 11:12:15 +0000205 spin_unlock_irqrestore(&l2x0_lock, flags);
Catalin Marinas382266a2007-02-05 14:48:19 +0100206}
207
208void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
209{
210 __u32 aux;
211
212 l2x0_base = base;
213
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100214 /*
215 * Check if l2x0 controller is already enabled.
216 * If you are booting from non-secure mode
217 * accessing the below registers will fault.
218 */
219 if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
Catalin Marinas382266a2007-02-05 14:48:19 +0100220
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100221 /* l2x0 controller is disabled */
Catalin Marinas382266a2007-02-05 14:48:19 +0100222
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100223 aux = readl(l2x0_base + L2X0_AUX_CTRL);
224 aux &= aux_mask;
225 aux |= aux_val;
226 writel(aux, l2x0_base + L2X0_AUX_CTRL);
Catalin Marinas382266a2007-02-05 14:48:19 +0100227
Srinidhi Kasagar48371cd2009-12-02 06:18:03 +0100228 l2x0_inv_all();
229
230 /* enable L2X0 */
231 writel(1, l2x0_base + L2X0_CTRL);
232 }
Catalin Marinas382266a2007-02-05 14:48:19 +0100233
234 outer_cache.inv_range = l2x0_inv_range;
235 outer_cache.clean_range = l2x0_clean_range;
236 outer_cache.flush_range = l2x0_flush_range;
Catalin Marinas23107c52010-03-24 16:48:53 +0100237 outer_cache.sync = l2x0_cache_sync;
Catalin Marinas382266a2007-02-05 14:48:19 +0100238
239 printk(KERN_INFO "L2X0 cache controller enabled\n");
240}