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gerrit-public.fairphone.software / kernel / msm-4.9 / ce01b14ecf19a18cd95e698f915f5ea582086c21 / . / arch / arm / boot / dts / r8a7792.dtsi
blob: 228860d9464ac006660a96f6516428be5b3342b2 [file] [log] [blame]
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
Sergei Shtylyov8fd763c2016-06-21 01:31:01 +0300[diff] [blame]24 enable-method = "renesas,apmu";
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
30 clock-frequency = <1000000000>;
31 clocks = <&cpg_clocks R8A7792_CLK_Z>;
32 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
33 next-level-cache = <&L2_CA15>;
34 };
35
Sergei Shtylyov8fd763c2016-06-21 01:31:01 +0300[diff] [blame]36 cpu1: cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <1>;
40 clock-frequency = <1000000000>;
41 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
42 next-level-cache = <&L2_CA15>;
43 };
44
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]45 L2_CA15: cache-controller@0 {
46 compatible = "cache";
47 reg = <0>;
48 cache-unified;
49 cache-level = <2>;
50 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
51 };
52 };
53
54 soc {
55 compatible = "simple-bus";
56 interrupt-parent = <&gic>;
57
58 #address-cells = <2>;
59 #size-cells = <2>;
60 ranges;
61
Sergei Shtylyov8fd763c2016-06-21 01:31:01 +0300[diff] [blame]62 apmu@e6152000 {
63 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
64 reg = <0 0xe6152000 0 0x188>;
65 cpus = <&cpu0 &cpu1>;
66 };
67
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]68 gic: interrupt-controller@f1001000 {
69 compatible = "arm,gic-400";
70 #interrupt-cells = <3>;
71 interrupt-controller;
72 reg = <0 0xf1001000 0 0x1000>,
73 <0 0xf1002000 0 0x1000>,
74 <0 0xf1004000 0 0x2000>,
75 <0 0xf1006000 0 0x2000>;
76 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
77 IRQ_TYPE_LEVEL_HIGH)>;
78 };
79
Sergei Shtylyov56efdbe52016-06-13 00:12:06 +0300[diff] [blame]80 irqc: interrupt-controller@e61c0000 {
81 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
82 #interrupt-cells = <2>;
83 interrupt-controller;
84 reg = <0 0xe61c0000 0 0x200>;
85 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
90 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
91 };
92
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]93 timer {
94 compatible = "arm,armv7-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
98 IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
100 IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
102 IRQ_TYPE_LEVEL_LOW)>;
103 };
104
105 sysc: system-controller@e6180000 {
106 compatible = "renesas,r8a7792-sysc";
107 reg = <0 0xe6180000 0 0x0200>;
108 #power-domain-cells = <1>;
109 };
110
Sergei Shtylyov02183a52016-07-15 00:00:05 +0300[diff] [blame]111 pfc: pin-controller@e6060000 {
112 compatible = "renesas,pfc-r8a7792";
113 reg = <0 0xe6060000 0 0x144>;
114 };
115
Sergei Shtylyov63359c22016-07-06 01:02:20 +0300[diff] [blame]116 gpio0: gpio@e6050000 {
117 compatible = "renesas,gpio-r8a7792",
118 "renesas,gpio-rcar";
119 reg = <0 0xe6050000 0 0x50>;
120 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 gpio-ranges = <&pfc 0 0 29>;
124 #interrupt-cells = <2>;
125 interrupt-controller;
126 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
127 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
128 };
129
130 gpio1: gpio@e6051000 {
131 compatible = "renesas,gpio-r8a7792",
132 "renesas,gpio-rcar";
133 reg = <0 0xe6051000 0 0x50>;
134 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
135 #gpio-cells = <2>;
136 gpio-controller;
137 gpio-ranges = <&pfc 0 32 23>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
140 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
141 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
142 };
143
144 gpio2: gpio@e6052000 {
145 compatible = "renesas,gpio-r8a7792",
146 "renesas,gpio-rcar";
147 reg = <0 0xe6052000 0 0x50>;
148 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
149 #gpio-cells = <2>;
150 gpio-controller;
151 gpio-ranges = <&pfc 0 64 32>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
155 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
156 };
157
158 gpio3: gpio@e6053000 {
159 compatible = "renesas,gpio-r8a7792",
160 "renesas,gpio-rcar";
161 reg = <0 0xe6053000 0 0x50>;
162 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
163 #gpio-cells = <2>;
164 gpio-controller;
165 gpio-ranges = <&pfc 0 96 28>;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
169 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
170 };
171
172 gpio4: gpio@e6054000 {
173 compatible = "renesas,gpio-r8a7792",
174 "renesas,gpio-rcar";
175 reg = <0 0xe6054000 0 0x50>;
176 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
177 #gpio-cells = <2>;
178 gpio-controller;
179 gpio-ranges = <&pfc 0 128 17>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
183 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
184 };
185
186 gpio5: gpio@e6055000 {
187 compatible = "renesas,gpio-r8a7792",
188 "renesas,gpio-rcar";
189 reg = <0 0xe6055000 0 0x50>;
190 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
191 #gpio-cells = <2>;
192 gpio-controller;
193 gpio-ranges = <&pfc 0 160 17>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
197 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
198 };
199
200 gpio6: gpio@e6055100 {
201 compatible = "renesas,gpio-r8a7792",
202 "renesas,gpio-rcar";
203 reg = <0 0xe6055100 0 0x50>;
204 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
205 #gpio-cells = <2>;
206 gpio-controller;
207 gpio-ranges = <&pfc 0 192 17>;
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
211 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
212 };
213
214 gpio7: gpio@e6055200 {
215 compatible = "renesas,gpio-r8a7792",
216 "renesas,gpio-rcar";
217 reg = <0 0xe6055200 0 0x50>;
218 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 224 17>;
222 #interrupt-cells = <2>;
223 interrupt-controller;
224 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
225 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
226 };
227
228 gpio8: gpio@e6055300 {
229 compatible = "renesas,gpio-r8a7792",
230 "renesas,gpio-rcar";
231 reg = <0 0xe6055300 0 0x50>;
232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 256 17>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
239 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
240 };
241
242 gpio9: gpio@e6055400 {
243 compatible = "renesas,gpio-r8a7792",
244 "renesas,gpio-rcar";
245 reg = <0 0xe6055400 0 0x50>;
246 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>;
248 gpio-controller;
249 gpio-ranges = <&pfc 0 288 17>;
250 #interrupt-cells = <2>;
251 interrupt-controller;
252 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
253 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
254 };
255
256 gpio10: gpio@e6055500 {
257 compatible = "renesas,gpio-r8a7792",
258 "renesas,gpio-rcar";
259 reg = <0 0xe6055500 0 0x50>;
260 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 320 32>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
268 };
269
270 gpio11: gpio@e6055600 {
271 compatible = "renesas,gpio-r8a7792",
272 "renesas,gpio-rcar";
273 reg = <0 0xe6055600 0 0x50>;
274 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
275 #gpio-cells = <2>;
276 gpio-controller;
277 gpio-ranges = <&pfc 0 352 30>;
278 #interrupt-cells = <2>;
279 interrupt-controller;
280 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
281 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
282 };
283
Sergei Shtylyovfdf8ec02016-06-13 00:08:18 +0300[diff] [blame]284 dmac0: dma-controller@e6700000 {
285 compatible = "renesas,dmac-r8a7792",
286 "renesas,rcar-dmac";
287 reg = <0 0xe6700000 0 0x20000>;
288 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
290 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
291 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
292 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
293 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
294 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
295 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
296 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
297 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
298 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
304 interrupt-names = "error",
305 "ch0", "ch1", "ch2", "ch3",
306 "ch4", "ch5", "ch6", "ch7",
307 "ch8", "ch9", "ch10", "ch11",
308 "ch12", "ch13", "ch14";
309 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
310 clock-names = "fck";
311 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
315
316 dmac1: dma-controller@e6720000 {
317 compatible = "renesas,dmac-r8a7792",
318 "renesas,rcar-dmac";
319 reg = <0 0xe6720000 0 0x20000>;
320 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
335 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "error",
337 "ch0", "ch1", "ch2", "ch3",
338 "ch4", "ch5", "ch6", "ch7",
339 "ch8", "ch9", "ch10", "ch11",
340 "ch12", "ch13", "ch14";
341 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
342 clock-names = "fck";
343 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
344 #dma-cells = <1>;
345 dma-channels = <15>;
346 };
347
Sergei Shtylyove66796b2016-06-13 00:09:42 +0300[diff] [blame]348 scif0: serial@e6e60000 {
349 compatible = "renesas,scif-r8a7792",
350 "renesas,rcar-gen2-scif", "renesas,scif";
351 reg = <0 0xe6e60000 0 64>;
352 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
354 <&scif_clk>;
355 clock-names = "fck", "brg_int", "scif_clk";
356 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
357 <&dmac1 0x29>, <&dmac1 0x2a>;
358 dma-names = "tx", "rx", "tx", "rx";
359 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
360 status = "disabled";
361 };
362
363 scif1: serial@e6e68000 {
364 compatible = "renesas,scif-r8a7792",
365 "renesas,rcar-gen2-scif", "renesas,scif";
366 reg = <0 0xe6e68000 0 64>;
367 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
369 <&scif_clk>;
370 clock-names = "fck", "brg_int", "scif_clk";
371 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
372 <&dmac1 0x2d>, <&dmac1 0x2e>;
373 dma-names = "tx", "rx", "tx", "rx";
374 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
375 status = "disabled";
376 };
377
378 scif2: serial@e6e58000 {
379 compatible = "renesas,scif-r8a7792",
380 "renesas,rcar-gen2-scif", "renesas,scif";
381 reg = <0 0xe6e58000 0 64>;
382 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
384 <&scif_clk>;
385 clock-names = "fck", "brg_int", "scif_clk";
386 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
387 <&dmac1 0x2b>, <&dmac1 0x2c>;
388 dma-names = "tx", "rx", "tx", "rx";
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
390 status = "disabled";
391 };
392
393 scif3: serial@e6ea8000 {
394 compatible = "renesas,scif-r8a7792",
395 "renesas,rcar-gen2-scif", "renesas,scif";
396 reg = <0 0xe6ea8000 0 64>;
397 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
399 <&scif_clk>;
400 clock-names = "fck", "brg_int", "scif_clk";
401 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
402 <&dmac1 0x2f>, <&dmac1 0x30>;
403 dma-names = "tx", "rx", "tx", "rx";
404 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
405 status = "disabled";
406 };
407
408 hscif0: serial@e62c0000 {
409 compatible = "renesas,hscif-r8a7792",
410 "renesas,rcar-gen2-hscif", "renesas,hscif";
411 reg = <0 0xe62c0000 0 96>;
412 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
414 <&scif_clk>;
415 clock-names = "fck", "brg_int", "scif_clk";
416 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
417 <&dmac1 0x39>, <&dmac1 0x3a>;
418 dma-names = "tx", "rx", "tx", "rx";
419 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
420 status = "disabled";
421 };
422
423 hscif1: serial@e62c8000 {
424 compatible = "renesas,hscif-r8a7792",
425 "renesas,rcar-gen2-hscif", "renesas,hscif";
426 reg = <0 0xe62c8000 0 96>;
427 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
429 <&scif_clk>;
430 clock-names = "fck", "brg_int", "scif_clk";
431 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
432 <&dmac1 0x4d>, <&dmac1 0x4e>;
433 dma-names = "tx", "rx", "tx", "rx";
434 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
435 status = "disabled";
436 };
437
Sergei Shtylyovce01b142016-07-23 21:11:26 +0300[diff] [blame^]438 sdhi0: sd@ee100000 {
439 compatible = "renesas,sdhi-r8a7792";
440 reg = <0 0xee100000 0 0x328>;
441 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
442 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
443 <&dmac1 0xcd>, <&dmac1 0xce>;
444 dma-names = "tx", "rx", "tx", "rx";
445 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
446 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
447 status = "disabled";
448 };
449
Sergei Shtylyov3e1839e2016-06-17 01:03:53 +0300[diff] [blame]450 jpu: jpeg-codec@fe980000 {
451 compatible = "renesas,jpu-r8a7792",
452 "renesas,rcar-gen2-jpu";
453 reg = <0 0xfe980000 0 0x10300>;
454 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
456 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
457 };
458
Sergei Shtylyovb12dcdc2016-07-05 00:23:30 +0300[diff] [blame]459 avb: ethernet@e6800000 {
460 compatible = "renesas,etheravb-r8a7792",
461 "renesas,etheravb-rcar-gen2";
462 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
463 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
465 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
Sergei Shtylyovf947c022016-07-14 23:20:35 +0300[diff] [blame]471 can0: can@e6e80000 {
472 compatible = "renesas,can-r8a7792",
473 "renesas,rcar-gen2-can";
474 reg = <0 0xe6e80000 0 0x1000>;
475 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
477 <&rcan_clk>, <&can_clk>;
478 clock-names = "clkp1", "clkp2", "can_clk";
479 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
480 status = "disabled";
481 };
482
483 can1: can@e6e88000 {
484 compatible = "renesas,can-r8a7792",
485 "renesas,rcar-gen2-can";
486 reg = <0 0xe6e88000 0 0x1000>;
487 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
489 <&rcan_clk>, <&can_clk>;
490 clock-names = "clkp1", "clkp2", "can_clk";
491 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
492 status = "disabled";
493 };
494
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]495 /* Special CPG clocks */
496 cpg_clocks: cpg_clocks@e6150000 {
497 compatible = "renesas,r8a7792-cpg-clocks",
498 "renesas,rcar-gen2-cpg-clocks";
499 reg = <0 0xe6150000 0 0x1000>;
500 clocks = <&extal_clk>;
501 #clock-cells = <1>;
502 clock-output-names = "main", "pll0", "pll1", "pll3",
Sergei Shtylyove0c3f922016-07-12 00:52:43 +0300[diff] [blame]503 "lb", "qspi", "z";
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]504 #power-domain-cells = <0>;
505 };
506
507 /* Fixed factor clocks */
Sergei Shtylyov4b9b7b32016-07-12 00:51:58 +0300[diff] [blame]508 pll1_div2_clk: pll1_div2 {
509 compatible = "fixed-factor-clock";
510 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
511 #clock-cells = <0>;
512 clock-div = <2>;
513 clock-mult = <1>;
514 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]515 zs_clk: zs {
516 compatible = "fixed-factor-clock";
517 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
518 #clock-cells = <0>;
519 clock-div = <6>;
520 clock-mult = <1>;
521 };
Sergei Shtylyov08cafff2016-07-05 00:22:38 +0300[diff] [blame]522 hp_clk: hp {
523 compatible = "fixed-factor-clock";
524 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
525 #clock-cells = <0>;
526 clock-div = <12>;
527 clock-mult = <1>;
528 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]529 p_clk: p {
530 compatible = "fixed-factor-clock";
531 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
532 #clock-cells = <0>;
533 clock-div = <24>;
534 clock-mult = <1>;
535 };
536 cp_clk: cp {
537 compatible = "fixed-factor-clock";
538 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
539 #clock-cells = <0>;
540 clock-div = <48>;
541 clock-mult = <1>;
542 };
Sergei Shtylyoveebc8e22016-06-17 01:02:48 +0300[diff] [blame]543 m2_clk: m2 {
544 compatible = "fixed-factor-clock";
545 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
546 #clock-cells = <0>;
547 clock-div = <8>;
548 clock-mult = <1>;
549 };
Sergei Shtylyovfe683922016-07-23 21:10:31 +0300[diff] [blame]550 sd_clk: sd {
551 compatible = "fixed-factor-clock";
552 clocks = <&pll1_div2_clk>;
553 #clock-cells = <0>;
554 clock-div = <8>;
555 clock-mult = <1>;
556 };
Sergei Shtylyov47db0512016-07-14 23:19:44 +0300[diff] [blame]557 rcan_clk: rcan {
558 compatible = "fixed-factor-clock";
559 clocks = <&pll1_div2_clk>;
560 #clock-cells = <0>;
561 clock-div = <49>;
562 clock-mult = <1>;
563 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]564
565 /* Gate clocks */
Sergei Shtylyoveebc8e22016-06-17 01:02:48 +0300[diff] [blame]566 mstp1_clks: mstp1_clks@e6150134 {
567 compatible = "renesas,r8a7792-mstp-clocks",
568 "renesas,cpg-mstp-clocks";
569 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
570 clocks = <&m2_clk>;
571 #clock-cells = <1>;
572 clock-indices = <R8A7792_CLK_JPU>;
573 clock-output-names = "jpu";
574 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]575 mstp2_clks: mstp2_clks@e6150138 {
576 compatible = "renesas,r8a7792-mstp-clocks",
577 "renesas,cpg-mstp-clocks";
578 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
579 clocks = <&zs_clk>, <&zs_clk>;
580 #clock-cells = <1>;
581 clock-indices = <
582 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
583 >;
584 clock-output-names = "sys-dmac1", "sys-dmac0";
585 };
Sergei Shtylyovfe683922016-07-23 21:10:31 +0300[diff] [blame]586 mstp3_clks: mstp3_clks@e615013c {
587 compatible = "renesas,r8a7792-mstp-clocks",
588 "renesas,cpg-mstp-clocks";
589 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
590 clocks = <&sd_clk>;
591 #clock-cells = <1>;
592 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
593 clock-output-names = "sdhi0";
594 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]595 mstp4_clks: mstp4_clks@e6150140 {
596 compatible = "renesas,r8a7792-mstp-clocks",
597 "renesas,cpg-mstp-clocks";
598 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
599 clocks = <&cp_clk>;
600 #clock-cells = <1>;
601 clock-indices = <R8A7792_CLK_IRQC>;
602 clock-output-names = "irqc";
603 };
604 mstp7_clks: mstp7_clks@e615014c {
605 compatible = "renesas,r8a7792-mstp-clocks",
606 "renesas,cpg-mstp-clocks";
607 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
608 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
609 <&p_clk>, <&p_clk>;
610 #clock-cells = <1>;
611 clock-indices = <
612 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
613 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
614 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
615 >;
616 clock-output-names = "hscif1", "hscif0", "scif3",
617 "scif2", "scif1", "scif0";
618 };
Sergei Shtylyov08cafff2016-07-05 00:22:38 +0300[diff] [blame]619 mstp8_clks: mstp8_clks@e6150990 {
620 compatible = "renesas,r8a7792-mstp-clocks",
621 "renesas,cpg-mstp-clocks";
622 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
623 clocks = <&hp_clk>;
624 #clock-cells = <1>;
625 clock-indices = <R8A7792_CLK_ETHERAVB>;
626 clock-output-names = "etheravb";
627 };
Sergei Shtylyov4e2b4f62016-07-06 01:01:22 +0300[diff] [blame]628 mstp9_clks: mstp9_clks@e6150994 {
629 compatible = "renesas,r8a7792-mstp-clocks",
630 "renesas,cpg-mstp-clocks";
631 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
632 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
633 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
Sergei Shtylyov47db0512016-07-14 23:19:44 +0300[diff] [blame]634 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
635 <&cp_clk>, <&cp_clk>;
Sergei Shtylyov4e2b4f62016-07-06 01:01:22 +0300[diff] [blame]636 #clock-cells = <1>;
637 clock-indices = <
638 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
639 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
640 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
641 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
642 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
Sergei Shtylyov47db0512016-07-14 23:19:44 +0300[diff] [blame]643 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
Sergei Shtylyov4e2b4f62016-07-06 01:01:22 +0300[diff] [blame]644 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
645 >;
646 clock-output-names =
647 "gpio7", "gpio6", "gpio5", "gpio4",
648 "gpio3", "gpio2", "gpio1", "gpio0",
Sergei Shtylyov47db0512016-07-14 23:19:44 +0300[diff] [blame]649 "gpio11", "gpio10", "can1", "can0",
650 "gpio9", "gpio8";
Sergei Shtylyov4e2b4f62016-07-06 01:01:22 +0300[diff] [blame]651 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]652 };
653
654 /* External root clock */
655 extal_clk: extal {
656 compatible = "fixed-clock";
657 #clock-cells = <0>;
658 /* This value must be overridden by the board. */
659 clock-frequency = <0>;
660 };
661
662 /* External SCIF clock */
663 scif_clk: scif {
664 compatible = "fixed-clock";
665 #clock-cells = <0>;
666 /* This value must be overridden by the board. */
667 clock-frequency = <0>;
668 };
Sergei Shtylyov47db0512016-07-14 23:19:44 +0300[diff] [blame]669
670 /* External CAN clock */
671 can_clk: can {
672 compatible = "fixed-clock";
673 #clock-cells = <0>;
674 /* This value must be overridden by the board. */
675 clock-frequency = <0>;
676 };
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]677};