Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Synopsys Designware I2C adapter driver (master only). |
| 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
| 28 | #include <linux/kernel.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/i2c.h> |
| 32 | #include <linux/clk.h> |
| 33 | #include <linux/errno.h> |
| 34 | #include <linux/sched.h> |
| 35 | #include <linux/err.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/platform_device.h> |
| 38 | #include <linux/io.h> |
| 39 | |
| 40 | /* |
| 41 | * Registers offset |
| 42 | */ |
| 43 | #define DW_IC_CON 0x0 |
| 44 | #define DW_IC_TAR 0x4 |
| 45 | #define DW_IC_DATA_CMD 0x10 |
| 46 | #define DW_IC_SS_SCL_HCNT 0x14 |
| 47 | #define DW_IC_SS_SCL_LCNT 0x18 |
| 48 | #define DW_IC_FS_SCL_HCNT 0x1c |
| 49 | #define DW_IC_FS_SCL_LCNT 0x20 |
| 50 | #define DW_IC_INTR_STAT 0x2c |
| 51 | #define DW_IC_INTR_MASK 0x30 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 53 | #define DW_IC_RX_TL 0x38 |
| 54 | #define DW_IC_TX_TL 0x3c |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 55 | #define DW_IC_CLR_INTR 0x40 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 56 | #define DW_IC_CLR_RX_UNDER 0x44 |
| 57 | #define DW_IC_CLR_RX_OVER 0x48 |
| 58 | #define DW_IC_CLR_TX_OVER 0x4c |
| 59 | #define DW_IC_CLR_RD_REQ 0x50 |
| 60 | #define DW_IC_CLR_TX_ABRT 0x54 |
| 61 | #define DW_IC_CLR_RX_DONE 0x58 |
| 62 | #define DW_IC_CLR_ACTIVITY 0x5c |
| 63 | #define DW_IC_CLR_STOP_DET 0x60 |
| 64 | #define DW_IC_CLR_START_DET 0x64 |
| 65 | #define DW_IC_CLR_GEN_CALL 0x68 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 66 | #define DW_IC_ENABLE 0x6c |
| 67 | #define DW_IC_STATUS 0x70 |
| 68 | #define DW_IC_TXFLR 0x74 |
| 69 | #define DW_IC_RXFLR 0x78 |
| 70 | #define DW_IC_COMP_PARAM_1 0xf4 |
| 71 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
| 72 | |
| 73 | #define DW_IC_CON_MASTER 0x1 |
| 74 | #define DW_IC_CON_SPEED_STD 0x2 |
| 75 | #define DW_IC_CON_SPEED_FAST 0x4 |
| 76 | #define DW_IC_CON_10BITADDR_MASTER 0x10 |
| 77 | #define DW_IC_CON_RESTART_EN 0x20 |
| 78 | #define DW_IC_CON_SLAVE_DISABLE 0x40 |
| 79 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 80 | #define DW_IC_INTR_RX_UNDER 0x001 |
| 81 | #define DW_IC_INTR_RX_OVER 0x002 |
| 82 | #define DW_IC_INTR_RX_FULL 0x004 |
| 83 | #define DW_IC_INTR_TX_OVER 0x008 |
| 84 | #define DW_IC_INTR_TX_EMPTY 0x010 |
| 85 | #define DW_IC_INTR_RD_REQ 0x020 |
| 86 | #define DW_IC_INTR_TX_ABRT 0x040 |
| 87 | #define DW_IC_INTR_RX_DONE 0x080 |
| 88 | #define DW_IC_INTR_ACTIVITY 0x100 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 89 | #define DW_IC_INTR_STOP_DET 0x200 |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 90 | #define DW_IC_INTR_START_DET 0x400 |
| 91 | #define DW_IC_INTR_GEN_CALL 0x800 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 92 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 93 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
| 94 | DW_IC_INTR_TX_EMPTY | \ |
| 95 | DW_IC_INTR_TX_ABRT | \ |
| 96 | DW_IC_INTR_STOP_DET) |
| 97 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 98 | #define DW_IC_STATUS_ACTIVITY 0x1 |
| 99 | |
| 100 | #define DW_IC_ERR_TX_ABRT 0x1 |
| 101 | |
| 102 | /* |
| 103 | * status codes |
| 104 | */ |
| 105 | #define STATUS_IDLE 0x0 |
| 106 | #define STATUS_WRITE_IN_PROGRESS 0x1 |
| 107 | #define STATUS_READ_IN_PROGRESS 0x2 |
| 108 | |
| 109 | #define TIMEOUT 20 /* ms */ |
| 110 | |
| 111 | /* |
| 112 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register |
| 113 | * |
| 114 | * only expected abort codes are listed here |
| 115 | * refer to the datasheet for the full list |
| 116 | */ |
| 117 | #define ABRT_7B_ADDR_NOACK 0 |
| 118 | #define ABRT_10ADDR1_NOACK 1 |
| 119 | #define ABRT_10ADDR2_NOACK 2 |
| 120 | #define ABRT_TXDATA_NOACK 3 |
| 121 | #define ABRT_GCALL_NOACK 4 |
| 122 | #define ABRT_GCALL_READ 5 |
| 123 | #define ABRT_SBYTE_ACKDET 7 |
| 124 | #define ABRT_SBYTE_NORSTRT 9 |
| 125 | #define ABRT_10B_RD_NORSTRT 10 |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame^] | 126 | #define ABRT_MASTER_DIS 11 |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 127 | #define ARB_LOST 12 |
| 128 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame^] | 129 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
| 130 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) |
| 131 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) |
| 132 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) |
| 133 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) |
| 134 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) |
| 135 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) |
| 136 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) |
| 137 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) |
| 138 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) |
| 139 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) |
| 140 | |
| 141 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ |
| 142 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ |
| 143 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ |
| 144 | DW_IC_TX_ABRT_TXDATA_NOACK | \ |
| 145 | DW_IC_TX_ABRT_GCALL_NOACK) |
| 146 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 147 | static char *abort_sources[] = { |
| 148 | [ABRT_7B_ADDR_NOACK] = |
| 149 | "slave address not acknowledged (7bit mode)", |
| 150 | [ABRT_10ADDR1_NOACK] = |
| 151 | "first address byte not acknowledged (10bit mode)", |
| 152 | [ABRT_10ADDR2_NOACK] = |
| 153 | "second address byte not acknowledged (10bit mode)", |
| 154 | [ABRT_TXDATA_NOACK] = |
| 155 | "data not acknowledged", |
| 156 | [ABRT_GCALL_NOACK] = |
| 157 | "no acknowledgement for a general call", |
| 158 | [ABRT_GCALL_READ] = |
| 159 | "read after general call", |
| 160 | [ABRT_SBYTE_ACKDET] = |
| 161 | "start byte acknowledged", |
| 162 | [ABRT_SBYTE_NORSTRT] = |
| 163 | "trying to send start byte when restart is disabled", |
| 164 | [ABRT_10B_RD_NORSTRT] = |
| 165 | "trying to read when restart is disabled (10bit mode)", |
| 166 | [ARB_MASTER_DIS] = |
| 167 | "trying to use disabled adapter", |
| 168 | [ARB_LOST] = |
| 169 | "lost arbitration", |
| 170 | }; |
| 171 | |
| 172 | /** |
| 173 | * struct dw_i2c_dev - private i2c-designware data |
| 174 | * @dev: driver model device node |
| 175 | * @base: IO registers pointer |
| 176 | * @cmd_complete: tx completion indicator |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 177 | * @lock: protect this struct and IO registers |
| 178 | * @clk: input reference clock |
| 179 | * @cmd_err: run time hadware error code |
| 180 | * @msgs: points to an array of messages currently being transfered |
| 181 | * @msgs_num: the number of elements in msgs |
| 182 | * @msg_write_idx: the element index of the current tx message in the msgs |
| 183 | * array |
| 184 | * @tx_buf_len: the length of the current tx buffer |
| 185 | * @tx_buf: the current tx buffer |
| 186 | * @msg_read_idx: the element index of the current rx message in the msgs |
| 187 | * array |
| 188 | * @rx_buf_len: the length of the current rx buffer |
| 189 | * @rx_buf: the current rx buffer |
| 190 | * @msg_err: error status of the current transfer |
| 191 | * @status: i2c master status, one of STATUS_* |
| 192 | * @abort_source: copy of the TX_ABRT_SOURCE register |
| 193 | * @irq: interrupt number for the i2c master |
| 194 | * @adapter: i2c subsystem adapter node |
| 195 | * @tx_fifo_depth: depth of the hardware tx fifo |
| 196 | * @rx_fifo_depth: depth of the hardware rx fifo |
| 197 | */ |
| 198 | struct dw_i2c_dev { |
| 199 | struct device *dev; |
| 200 | void __iomem *base; |
| 201 | struct completion cmd_complete; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 202 | struct mutex lock; |
| 203 | struct clk *clk; |
| 204 | int cmd_err; |
| 205 | struct i2c_msg *msgs; |
| 206 | int msgs_num; |
| 207 | int msg_write_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 208 | u32 tx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 209 | u8 *tx_buf; |
| 210 | int msg_read_idx; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 211 | u32 rx_buf_len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 212 | u8 *rx_buf; |
| 213 | int msg_err; |
| 214 | unsigned int status; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 215 | u32 abort_source; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 216 | int irq; |
| 217 | struct i2c_adapter adapter; |
| 218 | unsigned int tx_fifo_depth; |
| 219 | unsigned int rx_fifo_depth; |
| 220 | }; |
| 221 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 222 | static u32 |
| 223 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 224 | { |
| 225 | /* |
| 226 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 227 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 228 | * will result in violation of the tHD;STA spec. |
| 229 | */ |
| 230 | if (cond) |
| 231 | /* |
| 232 | * Conditional expression: |
| 233 | * |
| 234 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 235 | * |
| 236 | * This is based on the DW manuals, and represents an ideal |
| 237 | * configuration. The resulting I2C bus speed will be |
| 238 | * faster than any of the others. |
| 239 | * |
| 240 | * If your hardware is free from tHD;STA issue, try this one. |
| 241 | */ |
| 242 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 243 | else |
| 244 | /* |
| 245 | * Conditional expression: |
| 246 | * |
| 247 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 248 | * |
| 249 | * This is just experimental rule; the tHD;STA period turned |
| 250 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 251 | * we could meet both tHIGH and tHD;STA timing specs. |
| 252 | * |
| 253 | * If unsure, you'd better to take this alternative. |
| 254 | * |
| 255 | * The reason why we need to take into account "tf" here, |
| 256 | * is the same as described in i2c_dw_scl_lcnt(). |
| 257 | */ |
| 258 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 259 | } |
| 260 | |
| 261 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 262 | { |
| 263 | /* |
| 264 | * Conditional expression: |
| 265 | * |
| 266 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 267 | * |
| 268 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 269 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 270 | * In order to meet the tLOW timing spec, we need to take into |
| 271 | * account the fall time of SCL signal (tf). Default tf value |
| 272 | * should be 0.3 us, for safety. |
| 273 | */ |
| 274 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 275 | } |
| 276 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 277 | /** |
| 278 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 279 | * @dev: device private data |
| 280 | * |
| 281 | * This functions configures and enables the I2C master. |
| 282 | * This function is called during I2C init function, and in case of timeout at |
| 283 | * run time. |
| 284 | */ |
| 285 | static void i2c_dw_init(struct dw_i2c_dev *dev) |
| 286 | { |
| 287 | u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 288 | u32 ic_con, hcnt, lcnt; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 289 | |
| 290 | /* Disable the adapter */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 291 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 292 | |
| 293 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 294 | |
| 295 | /* Standard-mode */ |
| 296 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 297 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 298 | 3, /* tf = 0.3 us */ |
| 299 | 0, /* 0: DW default, 1: Ideal */ |
| 300 | 0); /* No offset */ |
| 301 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 302 | 47, /* tLOW = 4.7 us */ |
| 303 | 3, /* tf = 0.3 us */ |
| 304 | 0); /* No offset */ |
| 305 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); |
| 306 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); |
| 307 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 308 | |
| 309 | /* Fast-mode */ |
| 310 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 311 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 312 | 3, /* tf = 0.3 us */ |
| 313 | 0, /* 0: DW default, 1: Ideal */ |
| 314 | 0); /* No offset */ |
| 315 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 316 | 13, /* tLOW = 1.3 us */ |
| 317 | 3, /* tf = 0.3 us */ |
| 318 | 0); /* No offset */ |
| 319 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); |
| 320 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); |
| 321 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 322 | |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 323 | /* Configure Tx/Rx FIFO threshold levels */ |
| 324 | writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); |
| 325 | writel(0, dev->base + DW_IC_RX_TL); |
| 326 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 327 | /* configure the i2c master */ |
| 328 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | |
| 329 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 330 | writel(ic_con, dev->base + DW_IC_CON); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | /* |
| 334 | * Waiting for bus not busy |
| 335 | */ |
| 336 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 337 | { |
| 338 | int timeout = TIMEOUT; |
| 339 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 340 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 341 | if (timeout <= 0) { |
| 342 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 343 | return -ETIMEDOUT; |
| 344 | } |
| 345 | timeout--; |
| 346 | mdelay(1); |
| 347 | } |
| 348 | |
| 349 | return 0; |
| 350 | } |
| 351 | |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 352 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 353 | { |
| 354 | struct i2c_msg *msgs = dev->msgs; |
| 355 | u32 ic_con; |
| 356 | |
| 357 | /* Disable the adapter */ |
| 358 | writel(0, dev->base + DW_IC_ENABLE); |
| 359 | |
| 360 | /* set the slave (target) address */ |
| 361 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); |
| 362 | |
| 363 | /* if the slave address is ten bit address, enable 10BITADDR */ |
| 364 | ic_con = readl(dev->base + DW_IC_CON); |
| 365 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 366 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 367 | else |
| 368 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
| 369 | writel(ic_con, dev->base + DW_IC_CON); |
| 370 | |
| 371 | /* Enable the adapter */ |
| 372 | writel(1, dev->base + DW_IC_ENABLE); |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 373 | |
| 374 | /* Enable interrupts */ |
| 375 | writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 376 | } |
| 377 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 378 | /* |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 379 | * Initiate (and continue) low level master read/write transaction. |
| 380 | * This function is only called from i2c_dw_isr, and pumping i2c_msg |
| 381 | * messages into the tx buffer. Even if the size of i2c_msg data is |
| 382 | * longer than the size of the tx buffer, it handles everything. |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 383 | */ |
| 384 | static void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 385 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 386 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 387 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 388 | u32 intr_mask; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 389 | int tx_limit, rx_limit; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 390 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 391 | u32 buf_len = dev->tx_buf_len; |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 392 | u8 *buf = dev->tx_buf;; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 393 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 394 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 395 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 396 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 397 | /* if target address has changed, we need to |
| 398 | * reprogram the target address in the i2c |
| 399 | * adapter when we are done with this transfer |
| 400 | */ |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 401 | if (msgs[dev->msg_write_idx].addr != addr) { |
| 402 | dev_err(dev->dev, |
| 403 | "%s: invalid target address\n", __func__); |
| 404 | dev->msg_err = -EINVAL; |
| 405 | break; |
| 406 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 407 | |
| 408 | if (msgs[dev->msg_write_idx].len == 0) { |
| 409 | dev_err(dev->dev, |
| 410 | "%s: invalid message length\n", __func__); |
| 411 | dev->msg_err = -EINVAL; |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 412 | break; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 416 | /* new i2c_msg */ |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 417 | buf = msgs[dev->msg_write_idx].buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 418 | buf_len = msgs[dev->msg_write_idx].len; |
| 419 | } |
| 420 | |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 421 | tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); |
| 422 | rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); |
| 423 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 424 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
| 425 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 426 | writel(0x100, dev->base + DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 427 | rx_limit--; |
| 428 | } else |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 429 | writel(*buf++, dev->base + DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 430 | tx_limit--; buf_len--; |
| 431 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 432 | |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 433 | dev->tx_buf = buf; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 434 | dev->tx_buf_len = buf_len; |
| 435 | |
| 436 | if (buf_len > 0) { |
| 437 | /* more bytes to be written */ |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 438 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 439 | break; |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 440 | } else |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 441 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 442 | } |
| 443 | |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 444 | /* |
| 445 | * If i2c_msg index search is completed, we don't need TX_EMPTY |
| 446 | * interrupt any more. |
| 447 | */ |
| 448 | if (dev->msg_write_idx == dev->msgs_num) |
| 449 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; |
| 450 | |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 451 | if (dev->msg_err) |
| 452 | intr_mask = 0; |
| 453 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 454 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 455 | } |
| 456 | |
| 457 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 458 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 459 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 460 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 461 | int rx_valid; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 462 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 463 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 464 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 465 | u8 *buf; |
| 466 | |
| 467 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 468 | continue; |
| 469 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 470 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 471 | len = msgs[dev->msg_read_idx].len; |
| 472 | buf = msgs[dev->msg_read_idx].buf; |
| 473 | } else { |
| 474 | len = dev->rx_buf_len; |
| 475 | buf = dev->rx_buf; |
| 476 | } |
| 477 | |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 478 | rx_valid = readl(dev->base + DW_IC_RXFLR); |
| 479 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 480 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 481 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 482 | |
| 483 | if (len > 0) { |
| 484 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 485 | dev->rx_buf_len = len; |
| 486 | dev->rx_buf = buf; |
| 487 | return; |
| 488 | } else |
| 489 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 490 | } |
| 491 | } |
| 492 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame^] | 493 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
| 494 | { |
| 495 | unsigned long abort_source = dev->abort_source; |
| 496 | int i; |
| 497 | |
| 498 | for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
| 499 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 500 | |
| 501 | if (abort_source & DW_IC_TX_ARB_LOST) |
| 502 | return -EAGAIN; |
| 503 | else if (abort_source & DW_IC_TX_ABRT_NOACK) |
| 504 | return -EREMOTEIO; |
| 505 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
| 506 | return -EINVAL; /* wrong msgs[] data */ |
| 507 | else |
| 508 | return -EIO; |
| 509 | } |
| 510 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 511 | /* |
| 512 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 513 | */ |
| 514 | static int |
| 515 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 516 | { |
| 517 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 518 | int ret; |
| 519 | |
| 520 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 521 | |
| 522 | mutex_lock(&dev->lock); |
| 523 | |
| 524 | INIT_COMPLETION(dev->cmd_complete); |
| 525 | dev->msgs = msgs; |
| 526 | dev->msgs_num = num; |
| 527 | dev->cmd_err = 0; |
| 528 | dev->msg_write_idx = 0; |
| 529 | dev->msg_read_idx = 0; |
| 530 | dev->msg_err = 0; |
| 531 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame^] | 532 | dev->abort_source = 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 533 | |
| 534 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 535 | if (ret < 0) |
| 536 | goto done; |
| 537 | |
| 538 | /* start the transfers */ |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 539 | i2c_dw_xfer_init(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 540 | |
| 541 | /* wait for tx to complete */ |
| 542 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 543 | if (ret == 0) { |
| 544 | dev_err(dev->dev, "controller timed out\n"); |
| 545 | i2c_dw_init(dev); |
| 546 | ret = -ETIMEDOUT; |
| 547 | goto done; |
| 548 | } else if (ret < 0) |
| 549 | goto done; |
| 550 | |
| 551 | if (dev->msg_err) { |
| 552 | ret = dev->msg_err; |
| 553 | goto done; |
| 554 | } |
| 555 | |
| 556 | /* no error */ |
| 557 | if (likely(!dev->cmd_err)) { |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 558 | /* Disable the adapter */ |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 559 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 560 | ret = num; |
| 561 | goto done; |
| 562 | } |
| 563 | |
| 564 | /* We have an error */ |
| 565 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame^] | 566 | ret = i2c_dw_handle_tx_abort(dev); |
| 567 | goto done; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 568 | } |
| 569 | ret = -EIO; |
| 570 | |
| 571 | done: |
| 572 | mutex_unlock(&dev->lock); |
| 573 | |
| 574 | return ret; |
| 575 | } |
| 576 | |
| 577 | static u32 i2c_dw_func(struct i2c_adapter *adap) |
| 578 | { |
Shinya Kuribayashi | 52d7e43 | 2009-11-06 21:50:02 +0900 | [diff] [blame] | 579 | return I2C_FUNC_I2C | |
| 580 | I2C_FUNC_10BIT_ADDR | |
| 581 | I2C_FUNC_SMBUS_BYTE | |
| 582 | I2C_FUNC_SMBUS_BYTE_DATA | |
| 583 | I2C_FUNC_SMBUS_WORD_DATA | |
| 584 | I2C_FUNC_SMBUS_I2C_BLOCK; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 585 | } |
| 586 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 587 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 588 | { |
| 589 | u32 stat; |
| 590 | |
| 591 | /* |
| 592 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 593 | * Ths unmasked raw version of interrupt status bits are available |
| 594 | * in the IC_RAW_INTR_STAT register. |
| 595 | * |
| 596 | * That is, |
| 597 | * stat = readl(IC_INTR_STAT); |
| 598 | * equals to, |
| 599 | * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); |
| 600 | * |
| 601 | * The raw version might be useful for debugging purposes. |
| 602 | */ |
| 603 | stat = readl(dev->base + DW_IC_INTR_STAT); |
| 604 | |
| 605 | /* |
| 606 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 607 | * you'll miss some interrupts, triggered during the period from |
| 608 | * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). |
| 609 | * |
| 610 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 611 | */ |
| 612 | if (stat & DW_IC_INTR_RX_UNDER) |
| 613 | readl(dev->base + DW_IC_CLR_RX_UNDER); |
| 614 | if (stat & DW_IC_INTR_RX_OVER) |
| 615 | readl(dev->base + DW_IC_CLR_RX_OVER); |
| 616 | if (stat & DW_IC_INTR_TX_OVER) |
| 617 | readl(dev->base + DW_IC_CLR_TX_OVER); |
| 618 | if (stat & DW_IC_INTR_RD_REQ) |
| 619 | readl(dev->base + DW_IC_CLR_RD_REQ); |
| 620 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 621 | /* |
| 622 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 623 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 624 | */ |
| 625 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); |
| 626 | readl(dev->base + DW_IC_CLR_TX_ABRT); |
| 627 | } |
| 628 | if (stat & DW_IC_INTR_RX_DONE) |
| 629 | readl(dev->base + DW_IC_CLR_RX_DONE); |
| 630 | if (stat & DW_IC_INTR_ACTIVITY) |
| 631 | readl(dev->base + DW_IC_CLR_ACTIVITY); |
| 632 | if (stat & DW_IC_INTR_STOP_DET) |
| 633 | readl(dev->base + DW_IC_CLR_STOP_DET); |
| 634 | if (stat & DW_IC_INTR_START_DET) |
| 635 | readl(dev->base + DW_IC_CLR_START_DET); |
| 636 | if (stat & DW_IC_INTR_GEN_CALL) |
| 637 | readl(dev->base + DW_IC_CLR_GEN_CALL); |
| 638 | |
| 639 | return stat; |
| 640 | } |
| 641 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 642 | /* |
| 643 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 644 | * occurs. |
| 645 | */ |
| 646 | static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
| 647 | { |
| 648 | struct dw_i2c_dev *dev = dev_id; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 649 | u32 stat; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 650 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 651 | stat = i2c_dw_read_clear_intrbits(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 652 | dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 653 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 654 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 655 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 656 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 657 | |
| 658 | /* |
| 659 | * Anytime TX_ABRT is set, the contents of the tx/rx |
| 660 | * buffers are flushed. Make sure to skip them. |
| 661 | */ |
| 662 | writel(0, dev->base + DW_IC_INTR_MASK); |
| 663 | goto tx_aborted; |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 664 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 665 | |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 666 | if (stat & DW_IC_INTR_RX_FULL) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 667 | i2c_dw_read(dev); |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 668 | |
| 669 | if (stat & DW_IC_INTR_TX_EMPTY) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 670 | i2c_dw_xfer_msg(dev); |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 671 | |
| 672 | /* |
| 673 | * No need to modify or disable the interrupt mask here. |
| 674 | * i2c_dw_xfer_msg() will take care of it according to |
| 675 | * the current transmit status. |
| 676 | */ |
| 677 | |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 678 | tx_aborted: |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 679 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 680 | complete(&dev->cmd_complete); |
| 681 | |
| 682 | return IRQ_HANDLED; |
| 683 | } |
| 684 | |
| 685 | static struct i2c_algorithm i2c_dw_algo = { |
| 686 | .master_xfer = i2c_dw_xfer, |
| 687 | .functionality = i2c_dw_func, |
| 688 | }; |
| 689 | |
| 690 | static int __devinit dw_i2c_probe(struct platform_device *pdev) |
| 691 | { |
| 692 | struct dw_i2c_dev *dev; |
| 693 | struct i2c_adapter *adap; |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 694 | struct resource *mem, *ioarea; |
| 695 | int irq, r; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 696 | |
| 697 | /* NOTE: driver uses the static register mapping */ |
| 698 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 699 | if (!mem) { |
| 700 | dev_err(&pdev->dev, "no mem resource?\n"); |
| 701 | return -EINVAL; |
| 702 | } |
| 703 | |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 704 | irq = platform_get_irq(pdev, 0); |
| 705 | if (irq < 0) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 706 | dev_err(&pdev->dev, "no irq resource?\n"); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 707 | return irq; /* -ENXIO */ |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 708 | } |
| 709 | |
| 710 | ioarea = request_mem_region(mem->start, resource_size(mem), |
| 711 | pdev->name); |
| 712 | if (!ioarea) { |
| 713 | dev_err(&pdev->dev, "I2C region already claimed\n"); |
| 714 | return -EBUSY; |
| 715 | } |
| 716 | |
| 717 | dev = kzalloc(sizeof(struct dw_i2c_dev), GFP_KERNEL); |
| 718 | if (!dev) { |
| 719 | r = -ENOMEM; |
| 720 | goto err_release_region; |
| 721 | } |
| 722 | |
| 723 | init_completion(&dev->cmd_complete); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 724 | mutex_init(&dev->lock); |
| 725 | dev->dev = get_device(&pdev->dev); |
Shinya Kuribayashi | 91b52ca | 2009-11-06 21:45:07 +0900 | [diff] [blame] | 726 | dev->irq = irq; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 727 | platform_set_drvdata(pdev, dev); |
| 728 | |
| 729 | dev->clk = clk_get(&pdev->dev, NULL); |
| 730 | if (IS_ERR(dev->clk)) { |
| 731 | r = -ENODEV; |
| 732 | goto err_free_mem; |
| 733 | } |
| 734 | clk_enable(dev->clk); |
| 735 | |
| 736 | dev->base = ioremap(mem->start, resource_size(mem)); |
| 737 | if (dev->base == NULL) { |
| 738 | dev_err(&pdev->dev, "failure mapping io resources\n"); |
| 739 | r = -EBUSY; |
| 740 | goto err_unuse_clocks; |
| 741 | } |
| 742 | { |
| 743 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); |
| 744 | |
| 745 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; |
| 746 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; |
| 747 | } |
| 748 | i2c_dw_init(dev); |
| 749 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 750 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 751 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 752 | if (r) { |
| 753 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); |
| 754 | goto err_iounmap; |
| 755 | } |
| 756 | |
| 757 | adap = &dev->adapter; |
| 758 | i2c_set_adapdata(adap, dev); |
| 759 | adap->owner = THIS_MODULE; |
| 760 | adap->class = I2C_CLASS_HWMON; |
| 761 | strlcpy(adap->name, "Synopsys DesignWare I2C adapter", |
| 762 | sizeof(adap->name)); |
| 763 | adap->algo = &i2c_dw_algo; |
| 764 | adap->dev.parent = &pdev->dev; |
| 765 | |
| 766 | adap->nr = pdev->id; |
| 767 | r = i2c_add_numbered_adapter(adap); |
| 768 | if (r) { |
| 769 | dev_err(&pdev->dev, "failure adding adapter\n"); |
| 770 | goto err_free_irq; |
| 771 | } |
| 772 | |
| 773 | return 0; |
| 774 | |
| 775 | err_free_irq: |
| 776 | free_irq(dev->irq, dev); |
| 777 | err_iounmap: |
| 778 | iounmap(dev->base); |
| 779 | err_unuse_clocks: |
| 780 | clk_disable(dev->clk); |
| 781 | clk_put(dev->clk); |
| 782 | dev->clk = NULL; |
| 783 | err_free_mem: |
| 784 | platform_set_drvdata(pdev, NULL); |
| 785 | put_device(&pdev->dev); |
| 786 | kfree(dev); |
| 787 | err_release_region: |
| 788 | release_mem_region(mem->start, resource_size(mem)); |
| 789 | |
| 790 | return r; |
| 791 | } |
| 792 | |
| 793 | static int __devexit dw_i2c_remove(struct platform_device *pdev) |
| 794 | { |
| 795 | struct dw_i2c_dev *dev = platform_get_drvdata(pdev); |
| 796 | struct resource *mem; |
| 797 | |
| 798 | platform_set_drvdata(pdev, NULL); |
| 799 | i2c_del_adapter(&dev->adapter); |
| 800 | put_device(&pdev->dev); |
| 801 | |
| 802 | clk_disable(dev->clk); |
| 803 | clk_put(dev->clk); |
| 804 | dev->clk = NULL; |
| 805 | |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 806 | writel(0, dev->base + DW_IC_ENABLE); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 807 | free_irq(dev->irq, dev); |
| 808 | kfree(dev); |
| 809 | |
| 810 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 811 | release_mem_region(mem->start, resource_size(mem)); |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | /* work with hotplug and coldplug */ |
| 816 | MODULE_ALIAS("platform:i2c_designware"); |
| 817 | |
| 818 | static struct platform_driver dw_i2c_driver = { |
| 819 | .remove = __devexit_p(dw_i2c_remove), |
| 820 | .driver = { |
| 821 | .name = "i2c_designware", |
| 822 | .owner = THIS_MODULE, |
| 823 | }, |
| 824 | }; |
| 825 | |
| 826 | static int __init dw_i2c_init_driver(void) |
| 827 | { |
| 828 | return platform_driver_probe(&dw_i2c_driver, dw_i2c_probe); |
| 829 | } |
| 830 | module_init(dw_i2c_init_driver); |
| 831 | |
| 832 | static void __exit dw_i2c_exit_driver(void) |
| 833 | { |
| 834 | platform_driver_unregister(&dw_i2c_driver); |
| 835 | } |
| 836 | module_exit(dw_i2c_exit_driver); |
| 837 | |
| 838 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); |
| 839 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter"); |
| 840 | MODULE_LICENSE("GPL"); |