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Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001/*
2 * Driver for DBRI sound chip found on Sparcs.
Martin Habets43388292005-09-10 15:39:00 +02003 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02004 *
Krzysztof Helt1be54c82006-08-21 19:30:57 +02005 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02007 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020011 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020013 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020019 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020020 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020022 * available from the Lucent (formerly AT&T microelectronics) home
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020023 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020030 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020032 * device (short pipes).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020033 * A timeslot defines the bit-offset and no. of bits read from a serial device.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020034 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020039 * parameters (volume, output selection) time multiplexed in 8 byte
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020040 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020043 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020045 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
Martin Habets43388292005-09-10 15:39:00 +020048 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
Adrian Bunkd254c8f2006-06-30 18:29:51 +020051 * cs4215_* CS4215 codec specific stuff
Martin Habets43388292005-09-10 15:39:00 +020052 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020054 */
55
56#include <sound/driver.h>
57#include <linux/interrupt.h>
58#include <linux/delay.h>
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020059#include <linux/irq.h>
60#include <linux/io.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020061
62#include <sound/core.h>
63#include <sound/pcm.h>
64#include <sound/pcm_params.h>
65#include <sound/info.h>
66#include <sound/control.h>
67#include <sound/initval.h>
68
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020069#include <asm/sbus.h>
70#include <asm/atomic.h>
71
72MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73MODULE_DESCRIPTION("Sun DBRI");
74MODULE_LICENSE("GPL");
75MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
76
77static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020079/* Enable this card */
80static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020081
82module_param_array(index, int, NULL, 0444);
83MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
84module_param_array(id, charp, NULL, 0444);
85MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
86module_param_array(enable, bool, NULL, 0444);
87MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
88
Krzysztof Heltab93c7a2006-08-23 11:37:36 +020089#undef DBRI_DEBUG
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020090
91#define D_INT (1<<0)
92#define D_GEN (1<<1)
93#define D_CMD (1<<2)
94#define D_MM (1<<3)
95#define D_USR (1<<4)
96#define D_DESC (1<<5)
97
Takashi Iwai6581f4e2006-05-17 17:14:51 +020098static int dbri_debug;
Martin Habets43388292005-09-10 15:39:00 +020099module_param(dbri_debug, int, 0644);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200100MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
101
102#ifdef DBRI_DEBUG
103static char *cmds[] = {
104 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
105 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
106};
107
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200108#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200109
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200110#else
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200111#define dprintk(a, x...) do { } while (0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200112
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200113#endif /* DBRI_DEBUG */
114
Krzysztof Helt42fe7642006-08-16 12:53:34 +0200115#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
116 (intr << 27) | \
117 value)
118
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200119/***************************************************************************
120 CS4215 specific definitions and structures
121****************************************************************************/
122
123struct cs4215 {
124 __u8 data[4]; /* Data mode: Time slots 5-8 */
125 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
126 __u8 onboard;
127 __u8 offset; /* Bit offset from frame sync to time slot 1 */
128 volatile __u32 status;
129 volatile __u32 version;
130 __u8 precision; /* In bits, either 8 or 16 */
131 __u8 channels; /* 1 or 2 */
132};
133
134/*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200135 * Control mode first
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200136 */
137
138/* Time Slot 1, Status register */
139#define CS4215_CLB (1<<2) /* Control Latch Bit */
140#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
141 /* 0: line: 2.8V, speaker 8V */
142#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
143#define CS4215_RSRVD_1 (1<<5)
144
145/* Time Slot 2, Data Format Register */
146#define CS4215_DFR_LINEAR16 0
147#define CS4215_DFR_ULAW 1
148#define CS4215_DFR_ALAW 2
149#define CS4215_DFR_LINEAR8 3
150#define CS4215_DFR_STEREO (1<<2)
151static struct {
152 unsigned short freq;
153 unsigned char xtal;
154 unsigned char csval;
155} CS4215_FREQ[] = {
156 { 8000, (1 << 4), (0 << 3) },
157 { 16000, (1 << 4), (1 << 3) },
158 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
159 { 32000, (1 << 4), (3 << 3) },
160 /* { NA, (1 << 4), (4 << 3) }, */
161 /* { NA, (1 << 4), (5 << 3) }, */
162 { 48000, (1 << 4), (6 << 3) },
163 { 9600, (1 << 4), (7 << 3) },
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200164 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200165 { 11025, (2 << 4), (1 << 3) },
166 { 18900, (2 << 4), (2 << 3) },
167 { 22050, (2 << 4), (3 << 3) },
168 { 37800, (2 << 4), (4 << 3) },
169 { 44100, (2 << 4), (5 << 3) },
170 { 33075, (2 << 4), (6 << 3) },
171 { 6615, (2 << 4), (7 << 3) },
172 { 0, 0, 0}
173};
174
175#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
176
177#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
178
179/* Time Slot 3, Serial Port Control register */
180#define CS4215_XEN (1<<0) /* 0: Enable serial output */
181#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
182#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
183#define CS4215_BSEL_128 (1<<2)
184#define CS4215_BSEL_256 (2<<2)
185#define CS4215_MCK_MAST (0<<4) /* Master clock */
186#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
187#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
188#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
189#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
190
191/* Time Slot 4, Test Register */
192#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
193#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
194
195/* Time Slot 5, Parallel Port Register */
196/* Read only here and the same as the in data mode */
197
198/* Time Slot 6, Reserved */
199
200/* Time Slot 7, Version Register */
201#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
202
203/* Time Slot 8, Reserved */
204
205/*
206 * Data mode
207 */
208/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
209
210/* Time Slot 5, Output Setting */
211#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
212#define CS4215_LE (1<<6) /* Line Out Enable */
213#define CS4215_HE (1<<7) /* Headphone Enable */
214
215/* Time Slot 6, Output Setting */
216#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
217#define CS4215_SE (1<<6) /* Speaker Enable */
218#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
219
220/* Time Slot 7, Input Setting */
221#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
222#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200223#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200224#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
225#define CS4215_PIO1 (1<<7)
226
227/* Time Slot 8, Input Setting */
228#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
229#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
230
231/***************************************************************************
232 DBRI specific definitions and structures
233****************************************************************************/
234
235/* DBRI main registers */
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200236#define REG0 0x00 /* Status and Control */
237#define REG1 0x04 /* Mode and Interrupt */
238#define REG2 0x08 /* Parallel IO */
239#define REG3 0x0c /* Test */
240#define REG8 0x20 /* Command Queue Pointer */
241#define REG9 0x24 /* Interrupt Queue Pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200242
243#define DBRI_NO_CMDS 64
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200244#define DBRI_INT_BLK 64
245#define DBRI_NO_DESCS 64
246#define DBRI_NO_PIPES 32
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200247#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200248
249#define DBRI_REC 0
250#define DBRI_PLAY 1
251#define DBRI_NO_STREAMS 2
252
253/* One transmit/receive descriptor */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200254/* When ba != 0 descriptor is used */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200255struct dbri_mem {
256 volatile __u32 word1;
Krzysztof Helt16727d92006-08-17 16:59:28 +0200257 __u32 ba; /* Transmit/Receive Buffer Address */
258 __u32 nda; /* Next Descriptor Address */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200259 volatile __u32 word4;
260};
261
262/* This structure is in a DMA region where it can accessed by both
263 * the CPU and the DBRI
264 */
265struct dbri_dma {
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200266 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200267 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200268 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
269};
270
271#define dbri_dma_off(member, elem) \
272 ((u32)(unsigned long) \
273 (&(((struct dbri_dma *)0)->member[elem])))
274
275enum in_or_out { PIPEinput, PIPEoutput };
276
277struct dbri_pipe {
278 u32 sdp; /* SDP command word */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200279 int nextpipe; /* Next pipe in linked list */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200280 int length; /* Length of timeslot (bits) */
281 int first_desc; /* Index of first descriptor */
282 int desc; /* Index of active descriptor */
283 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
284};
285
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200286/* Per stream (playback or record) information */
Takashi Iwai475675d2005-11-17 15:11:51 +0100287struct dbri_streaminfo {
288 struct snd_pcm_substream *substream;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200289 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200290 int size; /* Size of DMA buffer */
291 size_t offset; /* offset in user buffer */
292 int pipe; /* Data pipe used */
293 int left_gain; /* mixer elements */
294 int right_gain;
Takashi Iwai475675d2005-11-17 15:11:51 +0100295};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200296
297/* This structure holds the information for both chips (DBRI & CS4215) */
Takashi Iwai475675d2005-11-17 15:11:51 +0100298struct snd_dbri {
299 struct snd_card *card; /* ALSA card */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200300
301 int regs_size, irq; /* Needed for unload */
302 struct sbus_dev *sdev; /* SBUS device info */
303 spinlock_t lock;
304
Krzysztof Helt16727d92006-08-17 16:59:28 +0200305 struct dbri_dma *dma; /* Pointer to our DMA block */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200306 u32 dma_dvma; /* DBRI visible DMA address */
307
308 void __iomem *regs; /* dbri HW regs */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200309 int dbri_irqp; /* intr queue pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200310
311 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200312 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200313 spinlock_t cmdlock; /* Protects cmd queue accesses */
314 s32 *cmdptr; /* Pointer to the last queued cmd */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200315
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200316 int chi_bpf;
317
318 struct cs4215 mm; /* mmcodec special info */
319 /* per stream (playback/record) info */
320 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
321
322 struct snd_dbri *next;
Takashi Iwai475675d2005-11-17 15:11:51 +0100323};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200324
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200325#define DBRI_MAX_VOLUME 63 /* Output volume */
326#define DBRI_MAX_GAIN 15 /* Input gain */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200327
328/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
329#define D_P (1<<15) /* Program command & queue pointer valid */
330#define D_G (1<<14) /* Allow 4-Word SBus Burst */
331#define D_S (1<<13) /* Allow 16-Word SBus Burst */
332#define D_E (1<<12) /* Allow 8-Word SBus Burst */
333#define D_X (1<<7) /* Sanity Timer Disable */
334#define D_T (1<<6) /* Permit activation of the TE interface */
335#define D_N (1<<5) /* Permit activation of the NT interface */
336#define D_C (1<<4) /* Permit activation of the CHI interface */
337#define D_F (1<<3) /* Force Sanity Timer Time-Out */
338#define D_D (1<<2) /* Disable Master Mode */
339#define D_H (1<<1) /* Halt for Analysis */
340#define D_R (1<<0) /* Soft Reset */
341
342/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
343#define D_LITTLE_END (1<<8) /* Byte Order */
344#define D_BIG_END (0<<8) /* Byte Order */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200345#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
346#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
347#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
348#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
349#define D_IR (1<<0) /* Interrupt Indicator (read only) */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200350
351/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
352#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
353#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
354#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
355#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
356#define D_ENPIO (0xf0) /* Enable all the pins */
357#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
358#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
359#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
360#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
361
362/* DBRI Commands (Page 20) */
363#define D_WAIT 0x0 /* Stop execution */
364#define D_PAUSE 0x1 /* Flush long pipes */
365#define D_JUMP 0x2 /* New command queue */
366#define D_IIQ 0x3 /* Initialize Interrupt Queue */
367#define D_REX 0x4 /* Report command execution via interrupt */
368#define D_SDP 0x5 /* Setup Data Pipe */
369#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
370#define D_DTS 0x7 /* Define Time Slot */
371#define D_SSP 0x8 /* Set short Data Pipe */
372#define D_CHI 0x9 /* Set CHI Global Mode */
373#define D_NT 0xa /* NT Command */
374#define D_TE 0xb /* TE Command */
375#define D_CDEC 0xc /* Codec setup */
376#define D_TEST 0xd /* No comment */
377#define D_CDM 0xe /* CHI Data mode command */
378
379/* Special bits for some commands */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200380#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200381
382/* Setup Data Pipe */
383/* IRM */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200384#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200385#define D_SDP_CHANGE (2<<18) /* Report any changes */
386#define D_SDP_EVERY (3<<18) /* Report any changes */
387#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
388#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
389
390/* Pipe data MODE */
391#define D_SDP_MEM (0<<13) /* To/from memory */
392#define D_SDP_HDLC (2<<13)
393#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
394#define D_SDP_SER (4<<13) /* Serial to serial */
395#define D_SDP_FIXED (6<<13) /* Short only */
396#define D_SDP_MODE(v) ((v)&(7<<13))
397
398#define D_SDP_TO_SER (1<<12) /* Direction */
399#define D_SDP_FROM_SER (0<<12) /* Direction */
400#define D_SDP_MSB (1<<11) /* Bit order within Byte */
401#define D_SDP_LSB (0<<11) /* Bit order within Byte */
402#define D_SDP_P (1<<10) /* Pointer Valid */
403#define D_SDP_A (1<<8) /* Abort */
404#define D_SDP_C (1<<7) /* Clear */
405
406/* Define Time Slot */
407#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
408#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
409#define D_DTS_INS (1<<15) /* Insert Time Slot */
410#define D_DTS_DEL (0<<15) /* Delete Time Slot */
411#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
412#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
413
414/* Time Slot defines */
415#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
416#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
417#define D_TS_DI (1<<13) /* Data Invert */
418#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
419#define D_TS_MONITOR (2<<10) /* Monitor pipe */
420#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
421#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
422#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200423#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200424
425/* Concentration Highway Interface Modes */
426#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
427#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
428#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
429#define D_CHI_OD (1<<13) /* Open Drain Enable */
430#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
431#define D_CHI_FD (1<<11) /* Frame Drive */
432#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
433
434/* NT: These are here for completeness */
435#define D_NT_FBIT (1<<17) /* Frame Bit */
436#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
437#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
438#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200439#define D_NT_ISNT (1<<13) /* Configure interface as NT */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200440#define D_NT_FT (1<<12) /* Fixed Timing */
441#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
442#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
443#define D_NT_ACT (1<<9) /* Activate Interface */
444#define D_NT_MFE (1<<8) /* Multiframe Enable */
445#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
446#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
447#define D_NT_FACT (1<<1) /* Force Activation */
448#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
449
450/* Codec Setup */
451#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
452#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
453#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
454
455/* Test */
456#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
457#define D_TEST_SIZE(v) ((v)<<11) /* */
458#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200459#define D_TEST_PROC 0x6 /* Microprocessor test */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200460#define D_TEST_SER 0x7 /* Serial-Controller test */
461#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
462#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
463#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
464#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
465#define D_TEST_DUMP 0xe /* ROM Dump */
466
467/* CHI Data Mode */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200468#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
469#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
470#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
471#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
472#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
473#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200474
475/* The Interrupts */
476#define D_INTR_BRDY 1 /* Buffer Ready for processing */
477#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
478#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
479#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
480#define D_INTR_EOL 5 /* End of List */
481#define D_INTR_CMDI 6 /* Command has bean read */
482#define D_INTR_XCMP 8 /* Transmission of frame complete */
483#define D_INTR_SBRI 9 /* BRI status change info */
484#define D_INTR_FXDT 10 /* Fixed data change */
485#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
486#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
487#define D_INTR_DBYT 12 /* Dropped by frame slip */
488#define D_INTR_RBYT 13 /* Repeated by frame slip */
489#define D_INTR_LINT 14 /* Lost Interrupt */
490#define D_INTR_UNDR 15 /* DMA underrun */
491
492#define D_INTR_TE 32
493#define D_INTR_NT 34
494#define D_INTR_CHI 36
495#define D_INTR_CMD 38
496
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200497#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
498#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
499#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200500#define D_INTR_GETVAL(v) ((v) & 0xffff)
501#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
502
503#define D_P_0 0 /* TE receive anchor */
504#define D_P_1 1 /* TE transmit anchor */
505#define D_P_2 2 /* NT transmit anchor */
506#define D_P_3 3 /* NT receive anchor */
507#define D_P_4 4 /* CHI send data */
508#define D_P_5 5 /* CHI receive data */
509#define D_P_6 6 /* */
510#define D_P_7 7 /* */
511#define D_P_8 8 /* */
512#define D_P_9 9 /* */
513#define D_P_10 10 /* */
514#define D_P_11 11 /* */
515#define D_P_12 12 /* */
516#define D_P_13 13 /* */
517#define D_P_14 14 /* */
518#define D_P_15 15 /* */
519#define D_P_16 16 /* CHI anchor pipe */
520#define D_P_17 17 /* CHI send */
521#define D_P_18 18 /* CHI receive */
522#define D_P_19 19 /* CHI receive */
523#define D_P_20 20 /* CHI receive */
524#define D_P_21 21 /* */
525#define D_P_22 22 /* */
526#define D_P_23 23 /* */
527#define D_P_24 24 /* */
528#define D_P_25 25 /* */
529#define D_P_26 26 /* */
530#define D_P_27 27 /* */
531#define D_P_28 28 /* */
532#define D_P_29 29 /* */
533#define D_P_30 30 /* */
534#define D_P_31 31 /* */
535
536/* Transmit descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200537#define DBRI_TD_F (1 << 31) /* End of Frame */
538#define DBRI_TD_D (1 << 30) /* Do not append CRC */
539#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
540#define DBRI_TD_B (1 << 15) /* Final interrupt */
541#define DBRI_TD_M (1 << 14) /* Marker interrupt */
542#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
543#define DBRI_TD_FCNT(v) (v) /* Flag Count */
544#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
545#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
546#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
547#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
548 /* Maximum buffer size per TD: almost 8KB */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200549#define DBRI_TD_MAXCNT ((1 << 13) - 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200550
551/* Receive descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200552#define DBRI_RD_F (1 << 31) /* End of Frame */
553#define DBRI_RD_C (1 << 30) /* Completed buffer */
554#define DBRI_RD_B (1 << 15) /* Final interrupt */
555#define DBRI_RD_M (1 << 14) /* Marker interrupt */
556#define DBRI_RD_BCNT(v) (v) /* Buffer size */
557#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
558#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
559#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
560#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
561#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
562#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200563
564/* stream_info[] access */
565/* Translate the ALSA direction into the array index */
566#define DBRI_STREAMNO(substream) \
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200567 (substream->stream == \
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200569
570/* Return a pointer to dbri_streaminfo */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200571#define DBRI_STREAM(dbri, substream) \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200573
Takashi Iwai6581f4e2006-05-17 17:14:51 +0200574static struct snd_dbri *dbri_list; /* All DBRI devices */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200575
576/*
577 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
578 * So we have to reverse the bits. Note: not all bit lengths are supported
579 */
580static __u32 reverse_bytes(__u32 b, int len)
581{
582 switch (len) {
583 case 32:
584 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
585 case 16:
586 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
587 case 8:
588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
589 case 4:
590 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
591 case 2:
592 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
593 case 1:
594 case 0:
595 break;
596 default:
597 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
598 };
599
600 return b;
601}
602
603/*
604****************************************************************************
605************** DBRI initialization and command synchronization *************
606****************************************************************************
607
608Commands are sent to the DBRI by building a list of them in memory,
609then writing the address of the first list item to DBRI register 8.
Martin Habets43388292005-09-10 15:39:00 +0200610The list is terminated with a WAIT command, which generates a
611CPU interrupt to signal completion.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200612
613Since the DBRI can run in parallel with the CPU, several means of
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200614synchronization present themselves. The method implemented here uses
615the dbri_cmdwait() to wait for execution of batch of sent commands.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200616
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200617A circular command buffer is used here. A new command is being added
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200618while another can be executed. The scheme works by adding two WAIT commands
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200619after each sent batch of commands. When the next batch is prepared it is
620added after the WAIT commands then the WAITs are replaced with single JUMP
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200621command to the new batch. The the DBRI is forced to reread the last WAIT
622command (replaced by the JUMP by then). If the DBRI is still executing
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200623previous commands the request to reread the WAIT command is ignored.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200624
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200625Every time a routine wants to write commands to the DBRI, it must
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200626first call dbri_cmdlock() and get pointer to a free space in
627dbri->dma->cmd buffer. After this, the commands can be written to
628the buffer, and dbri_cmdsend() is called with the final pointer value
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200629to send them to the DBRI.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200630
631*/
632
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200633#define MAXLOOPS 20
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200634/*
635 * Wait for the current command string to execute
636 */
637static void dbri_cmdwait(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200638{
Martin Habets43388292005-09-10 15:39:00 +0200639 int maxloops = MAXLOOPS;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200640 unsigned long flags;
Martin Habets43388292005-09-10 15:39:00 +0200641
Martin Habets43388292005-09-10 15:39:00 +0200642 /* Delay if previous commands are still being processed */
Krzysztof Heltea543f12006-09-05 20:25:05 +0200643 spin_lock_irqsave(&dbri->lock, flags);
644 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
645 spin_unlock_irqrestore(&dbri->lock, flags);
Martin Habets43388292005-09-10 15:39:00 +0200646 msleep_interruptible(1);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200647 spin_lock_irqsave(&dbri->lock, flags);
648 }
649 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200650
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200651 if (maxloops == 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200652 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200653 else
Martin Habets43388292005-09-10 15:39:00 +0200654 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
655 MAXLOOPS - maxloops - 1);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200656}
657/*
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200658 * Lock the command queue and return pointer to space for len cmd words
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200659 * It locks the cmdlock spinlock.
660 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200661static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200662{
663 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
664 len += 2;
665 spin_lock(&dbri->cmdlock);
666 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
667 return dbri->cmdptr + 2;
668 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
669 return dbri->dma->cmd;
670 else
671 printk(KERN_ERR "DBRI: no space for commands.");
Martin Habets43388292005-09-10 15:39:00 +0200672
Al Viroae97dd92006-09-24 23:42:57 +0100673 return NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200674}
675
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200676/*
Robert P. J. Daybeb7dd82007-05-09 07:14:03 +0200677 * Send prepared cmd string. It works by writing a JUMP cmd into
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200678 * the last WAIT cmd and force DBRI to reread the cmd.
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200679 * The JUMP cmd points to the new cmd string.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200680 * It also releases the cmdlock spinlock.
Krzysztof Heltea543f12006-09-05 20:25:05 +0200681 *
Krzysztof Heltca405872006-12-18 14:41:03 +0100682 * Lock must be held before calling this.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200683 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200684static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200685{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200686 s32 tmp, addr;
687 static int wait_id = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200688
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200689 wait_id++;
690 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
691 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
692 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
693
694 /* Replace the last command with JUMP */
695 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
696 *(dbri->cmdptr+1) = addr;
697 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
698
699#ifdef DBRI_DEBUG
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200700 if (cmd > dbri->cmdptr) {
701 s32 *ptr;
702
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200703 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200704 dprintk(D_CMD, "cmd: %lx:%08x\n",
705 (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200706 } else {
707 s32 *ptr = dbri->cmdptr;
708
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200709 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200710 ptr++;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200711 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200712 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
713 dprintk(D_CMD, "cmd: %lx:%08x\n",
714 (unsigned long)ptr, *ptr);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200715 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200716#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200717
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200718 /* Reread the last command */
719 tmp = sbus_readl(dbri->regs + REG0);
720 tmp |= D_P;
721 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200722
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200723 dbri->cmdptr = cmd;
724 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200725}
726
727/* Lock must be held when calling this */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200728static void dbri_reset(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200729{
730 int i;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200731 u32 tmp;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200732
733 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
734 sbus_readl(dbri->regs + REG0),
735 sbus_readl(dbri->regs + REG2),
736 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
737
738 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
739 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
740 udelay(10);
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200741
742 /* A brute approach - DBRI falls back to working burst size by itself
743 * On SS20 D_S does not work, so do not try so high. */
744 tmp = sbus_readl(dbri->regs + REG0);
745 tmp |= D_G | D_E;
746 tmp &= ~D_S;
747 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200748}
749
750/* Lock must not be held before calling this */
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200751static void __init dbri_initialize(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200752{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200753 s32 *cmd;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200754 u32 dma_addr;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200755 unsigned long flags;
756 int n;
757
758 spin_lock_irqsave(&dbri->lock, flags);
759
760 dbri_reset(dbri);
761
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200762 /* Initialize pipes */
763 for (n = 0; n < DBRI_NO_PIPES; n++)
764 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
765
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200766 spin_lock_init(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200767 /*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200768 * Initialize the interrupt ring buffer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200769 */
770 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200771 dbri->dma->intr[0] = dma_addr;
772 dbri->dbri_irqp = 1;
773 /*
774 * Set up the interrupt queue
775 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200776 spin_lock(&dbri->cmdlock);
777 cmd = dbri->cmdptr = dbri->dma->cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200778 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
779 *(cmd++) = dma_addr;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200780 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
781 dbri->cmdptr = cmd;
782 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
783 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
784 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
785 sbus_writel(dma_addr, dbri->regs + REG8);
786 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200787
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200788 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200789 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200790}
791
792/*
793****************************************************************************
794************************** DBRI data pipe management ***********************
795****************************************************************************
796
797While DBRI control functions use the command and interrupt buffers, the
798main data path takes the form of data pipes, which can be short (command
799and interrupt driven), or long (attached to DMA buffers). These functions
800provide a rudimentary means of setting up and managing the DBRI's pipes,
801but the calling functions have to make sure they respect the pipes' linked
802list ordering, among other things. The transmit and receive functions
803here interface closely with the transmit and receive interrupt code.
804
805*/
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200806static inline int pipe_active(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200807{
808 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
809}
810
811/* reset_pipe(dbri, pipe)
812 *
813 * Called on an in-use pipe to clear anything being transmitted or received
814 * Lock must be held before calling this.
815 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200816static void reset_pipe(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200817{
818 int sdp;
819 int desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200820 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200821
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200822 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200823 printk(KERN_ERR "DBRI: reset_pipe called with "
824 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200825 return;
826 }
827
828 sdp = dbri->pipes[pipe].sdp;
829 if (sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200830 printk(KERN_ERR "DBRI: reset_pipe called "
831 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200832 return;
833 }
834
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200835 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200836 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
837 *(cmd++) = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200838 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
839 dbri_cmdsend(dbri, cmd, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200840
841 desc = dbri->pipes[pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200842 if (desc >= 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200843 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200844 dbri->dma->desc[desc].ba = 0;
845 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200846 desc = dbri->next_desc[desc];
847 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200848
849 dbri->pipes[pipe].desc = -1;
850 dbri->pipes[pipe].first_desc = -1;
851}
852
Krzysztof Heltea543f12006-09-05 20:25:05 +0200853/*
854 * Lock must be held before calling this.
855 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200856static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200857{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200858 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200859 printk(KERN_ERR "DBRI: setup_pipe called "
860 "with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200861 return;
862 }
863
864 if ((sdp & 0xf800) != sdp) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200865 printk(KERN_ERR "DBRI: setup_pipe called "
866 "with strange SDP value\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200867 /* sdp &= 0xf800; */
868 }
869
870 /* If this is a fixed receive pipe, arrange for an interrupt
871 * every time its data changes
872 */
873 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
874 sdp |= D_SDP_CHANGE;
875
876 sdp |= D_PIPE(pipe);
877 dbri->pipes[pipe].sdp = sdp;
878 dbri->pipes[pipe].desc = -1;
879 dbri->pipes[pipe].first_desc = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200880
881 reset_pipe(dbri, pipe);
882}
883
Krzysztof Heltea543f12006-09-05 20:25:05 +0200884/*
885 * Lock must be held before calling this.
886 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200887static void link_time_slot(struct snd_dbri *dbri, int pipe,
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200888 int prevpipe, int nextpipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200889 int length, int cycle)
890{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200891 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200892 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200893
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200894 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200895 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
896 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200897 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200898 "DBRI: link_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200899 return;
900 }
901
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200902 if (dbri->pipes[pipe].sdp == 0
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200903 || dbri->pipes[prevpipe].sdp == 0
904 || dbri->pipes[nextpipe].sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200905 printk(KERN_ERR "DBRI: link_time_slot called "
906 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200907 return;
908 }
909
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200910 dbri->pipes[prevpipe].nextpipe = pipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200911 dbri->pipes[pipe].nextpipe = nextpipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200912 dbri->pipes[pipe].length = length;
913
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200914 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200915
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200916 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
917 /* Deal with CHI special case:
918 * "If transmission on edges 0 or 1 is desired, then cycle n
919 * (where n = # of bit times per frame...) must be used."
920 * - DBRI data sheet, page 11
921 */
922 if (prevpipe == 16 && cycle == 0)
923 cycle = dbri->chi_bpf;
924
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200925 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
926 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
927 *(cmd++) = 0;
928 *(cmd++) =
929 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200930 } else {
931 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
932 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
933 *(cmd++) =
934 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
935 *(cmd++) = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200936 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200937 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200938
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200939 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200940}
941
Krzysztof Heltea543f12006-09-05 20:25:05 +0200942#if 0
943/*
944 * Lock must be held before calling this.
945 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200946static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200947 enum in_or_out direction, int prevpipe,
948 int nextpipe)
949{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200950 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200951 int val;
952
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200953 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200954 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
955 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200956 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200957 "DBRI: unlink_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200958 return;
959 }
960
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200961 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200962
963 if (direction == PIPEinput) {
964 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
965 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
966 *(cmd++) = D_TS_NEXT(nextpipe);
967 *(cmd++) = 0;
968 } else {
969 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
970 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
971 *(cmd++) = 0;
972 *(cmd++) = D_TS_NEXT(nextpipe);
973 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200974 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200975
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200976 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200977}
Krzysztof Heltea543f12006-09-05 20:25:05 +0200978#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200979
980/* xmit_fixed() / recv_fixed()
981 *
982 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
983 * expected to change much, and which we don't need to buffer.
984 * The DBRI only interrupts us when the data changes (receive pipes),
985 * or only changes the data when this function is called (transmit pipes).
986 * Only short pipes (numbers 16-31) can be used in fixed data mode.
987 *
988 * These function operate on a 32-bit field, no matter how large
989 * the actual time slot is. The interrupt handler takes care of bit
990 * ordering and alignment. An 8-bit time slot will always end up
991 * in the low-order 8 bits, filled either MSB-first or LSB-first,
Krzysztof Heltea543f12006-09-05 20:25:05 +0200992 * depending on the settings passed to setup_pipe().
993 *
994 * Lock must not be held before calling it.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200995 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200996static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200997{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200998 s32 *cmd;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200999 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001000
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001001 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Martin Habets43388292005-09-10 15:39:00 +02001002 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001003 return;
1004 }
1005
1006 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001007 printk(KERN_ERR "DBRI: xmit_fixed: "
1008 "Uninitialized pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001009 return;
1010 }
1011
1012 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Martin Habets43388292005-09-10 15:39:00 +02001013 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001014 return;
1015 }
1016
1017 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001018 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1019 pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001020 return;
1021 }
1022
1023 /* DBRI short pipes always transmit LSB first */
1024
1025 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1026 data = reverse_bytes(data, dbri->pipes[pipe].length);
1027
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001028 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001029
1030 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1031 *(cmd++) = data;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001032 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001033
Krzysztof Heltea543f12006-09-05 20:25:05 +02001034 spin_lock_irqsave(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001035 dbri_cmdsend(dbri, cmd, 3);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001036 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001037 dbri_cmdwait(dbri);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001038
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001039}
1040
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001041static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001042{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001043 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001044 printk(KERN_ERR "DBRI: recv_fixed called with "
1045 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001046 return;
1047 }
1048
1049 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001050 printk(KERN_ERR "DBRI: recv_fixed called on "
1051 "non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001052 return;
1053 }
1054
1055 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001056 printk(KERN_ERR "DBRI: recv_fixed called on "
1057 "transmit pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001058 return;
1059 }
1060
1061 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1062}
1063
1064/* setup_descs()
1065 *
1066 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1067 * with a DMA buffer.
1068 *
1069 * Only pipe numbers 0-15 can be used in this mode.
1070 *
1071 * This function takes a stream number pointing to a data buffer,
1072 * and work by building chains of descriptors which identify the
1073 * data buffers. Buffers too large for a single descriptor will
1074 * be spread across multiple descriptors.
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001075 *
1076 * All descriptors create a ring buffer.
Krzysztof Heltea543f12006-09-05 20:25:05 +02001077 *
1078 * Lock must be held before calling this.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001079 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001080static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001081{
Takashi Iwai475675d2005-11-17 15:11:51 +01001082 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001083 __u32 dvma_buffer;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001084 int desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001085 int len;
1086 int first_desc = -1;
1087 int last_desc = -1;
1088
1089 if (info->pipe < 0 || info->pipe > 15) {
Martin Habets43388292005-09-10 15:39:00 +02001090 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001091 return -2;
1092 }
1093
1094 if (dbri->pipes[info->pipe].sdp == 0) {
Martin Habets43388292005-09-10 15:39:00 +02001095 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001096 info->pipe);
1097 return -2;
1098 }
1099
1100 dvma_buffer = info->dvma_buffer;
1101 len = info->size;
1102
1103 if (streamno == DBRI_PLAY) {
1104 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001105 printk(KERN_ERR "DBRI: setup_descs: "
1106 "Called on receive pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001107 return -2;
1108 }
1109 } else {
1110 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001111 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +02001112 "DBRI: setup_descs: Called on transmit pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001113 info->pipe);
1114 return -2;
1115 }
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001116 /* Should be able to queue multiple buffers
1117 * to receive on a pipe
1118 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001119 if (pipe_active(dbri, info->pipe)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001120 printk(KERN_ERR "DBRI: recv_on_pipe: "
1121 "Called on active pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001122 return -2;
1123 }
1124
1125 /* Make sure buffer size is multiple of four */
1126 len &= ~3;
1127 }
1128
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001129 /* Free descriptors if pipe has any */
1130 desc = dbri->pipes[info->pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001131 if (desc >= 0)
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001132 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001133 dbri->dma->desc[desc].ba = 0;
1134 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001135 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001136 } while (desc != -1 &&
1137 desc != dbri->pipes[info->pipe].first_desc);
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001138
1139 dbri->pipes[info->pipe].desc = -1;
1140 dbri->pipes[info->pipe].first_desc = -1;
1141
1142 desc = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001143 while (len > 0) {
1144 int mylen;
1145
1146 for (; desc < DBRI_NO_DESCS; desc++) {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001147 if (!dbri->dma->desc[desc].ba)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001148 break;
1149 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001150
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001151 if (desc == DBRI_NO_DESCS) {
Martin Habets43388292005-09-10 15:39:00 +02001152 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001153 return -1;
1154 }
1155
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001156 if (len > DBRI_TD_MAXCNT)
1157 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1158 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001159 mylen = len;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001160
1161 if (mylen > period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001162 mylen = period;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001163
Krzysztof Heltc2735442006-08-21 19:27:35 +02001164 dbri->next_desc[desc] = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001165 dbri->dma->desc[desc].ba = dvma_buffer;
1166 dbri->dma->desc[desc].nda = 0;
1167
1168 if (streamno == DBRI_PLAY) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001169 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1170 dbri->dma->desc[desc].word4 = 0;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001171 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001172 } else {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001173 dbri->dma->desc[desc].word1 = 0;
1174 dbri->dma->desc[desc].word4 =
1175 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1176 }
1177
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001178 if (first_desc == -1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001179 first_desc = desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001180 else {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001181 dbri->next_desc[last_desc] = desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001182 dbri->dma->desc[last_desc].nda =
1183 dbri->dma_dvma + dbri_dma_off(desc, desc);
1184 }
1185
1186 last_desc = desc;
1187 dvma_buffer += mylen;
1188 len -= mylen;
1189 }
1190
1191 if (first_desc == -1 || last_desc == -1) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001192 printk(KERN_ERR "DBRI: setup_descs: "
1193 " Not enough descriptors available\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001194 return -1;
1195 }
1196
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001197 dbri->dma->desc[last_desc].nda =
1198 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1199 dbri->next_desc[last_desc] = first_desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001200 dbri->pipes[info->pipe].first_desc = first_desc;
1201 dbri->pipes[info->pipe].desc = first_desc;
1202
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001203#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001204 for (desc = first_desc; desc != -1;) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001205 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1206 desc,
1207 dbri->dma->desc[desc].word1,
1208 dbri->dma->desc[desc].ba,
1209 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001210 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001211 if (desc == first_desc)
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001212 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001213 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001214#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001215 return 0;
1216}
1217
1218/*
1219****************************************************************************
1220************************** DBRI - CHI interface ****************************
1221****************************************************************************
1222
1223The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1224multiplexed serial interface which the DBRI can operate in either master
1225(give clock/frame sync) or slave (take clock/frame sync) mode.
1226
1227*/
1228
1229enum master_or_slave { CHImaster, CHIslave };
1230
Krzysztof Heltea543f12006-09-05 20:25:05 +02001231/*
1232 * Lock must not be held before calling it.
1233 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001234static void reset_chi(struct snd_dbri *dbri,
1235 enum master_or_slave master_or_slave,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001236 int bits_per_frame)
1237{
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001238 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001239 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001240
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001241 /* Set CHI Anchor: Pipe 16 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001242
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001243 cmd = dbri_cmdlock(dbri, 4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001244 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001245 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1246 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1247 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1248 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1249 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1250 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001251
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001252 dbri->pipes[16].sdp = 1;
1253 dbri->pipes[16].nextpipe = 16;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001254
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001255 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001256
1257 if (master_or_slave == CHIslave) {
1258 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1259 *
1260 * CHICM = 0 (slave mode, 8 kHz frame rate)
1261 * IR = give immediate CHI status interrupt
1262 * EN = give CHI status interrupt upon change
1263 */
1264 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1265 } else {
1266 /* Setup DBRI for CHI Master - generate clock, FS
1267 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001268 * BPF = bits per 8 kHz frame
1269 * 12.288 MHz / CHICM_divisor = clock rate
1270 * FD = 1 - drive CHIFS on rising edge of CHICK
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001271 */
1272 int clockrate = bits_per_frame * 8;
1273 int divisor = 12288 / clockrate;
1274
1275 if (divisor > 255 || divisor * clockrate != 12288)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001276 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1277 "in setup_chi\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001278
1279 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1280 | D_CHI_BPF(bits_per_frame));
1281 }
1282
1283 dbri->chi_bpf = bits_per_frame;
1284
1285 /* CHI Data Mode
1286 *
1287 * RCE = 0 - receive on falling edge of CHICK
1288 * XCE = 1 - transmit on rising edge of CHICK
1289 * XEN = 1 - enable transmitter
1290 * REN = 1 - enable receiver
1291 */
1292
1293 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1294 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001295 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001296
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001297 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001298}
1299
1300/*
1301****************************************************************************
1302*********************** CS4215 audio codec management **********************
1303****************************************************************************
1304
1305In the standard SPARC audio configuration, the CS4215 codec is attached
1306to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1307
Krzysztof Heltea543f12006-09-05 20:25:05 +02001308 * Lock must not be held before calling it.
1309
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001310*/
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001311static __init void cs4215_setup_pipes(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001312{
Krzysztof Heltea543f12006-09-05 20:25:05 +02001313 unsigned long flags;
1314
1315 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001316 /*
1317 * Data mode:
1318 * Pipe 4: Send timeslots 1-4 (audio data)
1319 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1320 * Pipe 6: Receive timeslots 1-4 (audio data)
1321 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1322 * interrupt, and the rest of the data (slot 5 and 8) is
1323 * not relevant for us (only for doublechecking).
1324 *
1325 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001326 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001327 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001328 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001329 */
1330
1331 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1332 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1333 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1335
1336 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1337 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1338 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001339 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001340
1341 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001342}
1343
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001344static __init int cs4215_init_data(struct cs4215 *mm)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001345{
1346 /*
1347 * No action, memory resetting only.
1348 *
1349 * Data Time Slot 5-8
1350 * Speaker,Line and Headphone enable. Gain set to the half.
1351 * Input is mike.
1352 */
1353 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1354 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1355 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1356 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1357
1358 /*
1359 * Control Time Slot 1-4
1360 * 0: Default I/O voltage scale
1361 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1362 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1363 * 3: Tests disabled
1364 */
1365 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1366 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1367 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1368 mm->ctrl[3] = 0;
1369
1370 mm->status = 0;
1371 mm->version = 0xff;
1372 mm->precision = 8; /* For ULAW */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001373 mm->channels = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001374
1375 return 0;
1376}
1377
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001378static void cs4215_setdata(struct snd_dbri *dbri, int muted)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001379{
1380 if (muted) {
1381 dbri->mm.data[0] |= 63;
1382 dbri->mm.data[1] |= 63;
1383 dbri->mm.data[2] &= ~15;
1384 dbri->mm.data[3] &= ~15;
1385 } else {
1386 /* Start by setting the playback attenuation. */
Takashi Iwai475675d2005-11-17 15:11:51 +01001387 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001388 int left_gain = info->left_gain & 0x3f;
1389 int right_gain = info->right_gain & 0x3f;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001390
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001391 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1392 dbri->mm.data[1] &= ~0x3f;
1393 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1394 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1395
1396 /* Now set the recording gain. */
1397 info = &dbri->stream_info[DBRI_REC];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001398 left_gain = info->left_gain & 0xf;
1399 right_gain = info->right_gain & 0xf;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001400 dbri->mm.data[2] |= CS4215_LG(left_gain);
1401 dbri->mm.data[3] |= CS4215_RG(right_gain);
1402 }
1403
1404 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1405}
1406
1407/*
1408 * Set the CS4215 to data mode.
1409 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001410static void cs4215_open(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001411{
1412 int data_width;
1413 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001414 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001415
1416 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1417 dbri->mm.channels, dbri->mm.precision);
1418
1419 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1420 * to make sure this takes. This avoids clicking noises.
1421 */
1422
1423 cs4215_setdata(dbri, 1);
1424 udelay(125);
1425
1426 /*
1427 * Data mode:
1428 * Pipe 4: Send timeslots 1-4 (audio data)
1429 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1430 * Pipe 6: Receive timeslots 1-4 (audio data)
1431 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1432 * interrupt, and the rest of the data (slot 5 and 8) is
1433 * not relevant for us (only for doublechecking).
1434 *
1435 * Just like in control mode, the time slots are all offset by eight
1436 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1437 * even if it's the CHI master. Don't ask me...
1438 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001439 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001440 tmp = sbus_readl(dbri->regs + REG0);
1441 tmp &= ~(D_C); /* Disable CHI */
1442 sbus_writel(tmp, dbri->regs + REG0);
1443
1444 /* Switch CS4215 to data mode - set PIO3 to 1 */
1445 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1446 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1447
1448 reset_chi(dbri, CHIslave, 128);
1449
1450 /* Note: this next doesn't work for 8-bit stereo, because the two
1451 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1452 * (See CS4215 datasheet Fig 15)
1453 *
1454 * DBRI non-contiguous mode would be required to make this work.
1455 */
1456 data_width = dbri->mm.channels * dbri->mm.precision;
1457
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001458 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1459 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1460 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1461 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001462
1463 /* FIXME: enable CHI after _setdata? */
1464 tmp = sbus_readl(dbri->regs + REG0);
1465 tmp |= D_C; /* Enable CHI */
1466 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001467 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001468
1469 cs4215_setdata(dbri, 0);
1470}
1471
1472/*
1473 * Send the control information (i.e. audio format)
1474 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001475static int cs4215_setctrl(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001476{
1477 int i, val;
1478 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001479 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001480
1481 /* FIXME - let the CPU do something useful during these delays */
1482
1483 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1484 * to make sure this takes. This avoids clicking noises.
1485 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001486 cs4215_setdata(dbri, 1);
1487 udelay(125);
1488
1489 /*
1490 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1491 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1492 */
1493 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1494 sbus_writel(val, dbri->regs + REG2);
1495 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1496 udelay(34);
1497
1498 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1499 * operate as CHI master, supplying clocking and frame synchronization.
1500 *
1501 * In Data mode, however, the CS4215 must be CHI master to insure
1502 * that its data stream is synchronous with its codec.
1503 *
1504 * The upshot of all this? We start by putting the DBRI into master
1505 * mode, program the CS4215 in Control mode, then switch the CS4215
1506 * into Data mode and put the DBRI into slave mode. Various timing
1507 * requirements must be observed along the way.
1508 *
1509 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1510 * others?), the addressing of the CS4215's time slots is
1511 * offset by eight bits, so we add eight to all the "cycle"
1512 * values in the Define Time Slot (DTS) commands. This is
1513 * done in hardware by a TI 248 that delays the DBRI->4215
1514 * frame sync signal by eight clock cycles. Anybody know why?
1515 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001516 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001517 tmp = sbus_readl(dbri->regs + REG0);
1518 tmp &= ~D_C; /* Disable CHI */
1519 sbus_writel(tmp, dbri->regs + REG0);
1520
1521 reset_chi(dbri, CHImaster, 128);
1522
1523 /*
1524 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001525 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001526 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001527 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001528 */
1529
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001530 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1531 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1532 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001533 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001534
1535 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1536 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1537 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1538
Krzysztof Heltea543f12006-09-05 20:25:05 +02001539 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001540 tmp = sbus_readl(dbri->regs + REG0);
1541 tmp |= D_C; /* Enable CHI */
1542 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001543 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001544
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001545 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
Martin Habets43388292005-09-10 15:39:00 +02001546 msleep_interruptible(1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001547
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001548 if (i == 0) {
1549 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1550 dbri->mm.status);
1551 return -1;
1552 }
1553
1554 /* Disable changes to our copy of the version number, as we are about
1555 * to leave control mode.
1556 */
1557 recv_fixed(dbri, 19, NULL);
1558
1559 /* Terminate CS4215 control mode - data sheet says
1560 * "Set CLB=1 and send two more frames of valid control info"
1561 */
1562 dbri->mm.ctrl[0] |= CS4215_CLB;
1563 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1564
1565 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1566 udelay(250);
1567
1568 cs4215_setdata(dbri, 0);
1569
1570 return 0;
1571}
1572
1573/*
1574 * Setup the codec with the sampling rate, audio format and number of
1575 * channels.
1576 * As part of the process we resend the settings for the data
1577 * timeslots as well.
1578 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001579static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001580 snd_pcm_format_t format, unsigned int channels)
1581{
1582 int freq_idx;
1583 int ret = 0;
1584
1585 /* Lookup index for this rate */
1586 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1587 if (CS4215_FREQ[freq_idx].freq == rate)
1588 break;
1589 }
1590 if (CS4215_FREQ[freq_idx].freq != rate) {
1591 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1592 return -1;
1593 }
1594
1595 switch (format) {
1596 case SNDRV_PCM_FORMAT_MU_LAW:
1597 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1598 dbri->mm.precision = 8;
1599 break;
1600 case SNDRV_PCM_FORMAT_A_LAW:
1601 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1602 dbri->mm.precision = 8;
1603 break;
1604 case SNDRV_PCM_FORMAT_U8:
1605 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1606 dbri->mm.precision = 8;
1607 break;
1608 case SNDRV_PCM_FORMAT_S16_BE:
1609 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1610 dbri->mm.precision = 16;
1611 break;
1612 default:
1613 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1614 return -1;
1615 }
1616
1617 /* Add rate parameters */
1618 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1619 dbri->mm.ctrl[2] = CS4215_XCLK |
1620 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1621
1622 dbri->mm.channels = channels;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001623 if (channels == 2)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001624 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1625
1626 ret = cs4215_setctrl(dbri);
1627 if (ret == 0)
1628 cs4215_open(dbri); /* set codec to data mode */
1629
1630 return ret;
1631}
1632
1633/*
1634 *
1635 */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001636static __init int cs4215_init(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001637{
1638 u32 reg2 = sbus_readl(dbri->regs + REG2);
1639 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1640
1641 /* Look for the cs4215 chips */
1642 if (reg2 & D_PIO2) {
1643 dprintk(D_MM, "Onboard CS4215 detected\n");
1644 dbri->mm.onboard = 1;
1645 }
1646 if (reg2 & D_PIO0) {
1647 dprintk(D_MM, "Speakerbox detected\n");
1648 dbri->mm.onboard = 0;
1649
1650 if (reg2 & D_PIO2) {
1651 printk(KERN_INFO "DBRI: Using speakerbox / "
1652 "ignoring onboard mmcodec.\n");
1653 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1654 }
1655 }
1656
1657 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1658 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1659 return -EIO;
1660 }
1661
1662 cs4215_setup_pipes(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001663 cs4215_init_data(&dbri->mm);
1664
1665 /* Enable capture of the status & version timeslots. */
1666 recv_fixed(dbri, 18, &dbri->mm.status);
1667 recv_fixed(dbri, 19, &dbri->mm.version);
1668
1669 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1670 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1671 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1672 dbri->mm.offset);
1673 return -EIO;
1674 }
1675 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1676
1677 return 0;
1678}
1679
1680/*
1681****************************************************************************
1682*************************** DBRI interrupt handler *************************
1683****************************************************************************
1684
1685The DBRI communicates with the CPU mainly via a circular interrupt
1686buffer. When an interrupt is signaled, the CPU walks through the
1687buffer and calls dbri_process_one_interrupt() for each interrupt word.
1688Complicated interrupts are handled by dedicated functions (which
1689appear first in this file). Any pending interrupts can be serviced by
1690calling dbri_process_interrupt_buffer(), which works even if the CPU's
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001691interrupts are disabled.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001692
1693*/
1694
1695/* xmit_descs()
1696 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001697 * Starts transmitting the current TD's for recording/playing.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001698 * For playback, ALSA has filled the DMA memory with new data (we hope).
1699 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001700static void xmit_descs(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001701{
Takashi Iwai475675d2005-11-17 15:11:51 +01001702 struct dbri_streaminfo *info;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001703 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001704 unsigned long flags;
1705 int first_td;
1706
1707 if (dbri == NULL)
1708 return; /* Disabled */
1709
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001710 info = &dbri->stream_info[DBRI_REC];
1711 spin_lock_irqsave(&dbri->lock, flags);
1712
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001713 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001714 first_td = dbri->pipes[info->pipe].first_desc;
1715
1716 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1717
1718 /* Stream could be closed by the time we run. */
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001719 if (first_td >= 0) {
1720 cmd = dbri_cmdlock(dbri, 2);
1721 *(cmd++) = DBRI_CMD(D_SDP, 0,
1722 dbri->pipes[info->pipe].sdp
1723 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001724 *(cmd++) = dbri->dma_dvma +
1725 dbri_dma_off(desc, first_td);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001726 dbri_cmdsend(dbri, cmd, 2);
1727
1728 /* Reset our admin of the pipe. */
1729 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001730 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001731 }
1732
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001733 info = &dbri->stream_info[DBRI_PLAY];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001734
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001735 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001736 first_td = dbri->pipes[info->pipe].first_desc;
1737
1738 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1739
1740 /* Stream could be closed by the time we run. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001741 if (first_td >= 0) {
1742 cmd = dbri_cmdlock(dbri, 2);
1743 *(cmd++) = DBRI_CMD(D_SDP, 0,
1744 dbri->pipes[info->pipe].sdp
1745 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001746 *(cmd++) = dbri->dma_dvma +
1747 dbri_dma_off(desc, first_td);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001748 dbri_cmdsend(dbri, cmd, 2);
1749
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001750 /* Reset our admin of the pipe. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001751 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001752 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001753 }
Krzysztof Heltea543f12006-09-05 20:25:05 +02001754
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001755 spin_unlock_irqrestore(&dbri->lock, flags);
1756}
1757
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001758/* transmission_complete_intr()
1759 *
1760 * Called by main interrupt handler when DBRI signals transmission complete
1761 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1762 *
Martin Habets43388292005-09-10 15:39:00 +02001763 * Walks through the pipe's list of transmit buffer descriptors and marks
1764 * them as available. Stops when the first descriptor is found without
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001765 * TBC (Transmit Buffer Complete) set, or we've run through them all.
Martin Habets43388292005-09-10 15:39:00 +02001766 *
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001767 * The DMA buffers are not released. They form a ring buffer and
1768 * they are filled by ALSA while others are transmitted by DMA.
1769 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001770 */
1771
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001772static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001773{
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001774 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1775 int td = dbri->pipes[pipe].desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001776 int status;
1777
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001778 while (td >= 0) {
1779 if (td >= DBRI_NO_DESCS) {
1780 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1781 return;
1782 }
1783
1784 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001785 if (!(status & DBRI_TD_TBC))
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001786 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001787
1788 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1789
1790 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001791 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001792
Krzysztof Heltc2735442006-08-21 19:27:35 +02001793 td = dbri->next_desc[td];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001794 dbri->pipes[pipe].desc = td;
1795 }
1796
1797 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001798 spin_unlock(&dbri->lock);
1799 snd_pcm_period_elapsed(info->substream);
1800 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001801}
1802
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001803static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001804{
Takashi Iwai475675d2005-11-17 15:11:51 +01001805 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001806 int rd = dbri->pipes[pipe].desc;
1807 s32 status;
1808
1809 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1810 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1811 return;
1812 }
1813
Krzysztof Heltc2735442006-08-21 19:27:35 +02001814 dbri->pipes[pipe].desc = dbri->next_desc[rd];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001815 status = dbri->dma->desc[rd].word1;
1816 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1817
1818 info = &dbri->stream_info[DBRI_REC];
1819 info->offset += DBRI_RD_CNT(status);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001820
1821 /* FIXME: Check status */
1822
1823 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1824 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1825
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001826 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001827 spin_unlock(&dbri->lock);
1828 snd_pcm_period_elapsed(info->substream);
1829 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001830}
1831
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001832static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001833{
1834 int val = D_INTR_GETVAL(x);
1835 int channel = D_INTR_GETCHAN(x);
1836 int command = D_INTR_GETCMD(x);
1837 int code = D_INTR_GETCODE(x);
1838#ifdef DBRI_DEBUG
1839 int rval = D_INTR_GETRVAL(x);
1840#endif
1841
1842 if (channel == D_INTR_CMD) {
1843 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1844 cmds[command], val);
1845 } else {
1846 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1847 channel, code, rval);
1848 }
1849
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001850 switch (code) {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001851 case D_INTR_CMDI:
1852 if (command != D_WAIT)
1853 printk(KERN_ERR "DBRI: Command read interrupt\n");
1854 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001855 case D_INTR_BRDY:
1856 reception_complete_intr(dbri, channel);
1857 break;
1858 case D_INTR_XCMP:
1859 case D_INTR_MINT:
1860 transmission_complete_intr(dbri, channel);
1861 break;
1862 case D_INTR_UNDR:
1863 /* UNDR - Transmission underrun
1864 * resend SDP command with clear pipe bit (C) set
1865 */
1866 {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001867 /* FIXME: do something useful in case of underrun */
1868 printk(KERN_ERR "DBRI: Underrun error\n");
1869#if 0
1870 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001871 int pipe = channel;
1872 int td = dbri->pipes[pipe].desc;
1873
1874 dbri->dma->desc[td].word4 = 0;
1875 cmd = dbri_cmdlock(dbri, NoGetLock);
1876 *(cmd++) = DBRI_CMD(D_SDP, 0,
1877 dbri->pipes[pipe].sdp
1878 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1879 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1880 dbri_cmdsend(dbri, cmd);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001881#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001882 }
1883 break;
1884 case D_INTR_FXDT:
1885 /* FXDT - Fixed data change */
1886 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1887 val = reverse_bytes(val, dbri->pipes[channel].length);
1888
1889 if (dbri->pipes[channel].recv_fixed_ptr)
1890 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1891 break;
1892 default:
1893 if (channel != D_INTR_CMD)
1894 printk(KERN_WARNING
1895 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1896 }
1897}
1898
1899/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1900 * buffer until it finds a zero word (indicating nothing more to do
1901 * right now). Non-zero words require processing and are handed off
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001902 * to dbri_process_one_interrupt AFTER advancing the pointer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001903 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001904static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001905{
1906 s32 x;
1907
1908 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1909 dbri->dma->intr[dbri->dbri_irqp] = 0;
1910 dbri->dbri_irqp++;
Krzysztof Helt6fb98282006-08-16 12:54:29 +02001911 if (dbri->dbri_irqp == DBRI_INT_BLK)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001912 dbri->dbri_irqp = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001913
1914 dbri_process_one_interrupt(dbri, x);
1915 }
1916}
1917
David Howells7d12e782006-10-05 14:55:46 +01001918static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001919{
Takashi Iwai475675d2005-11-17 15:11:51 +01001920 struct snd_dbri *dbri = dev_id;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001921 static int errcnt = 0;
1922 int x;
1923
1924 if (dbri == NULL)
1925 return IRQ_NONE;
1926 spin_lock(&dbri->lock);
1927
1928 /*
1929 * Read it, so the interrupt goes away.
1930 */
1931 x = sbus_readl(dbri->regs + REG1);
1932
1933 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1934 u32 tmp;
1935
1936 if (x & D_MRR)
1937 printk(KERN_ERR
1938 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1939 x);
1940 if (x & D_MLE)
1941 printk(KERN_ERR
1942 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1943 x);
1944 if (x & D_LBG)
1945 printk(KERN_ERR
1946 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1947 if (x & D_MBE)
1948 printk(KERN_ERR
1949 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1950
1951 /* Some of these SBus errors cause the chip's SBus circuitry
1952 * to be disabled, so just re-enable and try to keep going.
1953 *
1954 * The only one I've seen is MRR, which will be triggered
1955 * if you let a transmit pipe underrun, then try to CDP it.
1956 *
Martin Habets43388292005-09-10 15:39:00 +02001957 * If these things persist, we reset the chip.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001958 */
1959 if ((++errcnt) % 10 == 0) {
1960 dprintk(D_INT, "Interrupt errors exceeded.\n");
1961 dbri_reset(dbri);
1962 } else {
1963 tmp = sbus_readl(dbri->regs + REG0);
1964 tmp &= ~(D_D);
1965 sbus_writel(tmp, dbri->regs + REG0);
1966 }
1967 }
1968
1969 dbri_process_interrupt_buffer(dbri);
1970
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001971 spin_unlock(&dbri->lock);
1972
1973 return IRQ_HANDLED;
1974}
1975
1976/****************************************************************************
1977 PCM Interface
1978****************************************************************************/
Takashi Iwai475675d2005-11-17 15:11:51 +01001979static struct snd_pcm_hardware snd_dbri_pcm_hw = {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001980 .info = SNDRV_PCM_INFO_MMAP |
1981 SNDRV_PCM_INFO_INTERLEAVED |
1982 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1983 SNDRV_PCM_INFO_MMAP_VALID,
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001984 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1985 SNDRV_PCM_FMTBIT_A_LAW |
1986 SNDRV_PCM_FMTBIT_U8 |
1987 SNDRV_PCM_FMTBIT_S16_BE,
1988 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001989 .rate_min = 5512,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001990 .rate_max = 48000,
1991 .channels_min = 1,
1992 .channels_max = 2,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001993 .buffer_bytes_max = 64 * 1024,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001994 .period_bytes_min = 1,
1995 .period_bytes_max = DBRI_TD_MAXCNT,
1996 .periods_min = 1,
1997 .periods_max = 1024,
1998};
1999
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002000static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2001 struct snd_pcm_hw_rule *rule)
2002{
2003 struct snd_interval *c = hw_param_interval(params,
2004 SNDRV_PCM_HW_PARAM_CHANNELS);
2005 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2006 struct snd_mask fmt;
2007
2008 snd_mask_any(&fmt);
2009 if (c->min > 1) {
2010 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2011 return snd_mask_refine(f, &fmt);
2012 }
2013 return 0;
2014}
2015
2016static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2017 struct snd_pcm_hw_rule *rule)
2018{
2019 struct snd_interval *c = hw_param_interval(params,
2020 SNDRV_PCM_HW_PARAM_CHANNELS);
2021 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2022 struct snd_interval ch;
2023
2024 snd_interval_any(&ch);
2025 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002026 ch.min = 1;
2027 ch.max = 1;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002028 ch.integer = 1;
2029 return snd_interval_refine(c, &ch);
2030 }
2031 return 0;
2032}
2033
Takashi Iwai475675d2005-11-17 15:11:51 +01002034static int snd_dbri_open(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002035{
Takashi Iwai475675d2005-11-17 15:11:51 +01002036 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2037 struct snd_pcm_runtime *runtime = substream->runtime;
2038 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002039 unsigned long flags;
2040
2041 dprintk(D_USR, "open audio output.\n");
2042 runtime->hw = snd_dbri_pcm_hw;
2043
2044 spin_lock_irqsave(&dbri->lock, flags);
2045 info->substream = substream;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002046 info->offset = 0;
2047 info->dvma_buffer = 0;
2048 info->pipe = -1;
2049 spin_unlock_irqrestore(&dbri->lock, flags);
2050
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002051 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
Al Viroae97dd92006-09-24 23:42:57 +01002052 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002053 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002054 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2055 snd_hw_rule_channels, NULL,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002056 SNDRV_PCM_HW_PARAM_CHANNELS,
2057 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002058
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002059 cs4215_open(dbri);
2060
2061 return 0;
2062}
2063
Takashi Iwai475675d2005-11-17 15:11:51 +01002064static int snd_dbri_close(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002065{
Takashi Iwai475675d2005-11-17 15:11:51 +01002066 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2067 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002068
2069 dprintk(D_USR, "close audio output.\n");
2070 info->substream = NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002071 info->offset = 0;
2072
2073 return 0;
2074}
2075
Takashi Iwai475675d2005-11-17 15:11:51 +01002076static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2077 struct snd_pcm_hw_params *hw_params)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002078{
Takashi Iwai475675d2005-11-17 15:11:51 +01002079 struct snd_pcm_runtime *runtime = substream->runtime;
2080 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2081 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002082 int direction;
2083 int ret;
2084
2085 /* set sampling rate, audio format and number of channels */
2086 ret = cs4215_prepare(dbri, params_rate(hw_params),
2087 params_format(hw_params),
2088 params_channels(hw_params));
2089 if (ret != 0)
2090 return ret;
2091
2092 if ((ret = snd_pcm_lib_malloc_pages(substream,
2093 params_buffer_bytes(hw_params))) < 0) {
Martin Habets43388292005-09-10 15:39:00 +02002094 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002095 return ret;
2096 }
2097
2098 /* hw_params can get called multiple times. Only map the DMA once.
2099 */
2100 if (info->dvma_buffer == 0) {
2101 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2102 direction = SBUS_DMA_TODEVICE;
2103 else
2104 direction = SBUS_DMA_FROMDEVICE;
2105
2106 info->dvma_buffer = sbus_map_single(dbri->sdev,
2107 runtime->dma_area,
2108 params_buffer_bytes(hw_params),
2109 direction);
2110 }
2111
2112 direction = params_buffer_bytes(hw_params);
2113 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2114 direction, info->dvma_buffer);
2115 return 0;
2116}
2117
Takashi Iwai475675d2005-11-17 15:11:51 +01002118static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002119{
Takashi Iwai475675d2005-11-17 15:11:51 +01002120 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2121 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002122 int direction;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002123
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002124 dprintk(D_USR, "hw_free.\n");
2125
2126 /* hw_free can get called multiple times. Only unmap the DMA once.
2127 */
2128 if (info->dvma_buffer) {
2129 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2130 direction = SBUS_DMA_TODEVICE;
2131 else
2132 direction = SBUS_DMA_FROMDEVICE;
2133
2134 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2135 substream->runtime->buffer_size, direction);
2136 info->dvma_buffer = 0;
2137 }
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002138 if (info->pipe != -1) {
2139 reset_pipe(dbri, info->pipe);
2140 info->pipe = -1;
2141 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002142
2143 return snd_pcm_lib_free_pages(substream);
2144}
2145
Takashi Iwai475675d2005-11-17 15:11:51 +01002146static int snd_dbri_prepare(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002147{
Takashi Iwai475675d2005-11-17 15:11:51 +01002148 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2149 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002150 int ret;
2151
2152 info->size = snd_pcm_lib_buffer_bytes(substream);
2153 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2154 info->pipe = 4; /* Send pipe */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002155 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002156 info->pipe = 6; /* Receive pipe */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002157
2158 spin_lock_irq(&dbri->lock);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02002159 info->offset = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002160
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002161 /* Setup the all the transmit/receive descriptors to cover the
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002162 * whole DMA buffer.
2163 */
2164 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2165 snd_pcm_lib_period_bytes(substream));
2166
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002167 spin_unlock_irq(&dbri->lock);
2168
2169 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2170 return ret;
2171}
2172
Takashi Iwai475675d2005-11-17 15:11:51 +01002173static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002174{
Takashi Iwai475675d2005-11-17 15:11:51 +01002175 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2176 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002177 int ret = 0;
2178
2179 switch (cmd) {
2180 case SNDRV_PCM_TRIGGER_START:
2181 dprintk(D_USR, "start audio, period is %d bytes\n",
2182 (int)snd_pcm_lib_period_bytes(substream));
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002183 /* Re-submit the TDs. */
2184 xmit_descs(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002185 break;
2186 case SNDRV_PCM_TRIGGER_STOP:
2187 dprintk(D_USR, "stop audio.\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002188 reset_pipe(dbri, info->pipe);
2189 break;
2190 default:
2191 ret = -EINVAL;
2192 }
2193
2194 return ret;
2195}
2196
Takashi Iwai475675d2005-11-17 15:11:51 +01002197static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002198{
Takashi Iwai475675d2005-11-17 15:11:51 +01002199 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2200 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002201 snd_pcm_uframes_t ret;
2202
2203 ret = bytes_to_frames(substream->runtime, info->offset)
2204 % substream->runtime->buffer_size;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002205 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2206 ret, substream->runtime->buffer_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002207 return ret;
2208}
2209
Takashi Iwai475675d2005-11-17 15:11:51 +01002210static struct snd_pcm_ops snd_dbri_ops = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002211 .open = snd_dbri_open,
2212 .close = snd_dbri_close,
2213 .ioctl = snd_pcm_lib_ioctl,
2214 .hw_params = snd_dbri_hw_params,
2215 .hw_free = snd_dbri_hw_free,
2216 .prepare = snd_dbri_prepare,
2217 .trigger = snd_dbri_trigger,
2218 .pointer = snd_dbri_pointer,
2219};
2220
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002221static int __devinit snd_dbri_pcm(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002222{
Takashi Iwai475675d2005-11-17 15:11:51 +01002223 struct snd_pcm *pcm;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002224 int err;
2225
2226 if ((err = snd_pcm_new(dbri->card,
2227 /* ID */ "sun_dbri",
2228 /* device */ 0,
2229 /* playback count */ 1,
2230 /* capture count */ 1, &pcm)) < 0)
2231 return err;
2232 snd_assert(pcm != NULL, return -EINVAL);
2233
2234 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2235 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2236
2237 pcm->private_data = dbri;
2238 pcm->info_flags = 0;
2239 strcpy(pcm->name, dbri->card->shortname);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002240
2241 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2242 SNDRV_DMA_TYPE_CONTINUOUS,
2243 snd_dma_continuous_data(GFP_KERNEL),
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002244 64 * 1024, 64 * 1024)) < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002245 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002246
2247 return 0;
2248}
2249
2250/*****************************************************************************
2251 Mixer interface
2252*****************************************************************************/
2253
Takashi Iwai475675d2005-11-17 15:11:51 +01002254static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2255 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002256{
2257 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2258 uinfo->count = 2;
2259 uinfo->value.integer.min = 0;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002260 if (kcontrol->private_value == DBRI_PLAY)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002261 uinfo->value.integer.max = DBRI_MAX_VOLUME;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002262 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002263 uinfo->value.integer.max = DBRI_MAX_GAIN;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002264 return 0;
2265}
2266
Takashi Iwai475675d2005-11-17 15:11:51 +01002267static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2268 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002269{
Takashi Iwai475675d2005-11-17 15:11:51 +01002270 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2271 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002272 snd_assert(dbri != NULL, return -EINVAL);
2273 info = &dbri->stream_info[kcontrol->private_value];
2274 snd_assert(info != NULL, return -EINVAL);
2275
2276 ucontrol->value.integer.value[0] = info->left_gain;
2277 ucontrol->value.integer.value[1] = info->right_gain;
2278 return 0;
2279}
2280
Takashi Iwai475675d2005-11-17 15:11:51 +01002281static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2282 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002283{
Takashi Iwai475675d2005-11-17 15:11:51 +01002284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002285 struct dbri_streaminfo *info =
2286 &dbri->stream_info[kcontrol->private_value];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002287 int changed = 0;
2288
2289 if (info->left_gain != ucontrol->value.integer.value[0]) {
2290 info->left_gain = ucontrol->value.integer.value[0];
2291 changed = 1;
2292 }
2293 if (info->right_gain != ucontrol->value.integer.value[1]) {
2294 info->right_gain = ucontrol->value.integer.value[1];
2295 changed = 1;
2296 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002297 if (changed) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002298 /* First mute outputs, and wait 1/8000 sec (125 us)
2299 * to make sure this takes. This avoids clicking noises.
2300 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002301 cs4215_setdata(dbri, 1);
2302 udelay(125);
2303 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002304 }
2305 return changed;
2306}
2307
Takashi Iwai475675d2005-11-17 15:11:51 +01002308static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2309 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002310{
2311 int mask = (kcontrol->private_value >> 16) & 0xff;
2312
2313 uinfo->type = (mask == 1) ?
2314 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2315 uinfo->count = 1;
2316 uinfo->value.integer.min = 0;
2317 uinfo->value.integer.max = mask;
2318 return 0;
2319}
2320
Takashi Iwai475675d2005-11-17 15:11:51 +01002321static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2322 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002323{
Takashi Iwai475675d2005-11-17 15:11:51 +01002324 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002325 int elem = kcontrol->private_value & 0xff;
2326 int shift = (kcontrol->private_value >> 8) & 0xff;
2327 int mask = (kcontrol->private_value >> 16) & 0xff;
2328 int invert = (kcontrol->private_value >> 24) & 1;
2329 snd_assert(dbri != NULL, return -EINVAL);
2330
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002331 if (elem < 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002332 ucontrol->value.integer.value[0] =
2333 (dbri->mm.data[elem] >> shift) & mask;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002334 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002335 ucontrol->value.integer.value[0] =
2336 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002337
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002338 if (invert == 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002339 ucontrol->value.integer.value[0] =
2340 mask - ucontrol->value.integer.value[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002341 return 0;
2342}
2343
Takashi Iwai475675d2005-11-17 15:11:51 +01002344static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2345 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002346{
Takashi Iwai475675d2005-11-17 15:11:51 +01002347 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002348 int elem = kcontrol->private_value & 0xff;
2349 int shift = (kcontrol->private_value >> 8) & 0xff;
2350 int mask = (kcontrol->private_value >> 16) & 0xff;
2351 int invert = (kcontrol->private_value >> 24) & 1;
2352 int changed = 0;
2353 unsigned short val;
2354 snd_assert(dbri != NULL, return -EINVAL);
2355
2356 val = (ucontrol->value.integer.value[0] & mask);
2357 if (invert == 1)
2358 val = mask - val;
2359 val <<= shift;
2360
2361 if (elem < 4) {
2362 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2363 ~(mask << shift)) | val;
2364 changed = (val != dbri->mm.data[elem]);
2365 } else {
2366 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2367 ~(mask << shift)) | val;
2368 changed = (val != dbri->mm.ctrl[elem - 4]);
2369 }
2370
2371 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2372 "mixer-value=%ld, mm-value=0x%x\n",
2373 mask, changed, ucontrol->value.integer.value[0],
2374 dbri->mm.data[elem & 3]);
2375
2376 if (changed) {
2377 /* First mute outputs, and wait 1/8000 sec (125 us)
2378 * to make sure this takes. This avoids clicking noises.
2379 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002380 cs4215_setdata(dbri, 1);
2381 udelay(125);
2382 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002383 }
2384 return changed;
2385}
2386
2387/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2388 timeslots. Shift is the bit offset in the timeslot, mask defines the
2389 number of bits. invert is a boolean for use with attenuation.
2390 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002391#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2392{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2393 .info = snd_cs4215_info_single, \
2394 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2395 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2396 ((invert) << 24) },
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002397
Takashi Iwai475675d2005-11-17 15:11:51 +01002398static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002399 {
2400 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2401 .name = "Playback Volume",
2402 .info = snd_cs4215_info_volume,
2403 .get = snd_cs4215_get_volume,
2404 .put = snd_cs4215_put_volume,
2405 .private_value = DBRI_PLAY,
2406 },
2407 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2408 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2409 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2410 {
2411 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2412 .name = "Capture Volume",
2413 .info = snd_cs4215_info_volume,
2414 .get = snd_cs4215_get_volume,
2415 .put = snd_cs4215_put_volume,
2416 .private_value = DBRI_REC,
2417 },
2418 /* FIXME: mic/line switch */
2419 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2420 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2421 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2422 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2423};
2424
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002425static int __init snd_dbri_mixer(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002426{
Takashi Iwai475675d2005-11-17 15:11:51 +01002427 struct snd_card *card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002428 int idx, err;
2429
2430 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2431
2432 card = dbri->card;
2433 strcpy(card->mixername, card->shortname);
2434
Tobias Klauser6c2d8b52006-09-29 02:00:21 -07002435 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002436 err = snd_ctl_add(card,
2437 snd_ctl_new1(&dbri_controls[idx], dbri));
2438 if (err < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002439 return err;
2440 }
2441
2442 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2443 dbri->stream_info[idx].left_gain = 0;
2444 dbri->stream_info[idx].right_gain = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002445 }
2446
2447 return 0;
2448}
2449
2450/****************************************************************************
2451 /proc interface
2452****************************************************************************/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002453static void dbri_regs_read(struct snd_info_entry *entry,
2454 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002455{
Takashi Iwai475675d2005-11-17 15:11:51 +01002456 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002457
2458 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2459 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2460 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2461 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2462}
2463
2464#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002465static void dbri_debug_read(struct snd_info_entry *entry,
Takashi Iwai475675d2005-11-17 15:11:51 +01002466 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002467{
Takashi Iwai475675d2005-11-17 15:11:51 +01002468 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002469 int pipe;
2470 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2471
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002472 for (pipe = 0; pipe < 32; pipe++) {
2473 if (pipe_active(dbri, pipe)) {
2474 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2475 snd_iprintf(buffer,
2476 "Pipe %d: %s SDP=0x%x desc=%d, "
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002477 "len=%d next %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002478 pipe,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002479 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2480 "input",
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002481 pptr->sdp, pptr->desc,
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002482 pptr->length, pptr->nextpipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002483 }
2484 }
2485}
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002486#endif
2487
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002488void snd_dbri_proc(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002489{
Takashi Iwai475675d2005-11-17 15:11:51 +01002490 struct snd_info_entry *entry;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002491
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002492 if (!snd_card_proc_new(dbri->card, "regs", &entry))
Takashi Iwaibf850202006-04-28 15:13:41 +02002493 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002494
2495#ifdef DBRI_DEBUG
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002496 if (!snd_card_proc_new(dbri->card, "debug", &entry)) {
Takashi Iwaibf850202006-04-28 15:13:41 +02002497 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
Takashi Iwai8cb7b632005-12-01 10:48:37 +01002498 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2499 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002500#endif
2501}
2502
2503/*
2504****************************************************************************
2505**************************** Initialization ********************************
2506****************************************************************************
2507*/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002508static void snd_dbri_free(struct snd_dbri *dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002509
Takashi Iwai475675d2005-11-17 15:11:51 +01002510static int __init snd_dbri_create(struct snd_card *card,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002511 struct sbus_dev *sdev,
2512 struct linux_prom_irqs *irq, int dev)
2513{
Takashi Iwai475675d2005-11-17 15:11:51 +01002514 struct snd_dbri *dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002515 int err;
2516
2517 spin_lock_init(&dbri->lock);
2518 dbri->card = card;
2519 dbri->sdev = sdev;
2520 dbri->irq = irq->pri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002521
2522 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2523 &dbri->dma_dvma);
2524 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2525
2526 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2527 dbri->dma, dbri->dma_dvma);
2528
2529 /* Map the registers into memory. */
2530 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2531 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2532 dbri->regs_size, "DBRI Registers");
2533 if (!dbri->regs) {
2534 printk(KERN_ERR "DBRI: could not allocate registers\n");
2535 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2536 (void *)dbri->dma, dbri->dma_dvma);
2537 return -EIO;
2538 }
2539
Thomas Gleixner65ca68b2006-07-01 19:29:46 -07002540 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002541 "DBRI audio", dbri);
2542 if (err) {
2543 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2544 sbus_iounmap(dbri->regs, dbri->regs_size);
2545 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2546 (void *)dbri->dma, dbri->dma_dvma);
2547 return err;
2548 }
2549
2550 /* Do low level initialization of the DBRI and CS4215 chips */
2551 dbri_initialize(dbri);
2552 err = cs4215_init(dbri);
2553 if (err) {
2554 snd_dbri_free(dbri);
2555 return err;
2556 }
2557
2558 dbri->next = dbri_list;
2559 dbri_list = dbri;
2560
2561 return 0;
2562}
2563
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002564static void snd_dbri_free(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002565{
2566 dprintk(D_GEN, "snd_dbri_free\n");
2567 dbri_reset(dbri);
2568
2569 if (dbri->irq)
2570 free_irq(dbri->irq, dbri);
2571
2572 if (dbri->regs)
2573 sbus_iounmap(dbri->regs, dbri->regs_size);
2574
2575 if (dbri->dma)
2576 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2577 (void *)dbri->dma, dbri->dma_dvma);
2578}
2579
2580static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2581{
Takashi Iwai475675d2005-11-17 15:11:51 +01002582 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002583 struct linux_prom_irqs irq;
2584 struct resource *rp;
Takashi Iwai475675d2005-11-17 15:11:51 +01002585 struct snd_card *card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002586 static int dev = 0;
2587 int err;
2588
2589 if (sdev->prom_name[9] < 'e') {
2590 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2591 sdev->prom_name[9]);
2592 return -EIO;
2593 }
2594
2595 if (dev >= SNDRV_CARDS)
2596 return -ENODEV;
2597 if (!enable[dev]) {
2598 dev++;
2599 return -ENOENT;
2600 }
2601
Martin Habets43388292005-09-10 15:39:00 +02002602 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2603 if (err < 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002604 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n",
2605 dev);
Martin Habets43388292005-09-10 15:39:00 +02002606 return -ENODEV;
2607 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002608
2609 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
Takashi Iwai475675d2005-11-17 15:11:51 +01002610 sizeof(struct snd_dbri));
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002611 if (card == NULL)
2612 return -ENOMEM;
2613
2614 strcpy(card->driver, "DBRI");
2615 strcpy(card->shortname, "Sun DBRI");
2616 rp = &sdev->resource[0];
Andrew Morton5863aa62006-07-03 00:24:22 -07002617 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002618 card->shortname,
Greg Kroah-Hartmanaa0a2dd2006-06-12 14:50:27 -07002619 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002620
2621 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2622 snd_card_free(card);
2623 return err;
2624 }
2625
Takashi Iwai475675d2005-11-17 15:11:51 +01002626 dbri = card->private_data;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002627 err = snd_dbri_pcm(dbri);
2628 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002629 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002630
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002631 err = snd_dbri_mixer(dbri);
2632 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002633 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002634
2635 /* /proc file handling */
2636 snd_dbri_proc(dbri);
2637
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002638 err = snd_card_register(card);
2639 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002640 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002641
2642 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2643 dev, dbri->regs,
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002644 dbri->irq, sdev->prom_name[9], dbri->mm.version);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002645 dev++;
2646
2647 return 0;
Takashi Iwai16dab542005-09-05 17:17:58 +02002648
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002649_err:
Takashi Iwai16dab542005-09-05 17:17:58 +02002650 snd_dbri_free(dbri);
2651 snd_card_free(card);
2652 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002653}
2654
2655/* Probe for the dbri chip and then attach the driver. */
2656static int __init dbri_init(void)
2657{
2658 struct sbus_bus *sbus;
2659 struct sbus_dev *sdev;
2660 int found = 0;
2661
2662 /* Probe each SBUS for the DBRI chip(s). */
2663 for_all_sbusdev(sdev, sbus) {
2664 /*
2665 * The version is coded in the last character
2666 */
2667 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2668 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2669 sdev->prom_name, sdev->slot);
2670
2671 if (dbri_attach(sdev->prom_node, sdev) == 0)
2672 found++;
2673 }
2674 }
2675
2676 return (found > 0) ? 0 : -EIO;
2677}
2678
2679static void __exit dbri_exit(void)
2680{
Takashi Iwai475675d2005-11-17 15:11:51 +01002681 struct snd_dbri *this = dbri_list;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002682
2683 while (this != NULL) {
Takashi Iwai475675d2005-11-17 15:11:51 +01002684 struct snd_dbri *next = this->next;
2685 struct snd_card *card = this->card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002686
2687 snd_dbri_free(this);
2688 snd_card_free(card);
2689 this = next;
2690 }
2691 dbri_list = NULL;
2692}
2693
2694module_init(dbri_init);
2695module_exit(dbri_exit);