Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Watchdog driver for Atmel AT91SAM9x processors. |
| 3 | * |
| 4 | * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * The Watchdog Timer Mode Register can be only written to once. If the |
| 14 | * timeout need to be set from Linux, be sure that the bootstrap or the |
| 15 | * bootloader doesn't write to this register. |
| 16 | */ |
| 17 | |
Joe Perches | 27c766a | 2012-02-15 15:06:19 -0800 | [diff] [blame] | 18 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 19 | |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 20 | #include <linux/errno.h> |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 21 | #include <linux/init.h> |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 22 | #include <linux/interrupt.h> |
Andrew Victor | 2af29b7 | 2009-02-11 21:23:10 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 24 | #include <linux/kernel.h> |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 25 | #include <linux/module.h> |
| 26 | #include <linux/moduleparam.h> |
| 27 | #include <linux/platform_device.h> |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 28 | #include <linux/reboot.h> |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 29 | #include <linux/types.h> |
| 30 | #include <linux/watchdog.h> |
| 31 | #include <linux/jiffies.h> |
| 32 | #include <linux/timer.h> |
| 33 | #include <linux/bitops.h> |
| 34 | #include <linux/uaccess.h> |
Fabio Porcedda | be49bba | 2012-11-12 09:37:25 +0100 | [diff] [blame] | 35 | #include <linux/of.h> |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 36 | #include <linux/of_irq.h> |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 37 | |
Jean-Christophe Plagniol-Villard | e7b3914 | 2011-07-15 01:52:05 +0200 | [diff] [blame] | 38 | #include "at91sam9_wdt.h" |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 39 | |
| 40 | #define DRV_NAME "AT91SAM9 Watchdog" |
| 41 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 42 | #define wdt_read(wdt, field) \ |
| 43 | __raw_readl((wdt)->base + (field)) |
| 44 | #define wdt_write(wtd, field, val) \ |
| 45 | __raw_writel((val), (wdt)->base + (field)) |
Jean-Christophe PLAGNIOL-VILLARD | c1c30a2 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 46 | |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 47 | /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz, |
| 48 | * use this to convert a watchdog |
| 49 | * value from/to milliseconds. |
| 50 | */ |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 51 | #define ticks_to_hz_rounddown(t) ((((t) + 1) * HZ) >> 8) |
| 52 | #define ticks_to_hz_roundup(t) (((((t) + 1) * HZ) + 255) >> 8) |
| 53 | #define ticks_to_secs(t) (((t) + 1) >> 8) |
Boris BREZILLON | 1444797 | 2013-11-03 18:52:42 +0100 | [diff] [blame] | 54 | #define secs_to_ticks(s) ((s) ? (((s) << 8) - 1) : 0) |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 55 | |
| 56 | #define WDT_MR_RESET 0x3FFF2FFF |
| 57 | |
| 58 | /* Watchdog max counter value in ticks */ |
| 59 | #define WDT_COUNTER_MAX_TICKS 0xFFF |
| 60 | |
| 61 | /* Watchdog max delta/value in secs */ |
| 62 | #define WDT_COUNTER_MAX_SECS ticks_to_secs(WDT_COUNTER_MAX_TICKS) |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 63 | |
| 64 | /* Hardware timeout in seconds */ |
| 65 | #define WDT_HW_TIMEOUT 2 |
| 66 | |
| 67 | /* Timer heartbeat (500ms) */ |
| 68 | #define WDT_TIMEOUT (HZ/2) |
| 69 | |
| 70 | /* User land timeout */ |
| 71 | #define WDT_HEARTBEAT 15 |
Fabio Porcedda | c1fd5f6 | 2013-02-14 09:14:25 +0100 | [diff] [blame] | 72 | static int heartbeat; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 73 | module_param(heartbeat, int, 0); |
| 74 | MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. " |
| 75 | "(default = " __MODULE_STRING(WDT_HEARTBEAT) ")"); |
| 76 | |
Wim Van Sebroeck | 86a1e18 | 2012-03-05 16:51:11 +0100 | [diff] [blame] | 77 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 78 | module_param(nowayout, bool, 0); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 79 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " |
| 80 | "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 81 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 82 | #define to_wdt(wdd) container_of(wdd, struct at91wdt, wdd) |
| 83 | struct at91wdt { |
| 84 | struct watchdog_device wdd; |
Jean-Christophe PLAGNIOL-VILLARD | c1c30a2 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 85 | void __iomem *base; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 86 | unsigned long next_heartbeat; /* the next_heartbeat for the timer */ |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 87 | struct timer_list timer; /* The timer that pings the watchdog */ |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 88 | u32 mr; |
| 89 | u32 mr_mask; |
| 90 | unsigned long heartbeat; /* WDT heartbeat in jiffies */ |
| 91 | bool nowayout; |
| 92 | unsigned int irq; |
| 93 | }; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 94 | |
| 95 | /* ......................................................................... */ |
| 96 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 97 | static irqreturn_t wdt_interrupt(int irq, void *dev_id) |
| 98 | { |
| 99 | struct at91wdt *wdt = (struct at91wdt *)dev_id; |
| 100 | |
| 101 | if (wdt_read(wdt, AT91_WDT_SR)) { |
| 102 | pr_crit("at91sam9 WDT software reset\n"); |
| 103 | emergency_restart(); |
| 104 | pr_crit("Reboot didn't ?????\n"); |
| 105 | } |
| 106 | |
| 107 | return IRQ_HANDLED; |
| 108 | } |
| 109 | |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 110 | /* |
| 111 | * Reload the watchdog timer. (ie, pat the watchdog) |
| 112 | */ |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 113 | static inline void at91_wdt_reset(struct at91wdt *wdt) |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 114 | { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 115 | wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /* |
| 119 | * Timer tick |
| 120 | */ |
| 121 | static void at91_ping(unsigned long data) |
| 122 | { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 123 | struct at91wdt *wdt = (struct at91wdt *)data; |
| 124 | if (time_before(jiffies, wdt->next_heartbeat) || |
| 125 | !watchdog_active(&wdt->wdd)) { |
| 126 | at91_wdt_reset(wdt); |
| 127 | mod_timer(&wdt->timer, jiffies + wdt->heartbeat); |
| 128 | } else { |
Joe Perches | 27c766a | 2012-02-15 15:06:19 -0800 | [diff] [blame] | 129 | pr_crit("I will reset your machine !\n"); |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 130 | } |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 131 | } |
| 132 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 133 | static int at91_wdt_start(struct watchdog_device *wdd) |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 134 | { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 135 | struct at91wdt *wdt = to_wdt(wdd); |
| 136 | /* calculate when the next userspace timeout will be */ |
| 137 | wdt->next_heartbeat = jiffies + wdd->timeout * HZ; |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 138 | return 0; |
| 139 | } |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 140 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 141 | static int at91_wdt_stop(struct watchdog_device *wdd) |
| 142 | { |
| 143 | /* The watchdog timer hardware can not be stopped... */ |
| 144 | return 0; |
| 145 | } |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 146 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 147 | static int at91_wdt_set_timeout(struct watchdog_device *wdd, unsigned int new_timeout) |
| 148 | { |
| 149 | wdd->timeout = new_timeout; |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 150 | return at91_wdt_start(wdd); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 151 | } |
| 152 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 153 | static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt) |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 154 | { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 155 | u32 tmp; |
| 156 | u32 delta; |
| 157 | u32 value; |
| 158 | int err; |
| 159 | u32 mask = wdt->mr_mask; |
| 160 | unsigned long min_heartbeat = 1; |
Boris BREZILLON | f72fa00 | 2013-11-03 18:52:44 +0100 | [diff] [blame] | 161 | unsigned long max_heartbeat; |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 162 | struct device *dev = &pdev->dev; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 163 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 164 | tmp = wdt_read(wdt, AT91_WDT_MR); |
| 165 | if ((tmp & mask) != (wdt->mr & mask)) { |
| 166 | if (tmp == WDT_MR_RESET) { |
| 167 | wdt_write(wdt, AT91_WDT_MR, wdt->mr); |
| 168 | tmp = wdt_read(wdt, AT91_WDT_MR); |
| 169 | } |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 170 | } |
| 171 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 172 | if (tmp & AT91_WDT_WDDIS) { |
| 173 | if (wdt->mr & AT91_WDT_WDDIS) |
| 174 | return 0; |
| 175 | dev_err(dev, "watchdog is disabled\n"); |
| 176 | return -EINVAL; |
| 177 | } |
| 178 | |
| 179 | value = tmp & AT91_WDT_WDV; |
| 180 | delta = (tmp & AT91_WDT_WDD) >> 16; |
| 181 | |
| 182 | if (delta < value) |
| 183 | min_heartbeat = ticks_to_hz_roundup(value - delta); |
| 184 | |
Boris BREZILLON | f72fa00 | 2013-11-03 18:52:44 +0100 | [diff] [blame] | 185 | max_heartbeat = ticks_to_hz_rounddown(value); |
| 186 | if (!max_heartbeat) { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 187 | dev_err(dev, |
| 188 | "heartbeat is too small for the system to handle it correctly\n"); |
| 189 | return -EINVAL; |
| 190 | } |
| 191 | |
Boris BREZILLON | f72fa00 | 2013-11-03 18:52:44 +0100 | [diff] [blame] | 192 | /* |
| 193 | * Try to reset the watchdog counter 4 or 2 times more often than |
| 194 | * actually requested, to avoid spurious watchdog reset. |
| 195 | * If this is not possible because of the min_heartbeat value, reset |
| 196 | * it at the min_heartbeat period. |
| 197 | */ |
| 198 | if ((max_heartbeat / 4) >= min_heartbeat) |
| 199 | wdt->heartbeat = max_heartbeat / 4; |
| 200 | else if ((max_heartbeat / 2) >= min_heartbeat) |
| 201 | wdt->heartbeat = max_heartbeat / 2; |
| 202 | else |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 203 | wdt->heartbeat = min_heartbeat; |
Boris BREZILLON | f72fa00 | 2013-11-03 18:52:44 +0100 | [diff] [blame] | 204 | |
| 205 | if (max_heartbeat < min_heartbeat + 4) |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 206 | dev_warn(dev, |
| 207 | "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n"); |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 208 | |
| 209 | if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) { |
| 210 | err = request_irq(wdt->irq, wdt_interrupt, |
| 211 | IRQF_SHARED | IRQF_IRQPOLL, |
| 212 | pdev->name, wdt); |
| 213 | if (err) |
| 214 | return err; |
| 215 | } |
| 216 | |
| 217 | if ((tmp & wdt->mr_mask) != (wdt->mr & wdt->mr_mask)) |
| 218 | dev_warn(dev, |
| 219 | "watchdog already configured differently (mr = %x expecting %x)\n", |
| 220 | tmp & wdt->mr_mask, wdt->mr & wdt->mr_mask); |
| 221 | |
| 222 | setup_timer(&wdt->timer, at91_ping, (unsigned long)wdt); |
Boris BREZILLON | a04c3f0 | 2013-11-03 18:52:43 +0100 | [diff] [blame] | 223 | |
| 224 | /* |
| 225 | * Use min_heartbeat the first time to avoid spurious watchdog reset: |
| 226 | * we don't know for how long the watchdog counter is running, and |
| 227 | * - resetting it right now might trigger a watchdog fault reset |
| 228 | * - waiting for heartbeat time might lead to a watchdog timeout |
| 229 | * reset |
| 230 | */ |
| 231 | mod_timer(&wdt->timer, jiffies + min_heartbeat); |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 232 | |
| 233 | /* Try to set timeout from device tree first */ |
| 234 | if (watchdog_init_timeout(&wdt->wdd, 0, dev)) |
| 235 | watchdog_init_timeout(&wdt->wdd, heartbeat, dev); |
| 236 | watchdog_set_nowayout(&wdt->wdd, wdt->nowayout); |
| 237 | err = watchdog_register_device(&wdt->wdd); |
| 238 | if (err) |
| 239 | goto out_stop_timer; |
| 240 | |
| 241 | wdt->next_heartbeat = jiffies + wdt->wdd.timeout * HZ; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 242 | |
| 243 | return 0; |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 244 | |
| 245 | out_stop_timer: |
| 246 | del_timer(&wdt->timer); |
| 247 | return err; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 248 | } |
| 249 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 250 | /* ......................................................................... */ |
| 251 | |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 252 | static const struct watchdog_info at91_wdt_info = { |
| 253 | .identity = DRV_NAME, |
Wim Van Sebroeck | e73a780 | 2009-05-11 18:33:00 +0000 | [diff] [blame] | 254 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | |
| 255 | WDIOF_MAGICCLOSE, |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 256 | }; |
| 257 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 258 | static const struct watchdog_ops at91_wdt_ops = { |
| 259 | .owner = THIS_MODULE, |
| 260 | .start = at91_wdt_start, |
| 261 | .stop = at91_wdt_stop, |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 262 | .set_timeout = at91_wdt_set_timeout, |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 263 | }; |
| 264 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 265 | #if defined(CONFIG_OF) |
| 266 | static int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) |
| 267 | { |
| 268 | u32 min = 0; |
| 269 | u32 max = WDT_COUNTER_MAX_SECS; |
| 270 | const char *tmp; |
| 271 | |
| 272 | /* Get the interrupts property */ |
| 273 | wdt->irq = irq_of_parse_and_map(np, 0); |
| 274 | if (!wdt->irq) |
| 275 | dev_warn(wdt->wdd.parent, "failed to get IRQ from DT\n"); |
| 276 | |
| 277 | if (!of_property_read_u32_index(np, "atmel,max-heartbeat-sec", 0, |
| 278 | &max)) { |
| 279 | if (!max || max > WDT_COUNTER_MAX_SECS) |
| 280 | max = WDT_COUNTER_MAX_SECS; |
| 281 | |
| 282 | if (!of_property_read_u32_index(np, "atmel,min-heartbeat-sec", |
| 283 | 0, &min)) { |
| 284 | if (min >= max) |
| 285 | min = max - 1; |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | min = secs_to_ticks(min); |
| 290 | max = secs_to_ticks(max); |
| 291 | |
| 292 | wdt->mr_mask = 0x3FFFFFFF; |
| 293 | wdt->mr = 0; |
| 294 | if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) && |
| 295 | !strcmp(tmp, "software")) { |
| 296 | wdt->mr |= AT91_WDT_WDFIEN; |
| 297 | wdt->mr_mask &= ~AT91_WDT_WDRPROC; |
| 298 | } else { |
| 299 | wdt->mr |= AT91_WDT_WDRSTEN; |
| 300 | } |
| 301 | |
| 302 | if (!of_property_read_string(np, "atmel,reset-type", &tmp) && |
| 303 | !strcmp(tmp, "proc")) |
| 304 | wdt->mr |= AT91_WDT_WDRPROC; |
| 305 | |
| 306 | if (of_property_read_bool(np, "atmel,disable")) { |
| 307 | wdt->mr |= AT91_WDT_WDDIS; |
| 308 | wdt->mr_mask &= AT91_WDT_WDDIS; |
| 309 | } |
| 310 | |
| 311 | if (of_property_read_bool(np, "atmel,idle-halt")) |
| 312 | wdt->mr |= AT91_WDT_WDIDLEHLT; |
| 313 | |
| 314 | if (of_property_read_bool(np, "atmel,dbg-halt")) |
| 315 | wdt->mr |= AT91_WDT_WDDBGHLT; |
| 316 | |
| 317 | wdt->mr |= max | ((max - min) << 16); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | #else |
| 322 | static inline int of_at91wdt_init(struct device_node *np, struct at91wdt *wdt) |
| 323 | { |
| 324 | return 0; |
| 325 | } |
| 326 | #endif |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 327 | |
| 328 | static int __init at91wdt_probe(struct platform_device *pdev) |
| 329 | { |
Jean-Christophe PLAGNIOL-VILLARD | c1c30a2 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 330 | struct resource *r; |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 331 | int err; |
| 332 | struct at91wdt *wdt; |
| 333 | |
| 334 | wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); |
| 335 | if (!wdt) |
| 336 | return -ENOMEM; |
| 337 | |
| 338 | wdt->mr = (WDT_HW_TIMEOUT * 256) | AT91_WDT_WDRSTEN | AT91_WDT_WDD | |
| 339 | AT91_WDT_WDDBGHLT | AT91_WDT_WDIDLEHLT; |
| 340 | wdt->mr_mask = 0x3FFFFFFF; |
| 341 | wdt->nowayout = nowayout; |
| 342 | wdt->wdd.parent = &pdev->dev; |
| 343 | wdt->wdd.info = &at91_wdt_info; |
| 344 | wdt->wdd.ops = &at91_wdt_ops; |
| 345 | wdt->wdd.timeout = WDT_HEARTBEAT; |
| 346 | wdt->wdd.min_timeout = 1; |
| 347 | wdt->wdd.max_timeout = 0xFFFF; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 348 | |
Jean-Christophe PLAGNIOL-VILLARD | c1c30a2 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 349 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 350 | wdt->base = devm_ioremap_resource(&pdev->dev, r); |
| 351 | if (IS_ERR(wdt->base)) |
| 352 | return PTR_ERR(wdt->base); |
| 353 | |
| 354 | if (pdev->dev.of_node) { |
| 355 | err = of_at91wdt_init(pdev->dev.of_node, wdt); |
| 356 | if (err) |
| 357 | return err; |
Jean-Christophe PLAGNIOL-VILLARD | c1c30a2 | 2011-11-02 01:43:31 +0800 | [diff] [blame] | 358 | } |
| 359 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 360 | err = at91_wdt_init(pdev, wdt); |
| 361 | if (err) |
| 362 | return err; |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 363 | |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 364 | platform_set_drvdata(pdev, wdt); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 365 | |
Joe Perches | 27c766a | 2012-02-15 15:06:19 -0800 | [diff] [blame] | 366 | pr_info("enabled (heartbeat=%d sec, nowayout=%d)\n", |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 367 | wdt->wdd.timeout, wdt->nowayout); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 368 | |
| 369 | return 0; |
| 370 | } |
| 371 | |
| 372 | static int __exit at91wdt_remove(struct platform_device *pdev) |
| 373 | { |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 374 | struct at91wdt *wdt = platform_get_drvdata(pdev); |
| 375 | watchdog_unregister_device(&wdt->wdd); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 376 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 377 | pr_warn("I quit now, hardware will probably reboot!\n"); |
Boris BREZILLON | 5161b31 | 2013-10-04 09:24:12 +0200 | [diff] [blame] | 378 | del_timer(&wdt->timer); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 379 | |
Wenyou Yang | 490ac7af | 2013-02-01 15:06:21 +0800 | [diff] [blame] | 380 | return 0; |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 381 | } |
| 382 | |
Fabio Porcedda | be49bba | 2012-11-12 09:37:25 +0100 | [diff] [blame] | 383 | #if defined(CONFIG_OF) |
Arnd Bergmann | 6c41e47 | 2013-01-25 14:14:27 +0000 | [diff] [blame] | 384 | static const struct of_device_id at91_wdt_dt_ids[] = { |
Fabio Porcedda | be49bba | 2012-11-12 09:37:25 +0100 | [diff] [blame] | 385 | { .compatible = "atmel,at91sam9260-wdt" }, |
| 386 | { /* sentinel */ } |
| 387 | }; |
| 388 | |
| 389 | MODULE_DEVICE_TABLE(of, at91_wdt_dt_ids); |
| 390 | #endif |
| 391 | |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 392 | static struct platform_driver at91wdt_driver = { |
| 393 | .remove = __exit_p(at91wdt_remove), |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 394 | .driver = { |
| 395 | .name = "at91_wdt", |
| 396 | .owner = THIS_MODULE, |
Fabio Porcedda | be49bba | 2012-11-12 09:37:25 +0100 | [diff] [blame] | 397 | .of_match_table = of_match_ptr(at91_wdt_dt_ids), |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 398 | }, |
| 399 | }; |
| 400 | |
Fabio Porcedda | 1cb9204 | 2013-01-09 12:15:27 +0100 | [diff] [blame] | 401 | module_platform_driver_probe(at91wdt_driver, at91wdt_probe); |
Renaud CERRATO | e6bb42e | 2008-06-23 17:05:49 +0200 | [diff] [blame] | 402 | |
| 403 | MODULE_AUTHOR("Renaud CERRATO <r.cerrato@til-technologies.fr>"); |
| 404 | MODULE_DESCRIPTION("Watchdog driver for Atmel AT91SAM9x processors"); |
| 405 | MODULE_LICENSE("GPL"); |