Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 1 | /* |
| 2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port |
| 3 | * |
| 4 | * Copyright (C) 2008 Nokia Corporation |
| 5 | * |
Jarkko Nikula | b08f7a6 | 2009-04-17 14:42:26 +0300 | [diff] [blame] | 6 | * Contact: Jarkko Nikula <jhnikula@gmail.com> |
| 7 | * Peter Ujfalusi <peter.ujfalusi@nokia.com> |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * version 2 as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 21 | * 02110-1301 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/device.h> |
| 28 | #include <sound/core.h> |
| 29 | #include <sound/pcm.h> |
| 30 | #include <sound/pcm_params.h> |
| 31 | #include <sound/initval.h> |
| 32 | #include <sound/soc.h> |
| 33 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 34 | #include <plat/dma.h> |
| 35 | #include <plat/mcbsp.h> |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 36 | #include "omap-mcbsp.h" |
| 37 | #include "omap-pcm.h" |
| 38 | |
Jarkko Nikula | 0b60485 | 2008-11-12 17:05:51 +0200 | [diff] [blame] | 39 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 40 | |
Ilkka Koskinen | 83905c1 | 2010-02-22 12:21:12 +0000 | [diff] [blame] | 41 | #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \ |
| 42 | xhandler_get, xhandler_put) \ |
| 43 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
| 44 | .info = omap_mcbsp_st_info_volsw, \ |
| 45 | .get = xhandler_get, .put = xhandler_put, \ |
| 46 | .private_value = (unsigned long) &(struct soc_mixer_control) \ |
| 47 | {.min = xmin, .max = xmax} } |
| 48 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 49 | struct omap_mcbsp_data { |
| 50 | unsigned int bus_id; |
| 51 | struct omap_mcbsp_reg_cfg regs; |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 52 | unsigned int fmt; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 53 | /* |
| 54 | * Flags indicating is the bus already activated and configured by |
| 55 | * another substream |
| 56 | */ |
| 57 | int active; |
| 58 | int configured; |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 59 | unsigned int in_freq; |
| 60 | int clk_div; |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 61 | int wlen; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id) |
| 65 | |
| 66 | static struct omap_mcbsp_data mcbsp_data[NUM_LINKS]; |
| 67 | |
| 68 | /* |
| 69 | * Stream DMA parameters. DMA request line and port address are set runtime |
| 70 | * since they are different between OMAP1 and later OMAPs |
| 71 | */ |
Jarkko Nikula | 2e89713 | 2008-10-09 15:57:21 +0300 | [diff] [blame] | 72 | static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 73 | |
| 74 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) |
| 75 | static const int omap1_dma_reqs[][2] = { |
| 76 | { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX }, |
| 77 | { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX }, |
| 78 | { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX }, |
| 79 | }; |
| 80 | static const unsigned long omap1_mcbsp_port[][2] = { |
| 81 | { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, |
| 82 | OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, |
| 83 | { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, |
| 84 | OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, |
| 85 | { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1, |
| 86 | OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 }, |
| 87 | }; |
| 88 | #else |
| 89 | static const int omap1_dma_reqs[][2] = {}; |
| 90 | static const unsigned long omap1_mcbsp_port[][2] = {}; |
| 91 | #endif |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 92 | |
Tony Lindgren | a8eb7ca | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 93 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 94 | static const int omap24xx_dma_reqs[][2] = { |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 95 | { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, |
| 96 | { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, |
Tony Lindgren | a8eb7ca | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 97 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 98 | { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, |
| 99 | { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, |
| 100 | { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, |
| 101 | #endif |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 102 | }; |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 103 | #else |
| 104 | static const int omap24xx_dma_reqs[][2] = {}; |
| 105 | #endif |
| 106 | |
| 107 | #if defined(CONFIG_ARCH_OMAP2420) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 108 | static const unsigned long omap2420_mcbsp_port[][2] = { |
| 109 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, |
| 110 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, |
| 111 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, |
| 112 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, |
| 113 | }; |
| 114 | #else |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 115 | static const unsigned long omap2420_mcbsp_port[][2] = {}; |
| 116 | #endif |
| 117 | |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 118 | #if defined(CONFIG_ARCH_OMAP2430) |
| 119 | static const unsigned long omap2430_mcbsp_port[][2] = { |
| 120 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, |
| 121 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, |
| 122 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, |
| 123 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, |
| 124 | { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, |
| 125 | OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, |
| 126 | { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, |
| 127 | OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, |
| 128 | { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, |
| 129 | OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, |
| 130 | }; |
| 131 | #else |
| 132 | static const unsigned long omap2430_mcbsp_port[][2] = {}; |
| 133 | #endif |
| 134 | |
Tony Lindgren | a8eb7ca | 2010-02-12 12:26:48 -0800 | [diff] [blame] | 135 | #if defined(CONFIG_ARCH_OMAP3) |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 136 | static const unsigned long omap34xx_mcbsp_port[][2] = { |
| 137 | { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, |
| 138 | OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, |
| 139 | { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, |
| 140 | OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, |
| 141 | { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, |
| 142 | OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, |
| 143 | { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, |
| 144 | OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, |
| 145 | { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, |
| 146 | OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, |
| 147 | }; |
| 148 | #else |
| 149 | static const unsigned long omap34xx_mcbsp_port[][2] = {}; |
| 150 | #endif |
| 151 | |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 152 | static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) |
| 153 | { |
| 154 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 155 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 156 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 157 | struct omap_pcm_dma_data *dma_data; |
Eduardo Valentin | a0a499c | 2009-08-20 16:18:26 +0300 | [diff] [blame] | 158 | int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id); |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 159 | int words; |
Eduardo Valentin | a0a499c | 2009-08-20 16:18:26 +0300 | [diff] [blame] | 160 | |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 161 | dma_data = snd_soc_dai_get_dma_data(rtd->dai->cpu_dai, substream); |
| 162 | |
Eduardo Valentin | a0a499c | 2009-08-20 16:18:26 +0300 | [diff] [blame] | 163 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ |
| 164 | if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 165 | /* |
| 166 | * Configure McBSP threshold based on either: |
| 167 | * packet_size, when the sDMA is in packet mode, or |
| 168 | * based on the period size. |
| 169 | */ |
| 170 | if (dma_data->packet_size) |
| 171 | words = dma_data->packet_size; |
| 172 | else |
| 173 | words = snd_pcm_lib_period_bytes(substream) / |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 174 | (mcbsp_data->wlen / 8); |
Eduardo Valentin | a0a499c | 2009-08-20 16:18:26 +0300 | [diff] [blame] | 175 | else |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 176 | words = 1; |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 177 | |
| 178 | /* Configure McBSP internal buffer usage */ |
| 179 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 180 | omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words); |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 181 | else |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 182 | omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words); |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 183 | } |
| 184 | |
Peter Ujfalusi | ddc29b0 | 2010-06-03 07:39:36 +0300 | [diff] [blame] | 185 | static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params, |
| 186 | struct snd_pcm_hw_rule *rule) |
| 187 | { |
| 188 | struct snd_interval *buffer_size = hw_param_interval(params, |
| 189 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE); |
| 190 | struct snd_interval *channels = hw_param_interval(params, |
| 191 | SNDRV_PCM_HW_PARAM_CHANNELS); |
| 192 | struct omap_mcbsp_data *mcbsp_data = rule->private; |
| 193 | struct snd_interval frames; |
| 194 | int size; |
| 195 | |
| 196 | snd_interval_any(&frames); |
| 197 | size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id); |
| 198 | |
| 199 | frames.min = size / channels->min; |
| 200 | frames.integer = 1; |
| 201 | return snd_interval_refine(buffer_size, &frames); |
| 202 | } |
| 203 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 204 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, |
| 205 | struct snd_soc_dai *dai) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 206 | { |
| 207 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 208 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 209 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 210 | int bus_id = mcbsp_data->bus_id; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 211 | int err = 0; |
| 212 | |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 213 | if (!cpu_dai->active) |
| 214 | err = omap_mcbsp_request(bus_id); |
| 215 | |
Peter Ujfalusi | ddc29b0 | 2010-06-03 07:39:36 +0300 | [diff] [blame] | 216 | /* |
| 217 | * OMAP3 McBSP FIFO is word structured. |
| 218 | * McBSP2 has 1024 + 256 = 1280 word long buffer, |
| 219 | * McBSP1,3,4,5 has 128 word long buffer |
| 220 | * This means that the size of the FIFO depends on the sample format. |
| 221 | * For example on McBSP3: |
| 222 | * 16bit samples: size is 128 * 2 = 256 bytes |
| 223 | * 32bit samples: size is 128 * 4 = 512 bytes |
| 224 | * It is simpler to place constraint for buffer and period based on |
| 225 | * channels. |
| 226 | * McBSP3 as example again (16 or 32 bit samples): |
| 227 | * 1 channel (mono): size is 128 frames (128 words) |
| 228 | * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words) |
| 229 | * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words) |
| 230 | */ |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 231 | if (cpu_is_omap343x()) { |
Jarkko Nikula | 6984992 | 2009-03-27 15:32:01 +0200 | [diff] [blame] | 232 | /* |
Peter Ujfalusi | 998a8a6 | 2010-07-29 09:51:28 +0300 | [diff] [blame] | 233 | * Rule for the buffer size. We should not allow |
Peter Ujfalusi | ddc29b0 | 2010-06-03 07:39:36 +0300 | [diff] [blame] | 234 | * smaller buffer than the FIFO size to avoid underruns |
| 235 | */ |
| 236 | snd_pcm_hw_rule_add(substream->runtime, 0, |
| 237 | SNDRV_PCM_HW_PARAM_CHANNELS, |
| 238 | omap_mcbsp_hwrule_min_buffersize, |
| 239 | mcbsp_data, |
| 240 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1); |
| 241 | |
Peter Ujfalusi | 998a8a6 | 2010-07-29 09:51:28 +0300 | [diff] [blame] | 242 | /* Make sure, that the period size is always even */ |
| 243 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
| 244 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 245 | } |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 246 | |
| 247 | return err; |
| 248 | } |
| 249 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 250 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, |
| 251 | struct snd_soc_dai *dai) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 252 | { |
| 253 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 254 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 255 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 256 | |
| 257 | if (!cpu_dai->active) { |
| 258 | omap_mcbsp_free(mcbsp_data->bus_id); |
| 259 | mcbsp_data->configured = 0; |
| 260 | } |
| 261 | } |
| 262 | |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 263 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
| 264 | struct snd_soc_dai *dai) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 265 | { |
| 266 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 267 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 268 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
Jarkko Nikula | c12abc0 | 2009-08-07 09:59:47 +0300 | [diff] [blame] | 269 | int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 270 | |
| 271 | switch (cmd) { |
| 272 | case SNDRV_PCM_TRIGGER_START: |
| 273 | case SNDRV_PCM_TRIGGER_RESUME: |
| 274 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
Jarkko Nikula | c12abc0 | 2009-08-07 09:59:47 +0300 | [diff] [blame] | 275 | mcbsp_data->active++; |
| 276 | omap_mcbsp_start(mcbsp_data->bus_id, play, !play); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 277 | break; |
| 278 | |
| 279 | case SNDRV_PCM_TRIGGER_STOP: |
| 280 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 281 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
Jarkko Nikula | c12abc0 | 2009-08-07 09:59:47 +0300 | [diff] [blame] | 282 | omap_mcbsp_stop(mcbsp_data->bus_id, play, !play); |
| 283 | mcbsp_data->active--; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 284 | break; |
| 285 | default: |
| 286 | err = -EINVAL; |
| 287 | } |
| 288 | |
| 289 | return err; |
| 290 | } |
| 291 | |
Peter Ujfalusi | 75581d2 | 2010-03-03 15:08:09 +0200 | [diff] [blame] | 292 | static snd_pcm_sframes_t omap_mcbsp_dai_delay( |
| 293 | struct snd_pcm_substream *substream, |
| 294 | struct snd_soc_dai *dai) |
| 295 | { |
| 296 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
| 297 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
| 298 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 299 | u16 fifo_use; |
| 300 | snd_pcm_sframes_t delay; |
| 301 | |
| 302 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 303 | fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id); |
| 304 | else |
| 305 | fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id); |
| 306 | |
| 307 | /* |
| 308 | * Divide the used locations with the channel count to get the |
| 309 | * FIFO usage in samples (don't care about partial samples in the |
| 310 | * buffer). |
| 311 | */ |
| 312 | delay = fifo_use / substream->runtime->channels; |
| 313 | |
| 314 | return delay; |
| 315 | } |
| 316 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 317 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, |
Mark Brown | dee89c4 | 2008-11-18 22:11:38 +0000 | [diff] [blame] | 318 | struct snd_pcm_hw_params *params, |
| 319 | struct snd_soc_dai *dai) |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 320 | { |
| 321 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 322 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 323 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 324 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
Peter Ujfalusi | 81ec027 | 2010-07-29 09:51:26 +0300 | [diff] [blame] | 325 | struct omap_pcm_dma_data *dma_data; |
| 326 | int dma, bus_id = mcbsp_data->bus_id; |
Eduardo Valentin | caebc0c | 2009-08-20 16:18:25 +0300 | [diff] [blame] | 327 | int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT; |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 328 | int pkt_size = 0; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 329 | unsigned long port; |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 330 | unsigned int format, div, framesize, master; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 331 | |
Peter Ujfalusi | 81ec027 | 2010-07-29 09:51:26 +0300 | [diff] [blame] | 332 | dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream]; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 333 | if (cpu_class_is_omap1()) { |
| 334 | dma = omap1_dma_reqs[bus_id][substream->stream]; |
| 335 | port = omap1_mcbsp_port[bus_id][substream->stream]; |
| 336 | } else if (cpu_is_omap2420()) { |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 337 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 338 | port = omap2420_mcbsp_port[bus_id][substream->stream]; |
Jarkko Nikula | 406e2c4 | 2008-10-09 15:57:20 +0300 | [diff] [blame] | 339 | } else if (cpu_is_omap2430()) { |
| 340 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; |
| 341 | port = omap2430_mcbsp_port[bus_id][substream->stream]; |
| 342 | } else if (cpu_is_omap343x()) { |
| 343 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; |
| 344 | port = omap34xx_mcbsp_port[bus_id][substream->stream]; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 345 | } else { |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 346 | return -ENODEV; |
| 347 | } |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 348 | switch (params_format(params)) { |
| 349 | case SNDRV_PCM_FORMAT_S16_LE: |
Peter Ujfalusi | 81ec027 | 2010-07-29 09:51:26 +0300 | [diff] [blame] | 350 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S16; |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 351 | wlen = 16; |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 352 | break; |
| 353 | case SNDRV_PCM_FORMAT_S32_LE: |
Peter Ujfalusi | 81ec027 | 2010-07-29 09:51:26 +0300 | [diff] [blame] | 354 | dma_data->data_type = OMAP_DMA_DATA_TYPE_S32; |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 355 | wlen = 32; |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 356 | break; |
| 357 | default: |
| 358 | return -EINVAL; |
| 359 | } |
Peter Ujfalusi | 15d0143 | 2010-07-29 09:51:25 +0300 | [diff] [blame] | 360 | if (cpu_is_omap343x()) { |
| 361 | dma_data->set_threshold = omap_mcbsp_set_threshold; |
| 362 | /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */ |
| 363 | if (omap_mcbsp_get_dma_op_mode(bus_id) == |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 364 | MCBSP_DMA_MODE_THRESHOLD) { |
| 365 | int period_words, max_thrsh; |
| 366 | |
| 367 | period_words = params_period_bytes(params) / (wlen / 8); |
| 368 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 369 | max_thrsh = omap_mcbsp_get_max_tx_threshold( |
| 370 | mcbsp_data->bus_id); |
| 371 | else |
| 372 | max_thrsh = omap_mcbsp_get_max_rx_threshold( |
| 373 | mcbsp_data->bus_id); |
| 374 | /* |
| 375 | * If the period contains less or equal number of words, |
| 376 | * we are using the original threshold mode setup: |
| 377 | * McBSP threshold = sDMA frame size = period_size |
| 378 | * Otherwise we switch to sDMA packet mode: |
| 379 | * McBSP threshold = sDMA packet size |
| 380 | * sDMA frame size = period size |
| 381 | */ |
| 382 | if (period_words > max_thrsh) { |
| 383 | int divider = 0; |
| 384 | |
| 385 | /* |
| 386 | * Look for the biggest threshold value, which |
| 387 | * divides the period size evenly. |
| 388 | */ |
| 389 | divider = period_words / max_thrsh; |
| 390 | if (period_words % max_thrsh) |
| 391 | divider++; |
| 392 | while (period_words % divider && |
| 393 | divider < period_words) |
| 394 | divider++; |
| 395 | if (divider == period_words) |
| 396 | return -EINVAL; |
| 397 | |
| 398 | pkt_size = period_words / divider; |
| 399 | sync_mode = OMAP_DMA_SYNC_PACKET; |
| 400 | } else { |
| 401 | sync_mode = OMAP_DMA_SYNC_FRAME; |
| 402 | } |
| 403 | } |
Peter Ujfalusi | 15d0143 | 2010-07-29 09:51:25 +0300 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback"; |
| 407 | dma_data->dma_req = dma; |
| 408 | dma_data->port_addr = port; |
| 409 | dma_data->sync_mode = sync_mode; |
Peter Ujfalusi | cf80e15 | 2010-07-29 09:51:27 +0300 | [diff] [blame] | 410 | dma_data->packet_size = pkt_size; |
Daniel Mack | fd23b7d | 2010-03-19 14:52:55 +0000 | [diff] [blame] | 411 | |
Peter Ujfalusi | 81ec027 | 2010-07-29 09:51:26 +0300 | [diff] [blame] | 412 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 413 | |
| 414 | if (mcbsp_data->configured) { |
| 415 | /* McBSP already configured by another stream */ |
| 416 | return 0; |
| 417 | } |
| 418 | |
Peter Ujfalusi | c29b206 | 2009-04-15 15:38:55 +0300 | [diff] [blame] | 419 | format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
| 420 | wpf = channels = params_channels(params); |
Peter Ujfalusi | 299a151 | 2010-03-19 12:27:31 +0200 | [diff] [blame] | 421 | if (channels == 2 && (format == SND_SOC_DAIFMT_I2S || |
| 422 | format == SND_SOC_DAIFMT_LEFT_J)) { |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 423 | /* Use dual-phase frames */ |
| 424 | regs->rcr2 |= RPHASE; |
| 425 | regs->xcr2 |= XPHASE; |
| 426 | /* Set 1 word per (McBSP) frame for phase1 and phase2 */ |
| 427 | wpf--; |
| 428 | regs->rcr2 |= RFRLEN2(wpf - 1); |
| 429 | regs->xcr2 |= XFRLEN2(wpf - 1); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 430 | } |
| 431 | |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 432 | regs->rcr1 |= RFRLEN1(wpf - 1); |
| 433 | regs->xcr1 |= XFRLEN1(wpf - 1); |
| 434 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 435 | switch (params_format(params)) { |
| 436 | case SNDRV_PCM_FORMAT_S16_LE: |
| 437 | /* Set word lengths */ |
| 438 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); |
| 439 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); |
| 440 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); |
| 441 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 442 | break; |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 443 | case SNDRV_PCM_FORMAT_S32_LE: |
| 444 | /* Set word lengths */ |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 445 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); |
| 446 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32); |
| 447 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32); |
| 448 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32); |
| 449 | break; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 450 | default: |
| 451 | /* Unsupported PCM format */ |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 455 | /* In McBSP master modes, FRAME (i.e. sample rate) is generated |
| 456 | * by _counting_ BCLKs. Calculate frame size in BCLKs */ |
| 457 | master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK; |
| 458 | if (master == SND_SOC_DAIFMT_CBS_CFS) { |
| 459 | div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1; |
| 460 | framesize = (mcbsp_data->in_freq / div) / params_rate(params); |
| 461 | |
| 462 | if (framesize < wlen * channels) { |
| 463 | printk(KERN_ERR "%s: not enough bandwidth for desired rate and " |
| 464 | "channels\n", __func__); |
| 465 | return -EINVAL; |
| 466 | } |
| 467 | } else |
| 468 | framesize = wlen * channels; |
| 469 | |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 470 | /* Set FS period and length in terms of bit clock periods */ |
Peter Ujfalusi | c29b206 | 2009-04-15 15:38:55 +0300 | [diff] [blame] | 471 | switch (format) { |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 472 | case SND_SOC_DAIFMT_I2S: |
Peter Ujfalusi | 299a151 | 2010-03-19 12:27:31 +0200 | [diff] [blame] | 473 | case SND_SOC_DAIFMT_LEFT_J: |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 474 | regs->srgr2 |= FPER(framesize - 1); |
| 475 | regs->srgr1 |= FWID((framesize >> 1) - 1); |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 476 | break; |
Peter Ujfalusi | 3ba191c | 2009-04-15 15:38:56 +0300 | [diff] [blame] | 477 | case SND_SOC_DAIFMT_DSP_A: |
Jarkko Nikula | bd25867 | 2008-12-22 10:21:36 +0200 | [diff] [blame] | 478 | case SND_SOC_DAIFMT_DSP_B: |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 479 | regs->srgr2 |= FPER(framesize - 1); |
Jarkko Nikula | 36ce858 | 2009-04-15 13:48:16 +0300 | [diff] [blame] | 480 | regs->srgr1 |= FWID(0); |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 481 | break; |
| 482 | } |
| 483 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 484 | omap_mcbsp_config(bus_id, &mcbsp_data->regs); |
Peter Ujfalusi | 3f02403 | 2010-06-03 07:39:35 +0300 | [diff] [blame] | 485 | mcbsp_data->wlen = wlen; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 486 | mcbsp_data->configured = 1; |
| 487 | |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /* |
| 492 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register |
| 493 | * cache is initialized here |
| 494 | */ |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 495 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 496 | unsigned int fmt) |
| 497 | { |
| 498 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 499 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
Jarkko Nikula | 36ce858 | 2009-04-15 13:48:16 +0300 | [diff] [blame] | 500 | unsigned int temp_fmt = fmt; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 501 | |
| 502 | if (mcbsp_data->configured) |
| 503 | return 0; |
| 504 | |
Jarkko Nikula | ba9d0fd | 2008-10-20 15:29:59 +0300 | [diff] [blame] | 505 | mcbsp_data->fmt = fmt; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 506 | memset(regs, 0, sizeof(*regs)); |
| 507 | /* Generic McBSP register settings */ |
| 508 | regs->spcr2 |= XINTM(3) | FREE; |
| 509 | regs->spcr1 |= RINTM(3); |
Eero Nurkkala | c721bbd | 2009-08-20 16:18:23 +0300 | [diff] [blame] | 510 | /* RFIG and XFIG are not defined in 34xx */ |
| 511 | if (!cpu_is_omap34xx()) { |
| 512 | regs->rcr2 |= RFIG; |
| 513 | regs->xcr2 |= XFIG; |
| 514 | } |
Misael Lopez Cruz | ef390c0 | 2009-01-29 13:29:46 +0200 | [diff] [blame] | 515 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { |
Jarkko Nikula | 32080af | 2009-08-23 12:24:26 +0300 | [diff] [blame] | 516 | regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE; |
| 517 | regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE; |
Misael Lopez Cruz | ef390c0 | 2009-01-29 13:29:46 +0200 | [diff] [blame] | 518 | } |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 519 | |
| 520 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 521 | case SND_SOC_DAIFMT_I2S: |
| 522 | /* 1-bit data delay */ |
| 523 | regs->rcr2 |= RDATDLY(1); |
| 524 | regs->xcr2 |= XDATDLY(1); |
| 525 | break; |
Peter Ujfalusi | 299a151 | 2010-03-19 12:27:31 +0200 | [diff] [blame] | 526 | case SND_SOC_DAIFMT_LEFT_J: |
| 527 | /* 0-bit data delay */ |
| 528 | regs->rcr2 |= RDATDLY(0); |
| 529 | regs->xcr2 |= XDATDLY(0); |
| 530 | regs->spcr1 |= RJUST(2); |
| 531 | /* Invert FS polarity configuration */ |
| 532 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; |
| 533 | break; |
Peter Ujfalusi | 3ba191c | 2009-04-15 15:38:56 +0300 | [diff] [blame] | 534 | case SND_SOC_DAIFMT_DSP_A: |
| 535 | /* 1-bit data delay */ |
| 536 | regs->rcr2 |= RDATDLY(1); |
| 537 | regs->xcr2 |= XDATDLY(1); |
| 538 | /* Invert FS polarity configuration */ |
| 539 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; |
| 540 | break; |
Jarkko Nikula | bd25867 | 2008-12-22 10:21:36 +0200 | [diff] [blame] | 541 | case SND_SOC_DAIFMT_DSP_B: |
Arun KS | 3336c5b | 2008-10-02 15:07:06 +0530 | [diff] [blame] | 542 | /* 0-bit data delay */ |
| 543 | regs->rcr2 |= RDATDLY(0); |
| 544 | regs->xcr2 |= XDATDLY(0); |
Jarkko Nikula | 36ce858 | 2009-04-15 13:48:16 +0300 | [diff] [blame] | 545 | /* Invert FS polarity configuration */ |
| 546 | temp_fmt ^= SND_SOC_DAIFMT_NB_IF; |
Arun KS | 3336c5b | 2008-10-02 15:07:06 +0530 | [diff] [blame] | 547 | break; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 548 | default: |
| 549 | /* Unsupported data format */ |
| 550 | return -EINVAL; |
| 551 | } |
| 552 | |
| 553 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 554 | case SND_SOC_DAIFMT_CBS_CFS: |
| 555 | /* McBSP master. Set FS and bit clocks as outputs */ |
| 556 | regs->pcr0 |= FSXM | FSRM | |
| 557 | CLKXM | CLKRM; |
| 558 | /* Sample rate generator drives the FS */ |
| 559 | regs->srgr2 |= FSGM; |
| 560 | break; |
| 561 | case SND_SOC_DAIFMT_CBM_CFM: |
| 562 | /* McBSP slave */ |
| 563 | break; |
| 564 | default: |
| 565 | /* Unsupported master/slave configuration */ |
| 566 | return -EINVAL; |
| 567 | } |
| 568 | |
| 569 | /* Set bit clock (CLKX/CLKR) and FS polarities */ |
Jarkko Nikula | 36ce858 | 2009-04-15 13:48:16 +0300 | [diff] [blame] | 570 | switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) { |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 571 | case SND_SOC_DAIFMT_NB_NF: |
| 572 | /* |
| 573 | * Normal BCLK + FS. |
| 574 | * FS active low. TX data driven on falling edge of bit clock |
| 575 | * and RX data sampled on rising edge of bit clock. |
| 576 | */ |
| 577 | regs->pcr0 |= FSXP | FSRP | |
| 578 | CLKXP | CLKRP; |
| 579 | break; |
| 580 | case SND_SOC_DAIFMT_NB_IF: |
| 581 | regs->pcr0 |= CLKXP | CLKRP; |
| 582 | break; |
| 583 | case SND_SOC_DAIFMT_IB_NF: |
| 584 | regs->pcr0 |= FSXP | FSRP; |
| 585 | break; |
| 586 | case SND_SOC_DAIFMT_IB_IF: |
| 587 | break; |
| 588 | default: |
| 589 | return -EINVAL; |
| 590 | } |
| 591 | |
| 592 | return 0; |
| 593 | } |
| 594 | |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 595 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 596 | int div_id, int div) |
| 597 | { |
| 598 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 599 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
| 600 | |
| 601 | if (div_id != OMAP_MCBSP_CLKGDV) |
| 602 | return -ENODEV; |
| 603 | |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 604 | mcbsp_data->clk_div = div; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 605 | regs->srgr1 |= CLKGDV(div - 1); |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
Liam Girdwood | 8687eb8 | 2008-07-07 16:08:07 +0100 | [diff] [blame] | 610 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 611 | int clk_id, unsigned int freq, |
| 612 | int dir) |
| 613 | { |
| 614 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); |
| 615 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; |
| 616 | int err = 0; |
| 617 | |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 618 | /* The McBSP signal muxing functions are only available on McBSP1 */ |
| 619 | if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR || |
| 620 | clk_id == OMAP_MCBSP_CLKR_SRC_CLKX || |
| 621 | clk_id == OMAP_MCBSP_FSR_SRC_FSR || |
| 622 | clk_id == OMAP_MCBSP_FSR_SRC_FSX) |
| 623 | if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0) |
| 624 | return -EINVAL; |
| 625 | |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 626 | mcbsp_data->in_freq = freq; |
| 627 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 628 | switch (clk_id) { |
| 629 | case OMAP_MCBSP_SYSCLK_CLK: |
| 630 | regs->srgr2 |= CLKSM; |
| 631 | break; |
| 632 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: |
Paul Walmsley | d135865 | 2010-10-08 11:40:19 -0600 | [diff] [blame^] | 633 | if (cpu_class_is_omap1()) { |
| 634 | err = -EINVAL; |
| 635 | break; |
| 636 | } |
| 637 | err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, |
| 638 | MCBSP_CLKS_PRCM_SRC); |
| 639 | break; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 640 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: |
Paul Walmsley | d135865 | 2010-10-08 11:40:19 -0600 | [diff] [blame^] | 641 | if (cpu_class_is_omap1()) { |
| 642 | err = 0; |
| 643 | break; |
| 644 | } |
| 645 | err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id, |
| 646 | MCBSP_CLKS_PAD_SRC); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 647 | break; |
| 648 | |
| 649 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: |
| 650 | regs->srgr2 |= CLKSM; |
| 651 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: |
| 652 | regs->pcr0 |= SCLKME; |
| 653 | break; |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 654 | |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 655 | |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 656 | case OMAP_MCBSP_CLKR_SRC_CLKR: |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 657 | omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR); |
| 658 | break; |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 659 | case OMAP_MCBSP_CLKR_SRC_CLKX: |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 660 | omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX); |
| 661 | break; |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 662 | case OMAP_MCBSP_FSR_SRC_FSR: |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 663 | omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR); |
| 664 | break; |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 665 | case OMAP_MCBSP_FSR_SRC_FSX: |
Paul Walmsley | cf4c87a | 2010-10-08 11:40:19 -0600 | [diff] [blame] | 666 | omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX); |
Jarkko Nikula | d2c0bda | 2009-08-28 15:35:35 +0300 | [diff] [blame] | 667 | break; |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 668 | default: |
| 669 | err = -ENODEV; |
| 670 | } |
| 671 | |
| 672 | return err; |
| 673 | } |
| 674 | |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 675 | static struct snd_soc_dai_ops omap_mcbsp_dai_ops = { |
| 676 | .startup = omap_mcbsp_dai_startup, |
| 677 | .shutdown = omap_mcbsp_dai_shutdown, |
| 678 | .trigger = omap_mcbsp_dai_trigger, |
Peter Ujfalusi | 75581d2 | 2010-03-03 15:08:09 +0200 | [diff] [blame] | 679 | .delay = omap_mcbsp_dai_delay, |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 680 | .hw_params = omap_mcbsp_dai_hw_params, |
| 681 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, |
| 682 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, |
| 683 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, |
| 684 | }; |
| 685 | |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 686 | #define OMAP_MCBSP_DAI_BUILDER(link_id) \ |
| 687 | { \ |
Jarkko Nikula | 0c758bd | 2008-11-21 14:31:33 +0200 | [diff] [blame] | 688 | .name = "omap-mcbsp-dai-"#link_id, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 689 | .id = (link_id), \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 690 | .playback = { \ |
Jarkko Nikula | 375e8a7 | 2008-11-25 12:45:09 +0200 | [diff] [blame] | 691 | .channels_min = 1, \ |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 692 | .channels_max = 16, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 693 | .rates = OMAP_MCBSP_RATES, \ |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 694 | .formats = SNDRV_PCM_FMTBIT_S16_LE | \ |
| 695 | SNDRV_PCM_FMTBIT_S32_LE, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 696 | }, \ |
| 697 | .capture = { \ |
Jarkko Nikula | 375e8a7 | 2008-11-25 12:45:09 +0200 | [diff] [blame] | 698 | .channels_min = 1, \ |
Graeme Gregory | 5f63ef9 | 2009-11-09 19:02:15 +0000 | [diff] [blame] | 699 | .channels_max = 16, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 700 | .rates = OMAP_MCBSP_RATES, \ |
Sergey Lapin | d98508a | 2010-05-13 19:48:16 +0400 | [diff] [blame] | 701 | .formats = SNDRV_PCM_FMTBIT_S16_LE | \ |
| 702 | SNDRV_PCM_FMTBIT_S32_LE, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 703 | }, \ |
Eric Miao | 6335d05 | 2009-03-03 09:41:00 +0800 | [diff] [blame] | 704 | .ops = &omap_mcbsp_dai_ops, \ |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 705 | .private_data = &mcbsp_data[(link_id)].bus_id, \ |
| 706 | } |
| 707 | |
| 708 | struct snd_soc_dai omap_mcbsp_dai[] = { |
| 709 | OMAP_MCBSP_DAI_BUILDER(0), |
| 710 | OMAP_MCBSP_DAI_BUILDER(1), |
| 711 | #if NUM_LINKS >= 3 |
| 712 | OMAP_MCBSP_DAI_BUILDER(2), |
| 713 | #endif |
| 714 | #if NUM_LINKS == 5 |
| 715 | OMAP_MCBSP_DAI_BUILDER(3), |
| 716 | OMAP_MCBSP_DAI_BUILDER(4), |
| 717 | #endif |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 718 | }; |
Jarkko Nikula | 8def464 | 2008-10-09 15:57:22 +0300 | [diff] [blame] | 719 | |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 720 | EXPORT_SYMBOL_GPL(omap_mcbsp_dai); |
| 721 | |
Ilkka Koskinen | 83905c1 | 2010-02-22 12:21:12 +0000 | [diff] [blame] | 722 | int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol, |
| 723 | struct snd_ctl_elem_info *uinfo) |
| 724 | { |
| 725 | struct soc_mixer_control *mc = |
| 726 | (struct soc_mixer_control *)kcontrol->private_value; |
| 727 | int max = mc->max; |
| 728 | int min = mc->min; |
| 729 | |
| 730 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
| 731 | uinfo->count = 1; |
| 732 | uinfo->value.integer.min = min; |
| 733 | uinfo->value.integer.max = max; |
| 734 | return 0; |
| 735 | } |
| 736 | |
| 737 | #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \ |
| 738 | static int \ |
| 739 | omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
| 740 | struct snd_ctl_elem_value *uc) \ |
| 741 | { \ |
| 742 | struct soc_mixer_control *mc = \ |
| 743 | (struct soc_mixer_control *)kc->private_value; \ |
| 744 | int max = mc->max; \ |
| 745 | int min = mc->min; \ |
| 746 | int val = uc->value.integer.value[0]; \ |
| 747 | \ |
| 748 | if (val < min || val > max) \ |
| 749 | return -EINVAL; \ |
| 750 | \ |
| 751 | /* OMAP McBSP implementation uses index values 0..4 */ \ |
| 752 | return omap_st_set_chgain((id)-1, channel, val); \ |
| 753 | } |
| 754 | |
| 755 | #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \ |
| 756 | static int \ |
| 757 | omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \ |
| 758 | struct snd_ctl_elem_value *uc) \ |
| 759 | { \ |
| 760 | s16 chgain; \ |
| 761 | \ |
| 762 | if (omap_st_get_chgain((id)-1, channel, &chgain)) \ |
| 763 | return -EAGAIN; \ |
| 764 | \ |
| 765 | uc->value.integer.value[0] = chgain; \ |
| 766 | return 0; \ |
| 767 | } |
| 768 | |
| 769 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0) |
| 770 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1) |
| 771 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0) |
| 772 | OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1) |
| 773 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0) |
| 774 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1) |
| 775 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0) |
| 776 | OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1) |
| 777 | |
| 778 | static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol, |
| 779 | struct snd_ctl_elem_value *ucontrol) |
| 780 | { |
| 781 | struct soc_mixer_control *mc = |
| 782 | (struct soc_mixer_control *)kcontrol->private_value; |
| 783 | u8 value = ucontrol->value.integer.value[0]; |
| 784 | |
| 785 | if (value == omap_st_is_enabled(mc->reg)) |
| 786 | return 0; |
| 787 | |
| 788 | if (value) |
| 789 | omap_st_enable(mc->reg); |
| 790 | else |
| 791 | omap_st_disable(mc->reg); |
| 792 | |
| 793 | return 1; |
| 794 | } |
| 795 | |
| 796 | static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol, |
| 797 | struct snd_ctl_elem_value *ucontrol) |
| 798 | { |
| 799 | struct soc_mixer_control *mc = |
| 800 | (struct soc_mixer_control *)kcontrol->private_value; |
| 801 | |
| 802 | ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg); |
| 803 | return 0; |
| 804 | } |
| 805 | |
| 806 | static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = { |
| 807 | SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0, |
| 808 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), |
| 809 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume", |
| 810 | -32768, 32767, |
| 811 | omap_mcbsp2_get_st_ch0_volume, |
| 812 | omap_mcbsp2_set_st_ch0_volume), |
| 813 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume", |
| 814 | -32768, 32767, |
| 815 | omap_mcbsp2_get_st_ch1_volume, |
| 816 | omap_mcbsp2_set_st_ch1_volume), |
| 817 | }; |
| 818 | |
| 819 | static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = { |
| 820 | SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0, |
| 821 | omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode), |
| 822 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume", |
| 823 | -32768, 32767, |
| 824 | omap_mcbsp3_get_st_ch0_volume, |
| 825 | omap_mcbsp3_set_st_ch0_volume), |
| 826 | OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume", |
| 827 | -32768, 32767, |
| 828 | omap_mcbsp3_get_st_ch1_volume, |
| 829 | omap_mcbsp3_set_st_ch1_volume), |
| 830 | }; |
| 831 | |
| 832 | int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id) |
| 833 | { |
| 834 | if (!cpu_is_omap34xx()) |
| 835 | return -ENODEV; |
| 836 | |
| 837 | switch (mcbsp_id) { |
| 838 | case 1: /* McBSP 2 */ |
| 839 | return snd_soc_add_controls(codec, omap_mcbsp2_st_controls, |
| 840 | ARRAY_SIZE(omap_mcbsp2_st_controls)); |
| 841 | case 2: /* McBSP 3 */ |
| 842 | return snd_soc_add_controls(codec, omap_mcbsp3_st_controls, |
| 843 | ARRAY_SIZE(omap_mcbsp3_st_controls)); |
| 844 | default: |
| 845 | break; |
| 846 | } |
| 847 | |
| 848 | return -EINVAL; |
| 849 | } |
| 850 | EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls); |
| 851 | |
Takashi Iwai | f73f2a6 | 2008-12-10 07:59:33 +0100 | [diff] [blame] | 852 | static int __init snd_omap_mcbsp_init(void) |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 853 | { |
| 854 | return snd_soc_register_dais(omap_mcbsp_dai, |
| 855 | ARRAY_SIZE(omap_mcbsp_dai)); |
| 856 | } |
Takashi Iwai | f73f2a6 | 2008-12-10 07:59:33 +0100 | [diff] [blame] | 857 | module_init(snd_omap_mcbsp_init); |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 858 | |
Takashi Iwai | f73f2a6 | 2008-12-10 07:59:33 +0100 | [diff] [blame] | 859 | static void __exit snd_omap_mcbsp_exit(void) |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 860 | { |
| 861 | snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai)); |
| 862 | } |
Takashi Iwai | f73f2a6 | 2008-12-10 07:59:33 +0100 | [diff] [blame] | 863 | module_exit(snd_omap_mcbsp_exit); |
Mark Brown | 3f4b783 | 2008-12-03 19:26:35 +0000 | [diff] [blame] | 864 | |
Jarkko Nikula | b08f7a6 | 2009-04-17 14:42:26 +0300 | [diff] [blame] | 865 | MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>"); |
Jarkko Nikula | 2e74796 | 2008-04-25 13:55:19 +0200 | [diff] [blame] | 866 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); |
| 867 | MODULE_LICENSE("GPL"); |