Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 1 | /* |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 2 | * Copyright (C) 2010 Google, Inc. |
| 3 | * |
| 4 | * Author: |
| 5 | * Colin Cross <ccross@google.com> |
| 6 | * Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation |
| 7 | * |
| 8 | * This software is licensed under the terms of the GNU General Public |
| 9 | * License version 2, as published by the Free Software Foundation, and |
| 10 | * may be copied, distributed, and modified under those terms. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/types.h> |
| 22 | #include <linux/sched.h> |
| 23 | #include <linux/cpufreq.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/io.h> |
| 29 | |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 30 | static struct cpufreq_frequency_table freq_table[] = { |
Viresh Kumar | 5d69030 | 2013-05-14 19:08:50 +0530 | [diff] [blame] | 31 | { .frequency = 216000 }, |
| 32 | { .frequency = 312000 }, |
| 33 | { .frequency = 456000 }, |
| 34 | { .frequency = 608000 }, |
| 35 | { .frequency = 760000 }, |
| 36 | { .frequency = 816000 }, |
| 37 | { .frequency = 912000 }, |
| 38 | { .frequency = 1000000 }, |
| 39 | { .frequency = CPUFREQ_TABLE_END }, |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | #define NUM_CPUS 2 |
| 43 | |
| 44 | static struct clk *cpu_clk; |
Stephen Warren | ce32dda | 2012-09-10 17:05:01 -0600 | [diff] [blame] | 45 | static struct clk *pll_x_clk; |
| 46 | static struct clk *pll_p_clk; |
Colin Cross | 7a28128 | 2010-11-22 18:54:36 -0800 | [diff] [blame] | 47 | static struct clk *emc_clk; |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 48 | |
Stephen Warren | ce32dda | 2012-09-10 17:05:01 -0600 | [diff] [blame] | 49 | static int tegra_cpu_clk_set_rate(unsigned long rate) |
| 50 | { |
| 51 | int ret; |
| 52 | |
| 53 | /* |
| 54 | * Take an extra reference to the main pll so it doesn't turn |
| 55 | * off when we move the cpu off of it |
| 56 | */ |
| 57 | clk_prepare_enable(pll_x_clk); |
| 58 | |
| 59 | ret = clk_set_parent(cpu_clk, pll_p_clk); |
| 60 | if (ret) { |
| 61 | pr_err("Failed to switch cpu to clock pll_p\n"); |
| 62 | goto out; |
| 63 | } |
| 64 | |
| 65 | if (rate == clk_get_rate(pll_p_clk)) |
| 66 | goto out; |
| 67 | |
| 68 | ret = clk_set_rate(pll_x_clk, rate); |
| 69 | if (ret) { |
| 70 | pr_err("Failed to change pll_x to %lu\n", rate); |
| 71 | goto out; |
| 72 | } |
| 73 | |
| 74 | ret = clk_set_parent(cpu_clk, pll_x_clk); |
| 75 | if (ret) { |
| 76 | pr_err("Failed to switch cpu to clock pll_x\n"); |
| 77 | goto out; |
| 78 | } |
| 79 | |
| 80 | out: |
| 81 | clk_disable_unprepare(pll_x_clk); |
| 82 | return ret; |
| 83 | } |
| 84 | |
Viresh Kumar | b43a7ff | 2013-03-24 11:56:43 +0530 | [diff] [blame] | 85 | static int tegra_update_cpu_speed(struct cpufreq_policy *policy, |
| 86 | unsigned long rate) |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 87 | { |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 88 | int ret = 0; |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 89 | |
Colin Cross | 7a28128 | 2010-11-22 18:54:36 -0800 | [diff] [blame] | 90 | /* |
| 91 | * Vote on memory bus frequency based on cpu frequency |
| 92 | * This sets the minimum frequency, display or avp may request higher |
| 93 | */ |
| 94 | if (rate >= 816000) |
| 95 | clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ |
| 96 | else if (rate >= 456000) |
| 97 | clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ |
| 98 | else |
| 99 | clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ |
| 100 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 101 | ret = tegra_cpu_clk_set_rate(rate * 1000); |
| 102 | if (ret) |
| 103 | pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n", |
| 104 | rate); |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 105 | |
Viresh Kumar | f56cc99 | 2013-06-19 11:18:20 +0530 | [diff] [blame] | 106 | return ret; |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 107 | } |
| 108 | |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 109 | static int tegra_target(struct cpufreq_policy *policy, unsigned int index) |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 110 | { |
Viresh Kumar | d351cb3 | 2014-03-04 11:00:30 +0800 | [diff] [blame^] | 111 | return tegra_update_cpu_speed(policy, freq_table[index].frequency); |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | static int tegra_cpu_init(struct cpufreq_policy *policy) |
| 115 | { |
Viresh Kumar | 99d428c | 2013-10-03 20:42:11 +0530 | [diff] [blame] | 116 | int ret; |
| 117 | |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 118 | if (policy->cpu >= NUM_CPUS) |
| 119 | return -EINVAL; |
| 120 | |
Prashant Gaikwad | 6a5278d | 2012-06-05 09:59:35 +0530 | [diff] [blame] | 121 | clk_prepare_enable(emc_clk); |
| 122 | clk_prepare_enable(cpu_clk); |
Colin Cross | 89a5fb8 | 2010-10-20 17:47:59 -0700 | [diff] [blame] | 123 | |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 124 | /* FIXME: what's the actual transition time? */ |
Viresh Kumar | 99d428c | 2013-10-03 20:42:11 +0530 | [diff] [blame] | 125 | ret = cpufreq_generic_init(policy, freq_table, 300 * 1000); |
| 126 | if (ret) { |
| 127 | clk_disable_unprepare(cpu_clk); |
| 128 | clk_disable_unprepare(emc_clk); |
| 129 | return ret; |
| 130 | } |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 131 | |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 132 | policy->clk = cpu_clk; |
Viresh Kumar | d351cb3 | 2014-03-04 11:00:30 +0800 | [diff] [blame^] | 133 | policy->suspend_freq = freq_table[0].frequency; |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 134 | return 0; |
| 135 | } |
| 136 | |
| 137 | static int tegra_cpu_exit(struct cpufreq_policy *policy) |
| 138 | { |
Viresh Kumar | 2e6a5c80 | 2013-09-16 18:56:40 +0530 | [diff] [blame] | 139 | cpufreq_frequency_table_put_attr(policy->cpu); |
Viresh Kumar | 99d428c | 2013-10-03 20:42:11 +0530 | [diff] [blame] | 140 | clk_disable_unprepare(cpu_clk); |
Prashant Gaikwad | 6a5278d | 2012-06-05 09:59:35 +0530 | [diff] [blame] | 141 | clk_disable_unprepare(emc_clk); |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 142 | return 0; |
| 143 | } |
| 144 | |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 145 | static struct cpufreq_driver tegra_cpufreq_driver = { |
Viresh Kumar | ae6b427 | 2013-12-03 11:20:45 +0530 | [diff] [blame] | 146 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
Viresh Kumar | 8e08cf0 | 2013-10-03 20:28:29 +0530 | [diff] [blame] | 147 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 148 | .target_index = tegra_target, |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 149 | .get = cpufreq_generic_get, |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 150 | .init = tegra_cpu_init, |
| 151 | .exit = tegra_cpu_exit, |
| 152 | .name = "tegra", |
Viresh Kumar | 8e08cf0 | 2013-10-03 20:28:29 +0530 | [diff] [blame] | 153 | .attr = cpufreq_generic_attr, |
Viresh Kumar | d351cb3 | 2014-03-04 11:00:30 +0800 | [diff] [blame^] | 154 | #ifdef CONFIG_PM |
| 155 | .suspend = cpufreq_generic_suspend, |
| 156 | #endif |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | static int __init tegra_cpufreq_init(void) |
| 160 | { |
Joseph Lo | b192b91 | 2013-08-23 09:43:58 +0800 | [diff] [blame] | 161 | cpu_clk = clk_get_sys(NULL, "cclk"); |
Richard Zhao | c26cefd | 2012-12-21 00:09:55 +0000 | [diff] [blame] | 162 | if (IS_ERR(cpu_clk)) |
| 163 | return PTR_ERR(cpu_clk); |
| 164 | |
| 165 | pll_x_clk = clk_get_sys(NULL, "pll_x"); |
| 166 | if (IS_ERR(pll_x_clk)) |
| 167 | return PTR_ERR(pll_x_clk); |
| 168 | |
Joseph Lo | b192b91 | 2013-08-23 09:43:58 +0800 | [diff] [blame] | 169 | pll_p_clk = clk_get_sys(NULL, "pll_p"); |
Richard Zhao | c26cefd | 2012-12-21 00:09:55 +0000 | [diff] [blame] | 170 | if (IS_ERR(pll_p_clk)) |
| 171 | return PTR_ERR(pll_p_clk); |
| 172 | |
| 173 | emc_clk = clk_get_sys("cpu", "emc"); |
| 174 | if (IS_ERR(emc_clk)) { |
| 175 | clk_put(cpu_clk); |
| 176 | return PTR_ERR(emc_clk); |
| 177 | } |
| 178 | |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 179 | return cpufreq_register_driver(&tegra_cpufreq_driver); |
| 180 | } |
| 181 | |
| 182 | static void __exit tegra_cpufreq_exit(void) |
| 183 | { |
| 184 | cpufreq_unregister_driver(&tegra_cpufreq_driver); |
Richard Zhao | c26cefd | 2012-12-21 00:09:55 +0000 | [diff] [blame] | 185 | clk_put(emc_clk); |
| 186 | clk_put(cpu_clk); |
Colin Cross | 7056d42 | 2010-04-22 20:30:13 -0700 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | |
| 190 | MODULE_AUTHOR("Colin Cross <ccross@android.com>"); |
| 191 | MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2"); |
| 192 | MODULE_LICENSE("GPL"); |
| 193 | module_init(tegra_cpufreq_init); |
| 194 | module_exit(tegra_cpufreq_exit); |