blob: a9d74eff5fc4b159367b1f8f03d7aa842e331dba [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov8e834c22010-12-25 22:44:01 +030011 * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
Joe Perches8d7b1c72011-01-31 08:39:24 -080017#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
Jeff Garzik669a5db2006-08-29 18:12:40 -040019#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27
28#define DRV_NAME "pata_hpt37x"
Joe Perches8d7b1c72011-01-31 08:39:24 -080029#define DRV_VERSION "0.6.23"
Jeff Garzik669a5db2006-08-29 18:12:40 -040030
31struct hpt_clock {
32 u8 xfer_speed;
33 u32 timing;
34};
35
36struct hpt_chip {
37 const char *name;
38 unsigned int base;
39 struct hpt_clock const *clocks[4];
40};
41
42/* key for bus clock timings
43 * bit
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040044 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
45 * cycles = value + 1
46 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
47 * cycles = value + 1
48 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040049 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040050 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040051 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040052 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
53 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
54 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
55 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
Jeff Garzik669a5db2006-08-29 18:12:40 -040056 * register access.
Sergei Shtylyovfd5e62e2009-12-07 23:38:11 +040057 * 28 UDMA enable.
58 * 29 DMA enable.
59 * 30 PIO_MST enable. If set, the chip is in bus master mode during
60 * PIO xfer.
61 * 31 FIFO enable. Only for PIO.
Jeff Garzik669a5db2006-08-29 18:12:40 -040062 */
63
Alan Coxfcc2f692007-03-08 23:28:52 +000064static struct hpt_clock hpt37x_timings_33[] = {
65 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
66 { XFER_UDMA_5, 0x12446231 },
67 { XFER_UDMA_4, 0x12446231 },
68 { XFER_UDMA_3, 0x126c6231 },
69 { XFER_UDMA_2, 0x12486231 },
70 { XFER_UDMA_1, 0x124c6233 },
71 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040072
Alan Coxfcc2f692007-03-08 23:28:52 +000073 { XFER_MW_DMA_2, 0x22406c31 },
74 { XFER_MW_DMA_1, 0x22406c33 },
75 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040076
Alan Coxfcc2f692007-03-08 23:28:52 +000077 { XFER_PIO_4, 0x06414e31 },
78 { XFER_PIO_3, 0x06414e42 },
79 { XFER_PIO_2, 0x06414e53 },
80 { XFER_PIO_1, 0x06814e93 },
81 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040082};
83
Alan Coxfcc2f692007-03-08 23:28:52 +000084static struct hpt_clock hpt37x_timings_50[] = {
85 { XFER_UDMA_6, 0x12848242 },
86 { XFER_UDMA_5, 0x12848242 },
87 { XFER_UDMA_4, 0x12ac8242 },
88 { XFER_UDMA_3, 0x128c8242 },
89 { XFER_UDMA_2, 0x120c8242 },
90 { XFER_UDMA_1, 0x12148254 },
91 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040092
Alan Coxfcc2f692007-03-08 23:28:52 +000093 { XFER_MW_DMA_2, 0x22808242 },
94 { XFER_MW_DMA_1, 0x22808254 },
95 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040096
Alan Coxfcc2f692007-03-08 23:28:52 +000097 { XFER_PIO_4, 0x0a81f442 },
98 { XFER_PIO_3, 0x0a81f443 },
99 { XFER_PIO_2, 0x0a81f454 },
100 { XFER_PIO_1, 0x0ac1f465 },
101 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400102};
103
Alan Coxfcc2f692007-03-08 23:28:52 +0000104static struct hpt_clock hpt37x_timings_66[] = {
105 { XFER_UDMA_6, 0x1c869c62 },
106 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
107 { XFER_UDMA_4, 0x1c8a9c62 },
108 { XFER_UDMA_3, 0x1c8e9c62 },
109 { XFER_UDMA_2, 0x1c929c62 },
110 { XFER_UDMA_1, 0x1c9a9c62 },
111 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400112
Alan Coxfcc2f692007-03-08 23:28:52 +0000113 { XFER_MW_DMA_2, 0x2c829c62 },
114 { XFER_MW_DMA_1, 0x2c829c66 },
115 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400116
Alan Coxfcc2f692007-03-08 23:28:52 +0000117 { XFER_PIO_4, 0x0c829c62 },
118 { XFER_PIO_3, 0x0c829c84 },
119 { XFER_PIO_2, 0x0c829ca6 },
120 { XFER_PIO_1, 0x0d029d26 },
121 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400122};
123
Jeff Garzik669a5db2006-08-29 18:12:40 -0400124
125static const struct hpt_chip hpt370 = {
126 "HPT370",
127 48,
128 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000129 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400130 NULL,
131 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700132 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400133 }
134};
135
136static const struct hpt_chip hpt370a = {
137 "HPT370A",
138 48,
139 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000140 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000142 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700143 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400144 }
145};
146
147static const struct hpt_chip hpt372 = {
148 "HPT372",
149 55,
150 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000151 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400152 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000153 hpt37x_timings_50,
154 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400155 }
156};
157
158static const struct hpt_chip hpt302 = {
159 "HPT302",
160 66,
161 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000162 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400163 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000164 hpt37x_timings_50,
165 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400166 }
167};
168
169static const struct hpt_chip hpt371 = {
170 "HPT371",
171 66,
172 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000173 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400174 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000175 hpt37x_timings_50,
176 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400177 }
178};
179
180static const struct hpt_chip hpt372a = {
181 "HPT372A",
182 66,
183 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000184 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400185 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000186 hpt37x_timings_50,
187 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188 }
189};
190
191static const struct hpt_chip hpt374 = {
192 "HPT374",
193 48,
194 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000195 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 NULL,
197 NULL,
198 NULL
199 }
200};
201
202/**
203 * hpt37x_find_mode - reset the hpt37x bus
204 * @ap: ATA port
205 * @speed: transfer mode
206 *
207 * Return the 32bit register programming information for this channel
208 * that matches the speed provided.
209 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400210
Jeff Garzik669a5db2006-08-29 18:12:40 -0400211static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
212{
213 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400214
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300215 while (clocks->xfer_speed) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400216 if (clocks->xfer_speed == speed)
217 return clocks->timing;
218 clocks++;
219 }
220 BUG();
221 return 0xffffffffU; /* silence compiler warning */
222}
223
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300224static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
225 const char * const list[])
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900227 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400228 int i = 0;
229
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900230 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900232 while (list[i] != NULL) {
233 if (!strcmp(list[i], model_num)) {
Joe Perches8d7b1c72011-01-31 08:39:24 -0800234 pr_warn("%s is not supported for %s\n",
235 modestr, list[i]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400236 return 1;
237 }
238 i++;
239 }
240 return 0;
241}
242
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300243static const char * const bad_ata33[] = {
244 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
245 "Maxtor 90845U3", "Maxtor 90650U2",
246 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
247 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
248 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
249 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400250 "Maxtor 90510D4",
251 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300252 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
253 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
254 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
255 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400256 NULL
257};
258
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300259static const char * const bad_ata100_5[] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400260 "IBM-DTLA-307075",
261 "IBM-DTLA-307060",
262 "IBM-DTLA-307045",
263 "IBM-DTLA-307030",
264 "IBM-DTLA-307020",
265 "IBM-DTLA-307015",
266 "IBM-DTLA-305040",
267 "IBM-DTLA-305030",
268 "IBM-DTLA-305020",
269 "IC35L010AVER07-0",
270 "IC35L020AVER07-0",
271 "IC35L030AVER07-0",
272 "IC35L040AVER07-0",
273 "IC35L060AVER07-0",
274 "WDC AC310200R",
275 NULL
276};
277
278/**
279 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280 * @adev: ATA device
281 *
282 * Block UDMA on devices that cause trouble with this controller.
283 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400284
Alan Coxa76b62c2007-03-09 09:34:07 -0500285static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400286{
Alan6929da42007-01-05 16:37:01 -0800287 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400288 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
289 mask &= ~ATA_MASK_UDMA;
290 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800291 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400292 }
Tejun Heoc7087652010-05-10 21:41:34 +0200293 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400294}
295
296/**
297 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400298 * @adev: ATA device
299 *
300 * Block UDMA on devices that cause trouble with this controller.
301 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400302
Alan Coxa76b62c2007-03-09 09:34:07 -0500303static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400304{
Alan Cox73946f92007-11-05 22:53:38 +0000305 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400306 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800307 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400308 }
Tejun Heoc7087652010-05-10 21:41:34 +0200309 return mask;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400310}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400311
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312/**
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300313 * hpt372_filter - mode selection filter
314 * @adev: ATA device
315 * @mask: mode mask
316 *
317 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
318 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
319 */
320static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask)
321{
322 if (ata_id_is_sata(adev->id))
323 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
324
325 return mask;
326}
327
328/**
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100329 * hpt37x_cable_detect - Detect the cable type
330 * @ap: ATA port to detect on
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331 *
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100332 * Return the cable type attached to this port
Jeff Garzik669a5db2006-08-29 18:12:40 -0400333 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400334
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100335static int hpt37x_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400336{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400337 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100338 u8 scr2, ata66;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500339
Jeff Garzik669a5db2006-08-29 18:12:40 -0400340 pci_read_config_byte(pdev, 0x5B, &scr2);
341 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
Bartlomiej Zolnierkiewicz10a9c962009-11-19 20:31:31 +0100342
343 udelay(10); /* debounce */
344
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345 /* Cable register now active */
346 pci_read_config_byte(pdev, 0x5A, &ata66);
347 /* Restore state */
348 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400349
Alan Cox22d5c762007-11-19 14:39:13 +0000350 if (ata66 & (2 >> ap->port_no))
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100351 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400352 else
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100353 return ATA_CBL_PATA80;
354}
355
356/**
357 * hpt374_fn1_cable_detect - Detect the cable type
358 * @ap: ATA port to detect on
359 *
360 * Return the cable type attached to this port
361 */
362
363static int hpt374_fn1_cable_detect(struct ata_port *ap)
364{
365 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
366 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
367 u16 mcr3;
368 u8 ata66;
369
370 /* Do the extra channel work */
371 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
372 /* Set bit 15 of 0x52 to enable TCBLID as input */
373 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
374 pci_read_config_byte(pdev, 0x5A, &ata66);
375 /* Reset TCBLID/FCBLID to output */
376 pci_write_config_word(pdev, mcrbase + 2, mcr3);
377
378 if (ata66 & (2 >> ap->port_no))
379 return ATA_CBL_PATA40;
380 else
381 return ATA_CBL_PATA80;
382}
383
384/**
385 * hpt37x_pre_reset - reset the hpt37x bus
386 * @link: ATA link to reset
387 * @deadline: deadline jiffies for the operation
388 *
Bartlomiej Zolnierkiewiczab81a502009-11-19 19:12:24 +0100389 * Perform the initial reset handling for the HPT37x.
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100390 */
391
392static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
393{
394 struct ata_port *ap = link->ap;
395 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
396 static const struct pci_bits hpt37x_enable_bits[] = {
397 { 0x50, 1, 0x04, 0x04 },
398 { 0x54, 1, 0x04, 0x04 }
399 };
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300400
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100401 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
402 return -ENOENT;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400403
404 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000405 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400406 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400407
Tejun Heo9363c382008-04-07 22:47:16 +0900408 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400409}
410
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400411static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev,
412 u8 mode)
413{
414 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
415 u32 addr1, addr2;
416 u32 reg, timing, mask;
417 u8 fast;
418
419 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
420 addr2 = 0x51 + 4 * ap->port_no;
421
422 /* Fast interrupt prediction disable, hold off interrupt disable */
423 pci_read_config_byte(pdev, addr2, &fast);
424 fast &= ~0x02;
425 fast |= 0x01;
426 pci_write_config_byte(pdev, addr2, fast);
427
428 /* Determine timing mask and find matching mode entry */
429 if (mode < XFER_MW_DMA_0)
430 mask = 0xcfc3ffff;
431 else if (mode < XFER_UDMA_0)
432 mask = 0x31c001ff;
433 else
434 mask = 0x303c0000;
435
436 timing = hpt37x_find_mode(ap, mode);
437
438 pci_read_config_dword(pdev, addr1, &reg);
439 reg = (reg & ~mask) | (timing & mask);
440 pci_write_config_dword(pdev, addr1, reg);
441}
Jeff Garzik669a5db2006-08-29 18:12:40 -0400442/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400443 * hpt370_set_piomode - PIO setup
444 * @ap: ATA interface
445 * @adev: device on the interface
446 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400447 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400448 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400449
Jeff Garzik669a5db2006-08-29 18:12:40 -0400450static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
451{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400452 hpt370_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400453}
454
455/**
456 * hpt370_set_dmamode - DMA timing setup
457 * @ap: ATA interface
458 * @adev: Device being configured
459 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400460 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400461 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400462
Jeff Garzik669a5db2006-08-29 18:12:40 -0400463static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
464{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400465 hpt370_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400466}
467
468/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400469 * hpt370_bmdma_end - DMA engine stop
470 * @qc: ATA command
471 *
472 * Work around the HPT370 DMA engine.
473 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400474
Jeff Garzik669a5db2006-08-29 18:12:40 -0400475static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
476{
477 struct ata_port *ap = qc->ap;
478 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900479 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400480 u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
481 u8 dma_cmd;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400482
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400483 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400484 udelay(20);
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400485 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400486 }
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400487 if (dma_stat & ATA_DMA_ACTIVE) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400488 /* Clear the engine */
489 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
490 udelay(10);
491 /* Stop DMA */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400492 dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
493 iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400494 /* Clear Error */
Sergei Shtylyov56f46f82009-12-05 00:37:43 +0400495 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
496 iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
497 bmdma + ATA_DMA_STATUS);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400498 /* Clear the engine */
499 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
500 udelay(10);
501 }
502 ata_bmdma_stop(qc);
503}
504
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400505static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev,
506 u8 mode)
507{
508 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
509 u32 addr1, addr2;
510 u32 reg, timing, mask;
511 u8 fast;
512
513 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
514 addr2 = 0x51 + 4 * ap->port_no;
515
516 /* Fast interrupt prediction disable, hold off interrupt disable */
517 pci_read_config_byte(pdev, addr2, &fast);
518 fast &= ~0x07;
519 pci_write_config_byte(pdev, addr2, fast);
520
521 /* Determine timing mask and find matching mode entry */
522 if (mode < XFER_MW_DMA_0)
523 mask = 0xcfc3ffff;
524 else if (mode < XFER_UDMA_0)
525 mask = 0x31c001ff;
526 else
527 mask = 0x303c0000;
528
529 timing = hpt37x_find_mode(ap, mode);
530
531 pci_read_config_dword(pdev, addr1, &reg);
532 reg = (reg & ~mask) | (timing & mask);
533 pci_write_config_dword(pdev, addr1, reg);
534}
535
Jeff Garzik669a5db2006-08-29 18:12:40 -0400536/**
537 * hpt372_set_piomode - PIO setup
538 * @ap: ATA interface
539 * @adev: device on the interface
540 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400541 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400542 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400543
Jeff Garzik669a5db2006-08-29 18:12:40 -0400544static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
545{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400546 hpt372_set_mode(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400547}
548
549/**
550 * hpt372_set_dmamode - DMA timing setup
551 * @ap: ATA interface
552 * @adev: Device being configured
553 *
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400554 * Set up the channel for MWDMA or UDMA modes.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400555 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400556
Jeff Garzik669a5db2006-08-29 18:12:40 -0400557static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
558{
Sergei Shtylyov1a1b1722009-12-07 23:30:06 +0400559 hpt372_set_mode(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400560}
561
562/**
563 * hpt37x_bmdma_end - DMA engine stop
564 * @qc: ATA command
565 *
566 * Clean up after the HPT372 and later DMA engine
567 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400568
Jeff Garzik669a5db2006-08-29 18:12:40 -0400569static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
570{
571 struct ata_port *ap = qc->ap;
572 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da42007-01-05 16:37:01 -0800573 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400574 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400575
Jeff Garzik669a5db2006-08-29 18:12:40 -0400576 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
577 pci_read_config_byte(pdev, mscreg, &msc_stat);
578 if (bwsr_stat & (1 << ap->port_no))
579 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
580 ata_bmdma_stop(qc);
581}
582
583
584static struct scsi_host_template hpt37x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900585 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400586};
587
588/*
589 * Configuration for HPT370
590 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400591
Jeff Garzik669a5db2006-08-29 18:12:40 -0400592static struct ata_port_operations hpt370_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900593 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400594
Jeff Garzik669a5db2006-08-29 18:12:40 -0400595 .bmdma_stop = hpt370_bmdma_stop,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400596
Tejun Heo029cfd62008-03-25 12:22:49 +0900597 .mode_filter = hpt370_filter,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100598 .cable_detect = hpt37x_cable_detect,
Tejun Heo029cfd62008-03-25 12:22:49 +0900599 .set_piomode = hpt370_set_piomode,
600 .set_dmamode = hpt370_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900601 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400602};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400603
604/*
605 * Configuration for HPT370A. Close to 370 but less filters
606 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400607
Jeff Garzik669a5db2006-08-29 18:12:40 -0400608static struct ata_port_operations hpt370a_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900609 .inherits = &hpt370_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400610 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400611};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400612
613/*
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300614 * Configuration for HPT371 and HPT302. Slightly different PIO and DMA
615 * mode setting functionality.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400616 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400617
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300618static struct ata_port_operations hpt302_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900619 .inherits = &ata_bmdma_port_ops,
620
621 .bmdma_stop = hpt37x_bmdma_stop,
622
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100623 .cable_detect = hpt37x_cable_detect,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400624 .set_piomode = hpt372_set_piomode,
625 .set_dmamode = hpt372_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900626 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400627};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400628
629/*
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300630 * Configuration for HPT372. Mode setting works like 371 and 302
631 * but we have a mode filter.
632 */
633
634static struct ata_port_operations hpt372_port_ops = {
635 .inherits = &hpt302_port_ops,
636 .mode_filter = hpt372_filter,
637};
638
639/*
640 * Configuration for HPT374. Mode setting and filtering works like 372
Tejun Heoa1efdab2008-03-25 12:22:50 +0900641 * but we have a different cable detection procedure for function 1.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400642 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400643
Tejun Heoa1efdab2008-03-25 12:22:50 +0900644static struct ata_port_operations hpt374_fn1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900645 .inherits = &hpt372_port_ops,
Bartlomiej Zolnierkiewicz9e87be92009-11-19 19:10:44 +0100646 .cable_detect = hpt374_fn1_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400647};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400648
649/**
Krzysztof Halasaad452d62009-09-20 16:22:51 +0200650 * hpt37x_clock_slot - Turn timing to PC clock entry
Jeff Garzik669a5db2006-08-29 18:12:40 -0400651 * @freq: Reported frequency timing
652 * @base: Base timing
653 *
654 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
655 * and 3 for 66Mhz)
656 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400657
Jeff Garzik669a5db2006-08-29 18:12:40 -0400658static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
659{
660 unsigned int f = (base * freq) / 192; /* Mhz */
661 if (f < 40)
662 return 0; /* 33Mhz slot */
663 if (f < 45)
664 return 1; /* 40Mhz slot */
665 if (f < 55)
666 return 2; /* 50Mhz slot */
667 return 3; /* 60Mhz slot */
668}
669
670/**
671 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400672 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400673 *
674 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
675 * succeeds
676 */
677
678static int hpt37x_calibrate_dpll(struct pci_dev *dev)
679{
680 u8 reg5b;
681 u32 reg5c;
682 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400683
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300684 for (tries = 0; tries < 0x5000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400685 udelay(50);
686 pci_read_config_byte(dev, 0x5b, &reg5b);
687 if (reg5b & 0x80) {
688 /* See if it stays set */
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300689 for (tries = 0; tries < 0x1000; tries++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400690 pci_read_config_byte(dev, 0x5b, &reg5b);
691 /* Failed ? */
692 if ((reg5b & 0x80) == 0)
693 return 0;
694 }
695 /* Turn off tuning, we have the DPLL set */
696 pci_read_config_dword(dev, 0x5c, &reg5c);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300697 pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400698 return 1;
699 }
700 }
701 /* Never went stable */
702 return 0;
703}
Alan Cox73946f92007-11-05 22:53:38 +0000704
705static u32 hpt374_read_freq(struct pci_dev *pdev)
706{
707 u32 freq;
708 unsigned long io_base = pci_resource_start(pdev, 4);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300709
Alan Cox73946f92007-11-05 22:53:38 +0000710 if (PCI_FUNC(pdev->devfn) & 1) {
Andrew Morton40f46f12007-12-13 16:01:38 -0800711 struct pci_dev *pdev_0;
712
713 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
Alan Cox73946f92007-11-05 22:53:38 +0000714 /* Someone hot plugged the controller on us ? */
715 if (pdev_0 == NULL)
716 return 0;
717 io_base = pci_resource_start(pdev_0, 4);
718 freq = inl(io_base + 0x90);
719 pci_dev_put(pdev_0);
Andrew Morton40f46f12007-12-13 16:01:38 -0800720 } else
Alan Cox73946f92007-11-05 22:53:38 +0000721 freq = inl(io_base + 0x90);
722 return freq;
723}
724
Jeff Garzik669a5db2006-08-29 18:12:40 -0400725/**
726 * hpt37x_init_one - Initialise an HPT37X/302
727 * @dev: PCI device
728 * @id: Entry in match table
729 *
730 * Initialise an HPT37x device. There are some interesting complications
731 * here. Firstly the chip may report 366 and be one of several variants.
732 * Secondly all the timings depend on the clock for the chip which we must
733 * detect and look up
734 *
735 * This is the known chip mappings. It may be missing a couple of later
736 * releases.
737 *
738 * Chip version PCI Rev Notes
739 * HPT366 4 (HPT366) 0 Other driver
740 * HPT366 4 (HPT366) 1 Other driver
741 * HPT368 4 (HPT366) 2 Other driver
742 * HPT370 4 (HPT366) 3 UDMA100
743 * HPT370A 4 (HPT366) 4 UDMA100
744 * HPT372 4 (HPT366) 5 UDMA133 (1)
745 * HPT372N 4 (HPT366) 6 Other driver
746 * HPT372A 5 (HPT372) 1 UDMA133 (1)
747 * HPT372N 5 (HPT372) 2 Other driver
748 * HPT302 6 (HPT302) 1 UDMA133
749 * HPT302N 6 (HPT302) 2 Other driver
750 * HPT371 7 (HPT371) * UDMA133
751 * HPT374 8 (HPT374) * UDMA133 4 channel
752 * HPT372N 9 (HPT372N) * Other driver
753 *
754 * (1) UDMA133 support depends on the bus clock
755 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400756
Jeff Garzik669a5db2006-08-29 18:12:40 -0400757static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
758{
759 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200760 static const struct ata_port_info info_hpt370 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400761 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100762 .pio_mask = ATA_PIO4,
763 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400764 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400765 .port_ops = &hpt370_port_ops
766 };
767 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200768 static const struct ata_port_info info_hpt370a = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400769 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100770 .pio_mask = ATA_PIO4,
771 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400772 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400773 .port_ops = &hpt370a_port_ops
774 };
Sergei Shtylyovfc2698d2011-01-05 21:59:49 +0300775 /* HPT370 - UDMA66 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200776 static const struct ata_port_info info_hpt370_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400777 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100778 .pio_mask = ATA_PIO4,
779 .mwdma_mask = ATA_MWDMA2,
Sergei Shtylyovfc2698d2011-01-05 21:59:49 +0300780 .udma_mask = ATA_UDMA4,
Alan Coxfcc2f692007-03-08 23:28:52 +0000781 .port_ops = &hpt370_port_ops
782 };
Sergei Shtylyovfc2698d2011-01-05 21:59:49 +0300783 /* HPT370A - UDMA66 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200784 static const struct ata_port_info info_hpt370a_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400785 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100786 .pio_mask = ATA_PIO4,
787 .mwdma_mask = ATA_MWDMA2,
Sergei Shtylyovfc2698d2011-01-05 21:59:49 +0300788 .udma_mask = ATA_UDMA4,
Alan Coxfcc2f692007-03-08 23:28:52 +0000789 .port_ops = &hpt370a_port_ops
790 };
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300791 /* HPT372 - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200792 static const struct ata_port_info info_hpt372 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400793 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100794 .pio_mask = ATA_PIO4,
795 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400796 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400797 .port_ops = &hpt372_port_ops
798 };
Sergei Shtylyov8e834c22010-12-25 22:44:01 +0300799 /* HPT371, 302 - UDMA133 */
800 static const struct ata_port_info info_hpt302 = {
801 .flags = ATA_FLAG_SLAVE_POSS,
802 .pio_mask = ATA_PIO4,
803 .mwdma_mask = ATA_MWDMA2,
804 .udma_mask = ATA_UDMA6,
805 .port_ops = &hpt302_port_ops
806 };
Sergei Shtylyovdefed552011-01-11 21:01:23 +0300807 /* HPT374 - UDMA100, function 1 uses different cable_detect method */
Tejun Heoa1efdab2008-03-25 12:22:50 +0900808 static const struct ata_port_info info_hpt374_fn0 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400809 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100810 .pio_mask = ATA_PIO4,
811 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400812 .udma_mask = ATA_UDMA5,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900813 .port_ops = &hpt372_port_ops
814 };
815 static const struct ata_port_info info_hpt374_fn1 = {
816 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100817 .pio_mask = ATA_PIO4,
818 .mwdma_mask = ATA_MWDMA2,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900819 .udma_mask = ATA_UDMA5,
820 .port_ops = &hpt374_fn1_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400821 };
822
823 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200824 void *private_data = NULL;
Tejun Heo887125e2008-03-25 12:22:49 +0900825 const struct ata_port_info *ppi[] = { NULL, NULL };
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400826 u8 rev = dev->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400827 u8 irqmask;
Alan Coxfcc2f692007-03-08 23:28:52 +0000828 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400829 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000830 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400831
Alan Coxfcc2f692007-03-08 23:28:52 +0000832 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400833
834 const struct hpt_chip *chip_table;
835 int clock_slot;
Tejun Heof08048e2008-03-25 12:22:47 +0900836 int rc;
837
838 rc = pcim_enable_device(dev);
839 if (rc)
840 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400841
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300842 switch (dev->device) {
843 case PCI_DEVICE_ID_TTI_HPT366:
Jeff Garzik669a5db2006-08-29 18:12:40 -0400844 /* May be a later chip in disguise. Check */
845 /* Older chips are in the HPT366 driver. Ignore them */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400846 if (rev < 3)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400847 return -ENODEV;
848 /* N series chips have their own driver. Ignore */
Sergei Shtylyov89d3b362009-11-24 22:54:49 +0400849 if (rev == 6)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400850 return -ENODEV;
851
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300852 switch (rev) {
853 case 3:
854 ppi[0] = &info_hpt370;
855 chip_table = &hpt370;
856 prefer_dpll = 0;
857 break;
858 case 4:
859 ppi[0] = &info_hpt370a;
860 chip_table = &hpt370a;
861 prefer_dpll = 0;
862 break;
863 case 5:
864 ppi[0] = &info_hpt372;
865 chip_table = &hpt372;
866 break;
867 default:
Joe Perches8d7b1c72011-01-31 08:39:24 -0800868 pr_err("Unknown HPT366 subtype, please report (%d)\n",
869 rev);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300870 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400871 }
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300872 break;
873 case PCI_DEVICE_ID_TTI_HPT372:
874 /* 372N if rev >= 2 */
875 if (rev >= 2)
876 return -ENODEV;
877 ppi[0] = &info_hpt372;
878 chip_table = &hpt372a;
879 break;
880 case PCI_DEVICE_ID_TTI_HPT302:
881 /* 302N if rev > 1 */
882 if (rev > 1)
883 return -ENODEV;
884 ppi[0] = &info_hpt302;
885 /* Check this */
886 chip_table = &hpt302;
887 break;
888 case PCI_DEVICE_ID_TTI_HPT371:
889 if (rev > 1)
890 return -ENODEV;
891 ppi[0] = &info_hpt302;
892 chip_table = &hpt371;
893 /*
894 * Single channel device, master is not present but the BIOS
895 * (or us for non x86) must mark it absent
896 */
897 pci_read_config_byte(dev, 0x50, &mcr1);
898 mcr1 &= ~0x04;
899 pci_write_config_byte(dev, 0x50, mcr1);
900 break;
901 case PCI_DEVICE_ID_TTI_HPT374:
902 chip_table = &hpt374;
903 if (!(PCI_FUNC(dev->devfn) & 1))
904 *ppi = &info_hpt374_fn0;
905 else
906 *ppi = &info_hpt374_fn1;
907 break;
908 default:
Joe Perches8d7b1c72011-01-31 08:39:24 -0800909 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
Sergei Shtylyov910f7bb2011-01-10 22:31:13 +0300910 return -ENODEV;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400911 }
912 /* Ok so this is a chip we support */
913
914 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
915 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
916 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
917 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
918
919 pci_read_config_byte(dev, 0x5A, &irqmask);
920 irqmask &= ~0x10;
921 pci_write_config_byte(dev, 0x5a, irqmask);
922
923 /*
924 * default to pci clock. make sure MA15/16 are set to output
925 * to prevent drives having problems with 40-pin cables. Needed
926 * for some drives such as IBM-DTLA which will not enter ready
927 * state on reset when PDIAG is a input.
928 */
929
Jeff Garzik85cd7252006-08-31 00:03:49 -0400930 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -0400931
Alan Coxfcc2f692007-03-08 23:28:52 +0000932 /*
933 * HighPoint does this for HPT372A.
934 * NOTE: This register is only writeable via I/O space.
935 */
936 if (chip_table == &hpt372a)
937 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400938
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300939 /*
940 * Some devices do not let this value be accessed via PCI space
941 * according to the old driver. In addition we must use the value
942 * from FN 0 on the HPT374.
943 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000944
Alan Cox73946f92007-11-05 22:53:38 +0000945 if (chip_table == &hpt374) {
946 freq = hpt374_read_freq(dev);
947 if (freq == 0)
948 return -ENODEV;
949 } else
950 freq = inl(iobase + 0x90);
951
Jeff Garzik669a5db2006-08-29 18:12:40 -0400952 if ((freq >> 12) != 0xABCDE) {
953 int i;
954 u8 sr;
955 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400956
Joe Perches8d7b1c72011-01-31 08:39:24 -0800957 pr_warn("BIOS has not set timing clocks\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -0400958
Jeff Garzik669a5db2006-08-29 18:12:40 -0400959 /* This is the process the HPT371 BIOS is reported to use */
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300960 for (i = 0; i < 128; i++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400961 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +0000962 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400963 udelay(15);
964 }
965 freq = total / 128;
966 }
967 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400968
Jeff Garzik669a5db2006-08-29 18:12:40 -0400969 /*
970 * Turn the frequency check into a band and then find a timing
971 * table to match it.
972 */
Jeff Garzika617c092007-05-21 20:14:23 -0400973
Jeff Garzik669a5db2006-08-29 18:12:40 -0400974 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +0000975 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400976 /*
977 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +0000978 *
979 * For non UDMA133 capable devices we should
980 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -0400981 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000982 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +0100983 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -0400984
Alan Cox960c8a12007-05-25 20:48:55 +0100985 /* Compute DPLL */
Tejun Heo887125e2008-03-25 12:22:49 +0900986 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -0400987
Alan Cox960c8a12007-05-25 20:48:55 +0100988 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +0000989 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +0100990 if (clock_slot > 1)
991 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +0000992
993 /* Select the DPLL clock. */
994 pci_write_config_byte(dev, 0x5b, 0x21);
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300995 pci_write_config_dword(dev, 0x5C,
996 (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400997
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +0300998 for (adjust = 0; adjust < 8; adjust++) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400999 if (hpt37x_calibrate_dpll(dev))
1000 break;
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001001 /*
1002 * See if it'll settle at a fractionally
1003 * different clock
1004 */
Alan Cox64a81702007-07-24 15:17:48 +01001005 if (adjust & 1)
1006 f_low -= adjust >> 1;
1007 else
1008 f_high += adjust >> 1;
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001009 pci_write_config_dword(dev, 0x5C,
1010 (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001011 }
1012 if (adjust == 8) {
Joe Perches8d7b1c72011-01-31 08:39:24 -08001013 pr_err("DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -04001014 return -ENODEV;
1015 }
Alan Cox960c8a12007-05-25 20:48:55 +01001016 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +02001017 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +00001018 else
Tejun Heo1626aeb2007-05-04 12:43:58 +02001019 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -04001020
Joe Perches8d7b1c72011-01-31 08:39:24 -08001021 pr_info("bus clock %dMHz, using %dMHz DPLL\n",
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001022 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001023 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +02001024 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -04001025 /*
Alan Coxa4734462007-04-26 00:19:25 -07001026 * Perform a final fixup. Note that we will have used the
1027 * DPLL on the HPT372 which means we don't have to worry
1028 * about lack of UDMA133 support on lower clocks
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001029 */
Jeff Garzik85cd7252006-08-31 00:03:49 -04001030
Tejun Heo887125e2008-03-25 12:22:49 +09001031 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1032 ppi[0] = &info_hpt370_33;
1033 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1034 ppi[0] = &info_hpt370a_33;
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001035
Joe Perches8d7b1c72011-01-31 08:39:24 -08001036 pr_info("%s using %dMHz bus clock\n",
Sergei Shtylyov40d69ba2011-01-10 21:39:34 +03001037 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001038 }
Alan Coxfcc2f692007-03-08 23:28:52 +00001039
Jeff Garzik669a5db2006-08-29 18:12:40 -04001040 /* Now kick off ATA set up */
Tejun Heo1c5afdf2010-05-19 22:10:22 +02001041 return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001042}
1043
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001044static const struct pci_device_id hpt37x[] = {
1045 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1046 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1047 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1048 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1049 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1050
1051 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001052};
1053
1054static struct pci_driver hpt37x_pci_driver = {
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001055 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001056 .id_table = hpt37x,
Sergei Shtylyov49bfbd32010-12-28 23:09:27 +03001057 .probe = hpt37x_init_one,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001058 .remove = ata_pci_remove_one
1059};
1060
Axel Lin2fc75da2012-04-19 13:43:05 +08001061module_pci_driver(hpt37x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001062
Jeff Garzik669a5db2006-08-29 18:12:40 -04001063MODULE_AUTHOR("Alan Cox");
1064MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1065MODULE_LICENSE("GPL");
1066MODULE_DEVICE_TABLE(pci, hpt37x);
1067MODULE_VERSION(DRV_VERSION);