Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include "hw.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 18 | #include "ar9003_mac.h" |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 19 | #include "ar9003_2p2_initvals.h" |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 20 | #include "ar9485_initvals.h" |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 21 | #include "ar9340_initvals.h" |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 22 | #include "ar9330_1p1_initvals.h" |
| 23 | #include "ar9330_1p2_initvals.h" |
Gabor Juhos | a0fbb9b | 2012-07-03 19:13:22 +0200 | [diff] [blame] | 24 | #include "ar955x_1p0_initvals.h" |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 25 | #include "ar9580_1p0_initvals.h" |
Rajkumar Manoharan | 76db2f8 | 2011-10-13 11:00:43 +0530 | [diff] [blame] | 26 | #include "ar9462_2p0_initvals.h" |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 27 | #include "ar9462_2p1_initvals.h" |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 28 | #include "ar9565_1p0_initvals.h" |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 29 | |
| 30 | /* General hardware code for the AR9003 hadware family */ |
| 31 | |
Luis R. Rodriguez | 886b42b | 2010-10-14 11:44:27 -0700 | [diff] [blame] | 32 | /* |
| 33 | * The AR9003 family uses a new INI format (pre, core, post |
| 34 | * arrays per subsystem). This provides support for the |
| 35 | * AR9003 2.2 chipsets. |
| 36 | */ |
| 37 | static void ar9003_hw_init_mode_regs(struct ath_hw *ah) |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 38 | { |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 39 | if (AR_SREV_9330_11(ah)) { |
| 40 | /* mac */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 41 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 42 | ar9331_1p1_mac_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 43 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 44 | ar9331_1p1_mac_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 45 | |
| 46 | /* bb */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 47 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 48 | ar9331_1p1_baseband_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 49 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 50 | ar9331_1p1_baseband_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 51 | |
| 52 | /* radio */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 53 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 54 | ar9331_1p1_radio_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 55 | |
| 56 | /* soc */ |
| 57 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 58 | ar9331_1p1_soc_preamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 59 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 60 | ar9331_1p1_soc_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 61 | |
| 62 | /* rx/tx gain */ |
| 63 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 64 | ar9331_common_rx_gain_1p1); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 65 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 66 | ar9331_modes_lowest_ob_db_tx_gain_1p1); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 67 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 68 | /* Japan 2484 Mhz CCK */ |
| 69 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 70 | ar9331_1p1_baseband_core_txfir_coeff_japan_2484); |
| 71 | |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 72 | /* additional clock settings */ |
| 73 | if (ah->is_clk_25mhz) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 74 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 75 | ar9331_1p1_xtal_25M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 76 | else |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 77 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 78 | ar9331_1p1_xtal_40M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 79 | } else if (AR_SREV_9330_12(ah)) { |
| 80 | /* mac */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 81 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 82 | ar9331_1p2_mac_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 83 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 84 | ar9331_1p2_mac_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 85 | |
| 86 | /* bb */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 87 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 88 | ar9331_1p2_baseband_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 89 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 90 | ar9331_1p2_baseband_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 91 | |
| 92 | /* radio */ |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 93 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 94 | ar9331_1p2_radio_core); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 95 | |
| 96 | /* soc */ |
| 97 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 98 | ar9331_1p2_soc_preamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 99 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 100 | ar9331_1p2_soc_postamble); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 101 | |
| 102 | /* rx/tx gain */ |
| 103 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 104 | ar9331_common_rx_gain_1p2); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 105 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 106 | ar9331_modes_lowest_ob_db_tx_gain_1p2); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 107 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 108 | /* Japan 2484 Mhz CCK */ |
| 109 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 110 | ar9331_1p2_baseband_core_txfir_coeff_japan_2484); |
| 111 | |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 112 | /* additional clock settings */ |
| 113 | if (ah->is_clk_25mhz) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 114 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 115 | ar9331_1p2_xtal_25M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 116 | else |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 117 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 118 | ar9331_1p2_xtal_40M); |
Gabor Juhos | 172805a | 2011-06-21 11:23:26 +0200 | [diff] [blame] | 119 | } else if (AR_SREV_9340(ah)) { |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 120 | /* mac */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 121 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 122 | ar9340_1p0_mac_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 123 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 124 | ar9340_1p0_mac_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 125 | |
| 126 | /* bb */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 127 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 128 | ar9340_1p0_baseband_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 129 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 130 | ar9340_1p0_baseband_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 131 | |
| 132 | /* radio */ |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 133 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 134 | ar9340_1p0_radio_core); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 135 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 136 | ar9340_1p0_radio_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 137 | |
| 138 | /* soc */ |
| 139 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 140 | ar9340_1p0_soc_preamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 141 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 142 | ar9340_1p0_soc_postamble); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 143 | |
| 144 | /* rx/tx gain */ |
| 145 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 146 | ar9340Common_wo_xlna_rx_gain_table_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 147 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 148 | ar9340Modes_high_ob_db_tx_gain_table_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 149 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 150 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 151 | ar9340Modes_fast_clock_1p0); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 152 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 153 | if (!ah->is_clk_25mhz) |
| 154 | INIT_INI_ARRAY(&ah->iniAdditional, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 155 | ar9340_1p0_radio_core_40M); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 156 | } else if (AR_SREV_9485_11(ah)) { |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 157 | /* mac */ |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 158 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 159 | ar9485_1_1_mac_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 160 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 161 | ar9485_1_1_mac_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 162 | |
| 163 | /* bb */ |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 164 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 165 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 166 | ar9485_1_1_baseband_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 167 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 168 | ar9485_1_1_baseband_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 169 | |
| 170 | /* radio */ |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 171 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 172 | ar9485_1_1_radio_core); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 173 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 174 | ar9485_1_1_radio_postamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 175 | |
| 176 | /* soc */ |
| 177 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 178 | ar9485_1_1_soc_preamble); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 179 | |
| 180 | /* rx/tx gain */ |
| 181 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 182 | ar9485Common_wo_xlna_rx_gain_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 183 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 184 | ar9485_modes_lowest_ob_db_tx_gain_1_1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 185 | |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 186 | /* Japan 2484 Mhz CCK */ |
| 187 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 188 | ar9485_1_1_baseband_core_txfir_coeff_japan_2484); |
| 189 | |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 190 | /* Load PCIE SERDES settings from INI */ |
| 191 | |
| 192 | /* Awake Setting */ |
| 193 | |
| 194 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 195 | ar9485_1_1_pcie_phy_clkreq_disable_L1); |
Vivek Natarajan | 1a63e2c | 2011-02-18 16:49:47 +0530 | [diff] [blame] | 196 | |
| 197 | /* Sleep Setting */ |
| 198 | |
| 199 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 200 | ar9485_1_1_pcie_phy_clkreq_disable_L1); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 201 | } else if (AR_SREV_9462_21(ah)) { |
| 202 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 203 | ar9462_2p1_mac_core); |
| 204 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 205 | ar9462_2p1_mac_postamble); |
| 206 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 207 | ar9462_2p1_baseband_core); |
| 208 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 209 | ar9462_2p1_baseband_postamble); |
| 210 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 211 | ar9462_2p1_radio_core); |
| 212 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 213 | ar9462_2p1_radio_postamble); |
| 214 | INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, |
| 215 | ar9462_2p1_radio_postamble_sys2ant); |
| 216 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 217 | ar9462_2p1_soc_preamble); |
| 218 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 219 | ar9462_2p1_soc_postamble); |
| 220 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 221 | ar9462_2p1_common_rx_gain); |
| 222 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
| 223 | ar9462_2p1_modes_fast_clock); |
| 224 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
| 225 | ar9462_2p1_baseband_core_txfir_coeff_japan_2484); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 226 | } else if (AR_SREV_9462_20(ah)) { |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 227 | |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 228 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 229 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 230 | ar9462_2p0_mac_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 231 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 232 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 233 | ar9462_2p0_baseband_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 234 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 235 | ar9462_2p0_baseband_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 236 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 237 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 238 | ar9462_2p0_radio_core); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 239 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 240 | ar9462_2p0_radio_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 241 | INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 242 | ar9462_2p0_radio_postamble_sys2ant); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 243 | |
| 244 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 245 | ar9462_2p0_soc_preamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 246 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 247 | ar9462_2p0_soc_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 248 | |
| 249 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 250 | ar9462_common_rx_gain_table_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 251 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 252 | /* Awake -> Sleep Setting */ |
| 253 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Rajkumar Manoharan | 1680260 | 2012-10-25 17:11:31 +0530 | [diff] [blame] | 254 | ar9462_pciephy_clkreq_disable_L1_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 255 | /* Sleep -> Awake Setting */ |
| 256 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Rajkumar Manoharan | 1680260 | 2012-10-25 17:11:31 +0530 | [diff] [blame] | 257 | ar9462_pciephy_clkreq_disable_L1_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 258 | |
| 259 | /* Fast clock modal settings */ |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 260 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 261 | ar9462_modes_fast_clock_2p0); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 262 | |
| 263 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 264 | ar9462_2p0_baseband_core_txfir_coeff_japan_2484); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 265 | } else if (AR_SREV_9550(ah)) { |
| 266 | /* mac */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 267 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 268 | ar955x_1p0_mac_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 269 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 270 | ar955x_1p0_mac_postamble); |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 271 | |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 272 | /* bb */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 273 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 274 | ar955x_1p0_baseband_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 275 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 276 | ar955x_1p0_baseband_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 277 | |
| 278 | /* radio */ |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 279 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 280 | ar955x_1p0_radio_core); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 281 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 282 | ar955x_1p0_radio_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 283 | |
| 284 | /* soc */ |
| 285 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 286 | ar955x_1p0_soc_preamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 287 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 288 | ar955x_1p0_soc_postamble); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 289 | |
| 290 | /* rx/tx gain */ |
| 291 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 292 | ar955x_1p0_common_wo_xlna_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 293 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 294 | ar955x_1p0_common_wo_xlna_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 295 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 296 | ar955x_1p0_modes_xpa_tx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 297 | |
| 298 | /* Fast clock modal settings */ |
| 299 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 300 | ar955x_1p0_modes_fast_clock); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 301 | } else if (AR_SREV_9580(ah)) { |
| 302 | /* mac */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 303 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 304 | ar9580_1p0_mac_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 305 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 306 | ar9580_1p0_mac_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 307 | |
| 308 | /* bb */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 309 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 310 | ar9580_1p0_baseband_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 311 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 312 | ar9580_1p0_baseband_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 313 | |
| 314 | /* radio */ |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 315 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 316 | ar9580_1p0_radio_core); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 317 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 318 | ar9580_1p0_radio_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 319 | |
| 320 | /* soc */ |
| 321 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 322 | ar9580_1p0_soc_preamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 323 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 324 | ar9580_1p0_soc_postamble); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 325 | |
| 326 | /* rx/tx gain */ |
| 327 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 328 | ar9580_1p0_rx_gain_table); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 329 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 330 | ar9580_1p0_low_ob_db_tx_gain_table); |
Luis R. Rodriguez | 5a63ef0 | 2011-08-24 15:36:08 -0700 | [diff] [blame] | 331 | |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 332 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 333 | ar9580_1p0_modes_fast_clock); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 334 | } else if (AR_SREV_9565(ah)) { |
| 335 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
| 336 | ar9565_1p0_mac_core); |
| 337 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
| 338 | ar9565_1p0_mac_postamble); |
| 339 | |
| 340 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
| 341 | ar9565_1p0_baseband_core); |
| 342 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
| 343 | ar9565_1p0_baseband_postamble); |
| 344 | |
| 345 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
| 346 | ar9565_1p0_radio_core); |
| 347 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
| 348 | ar9565_1p0_radio_postamble); |
| 349 | |
| 350 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
| 351 | ar9565_1p0_soc_preamble); |
| 352 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
| 353 | ar9565_1p0_soc_postamble); |
| 354 | |
| 355 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 356 | ar9565_1p0_Common_rx_gain_table); |
| 357 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 358 | ar9565_1p0_Modes_lowest_ob_db_tx_gain_table); |
| 359 | |
| 360 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Rajkumar Manoharan | 8446484 | 2012-10-25 17:16:51 +0530 | [diff] [blame] | 361 | ar9565_1p0_pciephy_clkreq_disable_L1); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 362 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Rajkumar Manoharan | 8446484 | 2012-10-25 17:16:51 +0530 | [diff] [blame] | 363 | ar9565_1p0_pciephy_clkreq_disable_L1); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 364 | |
| 365 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
| 366 | ar9565_1p0_modes_fast_clock); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 367 | } else { |
| 368 | /* mac */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 369 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 370 | ar9300_2p2_mac_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 371 | INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 372 | ar9300_2p2_mac_postamble); |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 373 | |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 374 | /* bb */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 375 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 376 | ar9300_2p2_baseband_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 377 | INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 378 | ar9300_2p2_baseband_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 379 | |
| 380 | /* radio */ |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 381 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 382 | ar9300_2p2_radio_core); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 383 | INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 384 | ar9300_2p2_radio_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 385 | |
| 386 | /* soc */ |
| 387 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 388 | ar9300_2p2_soc_preamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 389 | INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 390 | ar9300_2p2_soc_postamble); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 391 | |
| 392 | /* rx/tx gain */ |
| 393 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 394 | ar9300Common_rx_gain_table_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 395 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 396 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 397 | |
| 398 | /* Load PCIE SERDES settings from INI */ |
| 399 | |
| 400 | /* Awake Setting */ |
| 401 | |
| 402 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 403 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 404 | |
| 405 | /* Sleep Setting */ |
| 406 | |
| 407 | INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 408 | ar9300PciePhy_pll_on_clkreq_disable_L1_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 409 | |
| 410 | /* Fast clock modal settings */ |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 411 | INIT_INI_ARRAY(&ah->iniModesFastClock, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 412 | ar9300Modes_fast_clock_2p2); |
Vasanthakumar Thiagarajan | c88457e | 2010-12-06 04:27:37 -0800 | [diff] [blame] | 413 | } |
Luis R. Rodriguez | 7284635 | 2010-05-12 21:15:05 -0400 | [diff] [blame] | 414 | } |
| 415 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 416 | static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) |
| 417 | { |
| 418 | if (AR_SREV_9330_12(ah)) |
| 419 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 420 | ar9331_modes_lowest_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 421 | else if (AR_SREV_9330_11(ah)) |
| 422 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 423 | ar9331_modes_lowest_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 424 | else if (AR_SREV_9340(ah)) |
| 425 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 426 | ar9340Modes_lowest_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 427 | else if (AR_SREV_9485_11(ah)) |
| 428 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 429 | ar9485_modes_lowest_ob_db_tx_gain_1_1); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 430 | else if (AR_SREV_9550(ah)) |
| 431 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 432 | ar955x_1p0_modes_xpa_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 433 | else if (AR_SREV_9580(ah)) |
| 434 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 435 | ar9580_1p0_lowest_ob_db_tx_gain_table); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 436 | else if (AR_SREV_9462_21(ah)) |
| 437 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 438 | ar9462_2p1_modes_low_ob_db_tx_gain); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 439 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 440 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 441 | ar9462_modes_low_ob_db_tx_gain_table_2p0); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 442 | else if (AR_SREV_9565(ah)) |
| 443 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 444 | ar9565_1p0_modes_low_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 445 | else |
| 446 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 447 | ar9300Modes_lowest_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) |
| 451 | { |
| 452 | if (AR_SREV_9330_12(ah)) |
| 453 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 454 | ar9331_modes_high_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 455 | else if (AR_SREV_9330_11(ah)) |
| 456 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 457 | ar9331_modes_high_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 458 | else if (AR_SREV_9340(ah)) |
| 459 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 460 | ar9340Modes_high_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 461 | else if (AR_SREV_9485_11(ah)) |
| 462 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 463 | ar9485Modes_high_ob_db_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 464 | else if (AR_SREV_9580(ah)) |
| 465 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 466 | ar9580_1p0_high_ob_db_tx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 467 | else if (AR_SREV_9550(ah)) |
| 468 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 469 | ar955x_1p0_modes_no_xpa_tx_gain_table); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 470 | else if (AR_SREV_9462_21(ah)) |
| 471 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 472 | ar9462_2p1_modes_high_ob_db_tx_gain); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 473 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 474 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 475 | ar9462_modes_high_ob_db_tx_gain_table_2p0); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 476 | else if (AR_SREV_9565(ah)) |
| 477 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 478 | ar9565_1p0_modes_high_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 479 | else |
| 480 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 481 | ar9300Modes_high_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) |
| 485 | { |
| 486 | if (AR_SREV_9330_12(ah)) |
| 487 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 488 | ar9331_modes_low_ob_db_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 489 | else if (AR_SREV_9330_11(ah)) |
| 490 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 491 | ar9331_modes_low_ob_db_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 492 | else if (AR_SREV_9340(ah)) |
| 493 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 494 | ar9340Modes_low_ob_db_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 495 | else if (AR_SREV_9485_11(ah)) |
| 496 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 497 | ar9485Modes_low_ob_db_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 498 | else if (AR_SREV_9580(ah)) |
| 499 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 500 | ar9580_1p0_low_ob_db_tx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 501 | else if (AR_SREV_9565(ah)) |
| 502 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 503 | ar9565_1p0_modes_low_ob_db_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 504 | else |
| 505 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 506 | ar9300Modes_low_ob_db_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 507 | } |
| 508 | |
| 509 | static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) |
| 510 | { |
| 511 | if (AR_SREV_9330_12(ah)) |
| 512 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 513 | ar9331_modes_high_power_tx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 514 | else if (AR_SREV_9330_11(ah)) |
| 515 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 516 | ar9331_modes_high_power_tx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 517 | else if (AR_SREV_9340(ah)) |
| 518 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 519 | ar9340Modes_high_power_tx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 520 | else if (AR_SREV_9485_11(ah)) |
| 521 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 522 | ar9485Modes_high_power_tx_gain_1_1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 523 | else if (AR_SREV_9580(ah)) |
| 524 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 525 | ar9580_1p0_high_power_tx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 526 | else if (AR_SREV_9565(ah)) |
| 527 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 528 | ar9565_1p0_modes_high_power_tx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 529 | else |
| 530 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 531 | ar9300Modes_high_power_tx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 532 | } |
| 533 | |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 534 | static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) |
| 535 | { |
| 536 | if (AR_SREV_9340(ah)) |
| 537 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 538 | ar9340Modes_mixed_ob_db_tx_gain_table_1p0); |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 539 | else if (AR_SREV_9580(ah)) |
| 540 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 541 | ar9580_1p0_mixed_ob_db_tx_gain_table); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 542 | else if (AR_SREV_9462_21(ah)) |
| 543 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 544 | ar9462_2p1_modes_mix_ob_db_tx_gain); |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 545 | else |
| 546 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 547 | ar9300Modes_mixed_ob_db_tx_gain_table_2p2); |
Felix Fietkau | b05a011 | 2012-07-15 19:53:32 +0200 | [diff] [blame] | 548 | } |
| 549 | |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 550 | static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) |
| 551 | { |
| 552 | if (AR_SREV_9485_11(ah)) |
| 553 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 554 | ar9485Modes_green_ob_db_tx_gain_1_1); |
| 555 | else if (AR_SREV_9340(ah)) |
| 556 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 557 | ar9340Modes_ub124_tx_gain_table_1p0); |
| 558 | else if (AR_SREV_9580(ah)) |
| 559 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 560 | ar9580_1p0_type5_tx_gain_table); |
| 561 | else if (AR_SREV_9300_22(ah)) |
| 562 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 563 | ar9300Modes_type5_tx_gain_table_2p2); |
| 564 | } |
| 565 | |
| 566 | static void ar9003_tx_gain_table_mode6(struct ath_hw *ah) |
| 567 | { |
| 568 | if (AR_SREV_9340(ah)) |
| 569 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 570 | ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0); |
| 571 | else if (AR_SREV_9485_11(ah)) |
| 572 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 573 | ar9485Modes_green_spur_ob_db_tx_gain_1_1); |
| 574 | else if (AR_SREV_9580(ah)) |
| 575 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
| 576 | ar9580_1p0_type6_tx_gain_table); |
| 577 | } |
| 578 | |
| 579 | typedef void (*ath_txgain_tab)(struct ath_hw *ah); |
| 580 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 581 | static void ar9003_tx_gain_table_apply(struct ath_hw *ah) |
| 582 | { |
Felix Fietkau | eab6d79 | 2013-01-10 19:41:52 +0100 | [diff] [blame] | 583 | static const ath_txgain_tab modes[] = { |
| 584 | ar9003_tx_gain_table_mode0, |
| 585 | ar9003_tx_gain_table_mode1, |
| 586 | ar9003_tx_gain_table_mode2, |
| 587 | ar9003_tx_gain_table_mode3, |
| 588 | ar9003_tx_gain_table_mode4, |
| 589 | ar9003_tx_gain_table_mode5, |
| 590 | ar9003_tx_gain_table_mode6, |
| 591 | }; |
| 592 | int idx = ar9003_hw_get_tx_gain_idx(ah); |
| 593 | |
| 594 | if (idx >= ARRAY_SIZE(modes)) |
| 595 | idx = 0; |
| 596 | |
| 597 | modes[idx](ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 598 | } |
| 599 | |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 600 | static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) |
| 601 | { |
| 602 | if (AR_SREV_9330_12(ah)) |
| 603 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 604 | ar9331_common_rx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 605 | else if (AR_SREV_9330_11(ah)) |
| 606 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 607 | ar9331_common_rx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 608 | else if (AR_SREV_9340(ah)) |
| 609 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 610 | ar9340Common_rx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 611 | else if (AR_SREV_9485_11(ah)) |
| 612 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Sujith Manoharan | a796a1d | 2012-12-26 12:27:39 +0530 | [diff] [blame] | 613 | ar9485_common_rx_gain_1_1); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 614 | else if (AR_SREV_9550(ah)) { |
| 615 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 616 | ar955x_1p0_common_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 617 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 618 | ar955x_1p0_common_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 619 | } else if (AR_SREV_9580(ah)) |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 620 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 621 | ar9580_1p0_rx_gain_table); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 622 | else if (AR_SREV_9462_21(ah)) |
| 623 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 624 | ar9462_2p1_common_rx_gain); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 625 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 626 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 627 | ar9462_common_rx_gain_table_2p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 628 | else |
| 629 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 630 | ar9300Common_rx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) |
| 634 | { |
| 635 | if (AR_SREV_9330_12(ah)) |
| 636 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 637 | ar9331_common_wo_xlna_rx_gain_1p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 638 | else if (AR_SREV_9330_11(ah)) |
| 639 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 640 | ar9331_common_wo_xlna_rx_gain_1p1); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 641 | else if (AR_SREV_9340(ah)) |
| 642 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 643 | ar9340Common_wo_xlna_rx_gain_table_1p0); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 644 | else if (AR_SREV_9485_11(ah)) |
| 645 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 646 | ar9485Common_wo_xlna_rx_gain_1_1); |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 647 | else if (AR_SREV_9462_21(ah)) |
| 648 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 649 | ar9462_2p1_common_wo_xlna_rx_gain); |
Rajkumar Manoharan | 423e38e | 2011-10-13 11:00:44 +0530 | [diff] [blame] | 650 | else if (AR_SREV_9462_20(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 651 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 652 | ar9462_common_wo_xlna_rx_gain_table_2p0); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 653 | else if (AR_SREV_9550(ah)) { |
| 654 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 655 | ar955x_1p0_common_wo_xlna_rx_gain_table); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 656 | INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 657 | ar955x_1p0_common_wo_xlna_rx_gain_bounds); |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 658 | } else if (AR_SREV_9580(ah)) |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 659 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 660 | ar9580_1p0_wo_xlna_rx_gain_table); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 661 | else if (AR_SREV_9565(ah)) |
| 662 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 663 | ar9565_1p0_common_wo_xlna_rx_gain_table); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 664 | else |
| 665 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 666 | ar9300Common_wo_xlna_rx_gain_table_2p2); |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 667 | } |
| 668 | |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 669 | static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) |
| 670 | { |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 671 | if (AR_SREV_9462_21(ah)) { |
| 672 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 673 | ar9462_2p1_common_mixed_rx_gain); |
| 674 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, |
| 675 | ar9462_2p1_baseband_core_mix_rxgain); |
| 676 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, |
| 677 | ar9462_2p1_baseband_postamble_mix_rxgain); |
| 678 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, |
| 679 | ar9462_2p1_baseband_postamble_5g_xlna); |
| 680 | } else if (AR_SREV_9462_20(ah)) { |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 681 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
Felix Fietkau | a364517 | 2012-07-15 19:53:33 +0200 | [diff] [blame] | 682 | ar9462_common_mixed_rx_gain_table_2p0); |
Sujith Manoharan | c177fab | 2013-06-18 15:42:38 +0530 | [diff] [blame] | 683 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core, |
| 684 | ar9462_2p0_baseband_core_mix_rxgain); |
| 685 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble, |
| 686 | ar9462_2p0_baseband_postamble_mix_rxgain); |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 687 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, |
| 688 | ar9462_2p0_baseband_postamble_5g_xlna); |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | static void ar9003_rx_gain_table_mode3(struct ath_hw *ah) |
| 693 | { |
Sujith Manoharan | d567e4e | 2013-06-24 18:18:45 +0530 | [diff] [blame^] | 694 | if (AR_SREV_9462_21(ah)) { |
| 695 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 696 | ar9462_2p1_common_5g_xlna_only_rx_gain); |
| 697 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, |
| 698 | ar9462_2p1_baseband_postamble_5g_xlna); |
| 699 | } else if (AR_SREV_9462_20(ah)) { |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 700 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
| 701 | ar9462_2p0_5g_xlna_only_rxgain); |
| 702 | INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna, |
| 703 | ar9462_2p0_baseband_postamble_5g_xlna); |
| 704 | } |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 705 | } |
| 706 | |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 707 | static void ar9003_rx_gain_table_apply(struct ath_hw *ah) |
| 708 | { |
| 709 | switch (ar9003_hw_get_rx_gain_idx(ah)) { |
| 710 | case 0: |
| 711 | default: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 712 | ar9003_rx_gain_table_mode0(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 713 | break; |
| 714 | case 1: |
Senthil Balasubramanian | 4d0707e | 2011-09-13 22:38:17 +0530 | [diff] [blame] | 715 | ar9003_rx_gain_table_mode1(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 716 | break; |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 717 | case 2: |
| 718 | ar9003_rx_gain_table_mode2(ah); |
| 719 | break; |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 720 | case 3: |
| 721 | ar9003_rx_gain_table_mode3(ah); |
| 722 | break; |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 723 | } |
| 724 | } |
| 725 | |
| 726 | /* set gain table pointers according to values read from the eeprom */ |
| 727 | static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 728 | { |
| 729 | ar9003_tx_gain_table_apply(ah); |
| 730 | ar9003_rx_gain_table_apply(ah); |
| 731 | } |
| 732 | |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 733 | /* |
| 734 | * Helper for ASPM support. |
| 735 | * |
| 736 | * Disable PLL when in L0s as well as receiver clock when in L1. |
| 737 | * This power saving option must be enabled through the SerDes. |
| 738 | * |
| 739 | * Programming the SerDes must go through the same 288 bit serial shift |
| 740 | * register as the other analog registers. Hence the 9 writes. |
| 741 | */ |
| 742 | static void ar9003_hw_configpcipowersave(struct ath_hw *ah, |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 743 | bool power_off) |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 744 | { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 745 | /* Nothing to do on restore for 11N */ |
Stanislaw Gruszka | 84c87dc | 2011-08-05 13:10:32 +0200 | [diff] [blame] | 746 | if (!power_off /* !restore */) { |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 747 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
| 748 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
| 749 | |
| 750 | /* Several PCIe massages to ensure proper behaviour */ |
| 751 | if (ah->config.pcie_waen) |
| 752 | REG_WRITE(ah, AR_WA, ah->config.pcie_waen); |
Luis R. Rodriguez | 9a658d2 | 2010-06-21 18:38:47 -0400 | [diff] [blame] | 753 | else |
| 754 | REG_WRITE(ah, AR_WA, ah->WARegVal); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 755 | } |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 756 | |
| 757 | /* |
| 758 | * Configire PCIE after Ini init. SERDES values now come from ini file |
| 759 | * This enables PCIe low power mode. |
| 760 | */ |
Luis R. Rodriguez | 6a0ec30 | 2010-06-21 18:38:49 -0400 | [diff] [blame] | 761 | if (ah->config.pcieSerDesWrite) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 762 | unsigned int i; |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 763 | struct ar5416IniArray *array; |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 764 | |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 765 | array = power_off ? &ah->iniPcieSerdes : |
| 766 | &ah->iniPcieSerdesLowPower; |
| 767 | |
| 768 | for (i = 0; i < array->ia_rows; i++) { |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 769 | REG_WRITE(ah, |
Luis R. Rodriguez | d5c4d19 | 2010-06-21 18:38:50 -0400 | [diff] [blame] | 770 | INI_RA(array, i, 0), |
| 771 | INI_RA(array, i, 1)); |
Luis R. Rodriguez | 653fe37 | 2010-06-21 18:38:48 -0400 | [diff] [blame] | 772 | } |
| 773 | } |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 774 | } |
| 775 | |
| 776 | /* Sets up the AR9003 hardware familiy callbacks */ |
| 777 | void ar9003_hw_attach_ops(struct ath_hw *ah) |
| 778 | { |
| 779 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 780 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
| 781 | |
Felix Fietkau | 6aaacd8 | 2013-01-13 19:54:58 +0100 | [diff] [blame] | 782 | ar9003_hw_init_mode_regs(ah); |
Luis R. Rodriguez | c14a85d | 2010-04-15 17:39:21 -0400 | [diff] [blame] | 783 | priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs; |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 784 | |
| 785 | ops->config_pci_powersave = ar9003_hw_configpcipowersave; |
| 786 | |
| 787 | ar9003_hw_attach_phy_ops(ah); |
| 788 | ar9003_hw_attach_calib_ops(ah); |
| 789 | ar9003_hw_attach_mac_ops(ah); |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 790 | } |