Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _HW_H_ |
| 19 | #define _HW_H_ |
| 20 | |
| 21 | #include "targaddrs.h" |
| 22 | |
Kalle Valo | a58227e | 2014-10-13 09:40:59 +0300 | [diff] [blame] | 23 | #define ATH10K_FW_DIR "ath10k" |
| 24 | |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 25 | /* QCA988X 1.0 definitions (unsupported) */ |
| 26 | #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 |
| 27 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 28 | /* QCA988X 2.0 definitions */ |
| 29 | #define QCA988X_HW_2_0_VERSION 0x4100016c |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 30 | #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 |
Kalle Valo | a58227e | 2014-10-13 09:40:59 +0300 | [diff] [blame] | 31 | #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 32 | #define QCA988X_HW_2_0_FW_FILE "firmware.bin" |
| 33 | #define QCA988X_HW_2_0_OTP_FILE "otp.bin" |
| 34 | #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" |
| 35 | #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 |
| 36 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 37 | /* QCA6174 target BMI version signatures */ |
| 38 | #define QCA6174_HW_1_0_VERSION 0x05000000 |
| 39 | #define QCA6174_HW_1_1_VERSION 0x05000001 |
| 40 | #define QCA6174_HW_1_3_VERSION 0x05000003 |
| 41 | #define QCA6174_HW_2_1_VERSION 0x05010000 |
| 42 | #define QCA6174_HW_3_0_VERSION 0x05020000 |
| 43 | |
| 44 | enum qca6174_pci_rev { |
| 45 | QCA6174_PCI_REV_1_1 = 0x11, |
| 46 | QCA6174_PCI_REV_1_3 = 0x13, |
| 47 | QCA6174_PCI_REV_2_0 = 0x20, |
| 48 | QCA6174_PCI_REV_3_0 = 0x30, |
| 49 | }; |
| 50 | |
| 51 | enum qca6174_chip_id_rev { |
| 52 | QCA6174_HW_1_0_CHIP_ID_REV = 0, |
| 53 | QCA6174_HW_1_1_CHIP_ID_REV = 1, |
| 54 | QCA6174_HW_1_3_CHIP_ID_REV = 2, |
| 55 | QCA6174_HW_2_1_CHIP_ID_REV = 4, |
| 56 | QCA6174_HW_2_2_CHIP_ID_REV = 5, |
| 57 | QCA6174_HW_3_0_CHIP_ID_REV = 8, |
| 58 | QCA6174_HW_3_1_CHIP_ID_REV = 9, |
| 59 | QCA6174_HW_3_2_CHIP_ID_REV = 10, |
| 60 | }; |
| 61 | |
| 62 | #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" |
| 63 | #define QCA6174_HW_2_1_FW_FILE "firmware.bin" |
| 64 | #define QCA6174_HW_2_1_OTP_FILE "otp.bin" |
| 65 | #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" |
| 66 | #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 |
| 67 | |
| 68 | #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" |
| 69 | #define QCA6174_HW_3_0_FW_FILE "firmware.bin" |
| 70 | #define QCA6174_HW_3_0_OTP_FILE "otp.bin" |
| 71 | #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" |
| 72 | #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 |
| 73 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 74 | #define ATH10K_FW_API2_FILE "firmware-2.bin" |
Michal Kazior | 24c88f7 | 2014-07-25 13:32:17 +0200 | [diff] [blame] | 75 | #define ATH10K_FW_API3_FILE "firmware-3.bin" |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 76 | |
Rajkumar Manoharan | 4a16fbe | 2014-12-17 12:21:12 +0200 | [diff] [blame] | 77 | /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ |
| 78 | #define ATH10K_FW_API4_FILE "firmware-4.bin" |
| 79 | |
Kalle Valo | 43d2a30 | 2014-09-10 18:23:30 +0300 | [diff] [blame] | 80 | #define ATH10K_FW_UTF_FILE "utf.bin" |
| 81 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 82 | /* includes also the null byte */ |
| 83 | #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" |
| 84 | |
Ben Greear | 384914b | 2014-08-25 08:37:32 +0300 | [diff] [blame] | 85 | #define REG_DUMP_COUNT_QCA988X 60 |
| 86 | |
Kalle Valo | 7869b4f | 2014-09-24 14:16:58 +0300 | [diff] [blame] | 87 | #define QCA988X_CAL_DATA_LEN 2116 |
| 88 | |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 89 | struct ath10k_fw_ie { |
| 90 | __le32 id; |
| 91 | __le32 len; |
| 92 | u8 data[0]; |
| 93 | }; |
| 94 | |
| 95 | enum ath10k_fw_ie_type { |
| 96 | ATH10K_FW_IE_FW_VERSION = 0, |
| 97 | ATH10K_FW_IE_TIMESTAMP = 1, |
| 98 | ATH10K_FW_IE_FEATURES = 2, |
| 99 | ATH10K_FW_IE_FW_IMAGE = 3, |
| 100 | ATH10K_FW_IE_OTP_IMAGE = 4, |
Kalle Valo | 202e86e | 2014-12-03 10:10:08 +0200 | [diff] [blame] | 101 | |
| 102 | /* WMI "operations" interface version, 32 bit value. Supported from |
| 103 | * FW API 4 and above. |
| 104 | */ |
| 105 | ATH10K_FW_IE_WMI_OP_VERSION = 5, |
| 106 | }; |
| 107 | |
| 108 | enum ath10k_fw_wmi_op_version { |
| 109 | ATH10K_FW_WMI_OP_VERSION_UNSET = 0, |
| 110 | |
| 111 | ATH10K_FW_WMI_OP_VERSION_MAIN = 1, |
| 112 | ATH10K_FW_WMI_OP_VERSION_10_1 = 2, |
| 113 | ATH10K_FW_WMI_OP_VERSION_10_2 = 3, |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 114 | ATH10K_FW_WMI_OP_VERSION_TLV = 4, |
Rajkumar Manoharan | 4a16fbe | 2014-12-17 12:21:12 +0200 | [diff] [blame] | 115 | ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, |
Kalle Valo | 202e86e | 2014-12-03 10:10:08 +0200 | [diff] [blame] | 116 | |
| 117 | /* keep last */ |
| 118 | ATH10K_FW_WMI_OP_VERSION_MAX, |
Kalle Valo | 1a22243 | 2013-09-27 19:55:07 +0300 | [diff] [blame] | 119 | }; |
| 120 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 121 | enum ath10k_hw_rev { |
| 122 | ATH10K_HW_QCA988X, |
| 123 | ATH10K_HW_QCA6174, |
| 124 | }; |
| 125 | |
| 126 | struct ath10k_hw_regs { |
| 127 | u32 rtc_state_cold_reset_mask; |
| 128 | u32 rtc_soc_base_address; |
| 129 | u32 rtc_wmac_base_address; |
| 130 | u32 soc_core_base_address; |
| 131 | u32 ce_wrapper_base_address; |
| 132 | u32 ce0_base_address; |
| 133 | u32 ce1_base_address; |
| 134 | u32 ce2_base_address; |
| 135 | u32 ce3_base_address; |
| 136 | u32 ce4_base_address; |
| 137 | u32 ce5_base_address; |
| 138 | u32 ce6_base_address; |
| 139 | u32 ce7_base_address; |
| 140 | u32 soc_reset_control_si0_rst_mask; |
| 141 | u32 soc_reset_control_ce_rst_mask; |
| 142 | u32 soc_chip_id_address; |
| 143 | u32 scratch_3_address; |
| 144 | }; |
| 145 | |
| 146 | extern const struct ath10k_hw_regs qca988x_regs; |
| 147 | extern const struct ath10k_hw_regs qca6174_regs; |
| 148 | |
| 149 | #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) |
| 150 | #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) |
| 151 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 152 | /* Known pecularities: |
| 153 | * - current FW doesn't support raw rx mode (last tested v599) |
| 154 | * - current FW dumps upon raw tx mode (last tested v599) |
| 155 | * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap |
| 156 | * - raw have FCS, nwifi doesn't |
| 157 | * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher |
| 158 | * param, llc/snap) are aligned to 4byte boundaries each */ |
| 159 | enum ath10k_hw_txrx_mode { |
| 160 | ATH10K_HW_TXRX_RAW = 0, |
| 161 | ATH10K_HW_TXRX_NATIVE_WIFI = 1, |
| 162 | ATH10K_HW_TXRX_ETHERNET = 2, |
Michal Kazior | 961d4c3 | 2013-08-09 10:13:34 +0200 | [diff] [blame] | 163 | |
| 164 | /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ |
| 165 | ATH10K_HW_TXRX_MGMT = 3, |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | enum ath10k_mcast2ucast_mode { |
| 169 | ATH10K_MCAST2UCAST_DISABLED = 0, |
| 170 | ATH10K_MCAST2UCAST_ENABLED = 1, |
| 171 | }; |
| 172 | |
Rajkumar Manoharan | bfdd793 | 2014-10-03 08:02:40 +0300 | [diff] [blame] | 173 | struct ath10k_pktlog_hdr { |
| 174 | __le16 flags; |
| 175 | __le16 missed_cnt; |
| 176 | __le16 log_type; |
| 177 | __le16 size; |
| 178 | __le32 timestamp; |
| 179 | u8 payload[0]; |
| 180 | } __packed; |
| 181 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 182 | /* Target specific defines for MAIN firmware */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 183 | #define TARGET_NUM_VDEVS 8 |
| 184 | #define TARGET_NUM_PEER_AST 2 |
| 185 | #define TARGET_NUM_WDS_ENTRIES 32 |
| 186 | #define TARGET_DMA_BURST_SIZE 0 |
| 187 | #define TARGET_MAC_AGGR_DELIM 0 |
| 188 | #define TARGET_AST_SKID_LIMIT 16 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 189 | #define TARGET_NUM_STATIONS 16 |
| 190 | #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ |
| 191 | (TARGET_NUM_VDEVS)) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 192 | #define TARGET_NUM_OFFLOAD_PEERS 0 |
| 193 | #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 |
| 194 | #define TARGET_NUM_PEER_KEYS 2 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 195 | #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 196 | #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 197 | #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 198 | #define TARGET_RX_TIMEOUT_LO_PRI 100 |
| 199 | #define TARGET_RX_TIMEOUT_HI_PRI 40 |
Michal Kazior | 4d316c7 | 2013-09-26 10:12:24 +0300 | [diff] [blame] | 200 | |
| 201 | /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and |
| 202 | * avoid a very expensive re-alignment in mac80211. */ |
| 203 | #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
| 204 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 205 | #define TARGET_SCAN_MAX_PENDING_REQS 4 |
| 206 | #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 |
| 207 | #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 |
| 208 | #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 209 | #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 |
| 210 | #define TARGET_NUM_MCAST_GROUPS 0 |
| 211 | #define TARGET_NUM_MCAST_TABLE_ELEMS 0 |
| 212 | #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 213 | #define TARGET_TX_DBG_LOG_SIZE 1024 |
| 214 | #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 |
| 215 | #define TARGET_VOW_CONFIG 0 |
| 216 | #define TARGET_NUM_MSDU_DESC (1024 + 400) |
| 217 | #define TARGET_MAX_FRAG_ENTRIES 0 |
| 218 | |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 219 | /* Target specific defines for 10.X firmware */ |
| 220 | #define TARGET_10X_NUM_VDEVS 16 |
| 221 | #define TARGET_10X_NUM_PEER_AST 2 |
| 222 | #define TARGET_10X_NUM_WDS_ENTRIES 32 |
| 223 | #define TARGET_10X_DMA_BURST_SIZE 0 |
| 224 | #define TARGET_10X_MAC_AGGR_DELIM 0 |
| 225 | #define TARGET_10X_AST_SKID_LIMIT 16 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 226 | #define TARGET_10X_NUM_STATIONS 128 |
| 227 | #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ |
| 228 | (TARGET_10X_NUM_VDEVS)) |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 229 | #define TARGET_10X_NUM_OFFLOAD_PEERS 0 |
| 230 | #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 |
| 231 | #define TARGET_10X_NUM_PEER_KEYS 2 |
Michal Kazior | cfd1061 | 2014-11-25 15:16:05 +0100 | [diff] [blame] | 232 | #define TARGET_10X_NUM_TIDS_MAX 256 |
| 233 | #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ |
| 234 | (TARGET_10X_NUM_PEERS) * 2) |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 235 | #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 236 | #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
| 237 | #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 |
| 238 | #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 |
Michal Kazior | 0d1a28f | 2013-10-07 20:00:36 -0700 | [diff] [blame] | 239 | #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
Bartosz Markowski | ec6a73f | 2013-09-26 17:47:14 +0200 | [diff] [blame] | 240 | #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 |
| 241 | #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 |
| 242 | #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 |
| 243 | #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 |
| 244 | #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 |
| 245 | #define TARGET_10X_NUM_MCAST_GROUPS 0 |
| 246 | #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 |
| 247 | #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED |
| 248 | #define TARGET_10X_TX_DBG_LOG_SIZE 1024 |
| 249 | #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 |
| 250 | #define TARGET_10X_VOW_CONFIG 0 |
| 251 | #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) |
| 252 | #define TARGET_10X_MAX_FRAG_ENTRIES 0 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 253 | |
Sujith Manoharan | f6603ff | 2015-01-12 12:30:02 +0200 | [diff] [blame] | 254 | /* 10.2 parameters */ |
| 255 | #define TARGET_10_2_DMA_BURST_SIZE 1 |
| 256 | |
Michal Kazior | ca996ec | 2014-12-03 10:11:32 +0200 | [diff] [blame] | 257 | /* Target specific defines for WMI-TLV firmware */ |
| 258 | #define TARGET_TLV_NUM_VDEVS 3 |
| 259 | #define TARGET_TLV_NUM_STATIONS 32 |
| 260 | #define TARGET_TLV_NUM_PEERS ((TARGET_TLV_NUM_STATIONS) + \ |
| 261 | (TARGET_TLV_NUM_VDEVS) + \ |
| 262 | 2) |
| 263 | #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) |
| 264 | #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) |
| 265 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 266 | /* Number of Copy Engines supported */ |
| 267 | #define CE_COUNT 8 |
| 268 | |
| 269 | /* |
| 270 | * Total number of PCIe MSI interrupts requested for all interrupt sources. |
| 271 | * PCIe standard forces this to be a power of 2. |
| 272 | * Some Host OS's limit MSI requests that can be granted to 8 |
| 273 | * so for now we abide by this limit and avoid requesting more |
| 274 | * than that. |
| 275 | */ |
| 276 | #define MSI_NUM_REQUEST_LOG2 3 |
| 277 | #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) |
| 278 | |
| 279 | /* |
| 280 | * Granted MSIs are assigned as follows: |
| 281 | * Firmware uses the first |
| 282 | * Remaining MSIs, if any, are used by Copy Engines |
| 283 | * This mapping is known to both Target firmware and Host software. |
| 284 | * It may be changed as long as Host and Target are kept in sync. |
| 285 | */ |
| 286 | /* MSI for firmware (errors, etc.) */ |
| 287 | #define MSI_ASSIGN_FW 0 |
| 288 | |
| 289 | /* MSIs for Copy Engines */ |
| 290 | #define MSI_ASSIGN_CE_INITIAL 1 |
| 291 | #define MSI_ASSIGN_CE_MAX 7 |
| 292 | |
| 293 | /* as of IP3.7.1 */ |
| 294 | #define RTC_STATE_V_ON 3 |
| 295 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 296 | #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 297 | #define RTC_STATE_V_LSB 0 |
| 298 | #define RTC_STATE_V_MASK 0x00000007 |
| 299 | #define RTC_STATE_ADDRESS 0x0000 |
| 300 | #define PCIE_SOC_WAKE_V_MASK 0x00000001 |
| 301 | #define PCIE_SOC_WAKE_ADDRESS 0x0004 |
| 302 | #define PCIE_SOC_WAKE_RESET 0x00000000 |
| 303 | #define SOC_GLOBAL_RESET_ADDRESS 0x0008 |
| 304 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 305 | #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address |
| 306 | #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 307 | #define MAC_COEX_BASE_ADDRESS 0x00006000 |
| 308 | #define BT_COEX_BASE_ADDRESS 0x00007000 |
| 309 | #define SOC_PCIE_BASE_ADDRESS 0x00008000 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 310 | #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 311 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 |
| 312 | #define WLAN_SI_BASE_ADDRESS 0x00010000 |
| 313 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 |
| 314 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 |
| 315 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 |
| 316 | #define EFUSE_BASE_ADDRESS 0x00030000 |
| 317 | #define FPGA_REG_BASE_ADDRESS 0x00039000 |
| 318 | #define WLAN_UART2_BASE_ADDRESS 0x00054c00 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 319 | #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address |
| 320 | #define CE0_BASE_ADDRESS ar->regs->ce0_base_address |
| 321 | #define CE1_BASE_ADDRESS ar->regs->ce1_base_address |
| 322 | #define CE2_BASE_ADDRESS ar->regs->ce2_base_address |
| 323 | #define CE3_BASE_ADDRESS ar->regs->ce3_base_address |
| 324 | #define CE4_BASE_ADDRESS ar->regs->ce4_base_address |
| 325 | #define CE5_BASE_ADDRESS ar->regs->ce5_base_address |
| 326 | #define CE6_BASE_ADDRESS ar->regs->ce6_base_address |
| 327 | #define CE7_BASE_ADDRESS ar->regs->ce7_base_address |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 328 | #define DBI_BASE_ADDRESS 0x00060000 |
| 329 | #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 |
| 330 | #define PCIE_LOCAL_BASE_ADDRESS 0x00080000 |
| 331 | |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 332 | #define SOC_RESET_CONTROL_ADDRESS 0x00000000 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 333 | #define SOC_RESET_CONTROL_OFFSET 0x00000000 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 334 | #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask |
| 335 | #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 336 | #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 337 | #define SOC_CPU_CLOCK_OFFSET 0x00000020 |
| 338 | #define SOC_CPU_CLOCK_STANDARD_LSB 0 |
| 339 | #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 340 | #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 |
| 341 | #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| 342 | #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 |
| 343 | #define SOC_LPO_CAL_OFFSET 0x000000e0 |
| 344 | #define SOC_LPO_CAL_ENABLE_LSB 20 |
| 345 | #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 346 | #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
| 347 | #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 348 | |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 349 | #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address |
Kalle Valo | e01ae68 | 2013-09-01 11:22:14 +0300 | [diff] [blame] | 350 | #define SOC_CHIP_ID_REV_LSB 8 |
| 351 | #define SOC_CHIP_ID_REV_MASK 0x00000f00 |
| 352 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 353 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
| 354 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 |
| 355 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 |
| 356 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| 357 | |
| 358 | #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 |
| 359 | #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 |
| 360 | #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c |
| 361 | #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 |
| 362 | #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 |
| 363 | #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 |
| 364 | #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 |
| 365 | #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c |
| 366 | |
| 367 | #define CLOCK_GPIO_OFFSET 0xffffffff |
| 368 | #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 |
| 369 | #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 |
| 370 | |
| 371 | #define SI_CONFIG_OFFSET 0x00000000 |
| 372 | #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 |
| 373 | #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 |
| 374 | #define SI_CONFIG_I2C_LSB 16 |
| 375 | #define SI_CONFIG_I2C_MASK 0x00010000 |
| 376 | #define SI_CONFIG_POS_SAMPLE_LSB 7 |
| 377 | #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 |
| 378 | #define SI_CONFIG_INACTIVE_DATA_LSB 5 |
| 379 | #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 |
| 380 | #define SI_CONFIG_INACTIVE_CLK_LSB 4 |
| 381 | #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 |
| 382 | #define SI_CONFIG_DIVIDER_LSB 0 |
| 383 | #define SI_CONFIG_DIVIDER_MASK 0x0000000f |
| 384 | #define SI_CS_OFFSET 0x00000004 |
| 385 | #define SI_CS_DONE_ERR_MASK 0x00000400 |
| 386 | #define SI_CS_DONE_INT_MASK 0x00000200 |
| 387 | #define SI_CS_START_LSB 8 |
| 388 | #define SI_CS_START_MASK 0x00000100 |
| 389 | #define SI_CS_RX_CNT_LSB 4 |
| 390 | #define SI_CS_RX_CNT_MASK 0x000000f0 |
| 391 | #define SI_CS_TX_CNT_LSB 0 |
| 392 | #define SI_CS_TX_CNT_MASK 0x0000000f |
| 393 | |
| 394 | #define SI_TX_DATA0_OFFSET 0x00000008 |
| 395 | #define SI_TX_DATA1_OFFSET 0x0000000c |
| 396 | #define SI_RX_DATA0_OFFSET 0x00000010 |
| 397 | #define SI_RX_DATA1_OFFSET 0x00000014 |
| 398 | |
| 399 | #define CORE_CTRL_CPU_INTR_MASK 0x00002000 |
Michal Kazior | 7c0f0e3 | 2014-10-20 14:14:38 +0200 | [diff] [blame] | 400 | #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 401 | #define CORE_CTRL_ADDRESS 0x0000 |
| 402 | #define PCIE_INTR_ENABLE_ADDRESS 0x0008 |
Michal Kazior | e539887 | 2013-11-25 14:06:20 +0100 | [diff] [blame] | 403 | #define PCIE_INTR_CAUSE_ADDRESS 0x000c |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 404 | #define PCIE_INTR_CLR_ADDRESS 0x0014 |
Michal Kazior | d63955b | 2015-01-24 12:14:49 +0200 | [diff] [blame^] | 405 | #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address |
Michal Kazior | fc36e3f | 2014-02-10 17:14:22 +0100 | [diff] [blame] | 406 | #define CPU_INTR_ADDRESS 0x0010 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 407 | |
| 408 | /* Firmware indications to the Host via SCRATCH_3 register. */ |
| 409 | #define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS) |
| 410 | #define FW_IND_EVENT_PENDING 1 |
| 411 | #define FW_IND_INITIALIZED 2 |
| 412 | |
| 413 | /* HOST_REG interrupt from firmware */ |
| 414 | #define PCIE_INTR_FIRMWARE_MASK 0x00000400 |
| 415 | #define PCIE_INTR_CE_MASK_ALL 0x0007f800 |
| 416 | |
| 417 | #define DRAM_BASE_ADDRESS 0x00400000 |
| 418 | |
| 419 | #define MISSING 0 |
| 420 | |
| 421 | #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 422 | #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET |
| 423 | #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET |
| 424 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET |
| 425 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| 426 | #define RESET_CONTROL_MBOX_RST_MASK MISSING |
| 427 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK |
| 428 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS |
| 429 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS |
| 430 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS |
| 431 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK |
| 432 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK |
| 433 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS |
| 434 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS |
| 435 | #define LOCAL_SCRATCH_OFFSET 0x18 |
| 436 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET |
| 437 | #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET |
| 438 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS |
| 439 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS |
| 440 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS |
| 441 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS |
| 442 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB |
| 443 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK |
| 444 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB |
| 445 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK |
| 446 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS |
| 447 | #define MBOX_BASE_ADDRESS MISSING |
| 448 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING |
| 449 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING |
| 450 | #define INT_STATUS_ENABLE_CPU_LSB MISSING |
| 451 | #define INT_STATUS_ENABLE_CPU_MASK MISSING |
| 452 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| 453 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| 454 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| 455 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| 456 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| 457 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| 458 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| 459 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| 460 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 461 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 462 | #define INT_STATUS_ENABLE_ADDRESS MISSING |
| 463 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 464 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 465 | #define HOST_INT_STATUS_ADDRESS MISSING |
| 466 | #define CPU_INT_STATUS_ADDRESS MISSING |
| 467 | #define ERROR_INT_STATUS_ADDRESS MISSING |
| 468 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| 469 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| 470 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| 471 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| 472 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| 473 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| 474 | #define COUNT_DEC_ADDRESS MISSING |
| 475 | #define HOST_INT_STATUS_CPU_MASK MISSING |
| 476 | #define HOST_INT_STATUS_CPU_LSB MISSING |
| 477 | #define HOST_INT_STATUS_ERROR_MASK MISSING |
| 478 | #define HOST_INT_STATUS_ERROR_LSB MISSING |
| 479 | #define HOST_INT_STATUS_COUNTER_MASK MISSING |
| 480 | #define HOST_INT_STATUS_COUNTER_LSB MISSING |
| 481 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| 482 | #define WINDOW_DATA_ADDRESS MISSING |
| 483 | #define WINDOW_READ_ADDR_ADDRESS MISSING |
| 484 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING |
| 485 | |
| 486 | #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) |
| 487 | |
| 488 | #endif /* _HW_H_ */ |