Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2 | * Performance events x86 architecture code |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 3 | * |
Ingo Molnar | 9814451 | 2009-04-29 14:52:50 +0200 | [diff] [blame] | 4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
| 5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar |
| 6 | * Copyright (C) 2009 Jaswinder Singh Rajput |
| 7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter |
| 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 11 | * |
| 12 | * For licencing details see kernel-base/COPYING |
| 13 | */ |
| 14 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 15 | #include <linux/perf_event.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 16 | #include <linux/capability.h> |
| 17 | #include <linux/notifier.h> |
| 18 | #include <linux/hardirq.h> |
| 19 | #include <linux/kprobes.h> |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 21 | #include <linux/kdebug.h> |
| 22 | #include <linux/sched.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 23 | #include <linux/uaccess.h> |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 24 | #include <linux/highmem.h> |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 25 | #include <linux/cpu.h> |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 26 | #include <linux/bitops.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 27 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 28 | #include <asm/apic.h> |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 29 | #include <asm/stacktrace.h> |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 30 | #include <asm/nmi.h> |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 31 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 32 | static u64 perf_event_mask __read_mostly; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 33 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 34 | /* The maximal number of PEBS events: */ |
| 35 | #define MAX_PEBS_EVENTS 4 |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 36 | |
| 37 | /* The size of a BTS record in bytes: */ |
| 38 | #define BTS_RECORD_SIZE 24 |
| 39 | |
| 40 | /* The size of a per-cpu BTS buffer in bytes: */ |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 41 | #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 42 | |
| 43 | /* The BTS overflow threshold in bytes from the end of the buffer: */ |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 44 | #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 45 | |
| 46 | |
| 47 | /* |
| 48 | * Bits in the debugctlmsr controlling branch tracing. |
| 49 | */ |
| 50 | #define X86_DEBUGCTL_TR (1 << 6) |
| 51 | #define X86_DEBUGCTL_BTS (1 << 7) |
| 52 | #define X86_DEBUGCTL_BTINT (1 << 8) |
| 53 | #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9) |
| 54 | #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10) |
| 55 | |
| 56 | /* |
| 57 | * A debug store configuration. |
| 58 | * |
| 59 | * We only support architectures that use 64bit fields. |
| 60 | */ |
| 61 | struct debug_store { |
| 62 | u64 bts_buffer_base; |
| 63 | u64 bts_index; |
| 64 | u64 bts_absolute_maximum; |
| 65 | u64 bts_interrupt_threshold; |
| 66 | u64 pebs_buffer_base; |
| 67 | u64 pebs_index; |
| 68 | u64 pebs_absolute_maximum; |
| 69 | u64 pebs_interrupt_threshold; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 70 | u64 pebs_event_reset[MAX_PEBS_EVENTS]; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 71 | }; |
| 72 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 73 | struct event_constraint { |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 74 | union { |
| 75 | unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
| 76 | u64 idxmsk64[1]; |
| 77 | }; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 78 | int code; |
| 79 | int cmask; |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 80 | int weight; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 81 | }; |
| 82 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 83 | struct cpu_hw_events { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 84 | struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 85 | unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 86 | unsigned long interrupts; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 87 | int enabled; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 88 | struct debug_store *ds; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 89 | |
| 90 | int n_events; |
| 91 | int n_added; |
| 92 | int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */ |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 93 | u64 tags[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 94 | struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */ |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 95 | }; |
| 96 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 97 | #define __EVENT_CONSTRAINT(c, n, m, w) {\ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 98 | { .idxmsk64[0] = (n) }, \ |
| 99 | .code = (c), \ |
| 100 | .cmask = (m), \ |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 101 | .weight = (w), \ |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 102 | } |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 103 | |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 104 | #define EVENT_CONSTRAINT(c, n, m) \ |
| 105 | __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n)) |
| 106 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 107 | #define INTEL_EVENT_CONSTRAINT(c, n) \ |
| 108 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 109 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 110 | #define FIXED_EVENT_CONSTRAINT(c, n) \ |
| 111 | EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK) |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 112 | |
Peter Zijlstra | ed8777f | 2010-01-27 23:07:46 +0100 | [diff] [blame] | 113 | #define EVENT_CONSTRAINT_END \ |
| 114 | EVENT_CONSTRAINT(0, 0, 0) |
| 115 | |
| 116 | #define for_each_event_constraint(e, c) \ |
| 117 | for ((e) = (c); (e)->cmask; (e)++) |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 118 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 119 | /* |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 120 | * struct x86_pmu - generic x86 pmu |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 121 | */ |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 122 | struct x86_pmu { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 123 | const char *name; |
| 124 | int version; |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 125 | int (*handle_irq)(struct pt_regs *); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 126 | void (*disable_all)(void); |
| 127 | void (*enable_all)(void); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 128 | void (*enable)(struct hw_perf_event *, int); |
| 129 | void (*disable)(struct hw_perf_event *, int); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 130 | unsigned eventsel; |
| 131 | unsigned perfctr; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 132 | u64 (*event_map)(int); |
| 133 | u64 (*raw_event)(u64); |
Jaswinder Singh Rajput | 169e41e | 2009-02-28 18:37:49 +0530 | [diff] [blame] | 134 | int max_events; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 135 | int num_events; |
| 136 | int num_events_fixed; |
| 137 | int event_bits; |
| 138 | u64 event_mask; |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 139 | int apic; |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 140 | u64 max_period; |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 141 | u64 intel_ctrl; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 142 | void (*enable_bts)(u64 config); |
| 143 | void (*disable_bts)(void); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 144 | |
| 145 | struct event_constraint * |
| 146 | (*get_event_constraints)(struct cpu_hw_events *cpuc, |
| 147 | struct perf_event *event); |
| 148 | |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 149 | void (*put_event_constraints)(struct cpu_hw_events *cpuc, |
| 150 | struct perf_event *event); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 151 | struct event_constraint *event_constraints; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 152 | }; |
| 153 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 154 | static struct x86_pmu x86_pmu __read_mostly; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 155 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 156 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 157 | .enabled = 1, |
| 158 | }; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 159 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 160 | static int x86_perf_event_set_period(struct perf_event *event, |
| 161 | struct hw_perf_event *hwc, int idx); |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 162 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 163 | /* |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 164 | * Not sure about some of these |
| 165 | */ |
| 166 | static const u64 p6_perfmon_event_map[] = |
| 167 | { |
| 168 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, |
| 169 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
Ingo Molnar | f64cccc | 2009-08-11 10:26:33 +0200 | [diff] [blame] | 170 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, |
| 171 | [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 172 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 173 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
| 174 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, |
| 175 | }; |
| 176 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 177 | static u64 p6_pmu_event_map(int hw_event) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 178 | { |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 179 | return p6_perfmon_event_map[hw_event]; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 180 | } |
| 181 | |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 182 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 183 | * Event setting that is specified not to count anything. |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 184 | * We use this to effectively disable a counter. |
| 185 | * |
| 186 | * L2_RQSTS with 0 MESI unit mask. |
| 187 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 188 | #define P6_NOP_EVENT 0x0000002EULL |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 189 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 190 | static u64 p6_pmu_raw_event(u64 hw_event) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 191 | { |
| 192 | #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL |
| 193 | #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL |
| 194 | #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL |
| 195 | #define P6_EVNTSEL_INV_MASK 0x00800000ULL |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 196 | #define P6_EVNTSEL_REG_MASK 0xFF000000ULL |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 197 | |
| 198 | #define P6_EVNTSEL_MASK \ |
| 199 | (P6_EVNTSEL_EVENT_MASK | \ |
| 200 | P6_EVNTSEL_UNIT_MASK | \ |
| 201 | P6_EVNTSEL_EDGE_MASK | \ |
| 202 | P6_EVNTSEL_INV_MASK | \ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 203 | P6_EVNTSEL_REG_MASK) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 204 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 205 | return hw_event & P6_EVNTSEL_MASK; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 206 | } |
| 207 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 208 | static struct event_constraint intel_p6_event_constraints[] = |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 209 | { |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 210 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */ |
| 211 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
| 212 | INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */ |
| 213 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ |
| 214 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ |
| 215 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 216 | EVENT_CONSTRAINT_END |
| 217 | }; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 218 | |
| 219 | /* |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 220 | * Intel PerfMon v3. Used on Core2 and later. |
| 221 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 222 | static const u64 intel_perfmon_event_map[] = |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 223 | { |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 224 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
| 225 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 226 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, |
| 227 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, |
| 228 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 229 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
| 230 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 231 | }; |
| 232 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 233 | static struct event_constraint intel_core_event_constraints[] = |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 234 | { |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 235 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ |
| 236 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ |
| 237 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ |
| 238 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ |
| 239 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ |
| 240 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ |
| 241 | EVENT_CONSTRAINT_END |
| 242 | }; |
| 243 | |
| 244 | static struct event_constraint intel_core2_event_constraints[] = |
| 245 | { |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 246 | FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */ |
| 247 | FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */ |
| 248 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
| 249 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ |
| 250 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ |
| 251 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ |
| 252 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ |
| 253 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ |
| 254 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ |
| 255 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ |
| 256 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 257 | EVENT_CONSTRAINT_END |
| 258 | }; |
| 259 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 260 | static struct event_constraint intel_nehalem_event_constraints[] = |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 261 | { |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 262 | FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */ |
| 263 | FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */ |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 264 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
| 265 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ |
| 266 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ |
| 267 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 268 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 269 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 270 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 271 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ |
| 272 | EVENT_CONSTRAINT_END |
| 273 | }; |
| 274 | |
| 275 | static struct event_constraint intel_westmere_event_constraints[] = |
| 276 | { |
| 277 | FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */ |
| 278 | FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */ |
| 279 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
| 280 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ |
| 281 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 282 | EVENT_CONSTRAINT_END |
| 283 | }; |
| 284 | |
| 285 | static struct event_constraint intel_gen_event_constraints[] = |
| 286 | { |
Peter Zijlstra | 8433be1 | 2010-01-22 15:38:26 +0100 | [diff] [blame] | 287 | FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */ |
| 288 | FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */ |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 289 | EVENT_CONSTRAINT_END |
| 290 | }; |
| 291 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 292 | static u64 intel_pmu_event_map(int hw_event) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 293 | { |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 294 | return intel_perfmon_event_map[hw_event]; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 295 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 296 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 297 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 298 | * Generalized hw caching related hw_event table, filled |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 299 | * in on a per model basis. A value of 0 means |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 300 | * 'not supported', -1 means 'hw_event makes no sense on |
| 301 | * this CPU', any other value means the raw hw_event |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 302 | * ID. |
| 303 | */ |
| 304 | |
| 305 | #define C(x) PERF_COUNT_HW_CACHE_##x |
| 306 | |
| 307 | static u64 __read_mostly hw_cache_event_ids |
| 308 | [PERF_COUNT_HW_CACHE_MAX] |
| 309 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 310 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
| 311 | |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 312 | static __initconst u64 westmere_hw_cache_event_ids |
| 313 | [PERF_COUNT_HW_CACHE_MAX] |
| 314 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 315 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 316 | { |
| 317 | [ C(L1D) ] = { |
| 318 | [ C(OP_READ) ] = { |
| 319 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
| 320 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ |
| 321 | }, |
| 322 | [ C(OP_WRITE) ] = { |
| 323 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
| 324 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ |
| 325 | }, |
| 326 | [ C(OP_PREFETCH) ] = { |
| 327 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ |
| 328 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ |
| 329 | }, |
| 330 | }, |
| 331 | [ C(L1I ) ] = { |
| 332 | [ C(OP_READ) ] = { |
| 333 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
| 334 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
| 335 | }, |
| 336 | [ C(OP_WRITE) ] = { |
| 337 | [ C(RESULT_ACCESS) ] = -1, |
| 338 | [ C(RESULT_MISS) ] = -1, |
| 339 | }, |
| 340 | [ C(OP_PREFETCH) ] = { |
| 341 | [ C(RESULT_ACCESS) ] = 0x0, |
| 342 | [ C(RESULT_MISS) ] = 0x0, |
| 343 | }, |
| 344 | }, |
| 345 | [ C(LL ) ] = { |
| 346 | [ C(OP_READ) ] = { |
| 347 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ |
| 348 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ |
| 349 | }, |
| 350 | [ C(OP_WRITE) ] = { |
| 351 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ |
| 352 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ |
| 353 | }, |
| 354 | [ C(OP_PREFETCH) ] = { |
| 355 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
| 356 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ |
| 357 | }, |
| 358 | }, |
| 359 | [ C(DTLB) ] = { |
| 360 | [ C(OP_READ) ] = { |
| 361 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
| 362 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ |
| 363 | }, |
| 364 | [ C(OP_WRITE) ] = { |
| 365 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
| 366 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ |
| 367 | }, |
| 368 | [ C(OP_PREFETCH) ] = { |
| 369 | [ C(RESULT_ACCESS) ] = 0x0, |
| 370 | [ C(RESULT_MISS) ] = 0x0, |
| 371 | }, |
| 372 | }, |
| 373 | [ C(ITLB) ] = { |
| 374 | [ C(OP_READ) ] = { |
| 375 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ |
| 376 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ |
| 377 | }, |
| 378 | [ C(OP_WRITE) ] = { |
| 379 | [ C(RESULT_ACCESS) ] = -1, |
| 380 | [ C(RESULT_MISS) ] = -1, |
| 381 | }, |
| 382 | [ C(OP_PREFETCH) ] = { |
| 383 | [ C(RESULT_ACCESS) ] = -1, |
| 384 | [ C(RESULT_MISS) ] = -1, |
| 385 | }, |
| 386 | }, |
| 387 | [ C(BPU ) ] = { |
| 388 | [ C(OP_READ) ] = { |
| 389 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ |
| 390 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ |
| 391 | }, |
| 392 | [ C(OP_WRITE) ] = { |
| 393 | [ C(RESULT_ACCESS) ] = -1, |
| 394 | [ C(RESULT_MISS) ] = -1, |
| 395 | }, |
| 396 | [ C(OP_PREFETCH) ] = { |
| 397 | [ C(RESULT_ACCESS) ] = -1, |
| 398 | [ C(RESULT_MISS) ] = -1, |
| 399 | }, |
| 400 | }, |
| 401 | }; |
| 402 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 403 | static __initconst u64 nehalem_hw_cache_event_ids |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 404 | [PERF_COUNT_HW_CACHE_MAX] |
| 405 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 406 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 407 | { |
| 408 | [ C(L1D) ] = { |
| 409 | [ C(OP_READ) ] = { |
| 410 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ |
| 411 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ |
| 412 | }, |
| 413 | [ C(OP_WRITE) ] = { |
| 414 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ |
| 415 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ |
| 416 | }, |
| 417 | [ C(OP_PREFETCH) ] = { |
| 418 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ |
| 419 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ |
| 420 | }, |
| 421 | }, |
| 422 | [ C(L1I ) ] = { |
| 423 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 424 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 425 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
| 426 | }, |
| 427 | [ C(OP_WRITE) ] = { |
| 428 | [ C(RESULT_ACCESS) ] = -1, |
| 429 | [ C(RESULT_MISS) ] = -1, |
| 430 | }, |
| 431 | [ C(OP_PREFETCH) ] = { |
| 432 | [ C(RESULT_ACCESS) ] = 0x0, |
| 433 | [ C(RESULT_MISS) ] = 0x0, |
| 434 | }, |
| 435 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 436 | [ C(LL ) ] = { |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 437 | [ C(OP_READ) ] = { |
| 438 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ |
| 439 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ |
| 440 | }, |
| 441 | [ C(OP_WRITE) ] = { |
| 442 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ |
| 443 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ |
| 444 | }, |
| 445 | [ C(OP_PREFETCH) ] = { |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 446 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ |
| 447 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 448 | }, |
| 449 | }, |
| 450 | [ C(DTLB) ] = { |
| 451 | [ C(OP_READ) ] = { |
| 452 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ |
| 453 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ |
| 454 | }, |
| 455 | [ C(OP_WRITE) ] = { |
| 456 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ |
| 457 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ |
| 458 | }, |
| 459 | [ C(OP_PREFETCH) ] = { |
| 460 | [ C(RESULT_ACCESS) ] = 0x0, |
| 461 | [ C(RESULT_MISS) ] = 0x0, |
| 462 | }, |
| 463 | }, |
| 464 | [ C(ITLB) ] = { |
| 465 | [ C(OP_READ) ] = { |
| 466 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 467 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 468 | }, |
| 469 | [ C(OP_WRITE) ] = { |
| 470 | [ C(RESULT_ACCESS) ] = -1, |
| 471 | [ C(RESULT_MISS) ] = -1, |
| 472 | }, |
| 473 | [ C(OP_PREFETCH) ] = { |
| 474 | [ C(RESULT_ACCESS) ] = -1, |
| 475 | [ C(RESULT_MISS) ] = -1, |
| 476 | }, |
| 477 | }, |
| 478 | [ C(BPU ) ] = { |
| 479 | [ C(OP_READ) ] = { |
| 480 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ |
| 481 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ |
| 482 | }, |
| 483 | [ C(OP_WRITE) ] = { |
| 484 | [ C(RESULT_ACCESS) ] = -1, |
| 485 | [ C(RESULT_MISS) ] = -1, |
| 486 | }, |
| 487 | [ C(OP_PREFETCH) ] = { |
| 488 | [ C(RESULT_ACCESS) ] = -1, |
| 489 | [ C(RESULT_MISS) ] = -1, |
| 490 | }, |
| 491 | }, |
| 492 | }; |
| 493 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 494 | static __initconst u64 core2_hw_cache_event_ids |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 495 | [PERF_COUNT_HW_CACHE_MAX] |
| 496 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 497 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 498 | { |
Thomas Gleixner | 0312af8 | 2009-06-08 07:42:04 +0200 | [diff] [blame] | 499 | [ C(L1D) ] = { |
| 500 | [ C(OP_READ) ] = { |
| 501 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ |
| 502 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ |
| 503 | }, |
| 504 | [ C(OP_WRITE) ] = { |
| 505 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ |
| 506 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ |
| 507 | }, |
| 508 | [ C(OP_PREFETCH) ] = { |
| 509 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ |
| 510 | [ C(RESULT_MISS) ] = 0, |
| 511 | }, |
| 512 | }, |
| 513 | [ C(L1I ) ] = { |
| 514 | [ C(OP_READ) ] = { |
| 515 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ |
| 516 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ |
| 517 | }, |
| 518 | [ C(OP_WRITE) ] = { |
| 519 | [ C(RESULT_ACCESS) ] = -1, |
| 520 | [ C(RESULT_MISS) ] = -1, |
| 521 | }, |
| 522 | [ C(OP_PREFETCH) ] = { |
| 523 | [ C(RESULT_ACCESS) ] = 0, |
| 524 | [ C(RESULT_MISS) ] = 0, |
| 525 | }, |
| 526 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 527 | [ C(LL ) ] = { |
Thomas Gleixner | 0312af8 | 2009-06-08 07:42:04 +0200 | [diff] [blame] | 528 | [ C(OP_READ) ] = { |
| 529 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ |
| 530 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ |
| 531 | }, |
| 532 | [ C(OP_WRITE) ] = { |
| 533 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ |
| 534 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ |
| 535 | }, |
| 536 | [ C(OP_PREFETCH) ] = { |
| 537 | [ C(RESULT_ACCESS) ] = 0, |
| 538 | [ C(RESULT_MISS) ] = 0, |
| 539 | }, |
| 540 | }, |
| 541 | [ C(DTLB) ] = { |
| 542 | [ C(OP_READ) ] = { |
| 543 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ |
| 544 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ |
| 545 | }, |
| 546 | [ C(OP_WRITE) ] = { |
| 547 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ |
| 548 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ |
| 549 | }, |
| 550 | [ C(OP_PREFETCH) ] = { |
| 551 | [ C(RESULT_ACCESS) ] = 0, |
| 552 | [ C(RESULT_MISS) ] = 0, |
| 553 | }, |
| 554 | }, |
| 555 | [ C(ITLB) ] = { |
| 556 | [ C(OP_READ) ] = { |
| 557 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ |
| 558 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ |
| 559 | }, |
| 560 | [ C(OP_WRITE) ] = { |
| 561 | [ C(RESULT_ACCESS) ] = -1, |
| 562 | [ C(RESULT_MISS) ] = -1, |
| 563 | }, |
| 564 | [ C(OP_PREFETCH) ] = { |
| 565 | [ C(RESULT_ACCESS) ] = -1, |
| 566 | [ C(RESULT_MISS) ] = -1, |
| 567 | }, |
| 568 | }, |
| 569 | [ C(BPU ) ] = { |
| 570 | [ C(OP_READ) ] = { |
| 571 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ |
| 572 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ |
| 573 | }, |
| 574 | [ C(OP_WRITE) ] = { |
| 575 | [ C(RESULT_ACCESS) ] = -1, |
| 576 | [ C(RESULT_MISS) ] = -1, |
| 577 | }, |
| 578 | [ C(OP_PREFETCH) ] = { |
| 579 | [ C(RESULT_ACCESS) ] = -1, |
| 580 | [ C(RESULT_MISS) ] = -1, |
| 581 | }, |
| 582 | }, |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 583 | }; |
| 584 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 585 | static __initconst u64 atom_hw_cache_event_ids |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 586 | [PERF_COUNT_HW_CACHE_MAX] |
| 587 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 588 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 589 | { |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 590 | [ C(L1D) ] = { |
| 591 | [ C(OP_READ) ] = { |
| 592 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ |
| 593 | [ C(RESULT_MISS) ] = 0, |
| 594 | }, |
| 595 | [ C(OP_WRITE) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 596 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 597 | [ C(RESULT_MISS) ] = 0, |
| 598 | }, |
| 599 | [ C(OP_PREFETCH) ] = { |
| 600 | [ C(RESULT_ACCESS) ] = 0x0, |
| 601 | [ C(RESULT_MISS) ] = 0, |
| 602 | }, |
| 603 | }, |
| 604 | [ C(L1I ) ] = { |
| 605 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 606 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ |
| 607 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 608 | }, |
| 609 | [ C(OP_WRITE) ] = { |
| 610 | [ C(RESULT_ACCESS) ] = -1, |
| 611 | [ C(RESULT_MISS) ] = -1, |
| 612 | }, |
| 613 | [ C(OP_PREFETCH) ] = { |
| 614 | [ C(RESULT_ACCESS) ] = 0, |
| 615 | [ C(RESULT_MISS) ] = 0, |
| 616 | }, |
| 617 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 618 | [ C(LL ) ] = { |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 619 | [ C(OP_READ) ] = { |
| 620 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ |
| 621 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ |
| 622 | }, |
| 623 | [ C(OP_WRITE) ] = { |
| 624 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ |
| 625 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ |
| 626 | }, |
| 627 | [ C(OP_PREFETCH) ] = { |
| 628 | [ C(RESULT_ACCESS) ] = 0, |
| 629 | [ C(RESULT_MISS) ] = 0, |
| 630 | }, |
| 631 | }, |
| 632 | [ C(DTLB) ] = { |
| 633 | [ C(OP_READ) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 634 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 635 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ |
| 636 | }, |
| 637 | [ C(OP_WRITE) ] = { |
Yong Wang | fecc8ac | 2009-06-09 21:15:53 +0800 | [diff] [blame] | 638 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ |
Thomas Gleixner | ad68922 | 2009-06-08 09:30:41 +0200 | [diff] [blame] | 639 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ |
| 640 | }, |
| 641 | [ C(OP_PREFETCH) ] = { |
| 642 | [ C(RESULT_ACCESS) ] = 0, |
| 643 | [ C(RESULT_MISS) ] = 0, |
| 644 | }, |
| 645 | }, |
| 646 | [ C(ITLB) ] = { |
| 647 | [ C(OP_READ) ] = { |
| 648 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ |
| 649 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ |
| 650 | }, |
| 651 | [ C(OP_WRITE) ] = { |
| 652 | [ C(RESULT_ACCESS) ] = -1, |
| 653 | [ C(RESULT_MISS) ] = -1, |
| 654 | }, |
| 655 | [ C(OP_PREFETCH) ] = { |
| 656 | [ C(RESULT_ACCESS) ] = -1, |
| 657 | [ C(RESULT_MISS) ] = -1, |
| 658 | }, |
| 659 | }, |
| 660 | [ C(BPU ) ] = { |
| 661 | [ C(OP_READ) ] = { |
| 662 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ |
| 663 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ |
| 664 | }, |
| 665 | [ C(OP_WRITE) ] = { |
| 666 | [ C(RESULT_ACCESS) ] = -1, |
| 667 | [ C(RESULT_MISS) ] = -1, |
| 668 | }, |
| 669 | [ C(OP_PREFETCH) ] = { |
| 670 | [ C(RESULT_ACCESS) ] = -1, |
| 671 | [ C(RESULT_MISS) ] = -1, |
| 672 | }, |
| 673 | }, |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 674 | }; |
| 675 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 676 | static u64 intel_pmu_raw_event(u64 hw_event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 677 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 678 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL |
| 679 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 680 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL |
| 681 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 682 | #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 683 | |
Ingo Molnar | 128f048 | 2009-06-03 22:19:36 +0200 | [diff] [blame] | 684 | #define CORE_EVNTSEL_MASK \ |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 685 | (INTEL_ARCH_EVTSEL_MASK | \ |
| 686 | INTEL_ARCH_UNIT_MASK | \ |
| 687 | INTEL_ARCH_EDGE_MASK | \ |
| 688 | INTEL_ARCH_INV_MASK | \ |
| 689 | INTEL_ARCH_CNT_MASK) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 690 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 691 | return hw_event & CORE_EVNTSEL_MASK; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 692 | } |
| 693 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 694 | static __initconst u64 amd_hw_cache_event_ids |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 695 | [PERF_COUNT_HW_CACHE_MAX] |
| 696 | [PERF_COUNT_HW_CACHE_OP_MAX] |
| 697 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = |
| 698 | { |
| 699 | [ C(L1D) ] = { |
| 700 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 701 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
| 702 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 703 | }, |
| 704 | [ C(OP_WRITE) ] = { |
Jaswinder Singh Rajput | d9f2a5e | 2009-06-20 13:19:25 +0530 | [diff] [blame] | 705 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 706 | [ C(RESULT_MISS) ] = 0, |
| 707 | }, |
| 708 | [ C(OP_PREFETCH) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 709 | [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ |
| 710 | [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 711 | }, |
| 712 | }, |
| 713 | [ C(L1I ) ] = { |
| 714 | [ C(OP_READ) ] = { |
| 715 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ |
| 716 | [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ |
| 717 | }, |
| 718 | [ C(OP_WRITE) ] = { |
| 719 | [ C(RESULT_ACCESS) ] = -1, |
| 720 | [ C(RESULT_MISS) ] = -1, |
| 721 | }, |
| 722 | [ C(OP_PREFETCH) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 723 | [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 724 | [ C(RESULT_MISS) ] = 0, |
| 725 | }, |
| 726 | }, |
Peter Zijlstra | 8be6e8f | 2009-06-11 14:19:11 +0200 | [diff] [blame] | 727 | [ C(LL ) ] = { |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 728 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 729 | [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ |
| 730 | [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 731 | }, |
| 732 | [ C(OP_WRITE) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 733 | [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 734 | [ C(RESULT_MISS) ] = 0, |
| 735 | }, |
| 736 | [ C(OP_PREFETCH) ] = { |
| 737 | [ C(RESULT_ACCESS) ] = 0, |
| 738 | [ C(RESULT_MISS) ] = 0, |
| 739 | }, |
| 740 | }, |
| 741 | [ C(DTLB) ] = { |
| 742 | [ C(OP_READ) ] = { |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 743 | [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ |
| 744 | [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */ |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 745 | }, |
| 746 | [ C(OP_WRITE) ] = { |
| 747 | [ C(RESULT_ACCESS) ] = 0, |
| 748 | [ C(RESULT_MISS) ] = 0, |
| 749 | }, |
| 750 | [ C(OP_PREFETCH) ] = { |
| 751 | [ C(RESULT_ACCESS) ] = 0, |
| 752 | [ C(RESULT_MISS) ] = 0, |
| 753 | }, |
| 754 | }, |
| 755 | [ C(ITLB) ] = { |
| 756 | [ C(OP_READ) ] = { |
| 757 | [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ |
| 758 | [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */ |
| 759 | }, |
| 760 | [ C(OP_WRITE) ] = { |
| 761 | [ C(RESULT_ACCESS) ] = -1, |
| 762 | [ C(RESULT_MISS) ] = -1, |
| 763 | }, |
| 764 | [ C(OP_PREFETCH) ] = { |
| 765 | [ C(RESULT_ACCESS) ] = -1, |
| 766 | [ C(RESULT_MISS) ] = -1, |
| 767 | }, |
| 768 | }, |
| 769 | [ C(BPU ) ] = { |
| 770 | [ C(OP_READ) ] = { |
| 771 | [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ |
| 772 | [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ |
| 773 | }, |
| 774 | [ C(OP_WRITE) ] = { |
| 775 | [ C(RESULT_ACCESS) ] = -1, |
| 776 | [ C(RESULT_MISS) ] = -1, |
| 777 | }, |
| 778 | [ C(OP_PREFETCH) ] = { |
| 779 | [ C(RESULT_ACCESS) ] = -1, |
| 780 | [ C(RESULT_MISS) ] = -1, |
| 781 | }, |
| 782 | }, |
| 783 | }; |
| 784 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 785 | /* |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 786 | * AMD Performance Monitor K7 and later. |
| 787 | */ |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 788 | static const u64 amd_perfmon_event_map[] = |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 789 | { |
Peter Zijlstra | f4dbfa8 | 2009-06-11 14:06:28 +0200 | [diff] [blame] | 790 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
| 791 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 792 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080, |
| 793 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0081, |
| 794 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 795 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 796 | }; |
| 797 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 798 | static u64 amd_pmu_event_map(int hw_event) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 799 | { |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 800 | return amd_perfmon_event_map[hw_event]; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 801 | } |
| 802 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 803 | static u64 amd_pmu_raw_event(u64 hw_event) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 804 | { |
Peter Zijlstra | 82bae4f8 | 2009-03-13 12:21:31 +0100 | [diff] [blame] | 805 | #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL |
| 806 | #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 807 | #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL |
| 808 | #define K7_EVNTSEL_INV_MASK 0x000800000ULL |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 809 | #define K7_EVNTSEL_REG_MASK 0x0FF000000ULL |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 810 | |
| 811 | #define K7_EVNTSEL_MASK \ |
| 812 | (K7_EVNTSEL_EVENT_MASK | \ |
| 813 | K7_EVNTSEL_UNIT_MASK | \ |
Peter Zijlstra | ff99be5 | 2009-05-25 17:39:03 +0200 | [diff] [blame] | 814 | K7_EVNTSEL_EDGE_MASK | \ |
| 815 | K7_EVNTSEL_INV_MASK | \ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 816 | K7_EVNTSEL_REG_MASK) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 817 | |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 818 | return hw_event & K7_EVNTSEL_MASK; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 819 | } |
| 820 | |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 821 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 822 | * Propagate event elapsed time into the generic event. |
| 823 | * Can only be executed on the CPU where the event is active. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 824 | * Returns the delta events processed. |
| 825 | */ |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 826 | static u64 |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 827 | x86_perf_event_update(struct perf_event *event, |
| 828 | struct hw_perf_event *hwc, int idx) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 829 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 830 | int shift = 64 - x86_pmu.event_bits; |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 831 | u64 prev_raw_count, new_raw_count; |
| 832 | s64 delta; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 833 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 834 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 835 | return 0; |
| 836 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 837 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 838 | * Careful: an NMI might modify the previous event value. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 839 | * |
| 840 | * Our tactic to handle this is to first atomically read and |
| 841 | * exchange a new raw count - then add that new-prev delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 842 | * count to the generic event atomically: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 843 | */ |
| 844 | again: |
| 845 | prev_raw_count = atomic64_read(&hwc->prev_count); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 846 | rdmsrl(hwc->event_base + idx, new_raw_count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 847 | |
| 848 | if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 849 | new_raw_count) != prev_raw_count) |
| 850 | goto again; |
| 851 | |
| 852 | /* |
| 853 | * Now we have the new raw value and have updated the prev |
| 854 | * timestamp already. We can now calculate the elapsed delta |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 855 | * (event-)time and add that to the generic event. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 856 | * |
| 857 | * Careful, not all hw sign-extends above the physical width |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 858 | * of the count. |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 859 | */ |
Peter Zijlstra | ec3232b | 2009-05-13 09:45:19 +0200 | [diff] [blame] | 860 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
| 861 | delta >>= shift; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 862 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 863 | atomic64_add(delta, &event->count); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 864 | atomic64_sub(delta, &hwc->period_left); |
Robert Richter | 4b7bfd0 | 2009-04-29 12:47:22 +0200 | [diff] [blame] | 865 | |
| 866 | return new_raw_count; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 867 | } |
| 868 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 869 | static atomic_t active_events; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 870 | static DEFINE_MUTEX(pmc_reserve_mutex); |
| 871 | |
| 872 | static bool reserve_pmc_hardware(void) |
| 873 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 874 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 875 | int i; |
| 876 | |
| 877 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 878 | disable_lapic_nmi_watchdog(); |
| 879 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 880 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 881 | if (!reserve_perfctr_nmi(x86_pmu.perfctr + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 882 | goto perfctr_fail; |
| 883 | } |
| 884 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 885 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 886 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 887 | goto eventsel_fail; |
| 888 | } |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 889 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 890 | |
| 891 | return true; |
| 892 | |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 893 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 894 | eventsel_fail: |
| 895 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 896 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 897 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 898 | i = x86_pmu.num_events; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 899 | |
| 900 | perfctr_fail: |
| 901 | for (i--; i >= 0; i--) |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 902 | release_perfctr_nmi(x86_pmu.perfctr + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 903 | |
| 904 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 905 | enable_lapic_nmi_watchdog(); |
| 906 | |
| 907 | return false; |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 908 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 909 | } |
| 910 | |
| 911 | static void release_pmc_hardware(void) |
| 912 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 913 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 914 | int i; |
| 915 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 916 | for (i = 0; i < x86_pmu.num_events; i++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 917 | release_perfctr_nmi(x86_pmu.perfctr + i); |
| 918 | release_evntsel_nmi(x86_pmu.eventsel + i); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 919 | } |
| 920 | |
| 921 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 922 | enable_lapic_nmi_watchdog(); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 923 | #endif |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 924 | } |
| 925 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 926 | static inline bool bts_available(void) |
| 927 | { |
| 928 | return x86_pmu.enable_bts != NULL; |
| 929 | } |
| 930 | |
| 931 | static inline void init_debug_store_on_cpu(int cpu) |
| 932 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 933 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 934 | |
| 935 | if (!ds) |
| 936 | return; |
| 937 | |
| 938 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 939 | (u32)((u64)(unsigned long)ds), |
| 940 | (u32)((u64)(unsigned long)ds >> 32)); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | static inline void fini_debug_store_on_cpu(int cpu) |
| 944 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 945 | if (!per_cpu(cpu_hw_events, cpu).ds) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 946 | return; |
| 947 | |
| 948 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); |
| 949 | } |
| 950 | |
| 951 | static void release_bts_hardware(void) |
| 952 | { |
| 953 | int cpu; |
| 954 | |
| 955 | if (!bts_available()) |
| 956 | return; |
| 957 | |
| 958 | get_online_cpus(); |
| 959 | |
| 960 | for_each_online_cpu(cpu) |
| 961 | fini_debug_store_on_cpu(cpu); |
| 962 | |
| 963 | for_each_possible_cpu(cpu) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 964 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 965 | |
| 966 | if (!ds) |
| 967 | continue; |
| 968 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 969 | per_cpu(cpu_hw_events, cpu).ds = NULL; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 970 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 971 | kfree((void *)(unsigned long)ds->bts_buffer_base); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 972 | kfree(ds); |
| 973 | } |
| 974 | |
| 975 | put_online_cpus(); |
| 976 | } |
| 977 | |
| 978 | static int reserve_bts_hardware(void) |
| 979 | { |
| 980 | int cpu, err = 0; |
| 981 | |
| 982 | if (!bts_available()) |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 983 | return 0; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 984 | |
| 985 | get_online_cpus(); |
| 986 | |
| 987 | for_each_possible_cpu(cpu) { |
| 988 | struct debug_store *ds; |
| 989 | void *buffer; |
| 990 | |
| 991 | err = -ENOMEM; |
| 992 | buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL); |
| 993 | if (unlikely(!buffer)) |
| 994 | break; |
| 995 | |
| 996 | ds = kzalloc(sizeof(*ds), GFP_KERNEL); |
| 997 | if (unlikely(!ds)) { |
| 998 | kfree(buffer); |
| 999 | break; |
| 1000 | } |
| 1001 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 1002 | ds->bts_buffer_base = (u64)(unsigned long)buffer; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1003 | ds->bts_index = ds->bts_buffer_base; |
| 1004 | ds->bts_absolute_maximum = |
| 1005 | ds->bts_buffer_base + BTS_BUFFER_SIZE; |
| 1006 | ds->bts_interrupt_threshold = |
| 1007 | ds->bts_absolute_maximum - BTS_OVFL_TH; |
| 1008 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1009 | per_cpu(cpu_hw_events, cpu).ds = ds; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1010 | err = 0; |
| 1011 | } |
| 1012 | |
| 1013 | if (err) |
| 1014 | release_bts_hardware(); |
| 1015 | else { |
| 1016 | for_each_online_cpu(cpu) |
| 1017 | init_debug_store_on_cpu(cpu); |
| 1018 | } |
| 1019 | |
| 1020 | put_online_cpus(); |
| 1021 | |
| 1022 | return err; |
| 1023 | } |
| 1024 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1025 | static void hw_perf_event_destroy(struct perf_event *event) |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1026 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1027 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1028 | release_pmc_hardware(); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1029 | release_bts_hardware(); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1030 | mutex_unlock(&pmc_reserve_mutex); |
| 1031 | } |
| 1032 | } |
| 1033 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1034 | static inline int x86_pmu_initialized(void) |
| 1035 | { |
| 1036 | return x86_pmu.handle_irq != NULL; |
| 1037 | } |
| 1038 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1039 | static inline int |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1040 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr) |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1041 | { |
| 1042 | unsigned int cache_type, cache_op, cache_result; |
| 1043 | u64 config, val; |
| 1044 | |
| 1045 | config = attr->config; |
| 1046 | |
| 1047 | cache_type = (config >> 0) & 0xff; |
| 1048 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
| 1049 | return -EINVAL; |
| 1050 | |
| 1051 | cache_op = (config >> 8) & 0xff; |
| 1052 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) |
| 1053 | return -EINVAL; |
| 1054 | |
| 1055 | cache_result = (config >> 16) & 0xff; |
| 1056 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) |
| 1057 | return -EINVAL; |
| 1058 | |
| 1059 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; |
| 1060 | |
| 1061 | if (val == 0) |
| 1062 | return -ENOENT; |
| 1063 | |
| 1064 | if (val == -1) |
| 1065 | return -EINVAL; |
| 1066 | |
| 1067 | hwc->config |= val; |
| 1068 | |
| 1069 | return 0; |
| 1070 | } |
| 1071 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1072 | static void intel_pmu_enable_bts(u64 config) |
| 1073 | { |
| 1074 | unsigned long debugctlmsr; |
| 1075 | |
| 1076 | debugctlmsr = get_debugctlmsr(); |
| 1077 | |
| 1078 | debugctlmsr |= X86_DEBUGCTL_TR; |
| 1079 | debugctlmsr |= X86_DEBUGCTL_BTS; |
| 1080 | debugctlmsr |= X86_DEBUGCTL_BTINT; |
| 1081 | |
| 1082 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) |
| 1083 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS; |
| 1084 | |
| 1085 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) |
| 1086 | debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR; |
| 1087 | |
| 1088 | update_debugctlmsr(debugctlmsr); |
| 1089 | } |
| 1090 | |
| 1091 | static void intel_pmu_disable_bts(void) |
| 1092 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1093 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1094 | unsigned long debugctlmsr; |
| 1095 | |
| 1096 | if (!cpuc->ds) |
| 1097 | return; |
| 1098 | |
| 1099 | debugctlmsr = get_debugctlmsr(); |
| 1100 | |
| 1101 | debugctlmsr &= |
| 1102 | ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT | |
| 1103 | X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR); |
| 1104 | |
| 1105 | update_debugctlmsr(debugctlmsr); |
| 1106 | } |
| 1107 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1108 | /* |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 1109 | * Setup the hardware configuration for a given attr_type |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1110 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1111 | static int __hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1112 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1113 | struct perf_event_attr *attr = &event->attr; |
| 1114 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1115 | u64 config; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1116 | int err; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1117 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1118 | if (!x86_pmu_initialized()) |
| 1119 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1120 | |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1121 | err = 0; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1122 | if (!atomic_inc_not_zero(&active_events)) { |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1123 | mutex_lock(&pmc_reserve_mutex); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1124 | if (atomic_read(&active_events) == 0) { |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1125 | if (!reserve_pmc_hardware()) |
| 1126 | err = -EBUSY; |
| 1127 | else |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 1128 | err = reserve_bts_hardware(); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1129 | } |
| 1130 | if (!err) |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1131 | atomic_inc(&active_events); |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1132 | mutex_unlock(&pmc_reserve_mutex); |
| 1133 | } |
| 1134 | if (err) |
| 1135 | return err; |
| 1136 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1137 | event->destroy = hw_perf_event_destroy; |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 1138 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1139 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1140 | * Generate PMC IRQs: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1141 | * (keep 'enabled' bit clear for now) |
| 1142 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1143 | hwc->config = ARCH_PERFMON_EVENTSEL_INT; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1144 | |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 1145 | hwc->idx = -1; |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1146 | hwc->last_cpu = -1; |
| 1147 | hwc->last_tag = ~0ULL; |
Stephane Eranian | b690081 | 2009-10-06 16:42:09 +0200 | [diff] [blame] | 1148 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1149 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1150 | * Count user and OS events unless requested not to. |
| 1151 | */ |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 1152 | if (!attr->exclude_user) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1153 | hwc->config |= ARCH_PERFMON_EVENTSEL_USR; |
Peter Zijlstra | 0d48696 | 2009-06-02 19:22:16 +0200 | [diff] [blame] | 1154 | if (!attr->exclude_kernel) |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1155 | hwc->config |= ARCH_PERFMON_EVENTSEL_OS; |
| 1156 | |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 1157 | if (!hwc->sample_period) { |
Peter Zijlstra | b23f332 | 2009-06-02 15:13:03 +0200 | [diff] [blame] | 1158 | hwc->sample_period = x86_pmu.max_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1159 | hwc->last_period = hwc->sample_period; |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 1160 | atomic64_set(&hwc->period_left, hwc->sample_period); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1161 | } else { |
| 1162 | /* |
| 1163 | * If we have a PMU initialized but no APIC |
| 1164 | * interrupts, we cannot sample hardware |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1165 | * events (user-space has to fall back and |
| 1166 | * sample via a hrtimer based software event): |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 1167 | */ |
| 1168 | if (!x86_pmu.apic) |
| 1169 | return -EOPNOTSUPP; |
Peter Zijlstra | bd2b5b1 | 2009-06-10 13:40:57 +0200 | [diff] [blame] | 1170 | } |
Ingo Molnar | d2517a4 | 2009-05-17 10:04:45 +0200 | [diff] [blame] | 1171 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1172 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 1173 | * Raw hw_event type provide the config in the hw_event structure |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1174 | */ |
Ingo Molnar | a21ca2c | 2009-06-06 09:58:57 +0200 | [diff] [blame] | 1175 | if (attr->type == PERF_TYPE_RAW) { |
| 1176 | hwc->config |= x86_pmu.raw_event(attr->config); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1177 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1178 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1179 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1180 | if (attr->type == PERF_TYPE_HW_CACHE) |
| 1181 | return set_ext_hw_attr(hwc, attr); |
| 1182 | |
| 1183 | if (attr->config >= x86_pmu.max_events) |
| 1184 | return -EINVAL; |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1185 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 1186 | /* |
| 1187 | * The generic map: |
| 1188 | */ |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1189 | config = x86_pmu.event_map(attr->config); |
| 1190 | |
| 1191 | if (config == 0) |
| 1192 | return -ENOENT; |
| 1193 | |
| 1194 | if (config == -1LL) |
| 1195 | return -EINVAL; |
| 1196 | |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 1197 | /* |
| 1198 | * Branch tracing: |
| 1199 | */ |
| 1200 | if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) && |
markus.t.metzger@intel.com | 1653192 | 2009-09-02 16:04:48 +0200 | [diff] [blame] | 1201 | (hwc->sample_period == 1)) { |
| 1202 | /* BTS is not supported by this architecture. */ |
| 1203 | if (!bts_available()) |
| 1204 | return -EOPNOTSUPP; |
| 1205 | |
| 1206 | /* BTS is currently only allowed for user-mode. */ |
| 1207 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
| 1208 | return -EOPNOTSUPP; |
| 1209 | } |
markus.t.metzger@intel.com | 747b50a | 2009-09-02 16:04:46 +0200 | [diff] [blame] | 1210 | |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1211 | hwc->config |= config; |
Peter Zijlstra | 4e935e4 | 2009-03-30 19:07:16 +0200 | [diff] [blame] | 1212 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1213 | return 0; |
| 1214 | } |
| 1215 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1216 | static void p6_pmu_disable_all(void) |
| 1217 | { |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1218 | u64 val; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1219 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1220 | /* p6 only has one enable register */ |
| 1221 | rdmsrl(MSR_P6_EVNTSEL0, val); |
| 1222 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 1223 | wrmsrl(MSR_P6_EVNTSEL0, val); |
| 1224 | } |
| 1225 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1226 | static void intel_pmu_disable_all(void) |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 1227 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1228 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1229 | |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 1230 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1231 | |
| 1232 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) |
| 1233 | intel_pmu_disable_bts(); |
Thomas Gleixner | 4ac1329 | 2008-12-09 21:43:39 +0100 | [diff] [blame] | 1234 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1235 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1236 | static void x86_pmu_disable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1237 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1238 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1239 | int idx; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1240 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1241 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1242 | u64 val; |
| 1243 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1244 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 1245 | continue; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1246 | rdmsrl(x86_pmu.eventsel + idx, val); |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 1247 | if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE)) |
| 1248 | continue; |
| 1249 | val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1250 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1251 | } |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1252 | } |
| 1253 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1254 | void hw_perf_disable(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1255 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1256 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1257 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1258 | if (!x86_pmu_initialized()) |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1259 | return; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1260 | |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 1261 | if (!cpuc->enabled) |
| 1262 | return; |
| 1263 | |
| 1264 | cpuc->n_added = 0; |
| 1265 | cpuc->enabled = 0; |
| 1266 | barrier(); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1267 | |
| 1268 | x86_pmu.disable_all(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1269 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1270 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1271 | static void p6_pmu_enable_all(void) |
| 1272 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1273 | unsigned long val; |
| 1274 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1275 | /* p6 only has one enable register */ |
| 1276 | rdmsrl(MSR_P6_EVNTSEL0, val); |
| 1277 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 1278 | wrmsrl(MSR_P6_EVNTSEL0, val); |
| 1279 | } |
| 1280 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1281 | static void intel_pmu_enable_all(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1282 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1283 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1284 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1285 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1286 | |
| 1287 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1288 | struct perf_event *event = |
| 1289 | cpuc->events[X86_PMC_IDX_FIXED_BTS]; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1290 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1291 | if (WARN_ON_ONCE(!event)) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1292 | return; |
| 1293 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1294 | intel_pmu_enable_bts(event->hw.config); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1295 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 1296 | } |
| 1297 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1298 | static void x86_pmu_enable_all(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1299 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1300 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1301 | int idx; |
| 1302 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1303 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
| 1304 | struct perf_event *event = cpuc->events[idx]; |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 1305 | u64 val; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1306 | |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1307 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 1308 | continue; |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 1309 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1310 | val = event->hw.config; |
Robert Richter | 4295ee6 | 2009-04-29 12:47:01 +0200 | [diff] [blame] | 1311 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1312 | wrmsrl(x86_pmu.eventsel + idx, val); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1313 | } |
| 1314 | } |
| 1315 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1316 | static const struct pmu pmu; |
| 1317 | |
| 1318 | static inline int is_x86_event(struct perf_event *event) |
| 1319 | { |
| 1320 | return event->pmu == &pmu; |
| 1321 | } |
| 1322 | |
| 1323 | static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
| 1324 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1325 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1326 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 1327 | int i, j, w, wmax, num = 0; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1328 | struct hw_perf_event *hwc; |
| 1329 | |
| 1330 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 1331 | |
| 1332 | for (i = 0; i < n; i++) { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1333 | constraints[i] = |
| 1334 | x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1335 | } |
| 1336 | |
| 1337 | /* |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1338 | * fastpath, try to reuse previous register |
| 1339 | */ |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 1340 | for (i = 0; i < n; i++) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1341 | hwc = &cpuc->event_list[i]->hw; |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 1342 | c = constraints[i]; |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1343 | |
| 1344 | /* never assigned */ |
| 1345 | if (hwc->idx == -1) |
| 1346 | break; |
| 1347 | |
| 1348 | /* constraint still honored */ |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1349 | if (!test_bit(hwc->idx, c->idxmsk)) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1350 | break; |
| 1351 | |
| 1352 | /* not already used */ |
| 1353 | if (test_bit(hwc->idx, used_mask)) |
| 1354 | break; |
| 1355 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1356 | set_bit(hwc->idx, used_mask); |
| 1357 | if (assign) |
| 1358 | assign[i] = hwc->idx; |
| 1359 | } |
Peter Zijlstra | c933c1a | 2010-01-22 16:40:12 +0100 | [diff] [blame] | 1360 | if (i == n) |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1361 | goto done; |
| 1362 | |
| 1363 | /* |
| 1364 | * begin slow path |
| 1365 | */ |
| 1366 | |
| 1367 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); |
| 1368 | |
| 1369 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1370 | * weight = number of possible counters |
| 1371 | * |
| 1372 | * 1 = most constrained, only works on one counter |
| 1373 | * wmax = least constrained, works on any counter |
| 1374 | * |
| 1375 | * assign events to counters starting with most |
| 1376 | * constrained events. |
| 1377 | */ |
| 1378 | wmax = x86_pmu.num_events; |
| 1379 | |
| 1380 | /* |
| 1381 | * when fixed event counters are present, |
| 1382 | * wmax is incremented by 1 to account |
| 1383 | * for one more choice |
| 1384 | */ |
| 1385 | if (x86_pmu.num_events_fixed) |
| 1386 | wmax++; |
| 1387 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1388 | for (w = 1, num = n; num && w <= wmax; w++) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1389 | /* for each event */ |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1390 | for (i = 0; num && i < n; i++) { |
Peter Zijlstra | 81269a0 | 2010-01-22 14:55:22 +0100 | [diff] [blame] | 1391 | c = constraints[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1392 | hwc = &cpuc->event_list[i]->hw; |
| 1393 | |
Peter Zijlstra | 272d30b | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1394 | if (c->weight != w) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1395 | continue; |
| 1396 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 1397 | for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1398 | if (!test_bit(j, used_mask)) |
| 1399 | break; |
| 1400 | } |
| 1401 | |
| 1402 | if (j == X86_PMC_IDX_MAX) |
| 1403 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1404 | |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1405 | set_bit(j, used_mask); |
| 1406 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1407 | if (assign) |
| 1408 | assign[i] = j; |
| 1409 | num--; |
| 1410 | } |
| 1411 | } |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1412 | done: |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1413 | /* |
| 1414 | * scheduling failed or is just a simulation, |
| 1415 | * free resources if necessary |
| 1416 | */ |
| 1417 | if (!assign || num) { |
| 1418 | for (i = 0; i < n; i++) { |
| 1419 | if (x86_pmu.put_event_constraints) |
| 1420 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); |
| 1421 | } |
| 1422 | } |
| 1423 | return num ? -ENOSPC : 0; |
| 1424 | } |
| 1425 | |
| 1426 | /* |
| 1427 | * dogrp: true if must collect siblings events (group) |
| 1428 | * returns total number of events and error code |
| 1429 | */ |
| 1430 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) |
| 1431 | { |
| 1432 | struct perf_event *event; |
| 1433 | int n, max_count; |
| 1434 | |
| 1435 | max_count = x86_pmu.num_events + x86_pmu.num_events_fixed; |
| 1436 | |
| 1437 | /* current number of events already accepted */ |
| 1438 | n = cpuc->n_events; |
| 1439 | |
| 1440 | if (is_x86_event(leader)) { |
| 1441 | if (n >= max_count) |
| 1442 | return -ENOSPC; |
| 1443 | cpuc->event_list[n] = leader; |
| 1444 | n++; |
| 1445 | } |
| 1446 | if (!dogrp) |
| 1447 | return n; |
| 1448 | |
| 1449 | list_for_each_entry(event, &leader->sibling_list, group_entry) { |
| 1450 | if (!is_x86_event(event) || |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 1451 | event->state <= PERF_EVENT_STATE_OFF) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1452 | continue; |
| 1453 | |
| 1454 | if (n >= max_count) |
| 1455 | return -ENOSPC; |
| 1456 | |
| 1457 | cpuc->event_list[n] = event; |
| 1458 | n++; |
| 1459 | } |
| 1460 | return n; |
| 1461 | } |
| 1462 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1463 | static inline void x86_assign_hw_event(struct perf_event *event, |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1464 | struct cpu_hw_events *cpuc, int i) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1465 | { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1466 | struct hw_perf_event *hwc = &event->hw; |
| 1467 | |
| 1468 | hwc->idx = cpuc->assign[i]; |
| 1469 | hwc->last_cpu = smp_processor_id(); |
| 1470 | hwc->last_tag = ++cpuc->tags[i]; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1471 | |
| 1472 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { |
| 1473 | hwc->config_base = 0; |
| 1474 | hwc->event_base = 0; |
| 1475 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { |
| 1476 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
| 1477 | /* |
| 1478 | * We set it so that event_base + idx in wrmsr/rdmsr maps to |
| 1479 | * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2: |
| 1480 | */ |
| 1481 | hwc->event_base = |
| 1482 | MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED; |
| 1483 | } else { |
| 1484 | hwc->config_base = x86_pmu.eventsel; |
| 1485 | hwc->event_base = x86_pmu.perfctr; |
| 1486 | } |
| 1487 | } |
| 1488 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1489 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
| 1490 | struct cpu_hw_events *cpuc, |
| 1491 | int i) |
| 1492 | { |
| 1493 | return hwc->idx == cpuc->assign[i] && |
| 1494 | hwc->last_cpu == smp_processor_id() && |
| 1495 | hwc->last_tag == cpuc->tags[i]; |
| 1496 | } |
| 1497 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1498 | static void x86_pmu_stop(struct perf_event *event); |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1499 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1500 | void hw_perf_enable(void) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1501 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1502 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1503 | struct perf_event *event; |
| 1504 | struct hw_perf_event *hwc; |
| 1505 | int i; |
| 1506 | |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 1507 | if (!x86_pmu_initialized()) |
Ingo Molnar | 2b9ff0d | 2008-12-14 18:36:30 +0100 | [diff] [blame] | 1508 | return; |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 1509 | |
| 1510 | if (cpuc->enabled) |
| 1511 | return; |
| 1512 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1513 | if (cpuc->n_added) { |
| 1514 | /* |
| 1515 | * apply assignment obtained either from |
| 1516 | * hw_perf_group_sched_in() or x86_pmu_enable() |
| 1517 | * |
| 1518 | * step1: save events moving to new counters |
| 1519 | * step2: reprogram moved events into new counters |
| 1520 | */ |
| 1521 | for (i = 0; i < cpuc->n_events; i++) { |
| 1522 | |
| 1523 | event = cpuc->event_list[i]; |
| 1524 | hwc = &event->hw; |
| 1525 | |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1526 | /* |
| 1527 | * we can avoid reprogramming counter if: |
| 1528 | * - assigned same counter as last time |
| 1529 | * - running on same CPU as last time |
| 1530 | * - no other event has used the counter since |
| 1531 | */ |
| 1532 | if (hwc->idx == -1 || |
| 1533 | match_prev_assignment(hwc, cpuc, i)) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1534 | continue; |
| 1535 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1536 | x86_pmu_stop(event); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1537 | |
| 1538 | hwc->idx = -1; |
| 1539 | } |
| 1540 | |
| 1541 | for (i = 0; i < cpuc->n_events; i++) { |
| 1542 | |
| 1543 | event = cpuc->event_list[i]; |
| 1544 | hwc = &event->hw; |
| 1545 | |
| 1546 | if (hwc->idx == -1) { |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1547 | x86_assign_hw_event(event, cpuc, i); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1548 | x86_perf_event_set_period(event, hwc, hwc->idx); |
| 1549 | } |
| 1550 | /* |
| 1551 | * need to mark as active because x86_pmu_disable() |
Stephane Eranian | 447a194 | 2010-02-01 14:50:01 +0200 | [diff] [blame] | 1552 | * clear active_mask and events[] yet it preserves |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1553 | * idx |
| 1554 | */ |
| 1555 | set_bit(hwc->idx, cpuc->active_mask); |
| 1556 | cpuc->events[hwc->idx] = event; |
| 1557 | |
| 1558 | x86_pmu.enable(hwc, hwc->idx); |
| 1559 | perf_event_update_userpage(event); |
| 1560 | } |
| 1561 | cpuc->n_added = 0; |
| 1562 | perf_events_lapic_init(); |
| 1563 | } |
Peter Zijlstra | 1a6e21f | 2010-01-27 23:07:47 +0100 | [diff] [blame] | 1564 | |
| 1565 | cpuc->enabled = 1; |
| 1566 | barrier(); |
| 1567 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 1568 | x86_pmu.enable_all(); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1569 | } |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1570 | |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 1571 | static inline u64 intel_pmu_get_status(void) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1572 | { |
| 1573 | u64 status; |
| 1574 | |
| 1575 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1576 | |
| 1577 | return status; |
| 1578 | } |
| 1579 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 1580 | static inline void intel_pmu_ack_status(u64 ack) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1581 | { |
| 1582 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); |
| 1583 | } |
| 1584 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1585 | static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1586 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1587 | (void)checking_wrmsrl(hwc->config_base + idx, |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1588 | hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1589 | } |
| 1590 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1591 | static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx) |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1592 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1593 | (void)checking_wrmsrl(hwc->config_base + idx, hwc->config); |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 1594 | } |
| 1595 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1596 | static inline void |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1597 | intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1598 | { |
| 1599 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 1600 | u64 ctrl_val, mask; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1601 | |
| 1602 | mask = 0xfULL << (idx * 4); |
| 1603 | |
| 1604 | rdmsrl(hwc->config_base, ctrl_val); |
| 1605 | ctrl_val &= ~mask; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1606 | (void)checking_wrmsrl(hwc->config_base, ctrl_val); |
| 1607 | } |
| 1608 | |
| 1609 | static inline void |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1610 | p6_pmu_disable_event(struct hw_perf_event *hwc, int idx) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1611 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1612 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1613 | u64 val = P6_NOP_EVENT; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1614 | |
Peter Zijlstra | 9c74fb5 | 2009-07-08 10:21:41 +0200 | [diff] [blame] | 1615 | if (cpuc->enabled) |
| 1616 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1617 | |
| 1618 | (void)checking_wrmsrl(hwc->config_base + idx, val); |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1619 | } |
| 1620 | |
| 1621 | static inline void |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1622 | intel_pmu_disable_event(struct hw_perf_event *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1623 | { |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1624 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { |
| 1625 | intel_pmu_disable_bts(); |
| 1626 | return; |
| 1627 | } |
| 1628 | |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1629 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 1630 | intel_pmu_disable_fixed(hwc, idx); |
| 1631 | return; |
| 1632 | } |
| 1633 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1634 | x86_pmu_disable_event(hwc, idx); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1635 | } |
| 1636 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1637 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1638 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1639 | /* |
| 1640 | * Set the next IRQ period, based on the hwc->period_left value. |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1641 | * To be called with the event disabled in hw: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1642 | */ |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1643 | static int |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1644 | x86_perf_event_set_period(struct perf_event *event, |
| 1645 | struct hw_perf_event *hwc, int idx) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1646 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1647 | s64 left = atomic64_read(&hwc->period_left); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1648 | s64 period = hwc->sample_period; |
| 1649 | int err, ret = 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1650 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1651 | if (idx == X86_PMC_IDX_FIXED_BTS) |
| 1652 | return 0; |
| 1653 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1654 | /* |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1655 | * If we are way outside a reasonable range then just skip forward: |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1656 | */ |
| 1657 | if (unlikely(left <= -period)) { |
| 1658 | left = period; |
| 1659 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1660 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1661 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1662 | } |
| 1663 | |
| 1664 | if (unlikely(left <= 0)) { |
| 1665 | left += period; |
| 1666 | atomic64_set(&hwc->period_left, left); |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 1667 | hwc->last_period = period; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1668 | ret = 1; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1669 | } |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 1670 | /* |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 1671 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
Ingo Molnar | 1c80f4b | 2009-05-15 08:25:22 +0200 | [diff] [blame] | 1672 | */ |
| 1673 | if (unlikely(left < 2)) |
| 1674 | left = 2; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1675 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1676 | if (left > x86_pmu.max_period) |
| 1677 | left = x86_pmu.max_period; |
| 1678 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1679 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1680 | |
| 1681 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1682 | * The hw event starts counting from this event offset, |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1683 | * mark it to be able to extra future deltas: |
| 1684 | */ |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1685 | atomic64_set(&hwc->prev_count, (u64)-left); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1686 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1687 | err = checking_wrmsrl(hwc->event_base + idx, |
| 1688 | (u64)(-left) & x86_pmu.event_mask); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1689 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1690 | perf_event_update_userpage(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1691 | |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1692 | return ret; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1693 | } |
| 1694 | |
| 1695 | static inline void |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1696 | intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx) |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1697 | { |
| 1698 | int idx = __idx - X86_PMC_IDX_FIXED; |
| 1699 | u64 ctrl_val, bits, mask; |
| 1700 | int err; |
| 1701 | |
| 1702 | /* |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1703 | * Enable IRQ generation (0x8), |
| 1704 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) |
| 1705 | * if requested: |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1706 | */ |
Paul Mackerras | 0475f9e | 2009-02-11 14:35:35 +1100 | [diff] [blame] | 1707 | bits = 0x8ULL; |
| 1708 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) |
| 1709 | bits |= 0x2; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1710 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) |
| 1711 | bits |= 0x1; |
Stephane Eranian | b27d515 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1712 | |
| 1713 | /* |
| 1714 | * ANY bit is supported in v3 and up |
| 1715 | */ |
| 1716 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) |
| 1717 | bits |= 0x4; |
| 1718 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1719 | bits <<= (idx * 4); |
| 1720 | mask = 0xfULL << (idx * 4); |
| 1721 | |
| 1722 | rdmsrl(hwc->config_base, ctrl_val); |
| 1723 | ctrl_val &= ~mask; |
| 1724 | ctrl_val |= bits; |
| 1725 | err = checking_wrmsrl(hwc->config_base, ctrl_val); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1726 | } |
| 1727 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1728 | static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1729 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1730 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 1731 | u64 val; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1732 | |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 1733 | val = hwc->config; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1734 | if (cpuc->enabled) |
Peter Zijlstra | 984b838 | 2009-07-10 09:59:56 +0200 | [diff] [blame] | 1735 | val |= ARCH_PERFMON_EVENTSEL0_ENABLE; |
| 1736 | |
| 1737 | (void)checking_wrmsrl(hwc->config_base + idx, val); |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1741 | static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1742 | { |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1743 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1744 | if (!__get_cpu_var(cpu_hw_events).enabled) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1745 | return; |
| 1746 | |
| 1747 | intel_pmu_enable_bts(hwc->config); |
| 1748 | return; |
| 1749 | } |
| 1750 | |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1751 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
| 1752 | intel_pmu_enable_fixed(hwc, idx); |
| 1753 | return; |
| 1754 | } |
| 1755 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1756 | __x86_pmu_enable_event(hwc, idx); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1757 | } |
| 1758 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1759 | static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx) |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1760 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1761 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | 7c90cc4 | 2009-04-29 12:47:18 +0200 | [diff] [blame] | 1762 | if (cpuc->enabled) |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 1763 | __x86_pmu_enable_event(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1764 | } |
| 1765 | |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1766 | /* |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1767 | * activate a single event |
| 1768 | * |
| 1769 | * The event is added to the group of enabled events |
| 1770 | * but only if it can be scehduled with existing events. |
| 1771 | * |
| 1772 | * Called with PMU disabled. If successful and return value 1, |
| 1773 | * then guaranteed to call perf_enable() and hw_perf_enable() |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1774 | */ |
| 1775 | static int x86_pmu_enable(struct perf_event *event) |
| 1776 | { |
| 1777 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1778 | struct hw_perf_event *hwc; |
| 1779 | int assign[X86_PMC_IDX_MAX]; |
| 1780 | int n, n0, ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1781 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1782 | hwc = &event->hw; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 1783 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1784 | n0 = cpuc->n_events; |
| 1785 | n = collect_events(cpuc, event, false); |
| 1786 | if (n < 0) |
| 1787 | return n; |
Ingo Molnar | 53b441a | 2009-05-25 21:41:28 +0200 | [diff] [blame] | 1788 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1789 | ret = x86_schedule_events(cpuc, n, assign); |
| 1790 | if (ret) |
| 1791 | return ret; |
| 1792 | /* |
| 1793 | * copy new assignment, now we know it is possible |
| 1794 | * will be used by hw_perf_enable() |
| 1795 | */ |
| 1796 | memcpy(cpuc->assign, assign, n*sizeof(int)); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1797 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1798 | cpuc->n_events = n; |
| 1799 | cpuc->n_added = n - n0; |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1800 | |
Ingo Molnar | 95cdd2e | 2008-12-21 13:50:42 +0100 | [diff] [blame] | 1801 | return 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1802 | } |
| 1803 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1804 | static int x86_pmu_start(struct perf_event *event) |
| 1805 | { |
| 1806 | struct hw_perf_event *hwc = &event->hw; |
| 1807 | |
| 1808 | if (hwc->idx == -1) |
| 1809 | return -EAGAIN; |
| 1810 | |
| 1811 | x86_perf_event_set_period(event, hwc, hwc->idx); |
| 1812 | x86_pmu.enable(hwc, hwc->idx); |
| 1813 | |
| 1814 | return 0; |
| 1815 | } |
| 1816 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1817 | static void x86_pmu_unthrottle(struct perf_event *event) |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1818 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1819 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1820 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1821 | |
| 1822 | if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX || |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1823 | cpuc->events[hwc->idx] != event)) |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 1824 | return; |
| 1825 | |
| 1826 | x86_pmu.enable(hwc, hwc->idx); |
| 1827 | } |
| 1828 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1829 | void perf_event_print_debug(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1830 | { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1831 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1832 | struct cpu_hw_events *cpuc; |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1833 | unsigned long flags; |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1834 | int cpu, idx; |
| 1835 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1836 | if (!x86_pmu.num_events) |
Ingo Molnar | 1e12567 | 2008-12-09 12:18:18 +0100 | [diff] [blame] | 1837 | return; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1838 | |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1839 | local_irq_save(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1840 | |
| 1841 | cpu = smp_processor_id(); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1842 | cpuc = &per_cpu(cpu_hw_events, cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1843 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 1844 | if (x86_pmu.version >= 2) { |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1845 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
| 1846 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); |
| 1847 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); |
| 1848 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1849 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1850 | pr_info("\n"); |
| 1851 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); |
| 1852 | pr_info("CPU#%d: status: %016llx\n", cpu, status); |
| 1853 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); |
| 1854 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 1855 | } |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1856 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1857 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1858 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 1859 | rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl); |
| 1860 | rdmsrl(x86_pmu.perfctr + idx, pmc_count); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1861 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 1862 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1863 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1864 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1865 | cpu, idx, pmc_ctrl); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1866 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1867 | cpu, idx, pmc_count); |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1868 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1869 | cpu, idx, prev_left); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1870 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1871 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1872 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
| 1873 | |
Jaswinder Singh Rajput | a1ef58f | 2009-02-28 18:45:39 +0530 | [diff] [blame] | 1874 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1875 | cpu, idx, pmc_count); |
| 1876 | } |
Peter Zijlstra | 5bb9efe | 2009-05-13 08:12:51 +0200 | [diff] [blame] | 1877 | local_irq_restore(flags); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1878 | } |
| 1879 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1880 | static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1881 | { |
| 1882 | struct debug_store *ds = cpuc->ds; |
| 1883 | struct bts_record { |
| 1884 | u64 from; |
| 1885 | u64 to; |
| 1886 | u64 flags; |
| 1887 | }; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1888 | struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS]; |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 1889 | struct bts_record *at, *top; |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1890 | struct perf_output_handle handle; |
| 1891 | struct perf_event_header header; |
| 1892 | struct perf_sample_data data; |
| 1893 | struct pt_regs regs; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1894 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1895 | if (!event) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1896 | return; |
| 1897 | |
| 1898 | if (!ds) |
| 1899 | return; |
| 1900 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 1901 | at = (struct bts_record *)(unsigned long)ds->bts_buffer_base; |
| 1902 | top = (struct bts_record *)(unsigned long)ds->bts_index; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1903 | |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1904 | if (top <= at) |
| 1905 | return; |
| 1906 | |
markus.t.metzger@intel.com | 596da17 | 2009-09-02 16:04:47 +0200 | [diff] [blame] | 1907 | ds->bts_index = ds->bts_buffer_base; |
| 1908 | |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1909 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1910 | data.period = event->hw.last_period; |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1911 | data.addr = 0; |
Xiao Guangrong | 5e855db | 2009-12-10 17:08:54 +0800 | [diff] [blame] | 1912 | data.raw = NULL; |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1913 | regs.ip = 0; |
| 1914 | |
| 1915 | /* |
| 1916 | * Prepare a generic sample, i.e. fill in the invariant fields. |
| 1917 | * We will overwrite the from and to address before we output |
| 1918 | * the sample. |
| 1919 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1920 | perf_prepare_sample(&header, &data, event, ®s); |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1921 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1922 | if (perf_output_begin(&handle, event, |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1923 | header.size * (top - at), 1, 1)) |
| 1924 | return; |
| 1925 | |
| 1926 | for (; at < top; at++) { |
| 1927 | data.ip = at->from; |
| 1928 | data.addr = at->to; |
| 1929 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1930 | perf_output_sample(&handle, &header, &data, event); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1931 | } |
| 1932 | |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1933 | perf_output_end(&handle); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1934 | |
| 1935 | /* There's new data available. */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1936 | event->hw.interrupts++; |
| 1937 | event->pending_kill = POLL_IN; |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1938 | } |
| 1939 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1940 | static void x86_pmu_stop(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1941 | { |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1942 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1943 | struct hw_perf_event *hwc = &event->hw; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1944 | int idx = hwc->idx; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1945 | |
Robert Richter | 0953423 | 2009-04-29 12:47:16 +0200 | [diff] [blame] | 1946 | /* |
| 1947 | * Must be done before we disable, otherwise the nmi handler |
| 1948 | * could reenable again: |
| 1949 | */ |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 1950 | clear_bit(idx, cpuc->active_mask); |
Robert Richter | d436989 | 2009-04-29 12:47:19 +0200 | [diff] [blame] | 1951 | x86_pmu.disable(hwc, idx); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1952 | |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 1953 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1954 | * Drain the remaining delta count out of a event |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 1955 | * that we are disabling: |
| 1956 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1957 | x86_perf_event_update(event, hwc, idx); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1958 | |
| 1959 | /* Drain the remaining BTS records. */ |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 1960 | if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) |
| 1961 | intel_pmu_drain_bts_buffer(cpuc); |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 1962 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1963 | cpuc->events[idx] = NULL; |
Peter Zijlstra | 2e84187 | 2010-01-25 15:58:43 +0100 | [diff] [blame] | 1964 | } |
| 1965 | |
| 1966 | static void x86_pmu_disable(struct perf_event *event) |
| 1967 | { |
| 1968 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
| 1969 | int i; |
| 1970 | |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 1971 | x86_pmu_stop(event); |
Peter Zijlstra | 194002b | 2009-06-22 16:35:24 +0200 | [diff] [blame] | 1972 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1973 | for (i = 0; i < cpuc->n_events; i++) { |
| 1974 | if (event == cpuc->event_list[i]) { |
| 1975 | |
| 1976 | if (x86_pmu.put_event_constraints) |
| 1977 | x86_pmu.put_event_constraints(cpuc, event); |
| 1978 | |
| 1979 | while (++i < cpuc->n_events) |
| 1980 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
| 1981 | |
| 1982 | --cpuc->n_events; |
Peter Zijlstra | 6c9687a | 2010-01-25 11:57:25 +0100 | [diff] [blame] | 1983 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 1984 | } |
| 1985 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1986 | perf_event_update_userpage(event); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1987 | } |
| 1988 | |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1989 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1990 | * Save and restart an expired event. Called by NMI contexts, |
| 1991 | * so it has to be careful about preempting normal event ops: |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 1992 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1993 | static int intel_pmu_save_and_restart(struct perf_event *event) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1994 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1995 | struct hw_perf_event *hwc = &event->hw; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1996 | int idx = hwc->idx; |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 1997 | int ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 1998 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 1999 | x86_perf_event_update(event, hwc, idx); |
| 2000 | ret = x86_perf_event_set_period(event, hwc, idx); |
Ingo Molnar | 7e2ae34 | 2008-12-09 11:40:46 +0100 | [diff] [blame] | 2001 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2002 | if (event->state == PERF_EVENT_STATE_ACTIVE) |
| 2003 | intel_pmu_enable_event(hwc, idx); |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 2004 | |
| 2005 | return ret; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2006 | } |
| 2007 | |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2008 | static void intel_pmu_reset(void) |
| 2009 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2010 | struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds; |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2011 | unsigned long flags; |
| 2012 | int idx; |
| 2013 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2014 | if (!x86_pmu.num_events) |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2015 | return; |
| 2016 | |
| 2017 | local_irq_save(flags); |
| 2018 | |
| 2019 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); |
| 2020 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2021 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2022 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); |
| 2023 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); |
| 2024 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2025 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2026 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
| 2027 | } |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 2028 | if (ds) |
| 2029 | ds->bts_index = ds->bts_buffer_base; |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2030 | |
| 2031 | local_irq_restore(flags); |
| 2032 | } |
| 2033 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2034 | /* |
| 2035 | * This handler is triggered by the local APIC, so the APIC IRQ handling |
| 2036 | * rules apply: |
| 2037 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 2038 | static int intel_pmu_handle_irq(struct pt_regs *regs) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2039 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2040 | struct perf_sample_data data; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2041 | struct cpu_hw_events *cpuc; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2042 | int bit, loops; |
Mike Galbraith | 4b39fd9 | 2009-01-23 14:36:16 +0100 | [diff] [blame] | 2043 | u64 ack, status; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 2044 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2045 | data.addr = 0; |
Xiao Guangrong | 5e855db | 2009-12-10 17:08:54 +0800 | [diff] [blame] | 2046 | data.raw = NULL; |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2047 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2048 | cpuc = &__get_cpu_var(cpu_hw_events); |
Ingo Molnar | 43874d2 | 2008-12-09 12:23:59 +0100 | [diff] [blame] | 2049 | |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 2050 | perf_disable(); |
Markus Metzger | 5622f29 | 2009-09-15 13:00:23 +0200 | [diff] [blame] | 2051 | intel_pmu_drain_bts_buffer(cpuc); |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 2052 | status = intel_pmu_get_status(); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 2053 | if (!status) { |
| 2054 | perf_enable(); |
| 2055 | return 0; |
| 2056 | } |
Ingo Molnar | 87b9cf4 | 2008-12-08 14:20:16 +0100 | [diff] [blame] | 2057 | |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 2058 | loops = 0; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2059 | again: |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 2060 | if (++loops > 100) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2061 | WARN_ONCE(1, "perfevents: irq loop stuck!\n"); |
| 2062 | perf_event_print_debug(); |
Ingo Molnar | aaba980 | 2009-05-26 08:10:00 +0200 | [diff] [blame] | 2063 | intel_pmu_reset(); |
| 2064 | perf_enable(); |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 2065 | return 1; |
| 2066 | } |
| 2067 | |
Mike Galbraith | d278c48 | 2009-02-09 07:38:50 +0100 | [diff] [blame] | 2068 | inc_irq_stat(apic_perf_irqs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2069 | ack = status; |
Ingo Molnar | 2f18d1e | 2008-12-22 11:10:42 +0100 | [diff] [blame] | 2070 | for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2071 | struct perf_event *event = cpuc->events[bit]; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2072 | |
| 2073 | clear_bit(bit, (unsigned long *) &status); |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 2074 | if (!test_bit(bit, cpuc->active_mask)) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2075 | continue; |
| 2076 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2077 | if (!intel_pmu_save_and_restart(event)) |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 2078 | continue; |
| 2079 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2080 | data.period = event->hw.last_period; |
Peter Zijlstra | 60f916d | 2009-06-15 19:00:20 +0200 | [diff] [blame] | 2081 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2082 | if (perf_event_overflow(event, 1, &data, regs)) |
| 2083 | intel_pmu_disable_event(&event->hw, bit); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2084 | } |
| 2085 | |
Robert Richter | dee5d90 | 2009-04-29 12:47:07 +0200 | [diff] [blame] | 2086 | intel_pmu_ack_status(ack); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2087 | |
| 2088 | /* |
| 2089 | * Repeat if there is more work to be done: |
| 2090 | */ |
Robert Richter | 19d84da | 2009-04-29 12:47:25 +0200 | [diff] [blame] | 2091 | status = intel_pmu_get_status(); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2092 | if (status) |
| 2093 | goto again; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 2094 | |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 2095 | perf_enable(); |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 2096 | |
| 2097 | return 1; |
Mike Galbraith | 1b023a9 | 2009-01-23 10:13:01 +0100 | [diff] [blame] | 2098 | } |
| 2099 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2100 | static int x86_pmu_handle_irq(struct pt_regs *regs) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 2101 | { |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2102 | struct perf_sample_data data; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2103 | struct cpu_hw_events *cpuc; |
| 2104 | struct perf_event *event; |
| 2105 | struct hw_perf_event *hwc; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2106 | int idx, handled = 0; |
Ingo Molnar | 9029a5e | 2009-05-15 08:26:20 +0200 | [diff] [blame] | 2107 | u64 val; |
| 2108 | |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2109 | data.addr = 0; |
Xiao Guangrong | 5e855db | 2009-12-10 17:08:54 +0800 | [diff] [blame] | 2110 | data.raw = NULL; |
Peter Zijlstra | df1a132 | 2009-06-10 21:02:22 +0200 | [diff] [blame] | 2111 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2112 | cpuc = &__get_cpu_var(cpu_hw_events); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 2113 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2114 | for (idx = 0; idx < x86_pmu.num_events; idx++) { |
Robert Richter | 43f6201 | 2009-04-29 16:55:56 +0200 | [diff] [blame] | 2115 | if (!test_bit(idx, cpuc->active_mask)) |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 2116 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 2117 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2118 | event = cpuc->events[idx]; |
| 2119 | hwc = &event->hw; |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 2120 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2121 | val = x86_perf_event_update(event, hwc, idx); |
| 2122 | if (val & (1ULL << (x86_pmu.event_bits - 1))) |
Peter Zijlstra | 48e22d5 | 2009-05-25 17:39:04 +0200 | [diff] [blame] | 2123 | continue; |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 2124 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 2125 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2126 | * event overflow |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 2127 | */ |
| 2128 | handled = 1; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2129 | data.period = event->hw.last_period; |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 2130 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2131 | if (!x86_perf_event_set_period(event, hwc, idx)) |
Peter Zijlstra | e4abb5d | 2009-06-02 16:08:20 +0200 | [diff] [blame] | 2132 | continue; |
| 2133 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2134 | if (perf_event_overflow(event, 1, &data, regs)) |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2135 | x86_pmu.disable(hwc, idx); |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 2136 | } |
Peter Zijlstra | 962bf7a | 2009-05-13 13:21:36 +0200 | [diff] [blame] | 2137 | |
Peter Zijlstra | 9e350de | 2009-06-10 21:34:59 +0200 | [diff] [blame] | 2138 | if (handled) |
| 2139 | inc_irq_stat(apic_perf_irqs); |
| 2140 | |
Robert Richter | a29aa8a | 2009-04-29 12:47:21 +0200 | [diff] [blame] | 2141 | return handled; |
| 2142 | } |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 2143 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 2144 | void smp_perf_pending_interrupt(struct pt_regs *regs) |
| 2145 | { |
| 2146 | irq_enter(); |
| 2147 | ack_APIC_irq(); |
| 2148 | inc_irq_stat(apic_pending_irqs); |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2149 | perf_event_do_pending(); |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 2150 | irq_exit(); |
| 2151 | } |
| 2152 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2153 | void set_perf_event_pending(void) |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 2154 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2155 | #ifdef CONFIG_X86_LOCAL_APIC |
Peter Zijlstra | 7d42896 | 2009-09-23 11:03:37 +0200 | [diff] [blame] | 2156 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
| 2157 | return; |
| 2158 | |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 2159 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2160 | #endif |
Peter Zijlstra | b6276f3 | 2009-04-06 11:45:03 +0200 | [diff] [blame] | 2161 | } |
| 2162 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2163 | void perf_events_lapic_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2164 | { |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2165 | #ifdef CONFIG_X86_LOCAL_APIC |
| 2166 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2167 | return; |
Robert Richter | 85cf9db | 2009-04-29 12:47:20 +0200 | [diff] [blame] | 2168 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2169 | /* |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 2170 | * Always use NMI for PMU |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2171 | */ |
Yong Wang | c323d95 | 2009-05-29 13:28:35 +0800 | [diff] [blame] | 2172 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2173 | #endif |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2174 | } |
| 2175 | |
| 2176 | static int __kprobes |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2177 | perf_event_nmi_handler(struct notifier_block *self, |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2178 | unsigned long cmd, void *__args) |
| 2179 | { |
| 2180 | struct die_args *args = __args; |
| 2181 | struct pt_regs *regs; |
| 2182 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2183 | if (!atomic_read(&active_events)) |
Peter Zijlstra | 63a809a | 2009-05-01 12:23:17 +0200 | [diff] [blame] | 2184 | return NOTIFY_DONE; |
| 2185 | |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 2186 | switch (cmd) { |
| 2187 | case DIE_NMI: |
| 2188 | case DIE_NMI_IPI: |
| 2189 | break; |
| 2190 | |
| 2191 | default: |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2192 | return NOTIFY_DONE; |
Peter Zijlstra | b0f3f28 | 2009-03-05 18:08:27 +0100 | [diff] [blame] | 2193 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2194 | |
| 2195 | regs = args->regs; |
| 2196 | |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2197 | #ifdef CONFIG_X86_LOCAL_APIC |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2198 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2199 | #endif |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 2200 | /* |
| 2201 | * Can't rely on the handled return value to say it was our NMI, two |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2202 | * events could trigger 'simultaneously' raising two back-to-back NMIs. |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 2203 | * |
| 2204 | * If the first NMI handles both, the latter will be empty and daze |
| 2205 | * the CPU. |
| 2206 | */ |
Yong Wang | a328810 | 2009-06-03 13:12:55 +0800 | [diff] [blame] | 2207 | x86_pmu.handle_irq(regs); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2208 | |
Peter Zijlstra | a4016a7 | 2009-05-14 14:52:17 +0200 | [diff] [blame] | 2209 | return NOTIFY_STOP; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2210 | } |
| 2211 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2212 | static struct event_constraint unconstrained; |
| 2213 | |
Peter Zijlstra | c91e0f5 | 2010-01-22 15:25:59 +0100 | [diff] [blame] | 2214 | static struct event_constraint bts_constraint = |
| 2215 | EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2216 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2217 | static struct event_constraint * |
| 2218 | intel_special_constraints(struct perf_event *event) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2219 | { |
| 2220 | unsigned int hw_event; |
| 2221 | |
| 2222 | hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK; |
| 2223 | |
| 2224 | if (unlikely((hw_event == |
| 2225 | x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) && |
| 2226 | (event->hw.sample_period == 1))) { |
| 2227 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2228 | return &bts_constraint; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2229 | } |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2230 | return NULL; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2231 | } |
| 2232 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2233 | static struct event_constraint * |
| 2234 | intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2235 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2236 | struct event_constraint *c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2237 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2238 | c = intel_special_constraints(event); |
| 2239 | if (c) |
| 2240 | return c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2241 | |
| 2242 | if (x86_pmu.event_constraints) { |
| 2243 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2244 | if ((event->hw.config & c->cmask) == c->code) |
| 2245 | return c; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2246 | } |
| 2247 | } |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2248 | |
| 2249 | return &unconstrained; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2250 | } |
| 2251 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2252 | static struct event_constraint * |
| 2253 | amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2254 | { |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2255 | return &unconstrained; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2256 | } |
| 2257 | |
| 2258 | static int x86_event_sched_in(struct perf_event *event, |
| 2259 | struct perf_cpu_context *cpuctx, int cpu) |
| 2260 | { |
| 2261 | int ret = 0; |
| 2262 | |
| 2263 | event->state = PERF_EVENT_STATE_ACTIVE; |
| 2264 | event->oncpu = cpu; |
| 2265 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; |
| 2266 | |
| 2267 | if (!is_x86_event(event)) |
| 2268 | ret = event->pmu->enable(event); |
| 2269 | |
| 2270 | if (!ret && !is_software_event(event)) |
| 2271 | cpuctx->active_oncpu++; |
| 2272 | |
| 2273 | if (!ret && event->attr.exclusive) |
| 2274 | cpuctx->exclusive = 1; |
| 2275 | |
| 2276 | return ret; |
| 2277 | } |
| 2278 | |
| 2279 | static void x86_event_sched_out(struct perf_event *event, |
| 2280 | struct perf_cpu_context *cpuctx, int cpu) |
| 2281 | { |
| 2282 | event->state = PERF_EVENT_STATE_INACTIVE; |
| 2283 | event->oncpu = -1; |
| 2284 | |
| 2285 | if (!is_x86_event(event)) |
| 2286 | event->pmu->disable(event); |
| 2287 | |
| 2288 | event->tstamp_running -= event->ctx->time - event->tstamp_stopped; |
| 2289 | |
| 2290 | if (!is_software_event(event)) |
| 2291 | cpuctx->active_oncpu--; |
| 2292 | |
| 2293 | if (event->attr.exclusive || !cpuctx->active_oncpu) |
| 2294 | cpuctx->exclusive = 0; |
| 2295 | } |
| 2296 | |
| 2297 | /* |
| 2298 | * Called to enable a whole group of events. |
| 2299 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. |
| 2300 | * Assumes the caller has disabled interrupts and has |
| 2301 | * frozen the PMU with hw_perf_save_disable. |
| 2302 | * |
| 2303 | * called with PMU disabled. If successful and return value 1, |
| 2304 | * then guaranteed to call perf_enable() and hw_perf_enable() |
| 2305 | */ |
| 2306 | int hw_perf_group_sched_in(struct perf_event *leader, |
| 2307 | struct perf_cpu_context *cpuctx, |
| 2308 | struct perf_event_context *ctx, int cpu) |
| 2309 | { |
| 2310 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
| 2311 | struct perf_event *sub; |
| 2312 | int assign[X86_PMC_IDX_MAX]; |
| 2313 | int n0, n1, ret; |
| 2314 | |
| 2315 | /* n0 = total number of events */ |
| 2316 | n0 = collect_events(cpuc, leader, true); |
| 2317 | if (n0 < 0) |
| 2318 | return n0; |
| 2319 | |
| 2320 | ret = x86_schedule_events(cpuc, n0, assign); |
| 2321 | if (ret) |
| 2322 | return ret; |
| 2323 | |
| 2324 | ret = x86_event_sched_in(leader, cpuctx, cpu); |
| 2325 | if (ret) |
| 2326 | return ret; |
| 2327 | |
| 2328 | n1 = 1; |
| 2329 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 2330 | if (sub->state > PERF_EVENT_STATE_OFF) { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2331 | ret = x86_event_sched_in(sub, cpuctx, cpu); |
| 2332 | if (ret) |
| 2333 | goto undo; |
| 2334 | ++n1; |
| 2335 | } |
| 2336 | } |
| 2337 | /* |
| 2338 | * copy new assignment, now we know it is possible |
| 2339 | * will be used by hw_perf_enable() |
| 2340 | */ |
| 2341 | memcpy(cpuc->assign, assign, n0*sizeof(int)); |
| 2342 | |
| 2343 | cpuc->n_events = n0; |
| 2344 | cpuc->n_added = n1; |
| 2345 | ctx->nr_active += n1; |
| 2346 | |
| 2347 | /* |
| 2348 | * 1 means successful and events are active |
| 2349 | * This is not quite true because we defer |
| 2350 | * actual activation until hw_perf_enable() but |
| 2351 | * this way we* ensure caller won't try to enable |
| 2352 | * individual events |
| 2353 | */ |
| 2354 | return 1; |
| 2355 | undo: |
| 2356 | x86_event_sched_out(leader, cpuctx, cpu); |
| 2357 | n0 = 1; |
| 2358 | list_for_each_entry(sub, &leader->sibling_list, group_entry) { |
| 2359 | if (sub->state == PERF_EVENT_STATE_ACTIVE) { |
| 2360 | x86_event_sched_out(sub, cpuctx, cpu); |
| 2361 | if (++n0 == n1) |
| 2362 | break; |
| 2363 | } |
| 2364 | } |
| 2365 | return ret; |
| 2366 | } |
| 2367 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2368 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
| 2369 | .notifier_call = perf_event_nmi_handler, |
Mike Galbraith | 5b75af0 | 2009-02-04 17:11:34 +0100 | [diff] [blame] | 2370 | .next = NULL, |
| 2371 | .priority = 1 |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2372 | }; |
| 2373 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2374 | static __initconst struct x86_pmu p6_pmu = { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2375 | .name = "p6", |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2376 | .handle_irq = x86_pmu_handle_irq, |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2377 | .disable_all = p6_pmu_disable_all, |
| 2378 | .enable_all = p6_pmu_enable_all, |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2379 | .enable = p6_pmu_enable_event, |
| 2380 | .disable = p6_pmu_disable_event, |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2381 | .eventsel = MSR_P6_EVNTSEL0, |
| 2382 | .perfctr = MSR_P6_PERFCTR0, |
| 2383 | .event_map = p6_pmu_event_map, |
| 2384 | .raw_event = p6_pmu_raw_event, |
| 2385 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2386 | .apic = 1, |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2387 | .max_period = (1ULL << 31) - 1, |
| 2388 | .version = 0, |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2389 | .num_events = 2, |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2390 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2391 | * Events have 40 bits implemented. However they are designed such |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2392 | * that bits [32-39] are sign extensions of bit 31. As such the |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2393 | * effective width of a event for P6-like PMU is 32 bits only. |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2394 | * |
| 2395 | * See IA-32 Intel Architecture Software developer manual Vol 3B |
| 2396 | */ |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2397 | .event_bits = 32, |
| 2398 | .event_mask = (1ULL << 32) - 1, |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2399 | .get_event_constraints = intel_get_event_constraints, |
| 2400 | .event_constraints = intel_p6_event_constraints |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2401 | }; |
| 2402 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2403 | static __initconst struct x86_pmu core_pmu = { |
| 2404 | .name = "core", |
| 2405 | .handle_irq = x86_pmu_handle_irq, |
| 2406 | .disable_all = x86_pmu_disable_all, |
| 2407 | .enable_all = x86_pmu_enable_all, |
| 2408 | .enable = x86_pmu_enable_event, |
| 2409 | .disable = x86_pmu_disable_event, |
| 2410 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
| 2411 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, |
| 2412 | .event_map = intel_pmu_event_map, |
| 2413 | .raw_event = intel_pmu_raw_event, |
| 2414 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
| 2415 | .apic = 1, |
| 2416 | /* |
| 2417 | * Intel PMCs cannot be accessed sanely above 32 bit width, |
| 2418 | * so we install an artificial 1<<31 period regardless of |
| 2419 | * the generic event period: |
| 2420 | */ |
| 2421 | .max_period = (1ULL << 31) - 1, |
| 2422 | .get_event_constraints = intel_get_event_constraints, |
| 2423 | .event_constraints = intel_core_event_constraints, |
| 2424 | }; |
| 2425 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2426 | static __initconst struct x86_pmu intel_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 2427 | .name = "Intel", |
Robert Richter | 39d81ea | 2009-04-29 12:47:05 +0200 | [diff] [blame] | 2428 | .handle_irq = intel_pmu_handle_irq, |
Peter Zijlstra | 9e35ad3 | 2009-05-13 16:21:38 +0200 | [diff] [blame] | 2429 | .disable_all = intel_pmu_disable_all, |
| 2430 | .enable_all = intel_pmu_enable_all, |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2431 | .enable = intel_pmu_enable_event, |
| 2432 | .disable = intel_pmu_disable_event, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2433 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
| 2434 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 2435 | .event_map = intel_pmu_event_map, |
| 2436 | .raw_event = intel_pmu_raw_event, |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2437 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2438 | .apic = 1, |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 2439 | /* |
| 2440 | * Intel PMCs cannot be accessed sanely above 32 bit width, |
| 2441 | * so we install an artificial 1<<31 period regardless of |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2442 | * the generic event period: |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 2443 | */ |
| 2444 | .max_period = (1ULL << 31) - 1, |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 2445 | .enable_bts = intel_pmu_enable_bts, |
| 2446 | .disable_bts = intel_pmu_disable_bts, |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2447 | .get_event_constraints = intel_get_event_constraints |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2448 | }; |
| 2449 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2450 | static __initconst struct x86_pmu amd_pmu = { |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 2451 | .name = "AMD", |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2452 | .handle_irq = x86_pmu_handle_irq, |
| 2453 | .disable_all = x86_pmu_disable_all, |
| 2454 | .enable_all = x86_pmu_enable_all, |
| 2455 | .enable = x86_pmu_enable_event, |
| 2456 | .disable = x86_pmu_disable_event, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2457 | .eventsel = MSR_K7_EVNTSEL0, |
| 2458 | .perfctr = MSR_K7_PERFCTR0, |
Robert Richter | 5f4ec28 | 2009-04-29 12:47:04 +0200 | [diff] [blame] | 2459 | .event_map = amd_pmu_event_map, |
| 2460 | .raw_event = amd_pmu_raw_event, |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2461 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2462 | .num_events = 4, |
| 2463 | .event_bits = 48, |
| 2464 | .event_mask = (1ULL << 48) - 1, |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2465 | .apic = 1, |
Robert Richter | c619b8f | 2009-04-29 12:47:23 +0200 | [diff] [blame] | 2466 | /* use highest bit to detect overflow */ |
| 2467 | .max_period = (1ULL << 47) - 1, |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2468 | .get_event_constraints = amd_get_event_constraints |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2469 | }; |
| 2470 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2471 | static __init int p6_pmu_init(void) |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2472 | { |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2473 | switch (boot_cpu_data.x86_model) { |
| 2474 | case 1: |
| 2475 | case 3: /* Pentium Pro */ |
| 2476 | case 5: |
| 2477 | case 6: /* Pentium II */ |
| 2478 | case 7: |
| 2479 | case 8: |
| 2480 | case 11: /* Pentium III */ |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2481 | case 9: |
| 2482 | case 13: |
Daniel Qarras | f1c6a58 | 2009-07-12 04:32:40 -0700 | [diff] [blame] | 2483 | /* Pentium M */ |
| 2484 | break; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2485 | default: |
| 2486 | pr_cont("unsupported p6 CPU model %d ", |
| 2487 | boot_cpu_data.x86_model); |
| 2488 | return -ENODEV; |
| 2489 | } |
| 2490 | |
Ingo Molnar | 04da8a4 | 2009-08-11 10:40:08 +0200 | [diff] [blame] | 2491 | x86_pmu = p6_pmu; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2492 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2493 | return 0; |
| 2494 | } |
| 2495 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2496 | static __init int intel_pmu_init(void) |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2497 | { |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 2498 | union cpuid10_edx edx; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 2499 | union cpuid10_eax eax; |
| 2500 | unsigned int unused; |
| 2501 | unsigned int ebx; |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 2502 | int version; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2503 | |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2504 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { |
| 2505 | /* check for P6 processor family */ |
| 2506 | if (boot_cpu_data.x86 == 6) { |
| 2507 | return p6_pmu_init(); |
| 2508 | } else { |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2509 | return -ENODEV; |
Vince Weaver | 11d1578 | 2009-07-08 17:46:14 -0400 | [diff] [blame] | 2510 | } |
| 2511 | } |
Robert Richter | da1a776 | 2009-04-29 12:46:58 +0200 | [diff] [blame] | 2512 | |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2513 | /* |
| 2514 | * Check whether the Architectural PerfMon supports |
Ingo Molnar | dfc6509 | 2009-09-21 11:31:35 +0200 | [diff] [blame] | 2515 | * Branch Misses Retired hw_event or not. |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2516 | */ |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 2517 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2518 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2519 | return -ENODEV; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2520 | |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 2521 | version = eax.split.version_id; |
| 2522 | if (version < 2) |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2523 | x86_pmu = core_pmu; |
| 2524 | else |
| 2525 | x86_pmu = intel_pmu; |
Ingo Molnar | 7bb497b | 2009-03-18 08:59:21 +0100 | [diff] [blame] | 2526 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2527 | x86_pmu.version = version; |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2528 | x86_pmu.num_events = eax.split.num_events; |
| 2529 | x86_pmu.event_bits = eax.split.bit_width; |
| 2530 | x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1; |
Ingo Molnar | 066d7de | 2009-05-04 19:04:09 +0200 | [diff] [blame] | 2531 | |
| 2532 | /* |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2533 | * Quirk: v2 perfmon does not report fixed-purpose events, so |
| 2534 | * assume at least 3 events: |
Ingo Molnar | 066d7de | 2009-05-04 19:04:09 +0200 | [diff] [blame] | 2535 | */ |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2536 | if (version > 1) |
| 2537 | x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2538 | |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2539 | /* |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2540 | * Install the hw-cache-events table: |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2541 | */ |
| 2542 | switch (boot_cpu_data.x86_model) { |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2543 | case 14: /* 65 nm core solo/duo, "Yonah" */ |
| 2544 | pr_cont("Core events, "); |
| 2545 | break; |
| 2546 | |
Yong Wang | dc81081 | 2009-06-10 17:06:12 +0800 | [diff] [blame] | 2547 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ |
| 2548 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ |
| 2549 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ |
| 2550 | case 29: /* six-core 45 nm xeon "Dunnington" */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2551 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 2552 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2553 | |
Peter Zijlstra | 8c48e44 | 2010-01-29 13:25:31 +0100 | [diff] [blame] | 2554 | x86_pmu.event_constraints = intel_core2_event_constraints; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2555 | pr_cont("Core2 events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2556 | break; |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 2557 | |
| 2558 | case 26: /* 45 nm nehalem, "Bloomfield" */ |
| 2559 | case 30: /* 45 nm nehalem, "Lynnfield" */ |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2560 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 2561 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2562 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2563 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2564 | pr_cont("Nehalem/Corei7 events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2565 | break; |
| 2566 | case 28: |
| 2567 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
Thomas Gleixner | 820a644 | 2009-06-08 19:10:25 +0200 | [diff] [blame] | 2568 | sizeof(hw_cache_event_ids)); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2569 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2570 | x86_pmu.event_constraints = intel_gen_event_constraints; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2571 | pr_cont("Atom events, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2572 | break; |
Peter Zijlstra | 452a339 | 2010-01-27 23:07:48 +0100 | [diff] [blame] | 2573 | |
| 2574 | case 37: /* 32 nm nehalem, "Clarkdale" */ |
| 2575 | case 44: /* 32 nm nehalem, "Gulftown" */ |
| 2576 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, |
| 2577 | sizeof(hw_cache_event_ids)); |
| 2578 | |
| 2579 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
| 2580 | pr_cont("Westmere events, "); |
| 2581 | break; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2582 | default: |
| 2583 | /* |
| 2584 | * default constraints for v2 and up |
| 2585 | */ |
| 2586 | x86_pmu.event_constraints = intel_gen_event_constraints; |
| 2587 | pr_cont("generic architected perfmon, "); |
Ingo Molnar | 8326f44 | 2009-06-05 20:22:46 +0200 | [diff] [blame] | 2588 | } |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2589 | return 0; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2590 | } |
| 2591 | |
Hiroshi Shimamoto | db48ccc | 2009-11-12 11:25:34 +0900 | [diff] [blame] | 2592 | static __init int amd_pmu_init(void) |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2593 | { |
Jaswinder Singh Rajput | 4d2be12 | 2009-06-11 15:28:09 +0530 | [diff] [blame] | 2594 | /* Performance-monitoring supported from K7 and later: */ |
| 2595 | if (boot_cpu_data.x86 < 6) |
| 2596 | return -ENODEV; |
| 2597 | |
Robert Richter | 4a06bd8 | 2009-04-29 12:47:11 +0200 | [diff] [blame] | 2598 | x86_pmu = amd_pmu; |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 2599 | |
Jaswinder Singh Rajput | f4db43a | 2009-06-13 01:06:21 +0530 | [diff] [blame] | 2600 | /* Events are common for all AMDs */ |
| 2601 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, |
| 2602 | sizeof(hw_cache_event_ids)); |
Thomas Gleixner | f86748e | 2009-06-08 22:33:10 +0200 | [diff] [blame] | 2603 | |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2604 | return 0; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2605 | } |
| 2606 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 2607 | static void __init pmu_check_apic(void) |
| 2608 | { |
| 2609 | if (cpu_has_apic) |
| 2610 | return; |
| 2611 | |
| 2612 | x86_pmu.apic = 0; |
| 2613 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 2614 | pr_info("no hardware sampling interrupt available.\n"); |
| 2615 | } |
| 2616 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2617 | void __init init_hw_perf_events(void) |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2618 | { |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2619 | int err; |
| 2620 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2621 | pr_info("Performance Events: "); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2622 | |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2623 | switch (boot_cpu_data.x86_vendor) { |
| 2624 | case X86_VENDOR_INTEL: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2625 | err = intel_pmu_init(); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2626 | break; |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2627 | case X86_VENDOR_AMD: |
Robert Richter | 72eae04 | 2009-04-29 12:47:10 +0200 | [diff] [blame] | 2628 | err = amd_pmu_init(); |
Jaswinder Singh Rajput | f87ad35 | 2009-02-27 20:15:14 +0530 | [diff] [blame] | 2629 | break; |
Robert Richter | 4138960 | 2009-04-29 12:47:00 +0200 | [diff] [blame] | 2630 | default: |
| 2631 | return; |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2632 | } |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2633 | if (err != 0) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2634 | pr_cont("no PMU driver, software events only.\n"); |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2635 | return; |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2636 | } |
Jaswinder Singh Rajput | b56a380 | 2009-02-27 18:09:09 +0530 | [diff] [blame] | 2637 | |
Cyrill Gorcunov | 1255803 | 2009-12-10 19:56:34 +0300 | [diff] [blame] | 2638 | pmu_check_apic(); |
| 2639 | |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2640 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
Robert Richter | faa28ae | 2009-04-29 12:47:13 +0200 | [diff] [blame] | 2641 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2642 | if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) { |
| 2643 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
| 2644 | x86_pmu.num_events, X86_PMC_MAX_GENERIC); |
| 2645 | x86_pmu.num_events = X86_PMC_MAX_GENERIC; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2646 | } |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2647 | perf_event_mask = (1 << x86_pmu.num_events) - 1; |
| 2648 | perf_max_events = x86_pmu.num_events; |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2649 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2650 | if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) { |
| 2651 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
| 2652 | x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED); |
| 2653 | x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED; |
Ingo Molnar | 703e937 | 2008-12-17 10:51:15 +0100 | [diff] [blame] | 2654 | } |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2655 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2656 | perf_event_mask |= |
| 2657 | ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED; |
| 2658 | x86_pmu.intel_ctrl = perf_event_mask; |
Ingo Molnar | 862a1a5 | 2008-12-17 13:09:20 +0100 | [diff] [blame] | 2659 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2660 | perf_events_lapic_init(); |
| 2661 | register_die_notifier(&perf_event_nmi_notifier); |
Ingo Molnar | 1123e3a | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2662 | |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2663 | unconstrained = (struct event_constraint) |
Peter Zijlstra | fce877e | 2010-01-29 13:25:12 +0100 | [diff] [blame] | 2664 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, |
| 2665 | 0, x86_pmu.num_events); |
Peter Zijlstra | 63b1464 | 2010-01-22 16:32:17 +0100 | [diff] [blame] | 2666 | |
Ingo Molnar | 57c0c15 | 2009-09-21 12:20:38 +0200 | [diff] [blame] | 2667 | pr_info("... version: %d\n", x86_pmu.version); |
| 2668 | pr_info("... bit width: %d\n", x86_pmu.event_bits); |
| 2669 | pr_info("... generic registers: %d\n", x86_pmu.num_events); |
| 2670 | pr_info("... value mask: %016Lx\n", x86_pmu.event_mask); |
| 2671 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
| 2672 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed); |
| 2673 | pr_info("... event mask: %016Lx\n", perf_event_mask); |
Ingo Molnar | 241771e | 2008-12-03 10:39:53 +0100 | [diff] [blame] | 2674 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2675 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2676 | static inline void x86_pmu_read(struct perf_event *event) |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 2677 | { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2678 | x86_perf_event_update(event, &event->hw, event->hw.idx); |
Ingo Molnar | ee06094 | 2008-12-13 09:00:03 +0100 | [diff] [blame] | 2679 | } |
| 2680 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 2681 | static const struct pmu pmu = { |
| 2682 | .enable = x86_pmu_enable, |
| 2683 | .disable = x86_pmu_disable, |
Stephane Eranian | d76a081 | 2010-02-08 17:06:01 +0200 | [diff] [blame^] | 2684 | .start = x86_pmu_start, |
| 2685 | .stop = x86_pmu_stop, |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 2686 | .read = x86_pmu_read, |
Peter Zijlstra | a78ac32 | 2009-05-25 17:39:05 +0200 | [diff] [blame] | 2687 | .unthrottle = x86_pmu_unthrottle, |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2688 | }; |
| 2689 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2690 | /* |
| 2691 | * validate a single event group |
| 2692 | * |
| 2693 | * validation include: |
Ingo Molnar | 184f412 | 2010-01-27 08:39:39 +0100 | [diff] [blame] | 2694 | * - check events are compatible which each other |
| 2695 | * - events do not compete for the same counter |
| 2696 | * - number of events <= number of counters |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2697 | * |
| 2698 | * validation ensures the group can be loaded onto the |
| 2699 | * PMU if it was the only group available. |
| 2700 | */ |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2701 | static int validate_group(struct perf_event *event) |
| 2702 | { |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2703 | struct perf_event *leader = event->group_leader; |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2704 | struct cpu_hw_events *fake_cpuc; |
| 2705 | int ret, n; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2706 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2707 | ret = -ENOMEM; |
| 2708 | fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO); |
| 2709 | if (!fake_cpuc) |
| 2710 | goto out; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2711 | |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2712 | /* |
| 2713 | * the event is not yet connected with its |
| 2714 | * siblings therefore we must first collect |
| 2715 | * existing siblings, then add the new event |
| 2716 | * before we can simulate the scheduling |
| 2717 | */ |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2718 | ret = -ENOSPC; |
| 2719 | n = collect_events(fake_cpuc, leader, true); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2720 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2721 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2722 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2723 | fake_cpuc->n_events = n; |
| 2724 | n = collect_events(fake_cpuc, event, false); |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2725 | if (n < 0) |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2726 | goto out_free; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2727 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2728 | fake_cpuc->n_events = n; |
Stephane Eranian | 1da53e0 | 2010-01-18 10:58:01 +0200 | [diff] [blame] | 2729 | |
Peter Zijlstra | 502568d | 2010-01-22 14:35:46 +0100 | [diff] [blame] | 2730 | ret = x86_schedule_events(fake_cpuc, n, NULL); |
| 2731 | |
| 2732 | out_free: |
| 2733 | kfree(fake_cpuc); |
| 2734 | out: |
| 2735 | return ret; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2736 | } |
| 2737 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2738 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2739 | { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 2740 | const struct pmu *tmp; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2741 | int err; |
| 2742 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2743 | err = __hw_perf_event_init(event); |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2744 | if (!err) { |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 2745 | /* |
| 2746 | * we temporarily connect event to its pmu |
| 2747 | * such that validate_group() can classify |
| 2748 | * it as an x86 event using is_x86_event() |
| 2749 | */ |
| 2750 | tmp = event->pmu; |
| 2751 | event->pmu = &pmu; |
| 2752 | |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2753 | if (event->group_leader != event) |
| 2754 | err = validate_group(event); |
Stephane Eranian | 8113070 | 2010-01-21 17:39:01 +0200 | [diff] [blame] | 2755 | |
| 2756 | event->pmu = tmp; |
Peter Zijlstra | fe9081c | 2009-10-08 11:56:07 +0200 | [diff] [blame] | 2757 | } |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 2758 | if (err) { |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2759 | if (event->destroy) |
| 2760 | event->destroy(event); |
Peter Zijlstra | 9ea98e1 | 2009-03-30 19:07:09 +0200 | [diff] [blame] | 2761 | return ERR_PTR(err); |
Peter Zijlstra | a1792cdac | 2009-09-09 10:04:47 +0200 | [diff] [blame] | 2762 | } |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2763 | |
Robert Richter | 4aeb0b4 | 2009-04-29 12:47:03 +0200 | [diff] [blame] | 2764 | return &pmu; |
Ingo Molnar | 621a01e | 2008-12-11 12:46:46 +0100 | [diff] [blame] | 2765 | } |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2766 | |
| 2767 | /* |
| 2768 | * callchain support |
| 2769 | */ |
| 2770 | |
| 2771 | static inline |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2772 | void callchain_store(struct perf_callchain_entry *entry, u64 ip) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2773 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2774 | if (entry->nr < PERF_MAX_STACK_DEPTH) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2775 | entry->ip[entry->nr++] = ip; |
| 2776 | } |
| 2777 | |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 2778 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry); |
| 2779 | static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2780 | |
| 2781 | |
| 2782 | static void |
| 2783 | backtrace_warning_symbol(void *data, char *msg, unsigned long symbol) |
| 2784 | { |
| 2785 | /* Ignore warnings */ |
| 2786 | } |
| 2787 | |
| 2788 | static void backtrace_warning(void *data, char *msg) |
| 2789 | { |
| 2790 | /* Ignore warnings */ |
| 2791 | } |
| 2792 | |
| 2793 | static int backtrace_stack(void *data, char *name) |
| 2794 | { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2795 | return 0; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2796 | } |
| 2797 | |
| 2798 | static void backtrace_address(void *data, unsigned long addr, int reliable) |
| 2799 | { |
| 2800 | struct perf_callchain_entry *entry = data; |
| 2801 | |
| 2802 | if (reliable) |
| 2803 | callchain_store(entry, addr); |
| 2804 | } |
| 2805 | |
| 2806 | static const struct stacktrace_ops backtrace_ops = { |
| 2807 | .warning = backtrace_warning, |
| 2808 | .warning_symbol = backtrace_warning_symbol, |
| 2809 | .stack = backtrace_stack, |
| 2810 | .address = backtrace_address, |
Frederic Weisbecker | 06d65bd | 2009-12-17 05:40:34 +0100 | [diff] [blame] | 2811 | .walk_stack = print_context_stack_bp, |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2812 | }; |
| 2813 | |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2814 | #include "../dumpstack.h" |
| 2815 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2816 | static void |
| 2817 | perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 2818 | { |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2819 | callchain_store(entry, PERF_CONTEXT_KERNEL); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2820 | callchain_store(entry, regs->ip); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2821 | |
Frederic Weisbecker | 48b5ba9 | 2009-12-31 05:53:02 +0100 | [diff] [blame] | 2822 | dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2823 | } |
| 2824 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2825 | /* |
| 2826 | * best effort, GUP based copy_from_user() that assumes IRQ or NMI context |
| 2827 | */ |
| 2828 | static unsigned long |
| 2829 | copy_from_user_nmi(void *to, const void __user *from, unsigned long n) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2830 | { |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2831 | unsigned long offset, addr = (unsigned long)from; |
| 2832 | int type = in_nmi() ? KM_NMI : KM_IRQ0; |
| 2833 | unsigned long size, len = 0; |
| 2834 | struct page *page; |
| 2835 | void *map; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2836 | int ret; |
| 2837 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2838 | do { |
| 2839 | ret = __get_user_pages_fast(addr, 1, 0, &page); |
| 2840 | if (!ret) |
| 2841 | break; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2842 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2843 | offset = addr & (PAGE_SIZE - 1); |
| 2844 | size = min(PAGE_SIZE - offset, n - len); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2845 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2846 | map = kmap_atomic(page, type); |
| 2847 | memcpy(to, map+offset, size); |
| 2848 | kunmap_atomic(map, type); |
| 2849 | put_page(page); |
| 2850 | |
| 2851 | len += size; |
| 2852 | to += size; |
| 2853 | addr += size; |
| 2854 | |
| 2855 | } while (len < n); |
| 2856 | |
| 2857 | return len; |
| 2858 | } |
| 2859 | |
| 2860 | static int copy_stack_frame(const void __user *fp, struct stack_frame *frame) |
| 2861 | { |
| 2862 | unsigned long bytes; |
| 2863 | |
| 2864 | bytes = copy_from_user_nmi(frame, fp, sizeof(*frame)); |
| 2865 | |
| 2866 | return bytes == sizeof(*frame); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2867 | } |
| 2868 | |
| 2869 | static void |
| 2870 | perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 2871 | { |
| 2872 | struct stack_frame frame; |
| 2873 | const void __user *fp; |
| 2874 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2875 | if (!user_mode(regs)) |
| 2876 | regs = task_pt_regs(current); |
| 2877 | |
Peter Zijlstra | 74193ef | 2009-06-15 13:07:24 +0200 | [diff] [blame] | 2878 | fp = (void __user *)regs->bp; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2879 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2880 | callchain_store(entry, PERF_CONTEXT_USER); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2881 | callchain_store(entry, regs->ip); |
| 2882 | |
Peter Zijlstra | f9188e0 | 2009-06-18 22:20:52 +0200 | [diff] [blame] | 2883 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2884 | frame.next_frame = NULL; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2885 | frame.return_address = 0; |
| 2886 | |
| 2887 | if (!copy_stack_frame(fp, &frame)) |
| 2888 | break; |
| 2889 | |
Ingo Molnar | 5a6cec3 | 2009-05-29 11:25:09 +0200 | [diff] [blame] | 2890 | if ((unsigned long)fp < regs->sp) |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2891 | break; |
| 2892 | |
| 2893 | callchain_store(entry, frame.return_address); |
Ingo Molnar | 038e836 | 2009-06-15 09:57:59 +0200 | [diff] [blame] | 2894 | fp = frame.next_frame; |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2895 | } |
| 2896 | } |
| 2897 | |
| 2898 | static void |
| 2899 | perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry) |
| 2900 | { |
| 2901 | int is_user; |
| 2902 | |
| 2903 | if (!regs) |
| 2904 | return; |
| 2905 | |
| 2906 | is_user = user_mode(regs); |
| 2907 | |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2908 | if (is_user && current->state != TASK_RUNNING) |
| 2909 | return; |
| 2910 | |
| 2911 | if (!is_user) |
| 2912 | perf_callchain_kernel(regs, entry); |
| 2913 | |
| 2914 | if (current->mm) |
| 2915 | perf_callchain_user(regs, entry); |
| 2916 | } |
| 2917 | |
| 2918 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) |
| 2919 | { |
| 2920 | struct perf_callchain_entry *entry; |
| 2921 | |
| 2922 | if (in_nmi()) |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 2923 | entry = &__get_cpu_var(pmc_nmi_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2924 | else |
Tejun Heo | 245b2e7 | 2009-06-24 15:13:48 +0900 | [diff] [blame] | 2925 | entry = &__get_cpu_var(pmc_irq_entry); |
Peter Zijlstra | d7d59fb | 2009-03-30 19:07:15 +0200 | [diff] [blame] | 2926 | |
| 2927 | entry->nr = 0; |
| 2928 | |
| 2929 | perf_do_callchain(regs, entry); |
| 2930 | |
| 2931 | return entry; |
| 2932 | } |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 2933 | |
Ingo Molnar | cdd6c48 | 2009-09-21 12:02:48 +0200 | [diff] [blame] | 2934 | void hw_perf_event_setup_online(int cpu) |
Markus Metzger | 30dd568 | 2009-07-21 15:56:48 +0200 | [diff] [blame] | 2935 | { |
| 2936 | init_debug_store_on_cpu(cpu); |
| 2937 | } |