Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ahci.c - AHCI SATA support |
| 3 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 8 | * Copyright 2004-2005 Red Hat, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | * |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2, or (at your option) |
| 14 | * any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; see the file COPYING. If not, write to |
| 23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 24 | * |
| 25 | * |
| 26 | * libata documentation is available via 'make {ps|pdf}docs', |
| 27 | * as Documentation/DocBook/libata.* |
| 28 | * |
| 29 | * AHCI hardware documentation: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | * |
| 33 | */ |
| 34 | |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/init.h> |
| 39 | #include <linux/blkdev.h> |
| 40 | #include <linux/delay.h> |
| 41 | #include <linux/interrupt.h> |
| 42 | #include <linux/sched.h> |
domen@coderock.org | 87507cf | 2005-04-08 09:53:06 +0200 | [diff] [blame] | 43 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 44 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 46 | #include <scsi/scsi_cmnd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | #include <linux/libata.h> |
| 48 | #include <asm/io.h> |
| 49 | |
| 50 | #define DRV_NAME "ahci" |
Jeff Garzik | 8676ce0 | 2006-06-26 20:41:33 -0400 | [diff] [blame] | 51 | #define DRV_VERSION "2.0" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | |
| 53 | |
| 54 | enum { |
| 55 | AHCI_PCI_BAR = 5, |
| 56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
| 57 | AHCI_DMA_BOUNDARY = 0xffffffff, |
| 58 | AHCI_USE_CLUSTERING = 0, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 59 | AHCI_MAX_CMDS = 32, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 60 | AHCI_CMD_SZ = 32, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 61 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | AHCI_RX_FIS_SZ = 256, |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 63 | AHCI_CMD_TBL_CDB = 0x40, |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 64 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
| 65 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), |
| 66 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, |
| 67 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | AHCI_RX_FIS_SZ, |
| 69 | AHCI_IRQ_ON_SG = (1 << 31), |
| 70 | AHCI_CMD_ATAPI = (1 << 5), |
| 71 | AHCI_CMD_WRITE = (1 << 6), |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 72 | AHCI_CMD_PREFETCH = (1 << 7), |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 73 | AHCI_CMD_RESET = (1 << 8), |
| 74 | AHCI_CMD_CLR_BUSY = (1 << 10), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | |
| 76 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 77 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | |
| 79 | board_ahci = 0, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 80 | board_ahci_vt8251 = 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
| 82 | /* global controller registers */ |
| 83 | HOST_CAP = 0x00, /* host capabilities */ |
| 84 | HOST_CTL = 0x04, /* global host control */ |
| 85 | HOST_IRQ_STAT = 0x08, /* interrupt status */ |
| 86 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ |
| 87 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ |
| 88 | |
| 89 | /* HOST_CTL bits */ |
| 90 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ |
| 91 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ |
| 92 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ |
| 93 | |
| 94 | /* HOST_CAP bits */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 95 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
Tejun Heo | 979db80 | 2006-05-15 21:03:52 +0900 | [diff] [blame] | 96 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
Tejun Heo | dd410ff | 2006-05-15 21:03:50 +0900 | [diff] [blame] | 97 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | |
| 99 | /* registers for each SATA port */ |
| 100 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ |
| 101 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ |
| 102 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ |
| 103 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ |
| 104 | PORT_IRQ_STAT = 0x10, /* interrupt status */ |
| 105 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ |
| 106 | PORT_CMD = 0x18, /* port command */ |
| 107 | PORT_TFDATA = 0x20, /* taskfile data */ |
| 108 | PORT_SIG = 0x24, /* device TF signature */ |
| 109 | PORT_CMD_ISSUE = 0x38, /* command issue */ |
| 110 | PORT_SCR = 0x28, /* SATA phy register block */ |
| 111 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ |
| 112 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ |
| 113 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ |
| 114 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ |
| 115 | |
| 116 | /* PORT_IRQ_{STAT,MASK} bits */ |
| 117 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ |
| 118 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ |
| 119 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ |
| 120 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ |
| 121 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ |
| 122 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ |
| 123 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ |
| 124 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ |
| 125 | |
| 126 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ |
| 127 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ |
| 128 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ |
| 129 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ |
| 130 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ |
| 131 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ |
| 132 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ |
| 133 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ |
| 134 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ |
| 135 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 136 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
| 137 | PORT_IRQ_IF_ERR | |
| 138 | PORT_IRQ_CONNECT | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 139 | PORT_IRQ_PHYRDY | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 140 | PORT_IRQ_UNK_FIS, |
| 141 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | |
| 142 | PORT_IRQ_TF_ERR | |
| 143 | PORT_IRQ_HBUS_DATA_ERR, |
| 144 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | |
| 145 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | |
| 146 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | |
| 148 | /* PORT_CMD bits */ |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 149 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
| 151 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ |
| 152 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ |
Tejun Heo | 22b4998 | 2006-01-23 21:38:44 +0900 | [diff] [blame] | 153 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
| 155 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ |
| 156 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ |
| 157 | |
| 158 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
| 159 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ |
| 160 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 161 | |
| 162 | /* hpriv->flags bits */ |
| 163 | AHCI_FLAG_MSI = (1 << 0), |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 164 | |
| 165 | /* ap->flags bits */ |
| 166 | AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24), |
Tejun Heo | 71f0737 | 2006-06-21 23:12:48 +0900 | [diff] [blame] | 167 | AHCI_FLAG_NO_NCQ = (1 << 25), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | struct ahci_cmd_hdr { |
| 171 | u32 opts; |
| 172 | u32 status; |
| 173 | u32 tbl_addr; |
| 174 | u32 tbl_addr_hi; |
| 175 | u32 reserved[4]; |
| 176 | }; |
| 177 | |
| 178 | struct ahci_sg { |
| 179 | u32 addr; |
| 180 | u32 addr_hi; |
| 181 | u32 reserved; |
| 182 | u32 flags_size; |
| 183 | }; |
| 184 | |
| 185 | struct ahci_host_priv { |
| 186 | unsigned long flags; |
| 187 | u32 cap; /* cache of HOST_CAP register */ |
| 188 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ |
| 189 | }; |
| 190 | |
| 191 | struct ahci_port_priv { |
| 192 | struct ahci_cmd_hdr *cmd_slot; |
| 193 | dma_addr_t cmd_slot_dma; |
| 194 | void *cmd_tbl; |
| 195 | dma_addr_t cmd_tbl_dma; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 196 | void *rx_fis; |
| 197 | dma_addr_t rx_fis_dma; |
| 198 | }; |
| 199 | |
| 200 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); |
| 201 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); |
| 202 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 203 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 205 | static void ahci_irq_clear(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 206 | static int ahci_port_start(struct ata_port *ap); |
| 207 | static void ahci_port_stop(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 208 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
| 209 | static void ahci_qc_prep(struct ata_queued_cmd *qc); |
| 210 | static u8 ahci_check_status(struct ata_port *ap); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 211 | static void ahci_freeze(struct ata_port *ap); |
| 212 | static void ahci_thaw(struct ata_port *ap); |
| 213 | static void ahci_error_handler(struct ata_port *ap); |
| 214 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 215 | static void ahci_remove_one (struct pci_dev *pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 217 | static struct scsi_host_template ahci_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | .module = THIS_MODULE, |
| 219 | .name = DRV_NAME, |
| 220 | .ioctl = ata_scsi_ioctl, |
| 221 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 222 | .change_queue_depth = ata_scsi_change_queue_depth, |
| 223 | .can_queue = AHCI_MAX_CMDS - 1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | .this_id = ATA_SHT_THIS_ID, |
| 225 | .sg_tablesize = AHCI_MAX_SG, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 226 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 227 | .emulated = ATA_SHT_EMULATED, |
| 228 | .use_clustering = AHCI_USE_CLUSTERING, |
| 229 | .proc_name = DRV_NAME, |
| 230 | .dma_boundary = AHCI_DMA_BOUNDARY, |
| 231 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 232 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | .bios_param = ata_std_bios_param, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | }; |
| 235 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 236 | static const struct ata_port_operations ahci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | .port_disable = ata_port_disable, |
| 238 | |
| 239 | .check_status = ahci_check_status, |
| 240 | .check_altstatus = ahci_check_status, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | .dev_select = ata_noop_dev_select, |
| 242 | |
| 243 | .tf_read = ahci_tf_read, |
| 244 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | .qc_prep = ahci_qc_prep, |
| 246 | .qc_issue = ahci_qc_issue, |
| 247 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 248 | .irq_handler = ahci_interrupt, |
| 249 | .irq_clear = ahci_irq_clear, |
| 250 | |
| 251 | .scr_read = ahci_scr_read, |
| 252 | .scr_write = ahci_scr_write, |
| 253 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 254 | .freeze = ahci_freeze, |
| 255 | .thaw = ahci_thaw, |
| 256 | |
| 257 | .error_handler = ahci_error_handler, |
| 258 | .post_internal_cmd = ahci_post_internal_cmd, |
| 259 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | .port_start = ahci_port_start, |
| 261 | .port_stop = ahci_port_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | }; |
| 263 | |
Arjan van de Ven | 98ac62d | 2005-11-28 10:06:23 +0100 | [diff] [blame] | 264 | static const struct ata_port_info ahci_port_info[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | /* board_ahci */ |
| 266 | { |
| 267 | .sht = &ahci_sht, |
| 268 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 269 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 270 | ATA_FLAG_SKIP_D2H_BSY, |
Brett Russ | 7da7931 | 2005-09-01 21:53:34 -0400 | [diff] [blame] | 271 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 273 | .port_ops = &ahci_ops, |
| 274 | }, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 275 | /* board_ahci_vt8251 */ |
| 276 | { |
| 277 | .sht = &ahci_sht, |
| 278 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
| 279 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 280 | ATA_FLAG_SKIP_D2H_BSY | |
Tejun Heo | 71f0737 | 2006-06-21 23:12:48 +0900 | [diff] [blame] | 281 | AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ, |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 282 | .pio_mask = 0x1f, /* pio0-4 */ |
| 283 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 284 | .port_ops = &ahci_ops, |
| 285 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | }; |
| 287 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 288 | static const struct pci_device_id ahci_pci_tbl[] = { |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 289 | /* Intel */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 290 | { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 291 | board_ahci }, /* ICH6 */ |
| 292 | { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 293 | board_ahci }, /* ICH6M */ |
| 294 | { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 295 | board_ahci }, /* ICH7 */ |
| 296 | { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 297 | board_ahci }, /* ICH7M */ |
| 298 | { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 299 | board_ahci }, /* ICH7R */ |
| 300 | { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 301 | board_ahci }, /* ULi M5288 */ |
Jason Gaston | 680d323 | 2005-04-16 15:24:45 -0700 | [diff] [blame] | 302 | { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 303 | board_ahci }, /* ESB2 */ |
| 304 | { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 305 | board_ahci }, /* ESB2 */ |
| 306 | { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 307 | board_ahci }, /* ESB2 */ |
Jason Gaston | 3db368f | 2005-08-10 06:18:43 -0700 | [diff] [blame] | 308 | { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 309 | board_ahci }, /* ICH7-M DH */ |
Jason Gaston | f285757 | 2006-01-09 11:09:13 -0800 | [diff] [blame] | 310 | { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 311 | board_ahci }, /* ICH8 */ |
| 312 | { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 313 | board_ahci }, /* ICH8 */ |
| 314 | { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 315 | board_ahci }, /* ICH8 */ |
| 316 | { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 317 | board_ahci }, /* ICH8M */ |
| 318 | { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 319 | board_ahci }, /* ICH8M */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 320 | |
| 321 | /* JMicron */ |
Jeff Garzik | bd12097 | 2006-01-29 02:47:03 -0500 | [diff] [blame] | 322 | { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 323 | board_ahci }, /* JMicron JMB360 */ |
Jeff Garzik | 8fa29b2 | 2006-06-22 23:19:15 -0400 | [diff] [blame] | 324 | { 0x197b, 0x2361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 325 | board_ahci }, /* JMicron JMB361 */ |
Jeff Garzik | 9220a2d | 2006-01-29 12:40:57 -0500 | [diff] [blame] | 326 | { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 327 | board_ahci }, /* JMicron JMB363 */ |
Jeff Garzik | 8fa29b2 | 2006-06-22 23:19:15 -0400 | [diff] [blame] | 328 | { 0x197b, 0x2365, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 329 | board_ahci }, /* JMicron JMB365 */ |
| 330 | { 0x197b, 0x2366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 331 | board_ahci }, /* JMicron JMB366 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 332 | |
| 333 | /* ATI */ |
Jeff Garzik | 8b316a3 | 2006-03-30 17:07:32 -0500 | [diff] [blame] | 334 | { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 335 | board_ahci }, /* ATI SB600 non-raid */ |
| 336 | { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 337 | board_ahci }, /* ATI SB600 raid */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 338 | |
| 339 | /* VIA */ |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 340 | { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 341 | board_ahci_vt8251 }, /* VIA VT8251 */ |
Jeff Garzik | fe7fa31 | 2006-06-22 23:05:36 -0400 | [diff] [blame] | 342 | |
| 343 | /* NVIDIA */ |
| 344 | { PCI_VENDOR_ID_NVIDIA, 0x044c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 345 | board_ahci }, /* MCP65 */ |
| 346 | { PCI_VENDOR_ID_NVIDIA, 0x044d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 347 | board_ahci }, /* MCP65 */ |
| 348 | { PCI_VENDOR_ID_NVIDIA, 0x044e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 349 | board_ahci }, /* MCP65 */ |
| 350 | { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
| 351 | board_ahci }, /* MCP65 */ |
| 352 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | { } /* terminate list */ |
| 354 | }; |
| 355 | |
| 356 | |
| 357 | static struct pci_driver ahci_pci_driver = { |
| 358 | .name = DRV_NAME, |
| 359 | .id_table = ahci_pci_tbl, |
| 360 | .probe = ahci_init_one, |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 361 | .remove = ahci_remove_one, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 362 | }; |
| 363 | |
| 364 | |
| 365 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) |
| 366 | { |
| 367 | return base + 0x100 + (port * 0x80); |
| 368 | } |
| 369 | |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 370 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 372 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | } |
| 374 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
| 376 | { |
| 377 | unsigned int sc_reg; |
| 378 | |
| 379 | switch (sc_reg_in) { |
| 380 | case SCR_STATUS: sc_reg = 0; break; |
| 381 | case SCR_CONTROL: sc_reg = 1; break; |
| 382 | case SCR_ERROR: sc_reg = 2; break; |
| 383 | case SCR_ACTIVE: sc_reg = 3; break; |
| 384 | default: |
| 385 | return 0xffffffffU; |
| 386 | } |
| 387 | |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 388 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | } |
| 390 | |
| 391 | |
| 392 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, |
| 393 | u32 val) |
| 394 | { |
| 395 | unsigned int sc_reg; |
| 396 | |
| 397 | switch (sc_reg_in) { |
| 398 | case SCR_STATUS: sc_reg = 0; break; |
| 399 | case SCR_CONTROL: sc_reg = 1; break; |
| 400 | case SCR_ERROR: sc_reg = 2; break; |
| 401 | case SCR_ACTIVE: sc_reg = 3; break; |
| 402 | default: |
| 403 | return; |
| 404 | } |
| 405 | |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 406 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | } |
| 408 | |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 409 | static int ahci_start_engine(void __iomem *port_mmio) |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 410 | { |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 411 | u32 tmp; |
| 412 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 413 | /* get current status */ |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 414 | tmp = readl(port_mmio + PORT_CMD); |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 415 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 416 | /* AHCI rev 1.1 section 10.3.1: |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 417 | * Software shall not set PxCMD.ST to '1' until it verifies |
| 418 | * that PxCMD.CR is '0' and has set PxCMD.FRE to '1' |
| 419 | */ |
| 420 | if ((tmp & PORT_CMD_FIS_RX) == 0) |
| 421 | return -EPERM; |
| 422 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 423 | /* wait for engine to become idle */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 424 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 425 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1,500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 426 | if (tmp & PORT_CMD_LIST_ON) |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 427 | return -EBUSY; |
| 428 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 429 | /* start DMA */ |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 430 | tmp |= PORT_CMD_START; |
| 431 | writel(tmp, port_mmio + PORT_CMD); |
| 432 | readl(port_mmio + PORT_CMD); /* flush */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 433 | |
| 434 | return 0; |
Tejun Heo | 7c76d1e | 2005-12-19 22:36:34 +0900 | [diff] [blame] | 435 | } |
| 436 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 437 | static int ahci_stop_engine(void __iomem *port_mmio) |
| 438 | { |
| 439 | u32 tmp; |
| 440 | |
| 441 | tmp = readl(port_mmio + PORT_CMD); |
| 442 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 443 | /* check if the HBA is idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 444 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
| 445 | return 0; |
| 446 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 447 | /* setting HBA to idle */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 448 | tmp &= ~PORT_CMD_START; |
| 449 | writel(tmp, port_mmio + PORT_CMD); |
| 450 | |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 451 | /* wait for engine to stop. This could be as long as 500 msec */ |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 452 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 453 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); |
Tejun Heo | d8fcd11 | 2006-07-26 15:59:25 +0900 | [diff] [blame^] | 454 | if (tmp & PORT_CMD_LIST_ON) |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 455 | return -EIO; |
| 456 | |
| 457 | return 0; |
| 458 | } |
| 459 | |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 460 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | { |
| 462 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
| 463 | struct ata_taskfile tf; |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 464 | u32 tmp; |
| 465 | |
| 466 | tmp = readl(port_mmio + PORT_SIG); |
| 467 | tf.lbah = (tmp >> 24) & 0xff; |
| 468 | tf.lbam = (tmp >> 16) & 0xff; |
| 469 | tf.lbal = (tmp >> 8) & 0xff; |
| 470 | tf.nsect = (tmp) & 0xff; |
| 471 | |
| 472 | return ata_dev_classify(&tf); |
| 473 | } |
| 474 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 475 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
| 476 | u32 opts) |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 477 | { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 478 | dma_addr_t cmd_tbl_dma; |
| 479 | |
| 480 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; |
| 481 | |
| 482 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); |
| 483 | pp->cmd_slot[tag].status = 0; |
| 484 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); |
| 485 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 486 | } |
| 487 | |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 488 | static int ahci_clo(struct ata_port *ap) |
| 489 | { |
| 490 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
| 491 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
| 492 | u32 tmp; |
| 493 | |
| 494 | if (!(hpriv->cap & HOST_CAP_CLO)) |
| 495 | return -EOPNOTSUPP; |
| 496 | |
| 497 | tmp = readl(port_mmio + PORT_CMD); |
| 498 | tmp |= PORT_CMD_CLO; |
| 499 | writel(tmp, port_mmio + PORT_CMD); |
| 500 | |
| 501 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
| 502 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); |
| 503 | if (tmp & PORT_CMD_CLO) |
| 504 | return -EIO; |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 509 | static int ahci_prereset(struct ata_port *ap) |
| 510 | { |
| 511 | if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) && |
| 512 | (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) { |
| 513 | /* ATA_BUSY hasn't cleared, so send a CLO */ |
| 514 | ahci_clo(ap); |
| 515 | } |
| 516 | |
| 517 | return ata_std_prereset(ap); |
| 518 | } |
| 519 | |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 520 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 521 | { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 522 | struct ahci_port_priv *pp = ap->private_data; |
| 523 | void __iomem *mmio = ap->host_set->mmio_base; |
| 524 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 525 | const u32 cmd_fis_len = 5; /* five dwords */ |
| 526 | const char *reason = NULL; |
| 527 | struct ata_taskfile tf; |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 528 | u32 tmp; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 529 | u8 *fis; |
| 530 | int rc; |
| 531 | |
| 532 | DPRINTK("ENTER\n"); |
| 533 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 534 | if (ata_port_offline(ap)) { |
Tejun Heo | c2a6585 | 2006-04-03 01:58:06 +0900 | [diff] [blame] | 535 | DPRINTK("PHY reports no device\n"); |
| 536 | *class = ATA_DEV_NONE; |
| 537 | return 0; |
| 538 | } |
| 539 | |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 540 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 541 | rc = ahci_stop_engine(port_mmio); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 542 | if (rc) { |
| 543 | reason = "failed to stop engine"; |
| 544 | goto fail_restart; |
| 545 | } |
| 546 | |
| 547 | /* check BUSY/DRQ, perform Command List Override if necessary */ |
| 548 | ahci_tf_read(ap, &tf); |
| 549 | if (tf.command & (ATA_BUSY | ATA_DRQ)) { |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 550 | rc = ahci_clo(ap); |
| 551 | |
| 552 | if (rc == -EOPNOTSUPP) { |
| 553 | reason = "port busy but CLO unavailable"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 554 | goto fail_restart; |
Bastiaan Jacques | bf2af2a | 2006-04-17 14:17:59 +0200 | [diff] [blame] | 555 | } else if (rc) { |
| 556 | reason = "port busy but CLO failed"; |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 557 | goto fail_restart; |
| 558 | } |
| 559 | } |
| 560 | |
| 561 | /* restart engine */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 562 | ahci_start_engine(port_mmio); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 563 | |
Tejun Heo | 3373efd | 2006-05-15 20:57:53 +0900 | [diff] [blame] | 564 | ata_tf_init(ap->device, &tf); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 565 | fis = pp->cmd_tbl; |
| 566 | |
| 567 | /* issue the first D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 568 | ahci_fill_cmd_slot(pp, 0, |
| 569 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 570 | |
| 571 | tf.ctl |= ATA_SRST; |
| 572 | ata_tf_to_fis(&tf, fis, 0); |
| 573 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 574 | |
| 575 | writel(1, port_mmio + PORT_CMD_ISSUE); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 576 | |
Tejun Heo | 75fe180 | 2006-04-11 22:22:29 +0900 | [diff] [blame] | 577 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
| 578 | if (tmp & 0x1) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 579 | rc = -EIO; |
| 580 | reason = "1st FIS failed"; |
| 581 | goto fail; |
| 582 | } |
| 583 | |
| 584 | /* spec says at least 5us, but be generous and sleep for 1ms */ |
| 585 | msleep(1); |
| 586 | |
| 587 | /* issue the second D2H Register FIS */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 588 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 589 | |
| 590 | tf.ctl &= ~ATA_SRST; |
| 591 | ata_tf_to_fis(&tf, fis, 0); |
| 592 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ |
| 593 | |
| 594 | writel(1, port_mmio + PORT_CMD_ISSUE); |
| 595 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 596 | |
| 597 | /* spec mandates ">= 2ms" before checking status. |
| 598 | * We wait 150ms, because that was the magic delay used for |
| 599 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time |
| 600 | * between when the ATA command register is written, and then |
| 601 | * status is checked. Because waiting for "a while" before |
| 602 | * checking status is fine, post SRST, we perform this magic |
| 603 | * delay here as well. |
| 604 | */ |
| 605 | msleep(150); |
| 606 | |
| 607 | *class = ATA_DEV_NONE; |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 608 | if (ata_port_online(ap)) { |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 609 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
| 610 | rc = -EIO; |
| 611 | reason = "device not ready"; |
| 612 | goto fail; |
| 613 | } |
| 614 | *class = ahci_dev_classify(ap); |
| 615 | } |
| 616 | |
| 617 | DPRINTK("EXIT, class=%u\n", *class); |
| 618 | return 0; |
| 619 | |
| 620 | fail_restart: |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 621 | ahci_start_engine(port_mmio); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 622 | fail: |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 623 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
Tejun Heo | 4658f79 | 2006-03-22 21:07:03 +0900 | [diff] [blame] | 624 | return rc; |
| 625 | } |
| 626 | |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 627 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
Tejun Heo | 422b759 | 2005-12-19 22:37:17 +0900 | [diff] [blame] | 628 | { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 629 | struct ahci_port_priv *pp = ap->private_data; |
| 630 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 631 | struct ata_taskfile tf; |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 632 | void __iomem *mmio = ap->host_set->mmio_base; |
| 633 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 634 | int rc; |
| 635 | |
| 636 | DPRINTK("ENTER\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 638 | ahci_stop_engine(port_mmio); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 639 | |
| 640 | /* clear D2H reception area to properly wait for D2H FIS */ |
| 641 | ata_tf_init(ap->device, &tf); |
| 642 | tf.command = 0xff; |
| 643 | ata_tf_to_fis(&tf, d2h_fis, 0); |
| 644 | |
Tejun Heo | 2bf2cb2 | 2006-04-11 22:16:45 +0900 | [diff] [blame] | 645 | rc = sata_std_hardreset(ap, class); |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 646 | |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 647 | ahci_start_engine(port_mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
Tejun Heo | 81952c5 | 2006-05-15 20:57:47 +0900 | [diff] [blame] | 649 | if (rc == 0 && ata_port_online(ap)) |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 650 | *class = ahci_dev_classify(ap); |
| 651 | if (*class == ATA_DEV_UNKNOWN) |
| 652 | *class = ATA_DEV_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 654 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
| 655 | return rc; |
| 656 | } |
| 657 | |
| 658 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
| 659 | { |
| 660 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
| 661 | u32 new_tmp, tmp; |
| 662 | |
| 663 | ata_std_postreset(ap, class); |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 664 | |
| 665 | /* Make sure port's ATAPI bit is set appropriately */ |
| 666 | new_tmp = tmp = readl(port_mmio + PORT_CMD); |
Tejun Heo | 4bd00f6 | 2006-02-11 16:26:02 +0900 | [diff] [blame] | 667 | if (*class == ATA_DEV_ATAPI) |
Jeff Garzik | 02eaa66 | 2005-11-12 01:32:19 -0500 | [diff] [blame] | 668 | new_tmp |= PORT_CMD_ATAPI; |
| 669 | else |
| 670 | new_tmp &= ~PORT_CMD_ATAPI; |
| 671 | if (new_tmp != tmp) { |
| 672 | writel(new_tmp, port_mmio + PORT_CMD); |
| 673 | readl(port_mmio + PORT_CMD); /* flush */ |
| 674 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | } |
| 676 | |
| 677 | static u8 ahci_check_status(struct ata_port *ap) |
| 678 | { |
Al Viro | 1e4f2a9 | 2005-10-21 06:46:02 +0100 | [diff] [blame] | 679 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 680 | |
| 681 | return readl(mmio + PORT_TFDATA) & 0xFF; |
| 682 | } |
| 683 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 685 | { |
| 686 | struct ahci_port_priv *pp = ap->private_data; |
| 687 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
| 688 | |
| 689 | ata_tf_from_fis(d2h_fis, tf); |
| 690 | } |
| 691 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 692 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | { |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 694 | struct scatterlist *sg; |
| 695 | struct ahci_sg *ahci_sg; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 696 | unsigned int n_sg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 697 | |
| 698 | VPRINTK("ENTER\n"); |
| 699 | |
| 700 | /* |
| 701 | * Next, the S/G list. |
| 702 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 703 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 704 | ata_for_each_sg(sg, qc) { |
| 705 | dma_addr_t addr = sg_dma_address(sg); |
| 706 | u32 sg_len = sg_dma_len(sg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 707 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 708 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); |
| 709 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); |
| 710 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 711 | |
Jeff Garzik | cedc9a4 | 2005-10-05 07:13:30 -0400 | [diff] [blame] | 712 | ahci_sg++; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 713 | n_sg++; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | } |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 715 | |
| 716 | return n_sg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | } |
| 718 | |
| 719 | static void ahci_qc_prep(struct ata_queued_cmd *qc) |
| 720 | { |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 721 | struct ata_port *ap = qc->ap; |
| 722 | struct ahci_port_priv *pp = ap->private_data; |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 723 | int is_atapi = is_atapi_taskfile(&qc->tf); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 724 | void *cmd_tbl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | u32 opts; |
| 726 | const u32 cmd_fis_len = 5; /* five dwords */ |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 727 | unsigned int n_elem; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | |
| 729 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | * Fill in command table information. First, the header, |
| 731 | * a SATA Register - Host to Device command FIS. |
| 732 | */ |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 733 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
| 734 | |
| 735 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 736 | if (is_atapi) { |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 737 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
| 738 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
Jeff Garzik | a0ea732 | 2005-06-04 01:13:15 -0400 | [diff] [blame] | 739 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 741 | n_elem = 0; |
| 742 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 743 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | |
Tejun Heo | cc9278e | 2006-02-10 17:25:47 +0900 | [diff] [blame] | 745 | /* |
| 746 | * Fill in command slot information. |
| 747 | */ |
| 748 | opts = cmd_fis_len | n_elem << 16; |
| 749 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
| 750 | opts |= AHCI_CMD_WRITE; |
| 751 | if (is_atapi) |
Tejun Heo | 4b10e55 | 2006-03-12 11:25:27 +0900 | [diff] [blame] | 752 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
Jeff Garzik | 828d09d | 2005-11-12 01:27:07 -0500 | [diff] [blame] | 753 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 754 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | } |
| 756 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 757 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 759 | struct ahci_port_priv *pp = ap->private_data; |
| 760 | struct ata_eh_info *ehi = &ap->eh_info; |
| 761 | unsigned int err_mask = 0, action = 0; |
| 762 | struct ata_queued_cmd *qc; |
| 763 | u32 serror; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 765 | ata_ehi_clear_desc(ehi); |
Jeff Garzik | 9f68a24 | 2005-11-15 14:03:47 -0500 | [diff] [blame] | 766 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 767 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
| 768 | serror = ahci_scr_read(ap, SCR_ERROR); |
| 769 | ahci_scr_write(ap, SCR_ERROR, serror); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 771 | /* analyze @irq_stat */ |
| 772 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 773 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 774 | if (irq_stat & PORT_IRQ_TF_ERR) |
| 775 | err_mask |= AC_ERR_DEV; |
| 776 | |
| 777 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { |
| 778 | err_mask |= AC_ERR_HOST_BUS; |
| 779 | action |= ATA_EH_SOFTRESET; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 780 | } |
| 781 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 782 | if (irq_stat & PORT_IRQ_IF_ERR) { |
| 783 | err_mask |= AC_ERR_ATA_BUS; |
| 784 | action |= ATA_EH_SOFTRESET; |
| 785 | ata_ehi_push_desc(ehi, ", interface fatal error"); |
| 786 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 788 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 789 | ata_ehi_hotplugged(ehi); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 790 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
| 791 | "connection status changed" : "PHY RDY changed"); |
| 792 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 794 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
| 795 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 797 | err_mask |= AC_ERR_HSM; |
| 798 | action |= ATA_EH_SOFTRESET; |
| 799 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", |
| 800 | unk[0], unk[1], unk[2], unk[3]); |
| 801 | } |
Jeff Garzik | b8f6153 | 2005-08-25 22:01:20 -0400 | [diff] [blame] | 802 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 803 | /* okay, let's hand over to EH */ |
| 804 | ehi->serror |= serror; |
| 805 | ehi->action |= action; |
| 806 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 808 | if (qc) |
| 809 | qc->err_mask |= err_mask; |
| 810 | else |
| 811 | ehi->err_mask |= err_mask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 812 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 813 | if (irq_stat & PORT_IRQ_FREEZE) |
| 814 | ata_port_freeze(ap); |
| 815 | else |
| 816 | ata_port_abort(ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | } |
| 818 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 819 | static void ahci_host_intr(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 821 | void __iomem *mmio = ap->host_set->mmio_base; |
| 822 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 823 | struct ata_eh_info *ehi = &ap->eh_info; |
| 824 | u32 status, qc_active; |
| 825 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | |
| 827 | status = readl(port_mmio + PORT_IRQ_STAT); |
| 828 | writel(status, port_mmio + PORT_IRQ_STAT); |
| 829 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 830 | if (unlikely(status & PORT_IRQ_ERROR)) { |
| 831 | ahci_error_intr(ap, status); |
| 832 | return; |
| 833 | } |
| 834 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 835 | if (ap->sactive) |
| 836 | qc_active = readl(port_mmio + PORT_SCR_ACT); |
| 837 | else |
| 838 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); |
| 839 | |
| 840 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); |
| 841 | if (rc > 0) |
| 842 | return; |
| 843 | if (rc < 0) { |
| 844 | ehi->err_mask |= AC_ERR_HSM; |
| 845 | ehi->action |= ATA_EH_SOFTRESET; |
| 846 | ata_port_freeze(ap); |
| 847 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 848 | } |
| 849 | |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 850 | /* hmmm... a spurious interupt */ |
| 851 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 852 | /* some devices send D2H reg with I bit set during NCQ command phase */ |
| 853 | if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS) |
| 854 | return; |
| 855 | |
Tejun Heo | 2a3917a | 2006-05-15 20:58:30 +0900 | [diff] [blame] | 856 | /* ignore interim PIO setup fis interrupts */ |
| 857 | if (ata_tag_valid(ap->active_tag)) { |
| 858 | struct ata_queued_cmd *qc = |
| 859 | ata_qc_from_tag(ap, ap->active_tag); |
| 860 | |
| 861 | if (qc && qc->tf.protocol == ATA_PROT_PIO && |
| 862 | (status & PORT_IRQ_PIOS_FIS)) |
| 863 | return; |
| 864 | } |
| 865 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 866 | if (ata_ratelimit()) |
| 867 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 868 | "(irq_stat 0x%x active_tag %d sactive 0x%x)\n", |
| 869 | status, ap->active_tag, ap->sactive); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 870 | } |
| 871 | |
| 872 | static void ahci_irq_clear(struct ata_port *ap) |
| 873 | { |
| 874 | /* TODO */ |
| 875 | } |
| 876 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 877 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | { |
| 879 | struct ata_host_set *host_set = dev_instance; |
| 880 | struct ahci_host_priv *hpriv; |
| 881 | unsigned int i, handled = 0; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 882 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | u32 irq_stat, irq_ack = 0; |
| 884 | |
| 885 | VPRINTK("ENTER\n"); |
| 886 | |
| 887 | hpriv = host_set->private_data; |
| 888 | mmio = host_set->mmio_base; |
| 889 | |
| 890 | /* sigh. 0xffffffff is a valid return from h/w */ |
| 891 | irq_stat = readl(mmio + HOST_IRQ_STAT); |
| 892 | irq_stat &= hpriv->port_map; |
| 893 | if (!irq_stat) |
| 894 | return IRQ_NONE; |
| 895 | |
| 896 | spin_lock(&host_set->lock); |
| 897 | |
| 898 | for (i = 0; i < host_set->n_ports; i++) { |
| 899 | struct ata_port *ap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 900 | |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 901 | if (!(irq_stat & (1 << i))) |
| 902 | continue; |
| 903 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | ap = host_set->ports[i]; |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 905 | if (ap) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 906 | ahci_host_intr(ap); |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 907 | VPRINTK("port %u\n", i); |
| 908 | } else { |
| 909 | VPRINTK("port %u (no irq)\n", i); |
Tejun Heo | 6971ed1 | 2006-03-11 12:47:54 +0900 | [diff] [blame] | 910 | if (ata_ratelimit()) |
| 911 | dev_printk(KERN_WARNING, host_set->dev, |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 912 | "interrupt on disabled port %u\n", i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 913 | } |
Jeff Garzik | 67846b3 | 2005-10-05 02:58:32 -0400 | [diff] [blame] | 914 | |
| 915 | irq_ack |= (1 << i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 916 | } |
| 917 | |
| 918 | if (irq_ack) { |
| 919 | writel(irq_ack, mmio + HOST_IRQ_STAT); |
| 920 | handled = 1; |
| 921 | } |
| 922 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 923 | spin_unlock(&host_set->lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 924 | |
| 925 | VPRINTK("EXIT\n"); |
| 926 | |
| 927 | return IRQ_RETVAL(handled); |
| 928 | } |
| 929 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 930 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | { |
| 932 | struct ata_port *ap = qc->ap; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 933 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 935 | if (qc->tf.protocol == ATA_PROT_NCQ) |
| 936 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); |
| 937 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
| 939 | |
| 940 | return 0; |
| 941 | } |
| 942 | |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 943 | static void ahci_freeze(struct ata_port *ap) |
| 944 | { |
| 945 | void __iomem *mmio = ap->host_set->mmio_base; |
| 946 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 947 | |
| 948 | /* turn IRQ off */ |
| 949 | writel(0, port_mmio + PORT_IRQ_MASK); |
| 950 | } |
| 951 | |
| 952 | static void ahci_thaw(struct ata_port *ap) |
| 953 | { |
| 954 | void __iomem *mmio = ap->host_set->mmio_base; |
| 955 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 956 | u32 tmp; |
| 957 | |
| 958 | /* clear IRQ */ |
| 959 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 960 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 961 | writel(1 << ap->id, mmio + HOST_IRQ_STAT); |
| 962 | |
| 963 | /* turn IRQ back on */ |
| 964 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); |
| 965 | } |
| 966 | |
| 967 | static void ahci_error_handler(struct ata_port *ap) |
| 968 | { |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 969 | void __iomem *mmio = ap->host_set->mmio_base; |
| 970 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 971 | |
Tejun Heo | b51e9e5 | 2006-06-29 01:29:30 +0900 | [diff] [blame] | 972 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 973 | /* restart engine */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 974 | ahci_stop_engine(port_mmio); |
| 975 | ahci_start_engine(port_mmio); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 976 | } |
| 977 | |
| 978 | /* perform recovery */ |
Tejun Heo | 4296971 | 2006-05-31 18:28:18 +0900 | [diff] [blame] | 979 | ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset, |
Tejun Heo | f5914a4 | 2006-05-31 18:27:48 +0900 | [diff] [blame] | 980 | ahci_postreset); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 981 | } |
| 982 | |
| 983 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
| 984 | { |
| 985 | struct ata_port *ap = qc->ap; |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 986 | void __iomem *mmio = ap->host_set->mmio_base; |
| 987 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 988 | |
| 989 | if (qc->flags & ATA_QCFLAG_FAILED) |
| 990 | qc->err_mask |= AC_ERR_OTHER; |
| 991 | |
| 992 | if (qc->err_mask) { |
| 993 | /* make DMA engine forget about the failed command */ |
zhao, forrest | 5457f219 | 2006-07-13 13:38:32 +0800 | [diff] [blame] | 994 | ahci_stop_engine(port_mmio); |
| 995 | ahci_start_engine(port_mmio); |
Tejun Heo | 78cd52d | 2006-05-15 20:58:29 +0900 | [diff] [blame] | 996 | } |
| 997 | } |
| 998 | |
Tejun Heo | 254950c | 2006-07-26 15:59:25 +0900 | [diff] [blame] | 999 | static int ahci_port_start(struct ata_port *ap) |
| 1000 | { |
| 1001 | struct device *dev = ap->host_set->dev; |
| 1002 | struct ahci_host_priv *hpriv = ap->host_set->private_data; |
| 1003 | struct ahci_port_priv *pp; |
| 1004 | void __iomem *mmio = ap->host_set->mmio_base; |
| 1005 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 1006 | void *mem; |
| 1007 | dma_addr_t mem_dma; |
| 1008 | int rc; |
| 1009 | |
| 1010 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); |
| 1011 | if (!pp) |
| 1012 | return -ENOMEM; |
| 1013 | memset(pp, 0, sizeof(*pp)); |
| 1014 | |
| 1015 | rc = ata_pad_alloc(ap, dev); |
| 1016 | if (rc) { |
| 1017 | kfree(pp); |
| 1018 | return rc; |
| 1019 | } |
| 1020 | |
| 1021 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); |
| 1022 | if (!mem) { |
| 1023 | ata_pad_free(ap, dev); |
| 1024 | kfree(pp); |
| 1025 | return -ENOMEM; |
| 1026 | } |
| 1027 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); |
| 1028 | |
| 1029 | /* |
| 1030 | * First item in chunk of DMA memory: 32-slot command table, |
| 1031 | * 32 bytes each in size |
| 1032 | */ |
| 1033 | pp->cmd_slot = mem; |
| 1034 | pp->cmd_slot_dma = mem_dma; |
| 1035 | |
| 1036 | mem += AHCI_CMD_SLOT_SZ; |
| 1037 | mem_dma += AHCI_CMD_SLOT_SZ; |
| 1038 | |
| 1039 | /* |
| 1040 | * Second item: Received-FIS area |
| 1041 | */ |
| 1042 | pp->rx_fis = mem; |
| 1043 | pp->rx_fis_dma = mem_dma; |
| 1044 | |
| 1045 | mem += AHCI_RX_FIS_SZ; |
| 1046 | mem_dma += AHCI_RX_FIS_SZ; |
| 1047 | |
| 1048 | /* |
| 1049 | * Third item: data area for storing a single command |
| 1050 | * and its scatter-gather table |
| 1051 | */ |
| 1052 | pp->cmd_tbl = mem; |
| 1053 | pp->cmd_tbl_dma = mem_dma; |
| 1054 | |
| 1055 | ap->private_data = pp; |
| 1056 | |
| 1057 | if (hpriv->cap & HOST_CAP_64) |
| 1058 | writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); |
| 1059 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); |
| 1060 | readl(port_mmio + PORT_LST_ADDR); /* flush */ |
| 1061 | |
| 1062 | if (hpriv->cap & HOST_CAP_64) |
| 1063 | writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); |
| 1064 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); |
| 1065 | readl(port_mmio + PORT_FIS_ADDR); /* flush */ |
| 1066 | |
| 1067 | writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | |
| 1068 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | |
| 1069 | PORT_CMD_START, port_mmio + PORT_CMD); |
| 1070 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1071 | |
| 1072 | return 0; |
| 1073 | } |
| 1074 | |
| 1075 | static void ahci_port_stop(struct ata_port *ap) |
| 1076 | { |
| 1077 | struct device *dev = ap->host_set->dev; |
| 1078 | struct ahci_port_priv *pp = ap->private_data; |
| 1079 | void __iomem *mmio = ap->host_set->mmio_base; |
| 1080 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
| 1081 | u32 tmp; |
| 1082 | |
| 1083 | tmp = readl(port_mmio + PORT_CMD); |
| 1084 | tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX); |
| 1085 | writel(tmp, port_mmio + PORT_CMD); |
| 1086 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1087 | |
| 1088 | /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so |
| 1089 | * this is slightly incorrect. |
| 1090 | */ |
| 1091 | msleep(500); |
| 1092 | |
| 1093 | ap->private_data = NULL; |
| 1094 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, |
| 1095 | pp->cmd_slot, pp->cmd_slot_dma); |
| 1096 | ata_pad_free(ap, dev); |
| 1097 | kfree(pp); |
| 1098 | } |
| 1099 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1100 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, |
| 1101 | unsigned int port_idx) |
| 1102 | { |
| 1103 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); |
| 1104 | base = ahci_port_base_ul(base, port_idx); |
| 1105 | VPRINTK("base now==0x%lx\n", base); |
| 1106 | |
| 1107 | port->cmd_addr = base; |
| 1108 | port->scr_addr = base + PORT_SCR; |
| 1109 | |
| 1110 | VPRINTK("EXIT\n"); |
| 1111 | } |
| 1112 | |
| 1113 | static int ahci_host_init(struct ata_probe_ent *probe_ent) |
| 1114 | { |
| 1115 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
| 1116 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
| 1117 | void __iomem *mmio = probe_ent->mmio_base; |
| 1118 | u32 tmp, cap_save; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1119 | unsigned int i, j, using_dac; |
| 1120 | int rc; |
| 1121 | void __iomem *port_mmio; |
| 1122 | |
| 1123 | cap_save = readl(mmio + HOST_CAP); |
| 1124 | cap_save &= ( (1<<28) | (1<<17) ); |
| 1125 | cap_save |= (1 << 27); |
| 1126 | |
| 1127 | /* global controller reset */ |
| 1128 | tmp = readl(mmio + HOST_CTL); |
| 1129 | if ((tmp & HOST_RESET) == 0) { |
| 1130 | writel(tmp | HOST_RESET, mmio + HOST_CTL); |
| 1131 | readl(mmio + HOST_CTL); /* flush */ |
| 1132 | } |
| 1133 | |
| 1134 | /* reset must complete within 1 second, or |
| 1135 | * the hardware should be considered fried. |
| 1136 | */ |
| 1137 | ssleep(1); |
| 1138 | |
| 1139 | tmp = readl(mmio + HOST_CTL); |
| 1140 | if (tmp & HOST_RESET) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1141 | dev_printk(KERN_ERR, &pdev->dev, |
| 1142 | "controller reset failed (0x%x)\n", tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1143 | return -EIO; |
| 1144 | } |
| 1145 | |
| 1146 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
| 1147 | (void) readl(mmio + HOST_CTL); /* flush */ |
| 1148 | writel(cap_save, mmio + HOST_CAP); |
| 1149 | writel(0xf, mmio + HOST_PORTS_IMPL); |
| 1150 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
| 1151 | |
Jeff Garzik | bd12097 | 2006-01-29 02:47:03 -0500 | [diff] [blame] | 1152 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
| 1153 | u16 tmp16; |
| 1154 | |
| 1155 | pci_read_config_word(pdev, 0x92, &tmp16); |
| 1156 | tmp16 |= 0xf; |
| 1157 | pci_write_config_word(pdev, 0x92, tmp16); |
| 1158 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | |
| 1160 | hpriv->cap = readl(mmio + HOST_CAP); |
| 1161 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); |
| 1162 | probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; |
| 1163 | |
| 1164 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", |
| 1165 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); |
| 1166 | |
| 1167 | using_dac = hpriv->cap & HOST_CAP_64; |
| 1168 | if (using_dac && |
| 1169 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
| 1170 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
| 1171 | if (rc) { |
| 1172 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1173 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1174 | dev_printk(KERN_ERR, &pdev->dev, |
| 1175 | "64-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1176 | return rc; |
| 1177 | } |
| 1178 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1179 | } else { |
| 1180 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 1181 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1182 | dev_printk(KERN_ERR, &pdev->dev, |
| 1183 | "32-bit DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1184 | return rc; |
| 1185 | } |
| 1186 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 1187 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1188 | dev_printk(KERN_ERR, &pdev->dev, |
| 1189 | "32-bit consistent DMA enable failed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1190 | return rc; |
| 1191 | } |
| 1192 | } |
| 1193 | |
| 1194 | for (i = 0; i < probe_ent->n_ports; i++) { |
| 1195 | #if 0 /* BIOSen initialize this incorrectly */ |
| 1196 | if (!(hpriv->port_map & (1 << i))) |
| 1197 | continue; |
| 1198 | #endif |
| 1199 | |
| 1200 | port_mmio = ahci_port_base(mmio, i); |
| 1201 | VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio); |
| 1202 | |
| 1203 | ahci_setup_port(&probe_ent->port[i], |
| 1204 | (unsigned long) mmio, i); |
| 1205 | |
| 1206 | /* make sure port is not active */ |
| 1207 | tmp = readl(port_mmio + PORT_CMD); |
| 1208 | VPRINTK("PORT_CMD 0x%x\n", tmp); |
| 1209 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 1210 | PORT_CMD_FIS_RX | PORT_CMD_START)) { |
| 1211 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | |
| 1212 | PORT_CMD_FIS_RX | PORT_CMD_START); |
| 1213 | writel(tmp, port_mmio + PORT_CMD); |
| 1214 | readl(port_mmio + PORT_CMD); /* flush */ |
| 1215 | |
| 1216 | /* spec says 500 msecs for each bit, so |
| 1217 | * this is slightly incorrect. |
| 1218 | */ |
| 1219 | msleep(500); |
| 1220 | } |
| 1221 | |
| 1222 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); |
| 1223 | |
| 1224 | j = 0; |
| 1225 | while (j < 100) { |
| 1226 | msleep(10); |
| 1227 | tmp = readl(port_mmio + PORT_SCR_STAT); |
| 1228 | if ((tmp & 0xf) == 0x3) |
| 1229 | break; |
| 1230 | j++; |
| 1231 | } |
| 1232 | |
| 1233 | tmp = readl(port_mmio + PORT_SCR_ERR); |
| 1234 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); |
| 1235 | writel(tmp, port_mmio + PORT_SCR_ERR); |
| 1236 | |
| 1237 | /* ack any pending irq events for this port */ |
| 1238 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
| 1239 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); |
| 1240 | if (tmp) |
| 1241 | writel(tmp, port_mmio + PORT_IRQ_STAT); |
| 1242 | |
| 1243 | writel(1 << i, mmio + HOST_IRQ_STAT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1244 | } |
| 1245 | |
| 1246 | tmp = readl(mmio + HOST_CTL); |
| 1247 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1248 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); |
| 1249 | tmp = readl(mmio + HOST_CTL); |
| 1250 | VPRINTK("HOST_CTL 0x%x\n", tmp); |
| 1251 | |
| 1252 | pci_set_master(pdev); |
| 1253 | |
| 1254 | return 0; |
| 1255 | } |
| 1256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
| 1258 | { |
| 1259 | struct ahci_host_priv *hpriv = probe_ent->private_data; |
| 1260 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1261 | void __iomem *mmio = probe_ent->mmio_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | u32 vers, cap, impl, speed; |
| 1263 | const char *speed_s; |
| 1264 | u16 cc; |
| 1265 | const char *scc_s; |
| 1266 | |
| 1267 | vers = readl(mmio + HOST_VERSION); |
| 1268 | cap = hpriv->cap; |
| 1269 | impl = hpriv->port_map; |
| 1270 | |
| 1271 | speed = (cap >> 20) & 0xf; |
| 1272 | if (speed == 1) |
| 1273 | speed_s = "1.5"; |
| 1274 | else if (speed == 2) |
| 1275 | speed_s = "3"; |
| 1276 | else |
| 1277 | speed_s = "?"; |
| 1278 | |
| 1279 | pci_read_config_word(pdev, 0x0a, &cc); |
| 1280 | if (cc == 0x0101) |
| 1281 | scc_s = "IDE"; |
| 1282 | else if (cc == 0x0106) |
| 1283 | scc_s = "SATA"; |
| 1284 | else if (cc == 0x0104) |
| 1285 | scc_s = "RAID"; |
| 1286 | else |
| 1287 | scc_s = "unknown"; |
| 1288 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1289 | dev_printk(KERN_INFO, &pdev->dev, |
| 1290 | "AHCI %02x%02x.%02x%02x " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1291 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
| 1292 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1293 | |
| 1294 | (vers >> 24) & 0xff, |
| 1295 | (vers >> 16) & 0xff, |
| 1296 | (vers >> 8) & 0xff, |
| 1297 | vers & 0xff, |
| 1298 | |
| 1299 | ((cap >> 8) & 0x1f) + 1, |
| 1300 | (cap & 0x1f) + 1, |
| 1301 | speed_s, |
| 1302 | impl, |
| 1303 | scc_s); |
| 1304 | |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1305 | dev_printk(KERN_INFO, &pdev->dev, |
| 1306 | "flags: " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1307 | "%s%s%s%s%s%s" |
| 1308 | "%s%s%s%s%s%s%s\n" |
| 1309 | , |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1310 | |
| 1311 | cap & (1 << 31) ? "64bit " : "", |
| 1312 | cap & (1 << 30) ? "ncq " : "", |
| 1313 | cap & (1 << 28) ? "ilck " : "", |
| 1314 | cap & (1 << 27) ? "stag " : "", |
| 1315 | cap & (1 << 26) ? "pm " : "", |
| 1316 | cap & (1 << 25) ? "led " : "", |
| 1317 | |
| 1318 | cap & (1 << 24) ? "clo " : "", |
| 1319 | cap & (1 << 19) ? "nz " : "", |
| 1320 | cap & (1 << 18) ? "only " : "", |
| 1321 | cap & (1 << 17) ? "pmp " : "", |
| 1322 | cap & (1 << 15) ? "pio " : "", |
| 1323 | cap & (1 << 14) ? "slum " : "", |
| 1324 | cap & (1 << 13) ? "part " : "" |
| 1325 | ); |
| 1326 | } |
| 1327 | |
| 1328 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 1329 | { |
| 1330 | static int printed_version; |
| 1331 | struct ata_probe_ent *probe_ent = NULL; |
| 1332 | struct ahci_host_priv *hpriv; |
| 1333 | unsigned long base; |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1334 | void __iomem *mmio_base; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1335 | unsigned int board_idx = (unsigned int) ent->driver_data; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1336 | int have_msi, pci_dev_busy = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1337 | int rc; |
| 1338 | |
| 1339 | VPRINTK("ENTER\n"); |
| 1340 | |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1341 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
| 1342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1343 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 1344 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1345 | |
root | 9545b57 | 2006-07-05 22:58:20 -0400 | [diff] [blame] | 1346 | /* JMicron-specific fixup: make sure we're in AHCI mode */ |
| 1347 | /* This is protected from races with ata_jmicron by the pci probe |
| 1348 | locking */ |
| 1349 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON) { |
| 1350 | /* AHCI enable, AHCI on function 0 */ |
| 1351 | pci_write_config_byte(pdev, 0x41, 0xa1); |
| 1352 | /* Function 1 is the PATA controller */ |
| 1353 | if (PCI_FUNC(pdev->devfn)) |
| 1354 | return -ENODEV; |
| 1355 | } |
| 1356 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1357 | rc = pci_enable_device(pdev); |
| 1358 | if (rc) |
| 1359 | return rc; |
| 1360 | |
| 1361 | rc = pci_request_regions(pdev, DRV_NAME); |
| 1362 | if (rc) { |
| 1363 | pci_dev_busy = 1; |
| 1364 | goto err_out; |
| 1365 | } |
| 1366 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1367 | if (pci_enable_msi(pdev) == 0) |
| 1368 | have_msi = 1; |
| 1369 | else { |
| 1370 | pci_intx(pdev, 1); |
| 1371 | have_msi = 0; |
| 1372 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1373 | |
| 1374 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); |
| 1375 | if (probe_ent == NULL) { |
| 1376 | rc = -ENOMEM; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1377 | goto err_out_msi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1378 | } |
| 1379 | |
| 1380 | memset(probe_ent, 0, sizeof(*probe_ent)); |
| 1381 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 1382 | INIT_LIST_HEAD(&probe_ent->node); |
| 1383 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1384 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1385 | if (mmio_base == NULL) { |
| 1386 | rc = -ENOMEM; |
| 1387 | goto err_out_free_ent; |
| 1388 | } |
| 1389 | base = (unsigned long) mmio_base; |
| 1390 | |
| 1391 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); |
| 1392 | if (!hpriv) { |
| 1393 | rc = -ENOMEM; |
| 1394 | goto err_out_iounmap; |
| 1395 | } |
| 1396 | memset(hpriv, 0, sizeof(*hpriv)); |
| 1397 | |
| 1398 | probe_ent->sht = ahci_port_info[board_idx].sht; |
| 1399 | probe_ent->host_flags = ahci_port_info[board_idx].host_flags; |
| 1400 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; |
| 1401 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; |
| 1402 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; |
| 1403 | |
| 1404 | probe_ent->irq = pdev->irq; |
Thomas Gleixner | 1d6f359 | 2006-07-01 19:29:42 -0700 | [diff] [blame] | 1405 | probe_ent->irq_flags = IRQF_SHARED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1406 | probe_ent->mmio_base = mmio_base; |
| 1407 | probe_ent->private_data = hpriv; |
| 1408 | |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 1409 | if (have_msi) |
| 1410 | hpriv->flags |= AHCI_FLAG_MSI; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1411 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1412 | /* initialize adapter */ |
| 1413 | rc = ahci_host_init(probe_ent); |
| 1414 | if (rc) |
| 1415 | goto err_out_hpriv; |
| 1416 | |
Tejun Heo | 71f0737 | 2006-06-21 23:12:48 +0900 | [diff] [blame] | 1417 | if (!(probe_ent->host_flags & AHCI_FLAG_NO_NCQ) && |
| 1418 | (hpriv->cap & HOST_CAP_NCQ)) |
Tejun Heo | 12fad3f | 2006-05-15 21:03:55 +0900 | [diff] [blame] | 1419 | probe_ent->host_flags |= ATA_FLAG_NCQ; |
| 1420 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1421 | ahci_print_info(probe_ent); |
| 1422 | |
| 1423 | /* FIXME: check ata_device_add return value */ |
| 1424 | ata_device_add(probe_ent); |
| 1425 | kfree(probe_ent); |
| 1426 | |
| 1427 | return 0; |
| 1428 | |
| 1429 | err_out_hpriv: |
| 1430 | kfree(hpriv); |
| 1431 | err_out_iounmap: |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1432 | pci_iounmap(pdev, mmio_base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1433 | err_out_free_ent: |
| 1434 | kfree(probe_ent); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1435 | err_out_msi: |
| 1436 | if (have_msi) |
| 1437 | pci_disable_msi(pdev); |
| 1438 | else |
| 1439 | pci_intx(pdev, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | pci_release_regions(pdev); |
| 1441 | err_out: |
| 1442 | if (!pci_dev_busy) |
| 1443 | pci_disable_device(pdev); |
| 1444 | return rc; |
| 1445 | } |
| 1446 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1447 | static void ahci_remove_one (struct pci_dev *pdev) |
| 1448 | { |
| 1449 | struct device *dev = pci_dev_to_dev(pdev); |
| 1450 | struct ata_host_set *host_set = dev_get_drvdata(dev); |
| 1451 | struct ahci_host_priv *hpriv = host_set->private_data; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1452 | unsigned int i; |
| 1453 | int have_msi; |
| 1454 | |
Tejun Heo | 720ba12 | 2006-05-31 18:28:13 +0900 | [diff] [blame] | 1455 | for (i = 0; i < host_set->n_ports; i++) |
| 1456 | ata_port_detach(host_set->ports[i]); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1457 | |
Jeff Garzik | 4b0060f | 2005-06-04 00:50:22 -0400 | [diff] [blame] | 1458 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1459 | free_irq(host_set->irq, host_set); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1460 | |
| 1461 | for (i = 0; i < host_set->n_ports; i++) { |
Tejun Heo | 720ba12 | 2006-05-31 18:28:13 +0900 | [diff] [blame] | 1462 | struct ata_port *ap = host_set->ports[i]; |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1463 | |
| 1464 | ata_scsi_release(ap->host); |
| 1465 | scsi_host_put(ap->host); |
| 1466 | } |
| 1467 | |
Jeff Garzik | e005f01 | 2005-08-30 04:18:28 -0400 | [diff] [blame] | 1468 | kfree(hpriv); |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1469 | pci_iounmap(pdev, host_set->mmio_base); |
Jeff Garzik | ead5de9 | 2005-05-31 11:53:57 -0400 | [diff] [blame] | 1470 | kfree(host_set); |
| 1471 | |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1472 | if (have_msi) |
| 1473 | pci_disable_msi(pdev); |
| 1474 | else |
| 1475 | pci_intx(pdev, 0); |
| 1476 | pci_release_regions(pdev); |
Jeff Garzik | 907f467 | 2005-05-12 15:03:42 -0400 | [diff] [blame] | 1477 | pci_disable_device(pdev); |
| 1478 | dev_set_drvdata(dev, NULL); |
| 1479 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1480 | |
| 1481 | static int __init ahci_init(void) |
| 1482 | { |
| 1483 | return pci_module_init(&ahci_pci_driver); |
| 1484 | } |
| 1485 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1486 | static void __exit ahci_exit(void) |
| 1487 | { |
| 1488 | pci_unregister_driver(&ahci_pci_driver); |
| 1489 | } |
| 1490 | |
| 1491 | |
| 1492 | MODULE_AUTHOR("Jeff Garzik"); |
| 1493 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); |
| 1494 | MODULE_LICENSE("GPL"); |
| 1495 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); |
Jeff Garzik | 6885433 | 2005-08-23 02:53:51 -0400 | [diff] [blame] | 1496 | MODULE_VERSION(DRV_VERSION); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1497 | |
| 1498 | module_init(ahci_init); |
| 1499 | module_exit(ahci_exit); |